Light-emitting substrate and method for manufacturing the same, backlight, display device

Abstract

The present disclosure provides a light-emitting substrate and a manufacturing method thereof, a backlight, and a display device. The light-emitting substrate includes a substrate including a plurality of light-emitting regions arranged in an array, each of the plurality of light-emitting regions including a driving circuit and at least one light-emitting unit connected to the driving circuit, a first conductive part located on the substrate and connected to the driving circuit and the at least one light-emitting unit in each of the light-emitting regions, and a second conductive part located on the substrate and including a plurality of pads. The first conductive part and the second conductive part are located in the same layer.

Description

Technical Field

[0001] The present disclosure relates to the technical field of optics, and particularly to a light-emitting substrate and a manufacturing method thereof, a backlight including the light-emitting substrate, and a display device including the light-emitting substrate.

Background Art

[0002] With the continuous development of display technology, the requirements of users for the contrast, brightness uniformity and stability of display devices are increasing. Display devices are generally divided into two types: liquid crystal display devices and organic light-emitting diode display devices. Liquid crystal display devices are widely applied because they have the advantages of being thin and light, shock-resistant, wide viewing angle, and high contrast. A liquid crystal display device generally includes a display panel and a backlight, and the backlight is generally installed on the non-display side of the display panel to provide a light source for the display operation of the display panel. The characteristics such as the contrast, brightness uniformity and stability of a liquid crystal display device are related to the structure and performance of the backlight.

Summary of the Invention

[0003] According to one aspect of the present disclosure, a light-emitting substrate is provided, which includes a plurality of light-emitting regions arranged in an array, and each of the plurality of light-emitting regions includes a driving circuit and at least one light-emitting unit connected to the driving circuit on a substrate, a first conductive part located on the substrate and connected to the driving circuit and the at least one light-emitting unit in each light-emitting region, and a second conductive part located on the substrate and including a plurality of pads. The first conductive part and the second conductive part are located in the same layer.

[0004] In some embodiments, the plurality of light-emitting regions are arranged in M ​​rows along a first direction and in N columns along a second direction intersecting the first direction, where M and N are both positive integers of 1 or more. The first conductive portion includes N drive voltage signal lines and N common voltage signal lines extending along the first direction, and each light-emitting region in each column includes one drive voltage signal line and one common voltage signal line, within each light-emitting region in each column, the drive voltage signal lines are connected to the first end of each light-emitting unit in the light-emitting region of that column, and the common voltage signal lines are connected to each drive circuit in the light-emitting region of that column, and within each light-emitting region in each column, the drive voltage signal lines, the light-emitting units, the drive circuits and the common voltage signal lines are sequentially arranged along the second direction.

[0005] In some embodiments, the orthographic projections of the drive voltage signal line, the light-emitting unit, the drive circuit, and the common voltage signal line on the substrate do not overlap with each other.

[0006] In some embodiments, each drive circuit comprises a plurality of terminals arranged in an array, the plurality of terminals arranged in at least two rows along the second direction. The plurality of terminals includes at least one output terminal and at least one common voltage terminal, the at least one output terminal and the at least one common voltage terminal located in different rows of the plurality of terminals. Within the light-emitting region of each row, the at least one output terminal of each drive circuit is connected in a one-to-one correspondence to the second end of the at least one light-emitting unit to which the drive circuit is connected, and the at least one common voltage terminal of each drive circuit is connected to the common voltage signal line within the light-emitting region of the row.

[0007] In some embodiments, the plurality of terminals further include address terminals, relay terminals, and power supply terminals. The driving circuits within the light-emitting regions of each column are sequentially connected in series. The address terminal of the i-th driving circuit is located on the side closer to the (i - 1)-th driving circuit of the i-th driving circuit. The relay terminal of the i-th driving circuit is located on the side closer to the (i + 1)-th driving circuit of the i-th driving circuit, where 1 < i < M and i is a positive integer. The address terminal is configured to receive an address signal, the relay terminal is configured to output a relay signal, and the power supply terminal is configured to receive a power supply voltage signal.

[0008] In some embodiments, the extending direction of the first conductive portion is parallel to the series connection direction of the driving circuits.

[0009] In some embodiments, the plurality of terminals of the driving circuit are arranged in the first column and the second column along the second direction. Within the light-emitting region of each column, the terminals of the first row of the driving circuit are located on the side adjacent to the driving voltage signal line of the driving circuit, and the terminals of the second row of the driving circuit are located on the side adjacent to the common voltage signal line of the driving circuit.

[0010] In some embodiments, the first conductive portion further includes N power signal lines. Each light-emitting region of each column includes one power signal line. Each power signal line includes a main body portion and a first connection portion. The main body portion of the power signal line extends along the first direction. Within the light-emitting region of each column, the power signal line is connected to the power supply terminal of each driving circuit within the light-emitting region of the column by the first connection portion, and the orthographic projection of the terminal of the first row on the substrate and the orthographic projection of the terminal of the second row on the substrate are respectively located on both sides of the orthographic projection of the power signal line on the substrate.

[0011] In some embodiments, the first conductive portion further includes N address signal lines extending along the first direction. Each light-emitting region of each column includes one address signal line. Within the light-emitting region of each column, the address signal line is connected to the address terminal of the first-stage driving circuit.

[0012] In some embodiments, the first conductive portion further includes cascaded wiring extending along the first direction, the cascaded wiring being located between two adjacent cascaded drive circuits within the light-emitting region of each row, and the relay terminal of the i-th stage drive circuit being connected to the address terminal of the i+1-th stage drive circuit via the cascaded wiring.

[0013] In some embodiments, the first conductive portion further includes N feedback signal lines extending along the first direction, and each light-emitting region of a row includes one feedback signal line. Within each light-emitting region of a row, the feedback signal line is connected to the relay terminal of the final stage drive circuit, and the feedback signal line is at least partially located on the side of the common voltage signal line within the light-emitting region of the row away from the drive circuit.

[0014] In some embodiments, the orthographic projections of the drive voltage signal line, the address signal line, the cascaded connection wiring, the power signal line, the common voltage signal line, and the feedback signal line on the substrate do not overlap with each other.

[0015] In some embodiments, the plurality of terminals of the drive circuit include the address terminal, the power supply terminal, the common voltage terminal, and the output terminal. The first row of terminals includes the output terminal and the address terminal, and the second row of terminals includes the common voltage terminal and the power supply terminal.

[0016] In some embodiments, the output terminal and the relay terminal of the drive circuit are the same terminal, and the drive circuit is configured to output a relay signal via the output terminal as the address signal for the next stage drive circuit cascaded to the drive circuit within a first time period, and to supply a drive signal via the output terminal to the at least one light-emitting unit connected to the drive circuit within a second time period.

[0017] In some embodiments, the plurality of terminals of the drive circuit further include data terminals, and the data terminals and the power terminals are located in different rows of the plurality of terminals.

[0018] In some embodiments, the drive circuit has multiple output terminals and at least one common voltage terminal. The first row of terminals includes the power terminal and the multiple output terminals, and the second row of terminals includes the address terminal, the relay terminal, the data terminal and at least one common voltage terminal.

[0019] In some embodiments, the first conductive portion further includes N data drive signal lines, each row of light-emitting regions includes one data drive signal line, each data drive signal line includes a body portion and a second connection portion, the body portion of the data drive signal line extends along the first direction. Within each row of light-emitting region, the data drive signal line is connected by the second connection portion to the data terminals of each drive circuit within the row of light-emitting region, and the orthographic projections of the terminals of the first row on the substrate and the orthographic projections of the terminals of the second row on the substrate are located on opposite sides of the orthographic projection of the data drive signal line on the substrate, and the orthographic projection of the data drive signal line on the substrate does not overlap with the orthographic projection of the power signal line on the substrate.

[0020] In some embodiments, the plurality of output terminals of the drive circuit are connected in a one-to-one correspondence to the second ends of a plurality of light-emitting units connected to the drive circuit. The drive circuit is configured to output a relay signal via the relay terminal as the address signal for the next stage drive circuit cascaded to the drive circuit within a first time period, and to supply drive signals to each of the plurality of light-emitting units via the plurality of output terminals within a second time period.

[0021] In some embodiments, the distance between the drive voltage signal line and other adjacent signal lines is 0.2 mm or more.

[0022] In some embodiments, the light-emitting substrate further includes a plurality of flexible circuit boards and a fan-out region. Each signal line of the first conductive portion includes a straight portion and a bent portion, the bent portion of each signal line is located within the fan-out region, and each signal line is connected to the plurality of flexible circuit boards by its bent portion, and the width of the bent portion of each signal line along the second direction is smaller than the width of two adjacent rows of light-emitting regions along the second direction.

[0023] In some embodiments, the included angle formed by the straight portion and the bent portion of each signal line is 80°-100°.

[0024] In some embodiments, the materials of the first conductive portion and the second conductive portion include copper.

[0025] In some embodiments, each light-emitting unit includes a plurality of light-emitting elements connected to each other, and each of the plurality of light-emitting elements includes a mini light-emitting diode or a micro light-emitting diode.

[0026] In some embodiments, the light-emitting substrate further includes a shielding ring, the shielding ring surrounds the outer periphery of the plurality of light-emitting regions, and the electrical signal received by the shielding ring is the same as the electrical signal received by the common voltage signal line.

[0027] In some embodiments, the light-emitting substrate further includes a buffer layer and an insulating layer. The buffer layer is located between the layer where the first conductive portion and the second conductive portion are located and the substrate, and the insulating layer is located on the side of the layer where the first conductive portion and the second conductive portion are located away from the substrate.

[0028] According to another aspect of the present disclosure, a backlight is provided, and the backlight includes the light-emitting substrate described in any one of the above embodiments.

[0029] According to still another aspect of the present disclosure, a display device is provided, and the display device includes the light-emitting substrate described in any one of the above embodiments.

[0030] According to a further aspect of the present disclosure, a method for manufacturing a light-emitting substrate is provided. The method includes supplying a substrate, forming a conductive layer on the substrate, and simultaneously forming a first conductive portion and a second conductive portion including a plurality of pads by patterning the conductive layer. The method further includes forming a plurality of light-emitting regions arranged in an array by attaching a plurality of driving circuits and a plurality of light-emitting units on the substrate, each of the plurality of light-emitting regions including a driving circuit and at least one light-emitting unit connected to the driving circuit. The first conductive portion is connected to the driving circuit and the at least one light-emitting unit within each light-emitting region.

Brief Description of the Drawings

[0031] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the embodiments are briefly described below. Obviously, the drawings described below are only examples of the embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0032] [Figure 1] FIG. 1 is an arrangement schematic diagram showing a light-emitting substrate according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a wiring schematic diagram showing a light-emitting substrate according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is an arrangement schematic diagram showing terminals of a driving circuit of the light-emitting substrate in FIG. 2. [Figure 4] FIG. 4 is an arrangement schematic diagram showing a first pad of the light-emitting substrate in FIG. 2. [Figure 5] FIG. 5 is a partial enlarged schematic diagram of FIG. 2. [Figure 6] FIG. 6 is a wiring schematic diagram showing a light-emitting substrate according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a wiring schematic diagram showing a light-emitting substrate according to another embodiment of the present disclosure. [Figure 8] FIG. 8 is an arrangement schematic diagram showing a first pad of the light-emitting substrate in FIG. 7. [Figure 9] Figure 9 is a partially enlarged schematic diagram of Figure 7. [Figure 10] Figure 10 is a partially enlarged schematic diagram of Figure 9. [Figure 11A] Figure 11A is a schematic diagram showing the arrangement of a flexible circuit board of a light-emitting substrate according to an embodiment of the present disclosure. [Figure 11B] Figure 11B is a magnified view of a portion of region I in Figure 11A. [Figure 12] Figure 12 is a schematic diagram showing the arrangement of the light-emitting unit of a light-emitting substrate according to an embodiment of the present disclosure. [Figure 13] Figure 13 is a schematic diagram showing the structure of a light-emitting substrate according to an embodiment of the present disclosure. [Figure 14] Figure 14 is a block diagram showing a backlight according to yet another embodiment of the present disclosure. [Figure 15] Figure 15 is a block diagram showing a display device according to a further embodiment of the present disclosure. [Figure 16] Figure 16 is a flowchart showing a method for manufacturing a light-emitting substrate according to a further embodiment of the present disclosure. [Modes for carrying out the invention]

[0033] The technical concepts of the embodiments of this disclosure will be described below clearly and completely with reference to the drawings of the embodiments of this disclosure. Clearly, the embodiments described are a part of the embodiments of this disclosure, but not all of them. Any other embodiments that a person skilled in the art can obtain based on the embodiments of this disclosure without requiring inventive work are all within the scope of this disclosure.

[0034] Embodiments of the present disclosure provide a light-emitting substrate, and Figure 1 shows a schematic arrangement diagram of the light-emitting substrate 100. As shown in Figure 1, the light-emitting substrate 100 comprises a substrate 101 and a first conductive portion 105 and a second conductive portion 106 disposed on the substrate 101. The substrate 101 includes a plurality of light-emitting regions 102 arranged in an array, and each light-emitting region 102 includes a drive circuit 103 and at least one light-emitting unit 104 connected to the drive circuit 103. The first conductive portion 105 is connected to the drive circuit 103 and the light-emitting unit 104 in each light-emitting region 102, and for example, the first conductive portion 105 may include a plurality of signal lines. In Figure 1, the dashed box on the left shows an enlarged schematic diagram of one light-emitting region 102. As shown in the enlarged schematic diagram, the second conductive portion 106 comprises a plurality of pads, which include, for example, a plurality of first pads 107 and a plurality of second pads 108. The drive circuit 103 is attached to the first pad 107, and the light-emitting unit 104 is attached to the second pad 108. The first conductive portion 105 and the second conductive portion 106 are located in the same layer. In this application, the term "A and B are located in the same layer" means that A and B are located on the surface of the same film layer and are in direct contact with that surface. In some embodiments, A and B are formed in the same film layer by the same process. In some embodiments, A and B are located on the surface of the same film layer and are in direct contact with that surface, and A and B have approximately the same height or thickness.

[0035] As should be understood, Figure 1 is merely a schematic representation of the connection relationship between the drive circuit 103 and the light-emitting unit 104 and the first conductive part 105 and the second conductive part 106. The dimensions of the drive circuit 103, the light-emitting unit 104, the first conductive part 105 and the second conductive part 106 are not depicted in proportion, and their relative positions do not necessarily perfectly correspond to their actual positions. In the drawing, proportions of certain areas and layers may be enlarged for clarity.

[0036] By positioning the first conductive portion 105 and the second conductive portion 106 on the same layer, the single-layer conductive layer not only manufactures the first pad 107 and the second pad 108 of the second conductive portion 106 and the wiring connecting the drive circuit 103 and the light-emitting unit 104, but also manufactures multiple signal lines of the first conductive portion 105 to transmit the corresponding electrical signals to the drive circuit 103 and the light-emitting unit 104 within each light-emitting region 102. In contrast, related technologies generally achieve the above electrical connection relationship with at least two conductive layers, namely the first conductive layer which manufactures the first and second pads, and the second conductive layer which is located on a different layer from the first conductive layer which manufactures the signal lines to transmit the corresponding electrical signals. The first conductive layer and the second conductive layer always inevitably overlap in the direction perpendicular to the substrate, but their overlapping region is a region with weak performance, so short circuits or open circuits are likely to occur between the first conductive layer and the second conductive layer, which affects the light-emitting performance of the light-emitting substrate. Furthermore, when manufacturing the first and second conductive layers located in different layers, it is necessary to use different masks, which significantly increases production costs. Compared to related technologies, the first conductive part 105 and the second conductive part 106 of this application are located in the same layer, and on the one hand, there is no overlap problem between the two conductive layers in a single conductive layer. Therefore, short circuits or open circuits due to overlap in the direction perpendicular to the substrate 101 of the first conductive part 105 and the second conductive part 106 can be completely avoided, thereby improving the light emission performance of the light-emitting substrate 100 and enhancing the light emission stability of the light-emitting substrate 100. On the other hand, in the manufacturing process, the first conductive part 105 and the second conductive part 106 can be formed simultaneously using the same material and the same process. Therefore, the number of masks used can be reduced, lowering production costs, and the manufacturing process can be simplified, improving production efficiency.

[0037] As shown in Figure 1, the multiple light-emitting regions 102 are arranged in M ​​rows along a first direction D1 and in N columns along a second direction D2 intersecting the first direction D1, where M and N are both positive integers of 1 or greater. The first direction D1 may be the vertical direction in the figure, the second direction D2 may be the horizontal direction in the figure, and the first direction D1 and the second direction D2 may be perpendicular to each other. The first conductive part 105 includes N drive voltage signal lines VLEDL and N common voltage signal lines GNDL extending along the first direction D1, thereby including one drive voltage signal line VLEDL and one common voltage signal line GNDL in each column's light-emitting region 001. In each column's light-emitting region 001, one drive voltage signal line VLEDL is connected to the first end of each light-emitting unit 104 within that column's light-emitting region 001, and one common voltage signal line GNDL is connected to each drive circuit 103 within that column's light-emitting region 001. The drive voltage signal line VLEDL is configured to supply a drive voltage to the light-emitting unit 104, and the common voltage signal line GNDL is configured to supply a common voltage (e.g., ground voltage) to the drive circuit 103. For example, if it is necessary to make a light-emitting unit 104 in a certain light-emitting region 102 light up, the drive voltage is increased and the common voltage is decreased to create a voltage difference on both sides of the light-emitting unit 104, thereby driving the light-emitting unit 104 to light up. In each row of light-emitting region 001, the drive voltage signal line VLEDL, the light-emitting unit 104, the drive circuit 103, and the common voltage signal line GNDL are arranged sequentially along the second direction D2. Taking the first column of light-emitting region 001 in Figure 1 as an example, each light-emitting unit 104 within the light-emitting region 001 of that column (i.e., light-emitting units 104 from rows 1 to M) is arranged in a light-emitting unit column, and each drive circuit 103 within the light-emitting region 001 of that column (i.e., drive circuits 103 from rows 1 to M) is arranged in a drive circuit column, and in the second direction D2, along the direction from left to right in the figure, the drive voltage signal line VLEDL, the light-emitting unit column, the drive circuit column, and the common voltage signal line GNDL are arranged in that order sequentially. In some embodiments, the orthographic projections of the drive voltage signal line VLEDL, the light-emitting unit column, the drive circuit column, and the common voltage signal line GNDL on the substrate 101 do not overlap with each other within the light-emitting region 001 of each column.This arrangement completely prevents short circuits or open circuits from occurring between the drive voltage signal line VLEDL and the common voltage signal line GNDL of the first conductive part 105 and the first pad 107 and the second pad 108 of the second conductive part 106, thereby improving the light emission performance of the light-emitting substrate 100 and enhancing the light emission stability of the light-emitting substrate 100.

[0038] The drive circuit 103 may be an integrated circuit, and in particular may be a package chip having multiple terminals. The drive circuit 103 may include one output terminal, or it may include at least two output terminals, for example, two output terminals, three output terminals, or four or more output terminals. The arrangement of each terminal of the drive circuit 103 in this application is optimized compared to related technologies, so that it can work well with the wiring of each signal line and prevent each signal line from overlapping in either a direction perpendicular to the substrate 101 or a direction parallel to the substrate 101.

[0039] The following describes some common characteristics of the light-emitting substrate 200 and the light-emitting substrate 300 with reference to Figures 2 and 7.

[0040] As shown in Figures 2 and 7, each drive circuit 103 comprises a plurality of terminals arranged in an array along a first direction D1 and a second direction D2, with the plurality of terminals arranged in at least two rows along the second direction D2. The plurality of terminals includes at least one output terminal Out and at least one common voltage terminal GND, with at least one output terminal Out and at least one common voltage terminal GND located in different rows of the plurality of terminals. Within the light-emitting region 001 of each row, at least one output terminal Out of each drive circuit 103 is connected in a one-to-one correspondence to the second end of at least one light-emitting unit 104 connected to the drive circuit 103, thereby transmitting a drive signal to at least one light-emitting unit 104, and at least one common voltage terminal GND of each drive circuit 103 is connected to a common voltage signal line GNDL, thereby receiving a common voltage (e.g., ground voltage) transmitted from the common voltage signal line GNDL.

[0041] The drive circuit 103 further includes an address terminal Di / Di_in, a relay terminal Out / Di_out, and a power supply terminal Pwr / Vcc. The drive circuits 103 in each light-emitting region 001 of each column are sequentially connected in series vertically. The address terminal Di / Di_in of the drive circuit 103 in the i-th stage is located on the side closer to the drive circuit 103 in the (i - 1)-th stage of the drive circuit 103 in the i-th stage, and the relay terminal Out / Di_out of the drive circuit 103 in the i-th stage is located on the side closer to the drive circuit 103 in the (i + 1)-th stage of the drive circuit 103 in the i-th stage, where 1 < i < M and i is a positive integer. In an embodiment of the present disclosure, the drive circuits 103 in each light-emitting region 001 of each column are sequentially connected in series vertically from bottom to top along the first direction D1. The drive circuit 103 in the i-th stage refers to the i-th drive circuit counted from the drive circuit 103 in the M-th row in each light-emitting region 001 of each column upward. For example, taking the light-emitting region 001 in the first column as an example, the drive circuit 103 located in the M-th row of the first column is the drive circuit in the first stage, the drive circuit 103 located in the (M - 1)-th row of the first column is the drive circuit in the second stage, and by analogy, the drive circuit 103 located in the second row of the first column is the drive circuit in the (M - 1)-th stage, and the drive circuit 103 located in the first row of the first column is the drive circuit in the M-th stage. In the drive circuit 103 shown in FIG. 2, the address terminal is Di, the relay terminal is Out, and the power supply terminal is Pwr. In this drive circuit 103, the output terminal Out is reused as the relay terminal, that is, the output terminal Out and the relay terminal are the same terminal, and the output terminal Out outputs different signals in different time periods. For example, it outputs a relay signal as the relay terminal and a drive signal as the output terminal. In the drive circuit 103 shown in FIG. 7, the address terminal is Di_in, the relay terminal is Di_out, and the power supply terminal is Vcc. In this drive circuit 103, the output terminal Out and the relay terminal Di_out are two different terminals. The address terminal Di / Di_in is configured to receive an address signal, the relay terminal Out / Di_out is configured to output a relay signal, and the power supply terminal Pwr / Vcc is configured to receive a power supply voltage signal.Multiple terminals of the drive circuit 103 are arranged in first and second rows along the second direction D2, with the terminals of the first row of the drive circuit 103 located on the side adjacent to the drive voltage signal line VLEDL of the drive circuit 103 (i.e., on the left side of the drive circuit 103) and the terminals of the second row of the drive circuit 103 located on the side adjacent to the common voltage signal line GNDL of the drive circuit 103 (i.e., on the right side of the drive circuit 103). This arrangement of the terminals of the drive circuit 103 helps to streamline and arrange each signal wiring, ensuring that each signal wire does not overlap with each other, thereby avoiding short circuits / open circuits or signal crosstalk caused by overlapping signal wiring.

[0042] As shown in Figures 2 and 7, the first conductive portion 105 further includes N address signal lines ADDRL extending along the first direction D1, and each column of light-emitting region 001 includes one address signal line ADDRL. Figures 2 and 7 show only the case where the light-emitting substrate includes four light-emitting regions 102 and the four light-emitting regions 102 are arranged in a 2x2 configuration, but this is only a screenshot of a part of the light-emitting substrate, and in reality, the light-emitting substrate generally includes multiple light-emitting regions 102, which are arranged in M ​​rows and N columns, where M and N are any positive integers greater than or equal to 1. Accordingly, each column of light-emitting region 001 includes multiple drive circuits 103, and these multiple drive circuits 103 are sequentially cascaded together by cascaded connection wiring 111 extending along the first direction D1. The address signal line ADDRL is connected to the address terminal Di / Di_in of the first stage drive circuit 103, and the relay terminal Out / Di_out of the preceding drive circuit is connected to the address terminal Di / Di_in of the next stage drive circuit 103 via the cascading connection wiring 111. In the example in Figure 2, two drive circuits 103 are included in the light-emitting area 001 of each column, and these two drive circuits 103 are sequentially cascaded together by the cascading connection wiring 111 extending along the first direction D1. The address signal line ADDRL is connected to the address terminal Di of the first stage drive circuit 103, and the relay terminal Out of the first stage drive circuit is connected to the address terminal Di of the second stage drive circuit 103 via the cascading connection wiring 111. In the example in Figure 7, two drive circuits 103 are included in the light-emitting area 001 of each column, and these two drive circuits 103 are sequentially cascaded together by the cascading connection wiring 111 extending along the first direction D1. The address signal line ADDRL is connected to the address terminal Di_in of the first-stage drive circuit 103, and the relay terminal Di_out of the first-stage drive circuit is connected to the address terminal Di_in of the second-stage drive circuit 103 via the cascaded connection wiring 111.

[0043] The address signal line ADDRL is configured to transmit an address signal to the address terminal Di / Di_in of the first-stage drive circuit 103 within the light-emitting area 001 of each column. After receiving the address signal, the first-stage drive circuit 103 can analyze, acquire, and store the address information in the address signal as its own address information. It can also modulate the incremented address information (new address information) into a relay signal by gradually increasing it by 1 or by another fixed amount. The relay terminal Out / Di_out of the first-stage drive circuit 103 transmits this relay signal to the address terminal Di / Di_in of the second-stage drive circuit 103 as its address information via the cascaded connection wiring 111. Naturally, the first-stage drive circuit 103 generates a relay signal by further converting its address information using any other appropriate function. The second-stage drive circuit 103 transmits a relay signal to the third-stage drive circuit 103 as address information for the third-stage drive circuit 103 using a similar method, and this is how it is inferred. Using this method, it is possible to set corresponding address information for each of the multiple drive circuits 103 that are cascaded within the light-emitting area 001 of each row. As can be seen from the above, for one row of light-emitting area 001, by supplying only one address signal via a single address signal line ADDRL, all the drive circuits 103 within the light-emitting area 001 of that row can acquire their respective address information. In this way, the number of signal lines is greatly reduced, saving wiring space and simplifying the control method.

[0044] As shown in Figures 2 and 7, the first conductive portion 105 further includes N feedback signal lines FBL extending along the first direction D1, and each column's light-emitting region 001 includes one feedback signal line FBL. Within each column's light-emitting region 001, the feedback signal line FBL is connected to the relay terminal Out / Di_out of the final stage drive circuit 103. The feedback signal line FBL is positioned on the side of the common voltage signal line GNDL that is away from the drive circuit 103, bypassing the common voltage signal line GNDL within the column's light-emitting region 001.

[0045] The first conductive portion 105 further includes N power signal lines PwrL / VccL, and each row of light-emitting region 001 includes one power signal line PwrL / VccL. Each power signal line PwrL / VccL includes a main body portion and a first connection portion 118, and the main body portion of the power signal line PwrL / VccL extends along the first direction D1. Within each row's light-emitting region 001, a single power signal line PwrL / VccL is connected by a first connection part 118 to the power terminals Pwr / Vcc of all drive circuits 103 within that row's light-emitting region 001. The orthographic projections of the first row terminals and the second row terminals of each drive circuit 103 on the substrate 101 are located on either side of the orthographic projection of the power signal line PwrL / VccL on the substrate 101. In other words, the power signal line PwrL / VccL is positioned within the region occupied by each drive circuit 103 and does not overlap with the first and second row terminals of each drive circuit 103. By positioning the power signal line PwrL / VccL within each row's light-emitting region 001 within the region occupied by each drive circuit 103, wiring space can be saved and overlap between the power signal line PwrL / VccL and other signal lines can be avoided.

[0046] In the embodiments of this disclosure, a signal line generally includes a main body portion and a connection portion. The main body portion limits the main direction of extension of the signal line, while the connection portion connects the signal line to necessary components. For example, the drive voltage signal line VLEDL is connected to the second end of the light-emitting unit 104 by its connection portion, the power signal line PwrL / VccL is connected to the power terminal Pwr / Vcc of the drive circuit 103 by the first connection portion 118, and the common voltage signal line GNDL is connected to the common voltage terminal GND of the drive circuit 103 by its connection portion. The connection portion of each signal line occupies a smaller area in terms of length or width compared to its main body portion. Therefore, in this specification, the phrase "X signal line extending along the first direction D1" limits the main body portion of the X signal line to extending along the first direction D1, but does not limit the connection portion of the X signal line to extending along the first direction D1. For example, the main body of each power signal line PwrL / VccL extends along the first direction D1, while its first connection portion 118 does not extend along the first direction D1 but extends along a direction intersecting the first direction D1 (for example, the second direction D2).

[0047] In each row of light-emitting region 001, the power signal lines PwrL / VccL are configured to transmit a power voltage signal to the power terminals Pwr / Vcc of each drive circuit 103, thereby supplying power voltage to each drive circuit 103. In one example, the power voltage signal is a power line carrier communication signal. In such a case, the power signal lines PwrL / VccL can not only supply power voltage to each drive circuit 103, but can also supply communication data to each drive circuit 103, which may be used to control the illumination time of at least one light-emitting unit 104 connected to the drive circuit 103, and further to control its visual illumination brightness. The power line carrier communication signal includes information corresponding to the communication data. For example, the communication data may be data indicating the illumination time and further representing the required illumination brightness. Compared to the normal Serial Peripheral Interface (SPI) protocol, the embodiments of this disclosure effectively reduce the number of signal lines by overlaying the communication data on the power signal lines PwrL / VccL using the Power Line Carrier Communication (PLC) protocol.

[0048] As can be seen from the examples in Figures 2 and 7, the terminals of the drive circuit 103 are arranged in the manner described above, so that the orthographic projections of the drive voltage signal line VLEDL, address signal line ADDRL, cascaded connection wiring 111, power signal line PwrL / VccL, common voltage signal line GNDL, and feedback signal line FBL of the first conductive part 105 do not overlap on the substrate 101 within the light-emitting region 001 of each row. In addition, the orthographic projections of the drive voltage signal line VLEDL, common voltage signal line GNDL, and feedback signal line FBL of the first conductive part 105 on the substrate 101 do not overlap with the orthographic projections of the first pad 107 and second pad 108 of the second conductive part 106 on the substrate 101. As a result, short circuits or open circuits due to overlap of the first conductive part 105 and the second conductive part 106 located on the same layer can be completely avoided, thereby improving the light-emitting performance of the light-emitting substrate and enhancing the light-emitting stability of the light-emitting substrate.

[0049] The above describes some common characteristics of the light-emitting substrate 200 and the light-emitting substrate 300. Below, we will explain the specific arrangement methods for the light-emitting substrate 200 and the light-emitting substrate 300, respectively, using two examples.

[0050] Figure 2 shows the arrangement of the light-emitting substrate 200. Figure 2 shows only four light-emitting regions 102, which are arranged in a 2x2 configuration. However, this is only a screenshot of a part of the light-emitting substrate 200, and the light-emitting substrate 200 may contain any appropriate number of light-emitting regions 102, and these appropriate number of light-emitting regions 102 may be arranged in multiple rows and multiple columns. The embodiments of this disclosure do not specifically limit the number of light-emitting regions 102 included in the light-emitting substrate 200. As shown, each light-emitting region 102 includes one drive circuit 103 and one light-emitting unit 104 connected to the drive circuit 103. Figure 3 shows the arrangement of the terminals of the drive circuit 103.

[0051] As shown in Figures 2 and 3, each drive circuit 103 has four terminals, which are the address terminal Di, the power supply terminal Pwr, the common voltage terminal GND, and the output terminal Out. The output terminal Out and the address terminal Di are the first row of terminals of the drive circuit 103, located on the side adjacent to the drive voltage signal line VLEDL of the drive circuit 103 (i.e., on the left side of the drive circuit 103), while the common voltage terminal GND and the power supply terminal Pwr are the second row of terminals of the drive circuit 103, located on the side adjacent to the common voltage signal line GNDL of the drive circuit 103 (i.e., on the right side of the drive circuit 103). The address terminal Di and the power supply terminal Pwr are located in the second row of multiple terminals, and the common voltage terminal GND and the output terminal Out are located in the first row of multiple terminals. As described above, the output terminal Out is reused as a relay terminal, and within the light-emitting region 001 of each row, one end of the output terminal Out of the first-stage drive circuit 103 (i.e., the drive circuit 103 located in the second row and first column in Figure 2) is connected to the light-emitting unit 104 corresponding to the drive circuit 103, and the other end is connected to the address terminal Di of the second-stage drive circuit 103 (i.e., the drive circuit 103 located in the first row and first column in Figure 2) via the cascading connection wiring 111. One end of the output terminal Out of the second-stage drive circuit 103 is connected to the light-emitting unit 104 corresponding to the drive circuit 103, and the other end is connected to the feedback wiring FBL. The output terminal Out can output different signals in different time periods. For example, the output terminal Out of the drive circuit 103 outputs a relay signal in one time period as the address signal of the next-stage drive circuit 103 cascaded to the drive circuit 103, and in another time period supplies a drive signal to the light-emitting unit 104 connected to the drive circuit 103, thereby causing the light-emitting unit 104 to emit light. The aforementioned one time period and another time period are two independent time periods, for example, the other time period follows the aforementioned one time period. The drive signal may be, for example, a drive current, and is intended to drive the light-emitting unit 104 to emit light. When the drive signal is a drive current, the drive current may flow from the output terminal Out to the light-emitting unit 104, or from the light-emitting unit 104 to the output terminal Out, and the direction of the drive current flow may be determined according to actual needs, and the embodiments of this disclosure are not limited thereto.

[0052] The spacing between each terminal of the drive circuit 103 of the light-emitting substrate 200 is generally determined by many factors (e.g., process limit capability, line width requirements between two rows of terminals, electrical design requirements, etc.), and the embodiments of this disclosure do not specifically limit this. For example, the spacing between the terminals of the first row and the terminals of the second row may be 70 to 300 μm, and the spacing between the terminals of the first row and the terminals of the second row may be 70 to 300 μm. As shown in Figure 3, in one example, the spacing S1 between the terminals of the first row and the terminals of the second row is 140 μm, and the spacing S2 between the terminals of the first row and the terminals of the second row is 120 μm. That is, the spacing between the output terminal Out and the common voltage terminal GND is 140 μm, the spacing between the address terminal Di and the power supply terminal Pwr is 140 μm, the spacing between the output terminal Out and the address terminal Di is 120 μm, and the spacing between the common voltage terminal GND and the power supply terminal Pwr is 120 μm. The four terminals of the drive circuit 103 occupy approximately the same area and have approximately the same length and width. The width S3 of each terminal along the second direction D2 is 80 μm, and the length S4 of each terminal along the first direction D1 is 100 μm. The distance S5 between the terminals of the second row and the first side surface of the drive circuit 103 (i.e., the lower edge of the drive circuit 103) is 25 μm, that is, the distance S5 between the address terminal Di and the power supply terminal Pwr and the lower edge of the drive circuit 103 is both 25 μm. The distance S5 between the terminals of the first row and the second side surface of the drive circuit 103 (i.e., the upper edge of the drive circuit 103) is 25 μm, that is, the distance S5 between the output terminal Out and the common voltage terminal GND and the upper edge of the drive circuit 103 is both 25 μm. The distance S6 between the terminals of the first row and the third side of the drive circuit 103 (i.e., the left edge of the drive circuit 103) is 25 μm, meaning that the distance S6 between the output terminal Out and the address terminal Di and the left edge of the drive circuit 103 is both 25 μm. The distance S6 between the terminals of the second row and the fourth side of the drive circuit 103 (i.e., the right edge of the drive circuit 103) is 25 μm, meaning that the distance S6 between the common voltage terminal GND and the power supply terminal Pwr and the right edge of the drive circuit 103 is both 25 μm. As can be seen from this, the length L of the drive circuit 103 along the first direction D1 is 370 μm, and the width W of the drive circuit 103 along the second direction D2 is 350 μm.Within the light-emitting region 001 of each row, the distance between the power signal line PwrL and the terminals of the first and second rows may be 10 to 100 μm, respectively. In one example, the width of the power signal line PwrL along the second direction D2 between the terminals of the first and second rows is 40 μm or more.

[0053] In the example shown in Figure 2, each column of the light-emitting region 001 includes the drive voltage signal line VLEDL, the address signal line ADDRL, the cascading connection wiring 111, the power signal line PwrL, the common voltage signal line GNDL, and the feedback signal line FBL. These signal lines do not overlap each other in either the direction perpendicular to the substrate 101 or the direction parallel to the substrate 101. The roles and arrangement of these signal lines are as described above, and for the sake of brevity, a detailed explanation is omitted here.

[0054] The operation method of the light-emitting substrate 200 in Figure 2 will be briefly explained below.

[0055] When the drive circuit 103 starts operating, it first completes initialization by supplying a power supply voltage to the power supply terminal Pwr of each drive circuit 103 within the light-emitting area 001 of each row via the power supply signal line PwrL, and in this way the drive circuit 103 is energized.

[0056] Next, an address writing operation is performed within the first time zone, that is, the ADDRL signal line inputs the address signal to the first stage drive circuit 103 via the address terminal Di, thereby writing the address.

[0057] Next, in the second time zone, the drive settings are configured, and the first-stage drive circuit 103 outputs a relay signal via its output terminal Out. This relay signal is then transmitted via the cascaded connection wiring 111 to the address terminal Di of the second-stage drive circuit 103 as its address signal. This process continues until all drive circuits 103 have completed setting their address information.

[0058] Subsequently, in the third time zone, a drive voltage is supplied to the drive voltage signal line VLEDL. For example, the third time zone is entered after all of the drive circuits 103 have acquired the corresponding address information. At this time, the drive voltage transmitted in the drive voltage signal line VLEDL becomes high level.

[0059] Next, in the fourth time zone, the output terminal Out of each drive circuit 103 is supplied with a drive signal (for example, a drive current) based on the required illumination time. At this time, the drive voltage signal line VLEDL, the light-emitting unit 104, the output terminal Out electrically connected to the light-emitting unit 104, and the common voltage signal line GNDL constitute a signal circuit, and the light-emitting unit 104 illuminates based on the required illumination time.

[0060] Finally, in the fifth time zone, the system is shut down, meaning the drive circuit 103 is powered off, the drive voltage supplied by the drive voltage signal line VLEDL becomes low, and the light-emitting unit 104 stops emitting light.

[0061] The light-emitting substrate 200 shown in Figure 2 can achieve region-specific dimming. The light-emitting substrate 200 includes multiple light-emitting regions 102, and each light-emitting region includes one drive circuit 103 and one light-emitting unit 104 connected to and controlled by the drive circuit 103, so that the light-emitting brightness of each light-emitting unit 104 can be controlled independently. For example, by setting the address signal and power supply voltage signal supplied to each drive circuit 103, the light-emitting time of each light-emitting unit 104 connected to each drive circuit 103 can be controlled, and the visual light-emitting brightness can be controlled. The light-emitting substrate 200 can achieve region-specific independent control of light-emitting brightness and has a wide range of applications. Moreover, the number of ports in each drive circuit 103 is small, the number of required control signals is small, and therefore the control method is simple, power consumption is low, and it is easy to operate. The light-emitting substrate 200 has a high degree of integration and can achieve high contrast display in cooperation with a liquid crystal display device.

[0062] Figure 4 shows the arrangement of the first pad 107 and its surrounding wiring. The drive circuit 103 shown in Figure 2 is attached to the first pad 107 and is electrically connected to the drive circuit 103. Four sub-pads are installed on the first pad 107 at positions corresponding to the four terminals of the drive circuit 103. These are the first sub-pad for attaching the address terminal Di, the second sub-pad for attaching the power terminal Pwr, the third sub-pad for attaching the common voltage terminal GND, and the fourth sub-pad for attaching the output terminal Out. The first sub-pad is connected to the address terminal Di of the drive circuit 103, the second sub-pad is connected to the power terminal Pwr of the drive circuit 103, the third sub-pad is connected to the common voltage terminal GND of the drive circuit 103, and the fourth sub-pad is connected to the output terminal Out of the drive circuit 103. The first sub-pad is connected to the address signal line ADDRL, thereby transmitting the address signal on the address signal line ADDRL to the address terminal Di. The second sub-pad is connected to the power signal line PwrL, thereby transmitting the power voltage signal on the power signal line PwrL to the power terminal Pwr. The third sub-pad is connected to the common voltage signal line GNDL, thereby transmitting the common voltage signal on the common voltage signal line GNDL to the common voltage terminal GND. One end of the fourth sub-pad is connected to the cascading connection wiring 111, so that within one time period the relay signal is output as the address signal for the next stage drive circuit 103 which is cascaded to the drive circuit 103, and the other end of the fourth sub-pad is connected to wiring 109, so that within another time period the drive signal is transmitted via wiring 109 to the light-emitting unit 104 which is connected to the drive circuit 103.

[0063] Figure 5 is a schematic partial view of Figure 2, showing two rows of light-emitting regions 001. Within each row of light-emitting region 001, four second pads 108 are sequentially connected in series to the first pad 107. Within each row of light-emitting region 001, the address signal line ADDRL, power signal line PwrL, common voltage signal line GNDL, and feedback signal line FBL are shown, but the drive voltage signal line VLEDL is not shown. However, as described above, although not shown, each row of light-emitting region 001 includes the drive voltage signal line VLEDL. As shown in the figure, the end of the address signal line ADDRL in the first row of light-emitting region 001 that is close to the first pad 107 is on almost the same plane as the end of the address signal line ADDRL in the second row of light-emitting region 001 that is close to the first pad 107, that is, the address signal line ADDRL in the first row of light-emitting region 001 has approximately the same length as the address signal line ADDRL in the second row of light-emitting region 001, and the end of the power signal line PwrL in the first row of light-emitting region 001 that is close to the first pad 107 is on almost the same plane as the end of the power signal line PwrL in the second row of light-emitting region 001 that is close to the first pad 107, that is, the power signal line PwrL in the first row of light-emitting region 001 has approximately the same length as the power signal line PwrL in the second row of light-emitting region 001, and the first row The end of the common voltage signal line GNDL in the first row of the light-emitting region 001 that is close to the first pad 107 is on approximately the same plane as the end of the common voltage signal line GNDL in the second row of the light-emitting region 001 that is close to the first pad 107, that is, the common voltage signal line GNDL in the first row of the light-emitting region 001 has approximately the same length as the common voltage signal line GNDL in the second row of the light-emitting region 001, and the end of the feedback signal line FBL in the first row of the light-emitting region 001 that is close to the first pad 107 is on approximately the same plane as the end of the feedback signal line FBL in the second row of the light-emitting region 001 that is close to the first pad 107, that is, the feedback signal line FBL in the first row of the light-emitting region 001 has approximately the same length as the feedback signal line FBL in the second row of the light-emitting region 001. Although not shown in the diagram, the end of the drive voltage signal line VLEDL in the first row of light-emitting region 001 that is close to the first pad 107 is on almost the same plane as the end of the drive voltage signal line VLEDL in the second row of light-emitting region 001 that is close to the first pad 107, that is, the drive voltage signal line VLEDL in the first row of light-emitting region 001 has approximately the same length as the drive voltage signal line VLEDL in the second row of light-emitting region 001.When the light-emitting substrate 200 includes N rows of light-emitting regions 001, the uniformity of each row of light-emitting regions 001 is maintained by ensuring that the same signal lines within each row of light-emitting region 001 are of approximately the same length. Here, "the same signal lines within each row of light-emitting region 001" refers to signal lines that perform the same role within each row of light-emitting region 001. For example, the drive voltage signal line VLEDL within the first row of light-emitting region 001 to the Nth row of light-emitting region 001 is the same signal line. This arrangement makes it possible to ensure that the same signal lines within each row of light-emitting region 001 are of approximately the same length, and therefore the signal lines within each row of light-emitting region 001 have approximately the same resistance and voltage drop, thereby providing relatively high brightness uniformity between each row of light-emitting region 001.

[0064] The light-emitting substrate 200 may also be provided with a shielding ring GND ESD Ring, which is shown in Figure 6. The shielding ring GND ESD Ring surrounds the outer periphery of multiple light-emitting regions 102, thereby performing an electrostatic shielding effect. The electrical signals received by the shielding ring GND ESD Ring are the same as the electrical signals received by the common voltage signal line GNDL. For example, if both the shielding ring GND ESD Ring and the common voltage signal line GNDL are connected to the binding electrodes of the binding region, and the binding electrodes connected to the shielding ring GND ESD Ring and the binding electrodes connected to the common voltage signal line GNDL have the same definition, the electrical signals received by the shielding ring GND ESD Ring are made the same as the electrical signals received by the common voltage signal line GNDL. The shielding ring GND ESD Ring may be located on the same layer as the first conductive part 105 and the second conductive part 106. The shape of the shielding ring GND ESD Ring is not limited to the shape shown in Figure 6, but may have any suitable shape as long as it performs an electrostatic shielding effect on the light-emitting regions 102. In one example, the width of the shielding ring GND ESD Ring is 200 μm or more.

[0065] Figure 7 shows the light-emitting substrate 300, and Figure 8 shows the arrangement of the terminals of the drive circuit 103 of the light-emitting substrate 300. Since the light-emitting substrate 300 shown in Figure 7 has almost the same structure as the light-emitting substrate 200 shown in Figure 2, the same drawing symbols are used to indicate the same components. Therefore, for detailed roles and functions of components in Figure 7 that have the same drawing symbols as in Figure 2, refer to the explanation in Figure 2. A detailed explanation is omitted here, and for the sake of brevity, the main differences will be discussed below.

[0066] Referring to Figures 7 and 8, the difference between the light-emitting substrate 300 in Figure 7 and the light-emitting substrate 200 in Figure 2 is that the drive circuit 103 of the light-emitting substrate 300 in Figure 7 has more terminals, there are multiple output terminals Out, and there is at least one common voltage terminal GND. Figure 7 shows the case where there are four output terminals Out and two common voltage terminals GND, but this is just one example. The number of output terminals Out may be more than four or less than four, and the number of common voltage terminals GND may be more than two or less than two. In the embodiments of this disclosure, there are at least two output terminals Out and at least one common voltage terminal GND. The drive circuit 103 also further includes a data terminal Data. As shown in Figures 7 and 8, the drive circuit 103 has two rows of terminals. The first row of terminals includes the power supply terminal Vcc and four output terminals Out1, Out2, Out3, and Out4, and is located on the side adjacent to the drive voltage signal line VLEDL of the drive circuit 103 (i.e., on the left side of the drive circuit 103). The second row of terminals includes the address terminal Di_in, the relay terminal Di_out, the data terminal Data, and two common voltage terminals GND, and is located on the side adjacent to the common voltage signal line GNDL of the drive circuit 103 (i.e., on the right side of the drive circuit 103). The multiple terminals of the drive circuit 103 are arranged in five rows, with the address terminal Di_in located in the fifth row of the multiple terminals and the relay terminal Di_out located in the first row of the multiple terminals. Figure 8 shows a case where the power terminal Vcc is located in the third row of the first column and the data terminal Data is located in the second row of the second column. However, this is merely an example, and the embodiments of this disclosure do not limit the specific position of the power terminal Vcc in the first column and the specific position of the data terminal Data in the second column. For example, the power terminal Vcc may be located in any of the first to fifth rows of the first column, and the data terminal Data may be located in any of the second to fourth rows of the second column.

[0067] As shown in the figure, the four output terminals Out1, Out2, Out3, and Out4 of the drive circuit 103 are connected one-to-one to the second terminals of the four light-emitting units 104, thereby supplying drive signals to the light-emitting units 104. In the example of Figure 7, the output terminals and relay terminals of the drive circuit 103 are different terminals. The drive circuit 103 is configured to output a relay signal via the relay terminal Di_out as an address signal for the next stage drive circuit 103 which is cascaded to the drive circuit 103 within one time period, and to supply drive signals to the four light-emitting units 104 via the four output terminals Out1, Out2, Out3, and Out4 within another time period. The one time period and the other time period are two independent time periods, for example, the other time period follows the one time period. The drive signal may be, for example, a drive current, and is intended to drive the light-emitting units 104 to emit light. Furthermore, if the drive signal is a drive current, the drive current may flow from the output terminals Out1, Out2, Out3, and Out4 to the light-emitting unit 104, or from the light-emitting unit 104 to the output terminals Out1, Out2, Out3, and Out4. The direction of the drive current flow may be determined according to actual needs, and the embodiments of this disclosure are not limited thereto.

[0068] Figure 7 shows only four light-emitting regions 102, arranged in a 2x2 configuration. However, this is merely a screenshot of a portion of the light-emitting substrate 300. The light-emitting substrate 300 may contain any appropriate number of light-emitting regions 102, and these may be arranged in M ​​rows and N columns, where M and N are any positive integers greater than or equal to 1. The embodiments of this disclosure do not specifically limit the number of light-emitting regions 102 included in the light-emitting substrate 300.

[0069] As described above, each column's light-emitting region 001 includes a drive voltage signal line VLEDL, an address signal line ADDRL, a cascaded connection wiring 111, a power signal line VccL, a common voltage signal line GNDL, and a feedback signal line FBL, all extending along the first direction D1, and their orthographic projections on the substrate 101 do not overlap. The roles and arrangement of these signal lines are as described above, and for the sake of brevity, a detailed explanation is omitted here. In addition, each column's light-emitting region 001 further includes one data drive signal line DataL. Each data drive signal line DataL includes a main body and a second connection part 119, with the main body of the data drive signal line DataL extending along the first direction D1. In each row's light-emitting region 001, one data drive signal line DataL is connected by a second connection part 119 to the data terminal Data of all drive circuits 103 within the row's light-emitting region 001, and the orthographic projections of the first row terminals and the second row terminals of each drive circuit 103 on the substrate 101 are located on either side of the orthographic projection of the data drive signal line DataL on the substrate 101, that is, the data drive signal line DataL is located within the region occupied by each drive circuit 103 and does not overlap with the first row terminals and the second row terminals of each drive circuit 103. The orthographic projection of the data drive signal line DataL on the substrate 101 also does not overlap with the orthographic projection of the power signal line VccL within the row's light-emitting region 001 on the substrate 101. By arranging the data drive signal lines DataL within the light-emitting region 001 of each row within the region occupied by each drive circuit 103, wiring space can be saved and overlap between the data drive signal lines DataL and other signal lines can be avoided.

[0070] In each row of light-emitting region 001, a single data drive signal line DataL is configured to supply drive data to the data terminal Data of each drive circuit 103. Multiple different drive data may be loaded onto the data drive signal line DataL. Each drive circuit 103 determines the corresponding drive data based on its address information and drives the light-emitting unit 104 connected to it based on the corresponding drive data. In this embodiment of the disclosure, by transmitting drive data to the data terminal Data of the drive circuit 103 via the data drive signal line DataL, the problem of having too many pads and wires due to data transmission via SPI (Serial Peripheral interface) can be avoided, and the structure of the light-emitting substrate 300, external circuitry, and drive circuit 103 can be simplified.

[0071] The spacing between terminals of the drive circuit 103 of the light-emitting substrate 300 is generally determined by many factors (e.g., process limit capability, line width requirements between two rows of terminals, electrical design requirements, etc.), and the embodiments of this disclosure do not specifically limit this. For example, the spacing between the terminals of the first row and the terminals of the second row may be 70 to 500 μm, and the spacing between terminals of any two adjacent rows of five rows may be 70 to 500 μm. As shown in Figure 8, in one example, the spacing S1 between the terminals of the first row and the terminals of the second row is 210 μm, and the spacing S2 between terminals of any two adjacent rows is 90 μm. Specifically, the distance between the first output terminal Out1 and the relay terminal Di_out, the distance between the second output terminal Out2 and the data terminal Data, the distance between the power supply terminal Vcc and the common voltage terminal GND, the distance between the third output terminal Out3 and the common voltage terminal GND, and the distance between the fourth output terminal Out4 and the address terminal Di_in are all S1, which is 210 μm, and the distance between the first output terminal Out1 and the second output terminal Out2, the distance between the second output terminal Out2 and the power supply terminal Vcc, the distance between the power supply terminal Vcc and the third output terminal Out3, the distance between the third output terminal Out3 and the fourth output terminal Out4, the distance between the relay terminal Di_out and the data terminal Data, the distance between the data terminal Data and the common voltage terminal GND, the distance between the common voltage terminal GND and the adjacent common voltage terminal GND, and the distance between the common voltage terminal GND and the address terminal Di_in are all S2, which is 90 μm. The ten terminals of the drive circuit 103 occupy approximately the same area and have approximately the same length and width. The width S3 of each terminal along the second direction D2 is 110 μm, and the length S4 of each terminal along the first direction D1 is 100 μm. The distance S5 between the terminals of the 5th row and the first side surface of the drive circuit 103 (i.e., the lower edge of the drive circuit 103) is 35 μm, that is, the distance S5 between the 4th output terminal Out4 and the address terminal Di_in and the lower edge of the drive circuit 103 is both 35 μm, and the distance S5 between the terminals of the 1st row and the second side surface of the drive circuit 103 (i.e., the upper edge of the drive circuit 103) is 35 μm, that is, the distance S5 between the 1st output terminal Out1 and the relay terminal Di_out and the upper edge of the drive circuit 103 is both 35 μm.The distance S6 between the terminals of the first row and the third side of the drive circuit 103 (i.e., the left edge of the drive circuit 103) is 25 μm, and the distance S6 between the terminals of the second row and the fourth side of the drive circuit 103 (i.e., the right edge of the drive circuit 103) is 25 μm. As can be seen from this, the length L of the drive circuit 103 along the first direction D1 is 930 μm, and the width W of the drive circuit 103 along the second direction D2 is 480 μm. Within the light-emitting region 001 of each row, the distance between the power signal line VccL and the terminals of the first and second rows may be 10 to 100 μm, and the distance between the data drive signal line DataL and the terminals of the first and second rows may be 10 to 100 μm. In one example, the width of the power signal line VccL and the data drive signal line DataL along the second direction D2 between the terminals of the first and second rows is 40 μm or more.

[0072] The single drive circuit 103 shown in Figure 7 has four output terminals, and therefore, one drive circuit 103 may be connected to four light-emitting units 104 simultaneously, thereby significantly reducing the amount of drive circuit 103 used and lowering the cost of the light-emitting substrate 300. Not only that, but because the amount of drive circuit 103 used is reduced, the difficulty of manufacturing the light-emitting substrate 300 is lowered, the impact of the binding yield of the drive circuit 103 on the yield of the light-emitting substrate 300 is mitigated, and the yield of the light-emitting substrate 300 can be further improved. In addition, by using the arrangement method described above for the terminals of the drive circuit 103, the orthographic projections of the drive voltage signal line VLEDL, address signal line ADDRL, cascaded connection wiring 111, power signal line VccL, data drive signal line DataL, common voltage signal line GNDL, and feedback signal line FBL of the first conductive part 105 on the substrate 101 can be prevented from overlapping with each other in the light-emitting region 001 of each row. In addition, the orthographic projections of the drive voltage signal line VLEDL, common voltage signal line GNDL, and feedback signal line FBL of the first conductive part 105 on the substrate 101 do not overlap with the orthographic projections of the first pad 107 and second pad 108 of the second conductive part 106 on the substrate 101. This completely avoids short circuits or open circuits caused by overlap between the first conductive part 105 and the second conductive part 106, thereby improving the light emission performance of the light-emitting substrate 300 and enhancing the light emission stability of the light-emitting substrate 300.

[0073] The following briefly describes the operation process of the light-emitting substrate 300 shown in Figure 7.

[0074] When the drive circuit 103 starts operating, it first completes initialization by supplying a power supply voltage to the power supply terminal Vcc of each drive circuit 103 within the light-emitting area 001 of each row via the power supply signal line VccL, and in this way the drive circuit 103 is energized.

[0075] Next, an address writing operation is performed within the first time zone, that is, the ADDRL signal line inputs the address signal to the first-stage drive circuit 103 via the address terminal Di_in, thereby writing the address. Furthermore, the first-stage drive circuit 103 outputs a relay signal via the relay terminal Di_out, and this relay signal is transmitted to the address terminal Di_in of the second-stage drive circuit 103 as the address signal for the second-stage drive circuit 103 via the cascaded connection wiring 111. This process is carried out in this manner until all drive circuits 103 have completed setting their address information.

[0076] Next, the drive settings are configured within the second time zone, and the initialization settings are performed by each data drive signal line DataL transmitting a drive data signal to the data terminal Data of each drive circuit 103 within the light-emitting area 001 of each row.

[0077] Subsequently, within the third time zone, a drive voltage is supplied to the drive voltage signal line VLEDL, and at this time, the drive voltage transmitted on the drive voltage signal line VLEDL becomes high level.

[0078] Next, within the fourth time zone, each drive circuit 103 generates a drive control signal that corresponds one-to-one to its respective output terminal based on the received drive data, and the drive control signal controls the current flowing through the corresponding output terminal. In this way, the drive circuit 103 controls the current flowing through the light-emitting unit 104 by the action of the drive voltage loaded onto the drive voltage signal line VLEDL, thereby achieving the objective of driving each light-emitting unit 104 connected by the drive circuit 103.

[0079] Finally, within the fifth time zone, the system is shut down, meaning the drive circuit 103 is powered off, the drive voltage supplied by the drive voltage signal line VLEDL becomes low, and the light-emitting unit 104 stops emitting light.

[0080] The light-emitting substrate 300 shown in Figure 7 can achieve region-specific dimming. Each drive circuit 103 is equipped with four output terminals Out1, Out2, Out3, and Out4. The drive circuit 103 further comprises a logic control module CTR and a control module CLM (not shown), the logic control module CTR including four modulation modules, namely the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, and the fourth modulation module PWMM4. The first output terminals Out1 to the fourth output terminals Out4 are connected in a one-to-one correspondence to the first modulation module PWMM1 to the fourth modulation module PWMM4. The control module CLM generates a first drive control signal, a second drive control signal, a third drive control signal, and a fourth drive control signal based on the drive data supplied by the data drive signal line DataL, and transmits them to the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, and the fourth modulation module PWMM4, respectively. Taking the first output terminal Out1 as an example, the first modulation module PWMM1 is electrically connected to the first output terminal Out1 and can be turned on or off by the control of the first drive control signal, thereby switching the connection between the first output terminal Out1 and the common voltage signal line GNDL on or off. When the first modulation module PWMM1 is on, the common voltage signal line GNDL, the first output terminal Out1, the light-emitting unit 104 electrically connected to the first output terminal Out1, and the drive voltage signal line VLEDL constitute a signal circuit, and the light-emitting unit 104 operates. When the first modulation module PWMM1 is off, the above signal circuit is turned off and the light-emitting unit 104 does not operate. In this way, the first modulation module PWMM1 can modulate the current flowing through the light-emitting unit 104 by the control of the first drive control signal, so that the current flowing through the light-emitting unit 104 exhibits a pulse width modulation signal. Based on the first drive control signal, the first modulation module PWMM1 can further control the operating state of the light-emitting unit 104 by modulating elements such as the duty cycle of the pulse width modulation signal flowing through the light-emitting unit 104.If the light-emitting unit 104 is equipped with an LED, increasing the duty cycle of the pulse width modulation signal extends the total light-emitting time within one display frame of the LED, further improving the total luminous brightness of the LED within that display frame and thus increasing the brightness of that area of ​​the light-emitting substrate 300. Conversely, decreasing the duty cycle of the pulse width modulation signal shortens the total light-emitting time within one display frame of the LED, further decreasing the total luminous brightness of the LED within that display frame and thus decreasing the brightness of that area of ​​the light-emitting substrate 300. This enables control of the brightness of the light-emitting unit 104 electrically connected to the first output terminal Out1. By controlling the brightness of the light-emitting units 104 electrically connected to the second output terminal Out2, third output terminal Out3, and fourth output terminal Out4, respectively, using a similar method, the brightness of each light-emitting unit 104 within the light-emitting substrate 300 can be controlled.

[0081] Figure 9 shows a magnified view of a row of light-emitting regions 001 of the light-emitting substrate 300 in Figure 7, and Figure 10 shows a further magnified view of the area within the dashed frame in Figure 9. As shown in Figures 9 and 10, the drive circuit 103 shown in Figure 7 is attached to the first pad 107, and the first pad 107 is electrically connected to the drive circuit 103. The second pad 108 includes two sub-pads, which are electrically connected, for example, to the anode and cathode of the light-emitting unit 104. The first pad 107 has 10 sub-pads positioned at locations corresponding to the 10 terminals of the drive circuit 103. These are the 1st to 4th sub-pads, each electrically connected to the 4 output terminals Out1 to Out4, the 5th sub-pad, which is electrically connected to the power supply terminal Vcc, the 6th and 7th sub-pads, which are electrically connected to the 2 common voltage terminals GND, the 8th sub-pad, which is electrically connected to the address terminal Di_in, the 9th sub-pad, which is electrically connected to the relay terminal Di_out, and the 10th sub-pad, which is electrically connected to the data terminal Data. The 4th sub-pad is connected to the two sub-pads of the second pad 108 via wiring, thereby transmitting the drive signal to the light-emitting unit 104, which is electrically connected to the 4th terminal Out4. The fifth sub-pad is connected to the power signal line VccL, thereby transmitting the power voltage signal on the power signal line VccL to the power terminal Vcc. The sixth and seventh sub-pads are connected to the common voltage signal line GNDL, thereby transmitting the common voltage signal on the common voltage signal line GNDL to the two common voltage terminals GND. The eighth sub-pad is connected to the address signal line ADDRL, thereby transmitting the address signal on the address signal line ADDRL to the address terminal Di_in. The ninth sub-pad is connected to the cascading wiring, thereby outputting the relay signal within one time period as the address signal for the next stage drive circuit 103 which is cascaded to the drive circuit 103.The 10th sub-pad is connected to the data drive signal line DataL, thereby transmitting the data drive signal on the data drive signal line DataL to the data terminal Data.

[0082] In the light-emitting substrates according to multiple embodiments of this disclosure, such as light-emitting substrate 100, light-emitting substrate 200, and light-emitting substrate 300, the spacing between each drive voltage signal line VLEDL and other adjacent signal lines must be 0.2 mm or more. This is because the voltage on the drive voltage signal line VLEDL is relatively high (e.g., about 10 to 50 V), but the voltage of other signal lines adjacent to the drive voltage signal line VLEDL is generally relatively low, and if the spacing is too small, malfunctions such as circuit failure are likely to occur. The spacing between other signal lines on the light-emitting substrate may be designed according to the process limit, and the embodiments of this disclosure do not specifically limit this. For example, if the process limit is 20 μm, the spacing between other signal lines on the light-emitting substrate may be 20 μm.

[0083] The materials of the first conductive portion 105 and the second conductive portion 106 may be any suitable conductive material, and the embodiments of this disclosure do not specifically limit this. For example, the materials of the first conductive portion 105 and the second conductive portion 106 include copper. In one example, the first conductive portion 105 and the second conductive portion 106 may be a laminate of Cu and CuNi. The side of the laminate that is close to the substrate 101 is a Cu layer, which may have a thickness of, for example, 2 μm, and Cu is a suitable material as an electrical signal transmission channel. The side of the laminate that is away from the substrate 101 is a CuNi layer, which may have a thickness of, for example, 0.6 μm, and the CuNi layer may be there to protect the Cu layer and prevent the surface of the low resistivity Cu layer from being exposed and oxidized. In another example, the first conductive portion 105 and the second conductive portion 106 may be a laminate of, for example, MoNb / Cu / MoNb, where the side of the laminate that is close to the substrate 101 is a MoNb layer with a thickness of about 300 Å and is mainly for strengthening the adhesion between the laminate and the substrate 101, the intermediate layer of the laminate is a Cu layer, where Cu is a suitable material for electrical signal transmission channels, and the side of the laminate that is away from the substrate 101 is a MoNb layer with a thickness of about 200 Å and is intended to protect the intermediate Cu layer and prevent the surface of the intermediate Cu layer, which has low resistivity, from being exposed and oxidized.

[0084] The light-emitting substrate described in any one of the above embodiments may further comprise a plurality of flexible circuit boards 110. Figure 11A shows the connection relationship between the plurality of flexible circuit boards 110 and signal lines, and Figure 11B shows a partially enlarged view of region I in Figure 11A, i.e., the connection relationship between one flexible circuit board 110 and signal lines. As shown in Figures 11A and 11B, the flexible circuit board 110 is installed within the binding region on the light-emitting substrate and is electrically connected to each signal line of the first conductive part 105 by binding electrodes 120 in the binding region. In the example of Figure 2, the flexible circuit board 110 is electrically connected to the drive voltage signal line VLEDL, address signal line ADDRL, power signal line PwrL, common voltage signal line GNDL, feedback signal line FBL, and shield ring GND ESD Ring of the first conductive part 105, and the flexible circuit board 110 supplies the same signal to the common voltage signal line GNDL and shield ring GND ESD Ring. In the example shown in Figure 7, the flexible circuit board 110 is electrically connected to the drive voltage signal line VLEDL, address signal line ADDRL, power signal line VccL, data drive signal line DataL, common voltage signal line GNDL, feedback signal line FBL, and shield ring GND ESD Ring of the first conductive part 105, and the flexible circuit board 110 supplies the same signal to the common voltage signal line GNDL and shield ring GND ESD Ring. Figure 11B shows only the light-emitting region of the last row, i.e., the light-emitting region of the Mth row, and shows the light-emitting regions of the four columns, i.e., the light-emitting region of the kth column, the light-emitting region of the (k+1)th column, the light-emitting region of the (k+2)th column, and the area occupied by each light-emitting region of each column is indicated by a dashed frame. These four light-emitting regions may be any four adjacent light-emitting regions in the N-column light-emitting region. Each light-emitting region of each column includes a light-emitting unit 104.Each signal line (for simplicity, only the drive voltage signal line VLEDL and the common voltage signal line GNDL are shown in the drawing) includes a straight portion 116 and a bent portion 117 extending along a first direction D1, the bent portion 117 being located within the fan-out region 114, and each signal line is connected to a binding electrode 120 by its bent portion 117, the binding electrode 120 is connected to a flexible circuit board 110, thereby achieving an electrical connection between each signal line and the flexible circuit board 110. The width of the bent portion 117 of each signal line along a second direction D2 is smaller than the width along the second direction D2 of two adjacent rows of light-emitting regions. Taking the k-th row of light-emitting region in Figure 11 as an example, the width T1 of the bent portion 117 of the drive voltage signal line VLEDL along a second direction D2 is smaller than the width T2 of the two adjacent rows (e.g., the k-th and k+1th rows) of light-emitting regions along a second direction D2. Within the fan-out region 114, the angle between the straight portion 116 and the bent portion 117 of each signal line is 80° to 100°. In one example, the angle between the straight portion 116 and the bent portion 117 of each signal line is 90°. In related technologies, each flexible circuit board corresponds to 5 to 15 rows of light-emitting regions, that is, each flexible circuit board is electrically connected to the signal lines within 5 to 15 rows of light-emitting regions. In this application, by increasing the number of flexible circuit boards 110, each flexible circuit board corresponds to 3 to 8 rows of light-emitting regions 001, that is, each flexible circuit board 110 is electrically connected to the signal lines within 3 to 8 rows of light-emitting regions 001. For example, in the example of Figure 11B, each flexible circuit board 110 is electrically connected to the signal lines within 4 rows of light-emitting regions 001. By increasing the number of flexible circuit boards 110 and combining this with a nearly right-angle bending design for the signal lines, each signal line can be extended in a nearly straight line to the binding area and connected to the flexible circuit board 110. Compared to related technologies, the fan-out area 114 of the light-emitting substrate according to the embodiment of this disclosure has a relatively narrow width, thereby reducing the width of the lower frame of the light-emitting substrate and helping to achieve a narrower frame.

[0085] Figure 12 shows several alternative arrangements of each light-emitting unit 104 as an example. Each light-emitting unit 104 comprises multiple light-emitting elements connected to each other, the first end of each element electrically connected to the drive voltage signal line VLEDL, and the second end of each element electrically connected to the output terminal Out of the drive circuit 103. Figure 12(a) shows a case where each light-emitting unit 104 comprises four light-emitting elements connected in series, arranged in 1 column * 4 rows; Figure 12(b) shows a case where each light-emitting unit 104 comprises four light-emitting elements connected in series, arranged in 2 columns * 2 rows; and Figure 12(c) shows a case where each light-emitting unit 104 comprises nine light-emitting elements connected in series, arranged in 3 columns * 3 rows. Of course, the multiple light-emitting elements in each light-emitting unit 104 are not limited to the above arrangements, and they may be arranged in any suitable manner. For example, the multiple light-emitting elements in each light-emitting unit 104 may be connected in parallel. In another example, multiple light-emitting elements in each light-emitting unit 104 may be connected in series and parallel. The number of light-emitting elements in each light-emitting unit 104 may be determined according to actual needs, for example, by the dimensions of the light-emitting substrate and the required brightness. Each light-emitting element may be an organic light-emitting diode or an inorganic light-emitting diode. In some embodiments, each light-emitting element may be a mini light-emitting diode (Mini LED) or a micro light-emitting diode (Mirco LED). The dimensions of a mini light-emitting diode are, for example, in the range of 100 to 500 micrometers, and the dimensions of a micro light-emitting diode are, for example, smaller than 100 micrometers. Embodiments of this disclosure do not limit the type and dimensions of the light-emitting elements of the light-emitting unit 104. High-dynamic-range (HDR) display can be achieved by using mini light-emitting diodes or micro light-emitting diodes as light-emitting elements in a light-emitting unit 104 and combining this with independent control of the brightness of each light-emitting unit 104. When such a light-emitting substrate is applied to a display device, the contrast of the display device can be significantly improved.

[0086] As shown in Figure 13, each embodiment of the present disclosure may further comprise a buffer layer 112 and a first insulating layer 113. The buffer layer 112 is located between the layer on which the first conductive portion 105 and the second conductive portion 106 are located and the substrate 101, and the first insulating layer 113 is located on the side of the layer on which the first conductive portion 105 and the second conductive portion 106 are located that is away from the substrate 101. The buffer layer 112 may also be for reducing the stress applied to the substrate 101 when manufacturing the first conductive portion 105 and the second conductive portion 106, thereby preventing bending deformation of the substrate 101. The buffer layer 112 can further prevent impurities in the substrate 101 from adversely affecting the conductive performance of the first conductive portion 105 and the second conductive portion 106. The buffer layer 112 may be any suitable material, for example, SiN. The first insulating layer 113 can protect the first conductive portion 105 and the second conductive portion 106 from oxidative corrosion by water, oxygen, etc. in the environment. The material of the first insulating layer 113 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the first insulating layer 113 may be a single film layer or may contain multiple film layers. The substrate 101 may be any suitable substrate such as a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, or a quartz substrate, and the embodiments of this disclosure do not limit the material of the substrate 101. Optionally, the light-emitting substrate may further include a second insulating layer 115, the second insulating layer 115 located on the side of the first insulating layer 113 away from the substrate 101. The material of the second insulating layer 115 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the second insulating layer 115 may be a single film layer or may contain multiple film layers.

[0087] According to another aspect of the present disclosure, a backlight is provided, a block diagram of which is shown in Figure 14, and which comprises a light-emitting substrate as described in any one of the embodiments described above. The backlight 400 can provide a display light source to a display panel in a display device as a backlight in a display device. Of course, the backlight 400 may be used in any other device that requires a light source, and the embodiments of the present disclosure do not specifically limit the use of the backlight 400.

[0088] Since the backlight 400 may have substantially the same technical effects as the light-emitting substrates described in each of the above embodiments, a detailed explanation of the technical effects of the backlight 400 will be omitted here for brevity.

[0089] According to yet another aspect of the present disclosure, a display device is provided, a block diagram of which a display device 500 is shown in Figure 15, the display device 500 comprising a light-emitting substrate as described in any one of the above embodiments. In some embodiments, the display device 500 may be a liquid crystal display device comprising a liquid crystal panel and a backlight installed on the non-display side of the liquid crystal panel, the backlight comprising a light-emitting substrate as described in any one of the above embodiments, and for example, for achieving HDR dimming for display operation. The liquid crystal display device may have a more uniform backlight brightness and a higher display contrast. The display device 500 may be any suitable display device, including, but not limited to, any product or component having a display function such as a mobile phone, tablet computer, television, display, notebook computer, digital photo frame, car navigation system, or e-book reader.

[0090] Since the display device 500 may have substantially the same technical effects as the light-emitting substrates described in each of the above embodiments, a detailed explanation of the technical effects of the display device 500 will be omitted here for the sake of brevity.

[0091] A further aspect of the present disclosure provides a method for manufacturing a light-emitting substrate, the flowchart of which is shown in Figure 16, and which is applied to a light-emitting substrate as described in any one of the above embodiments. Referring to Figures 2, 7 and 16, the method 600 may include the following steps S601 to S603.

[0092] S601 supplies substrate 101.

[0093] S602 A conductive layer is formed on the substrate 101, and a first conductive portion 105 and a second conductive portion 106 including a plurality of pads 107 and 108 are formed simultaneously by patterning the conductive layer.

[0094] S603 Multiple light-emitting regions 102 are formed by mounting multiple drive circuits 103 and multiple light-emitting units 104 on a substrate 101, and each light-emitting region 102 includes a drive circuit 103 and at least one light-emitting unit 104 connected to the drive circuit 103. The first conductive part 105 is configured to transmit electrical signals to the drive circuits 103 and at least one light-emitting unit 104 in each light-emitting region 102.

[0095] The following provides a more detailed explanation of each step in Method 600 using a specific example.

[0096] First, a substrate 101 is supplied. The substrate 101 may be any suitable substrate such as a plastic substrate, silicon substrate, ceramic substrate, glass substrate, or quartz substrate, and the embodiments of this disclosure do not limit the material of the substrate 101.

[0097] Subsequently, a buffer layer 112 is formed on the substrate 101, for example, by magnetron sputtering. The buffer layer 112 may also be used to reduce the stress applied to the substrate 101 when the first conductive part 105 and the second conductive part 106 are subsequently manufactured, thereby preventing bending deformation of the substrate 101. Furthermore, the buffer layer 112 can prevent impurities in the substrate 101 from adversely affecting the conductivity of the first conductive part 105 and the second conductive part 106 formed thereafter. The buffer layer 112 may be any suitable material, for example, SiN.

[0098] Next, a conductive layer is formed on the substrate 101 by magnetron sputtering or electroplating, and the first conductive part 105 and the second conductive part 106 are simultaneously formed by patterning the conductive layer. The first conductive part 105 may include the drive voltage signal line VLEDL, address signal line ADDRL, cascaded connection wiring 111, power signal line VccL, data drive signal line DataL, common voltage signal line GNDL, feedback signal line FBL, and a selectable shield ring GND ESD Ring. The second conductive part 106 includes a first pad 107 for mounting the drive circuit 103 and a second pad 108 for mounting the light-emitting unit 104. Since the thickness of a single magnetron sputter generally does not exceed 1 μm, when manufacturing a conductive layer thicker than 1 μm, it is generally necessary to form it by multiple sputtering passes. In one example, the formation process of the first conductive portion 105 and the second conductive portion 106 may be described as first forming a Cu layer of, for example, 2 μm thickness on the buffer layer 112 to transmit various electrical signals, and then forming a CuNi layer of, for example, 0.6 μm thickness on the Cu layer, wherein the CuNi layer protects the Cu layer and prevents the surface of the low-resistivity Cu layer from being exposed and oxidized. In another example, the formation process of the first conductive portion 105 and the second conductive portion 106 may be described as first forming a MoNb layer of about 300 Å thickness on the buffer layer 112, wherein the MoNb layer strengthens the adhesion between the film layer and the substrate 101, then forming a Cu layer on the MoNb layer to transmit various electrical signals, and finally forming a MoNb layer of about 200 Å thickness on the Cu layer to protect the intermediate Cu layer and prevent the surface of the low-resistivity intermediate Cu layer from being exposed and oxidized. When forming a first conductive portion 105 and a second conductive portion 106 on a substrate 101 by electroplating, a seed layer is first formed with MoNiTi to improve the nucleation density of metal crystal grains in the subsequent electroplating process. Then, a low-resistivity Cu layer is produced by electroplating, followed by an oxidation prevention layer, the material of which may be MoNiTi. After the conductive layer undergoes processes such as cleaning, coating, baking, photolithography, developing, hard baking, etching, and peeling, the first conductive portion 105 and the second conductive portion 106 are formed.Only two masks are needed to manufacture the first conductive part 105 and the second conductive part 106 located in the same layer. Compared to related technologies that use at least three masks to form conductive structures located in different layers, this reduces the number of masks required, simplifies the manufacturing process, and lowers production costs.

[0099] Subsequently, a first insulating layer 113 is formed by magnetron sputtering on the side of the layer where the first conductive portion 105 and the second conductive portion 106 are located that is away from the substrate 101. The first insulating layer 113 may be for protecting the first conductive portion 105 and the second conductive portion 106 from oxidative corrosion by water, oxygen, etc. in the environment. The material of the first insulating layer 113 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the first insulating layer 113 may be a single film layer or may contain multiple film layers.

[0100] As an option, a second insulating film layer may be coated on the side of the first insulating layer 113 away from the substrate 101, and the second insulating layer 115 is formed by performing various treatments on the second insulating film layer, such as curing, exposure, development, and etching. The material of the second insulating layer 115 may be an organic material, an inorganic material, or a combination of an organic material and an inorganic material, and the second insulating layer 115 may be a single film layer or may contain multiple film layers. When the second insulating layer 115 is formed on the light-emitting substrate, multiple vias are formed by etching the second insulating layer 115 and the first insulating layer 113.

[0101] Finally, by cutting the light-emitting substrate to the specified outline, the drive circuit 103 and the light-emitting unit 104 are electrically connected to the first pad 107 and the second pad 108 of the second conductive part 106 by the multiple vias, thereby attaching the drive circuit 103 and the light-emitting unit 104 to the corresponding pads. By connecting each signal line of the first conductive part 105 to the flexible circuit board 110 in the binding region, an electrical connection is achieved between the drive circuit 103 and the flexible circuit board 110, and finally the required light-emitting substrate is obtained.

[0102] The technical effects achieved by method 600 may be described by referring to the technical effects of the light-emitting substrates described in each of the above embodiments. Therefore, for the sake of brevity, a detailed explanation of the technical effects of method 600 is omitted here.

[0103] In the description of this disclosure, the directions or positional relationships indicated by terms such as "up," "down," "left," and "right" refer to the directions or positional relationships shown in the drawings and are merely for the purpose of making the disclosure easier to understand. The disclosure does not require that the equipment be configured and operated in a specific direction, and therefore should not be understood as limiting the disclosure.

[0104] In this specification, reference terms such as “one embodiment” and “another embodiment” mean that the specific characteristics, structures, materials, or features described with reference to that embodiment are included in at least one embodiment of this disclosure. In this specification, the schematic descriptions of the above terms do not necessarily apply to the same embodiment or example. Furthermore, the specific characteristics, structures, materials, or features described may be combined in an appropriate manner in any one or more embodiments or examples. Also, a person skilled in the art can combine and combine different embodiments or examples and the characteristics of different embodiments or examples described herein, provided that they do not contradict each other. Furthermore, in this specification, the terms “first” and “second” are for illustrative purposes only and should not be understood as indicating or implying relative importance or implicitly referring to the number of technical features shown.

[0105] As those skilled in the art will understand, the drawings illustrate the steps of the methods of this disclosure in a specific order; however, unless explicitly stated in the context, it is not required or implied that these steps must be performed in that specific order. Additional or alternative steps may be combined into a single step and / or a single step may be broken down into multiple steps. Other method steps may also be inserted between steps. The inserted steps may represent improvements to the methods described herein, or they may not relate to such methods. Furthermore, a given step may not be fully completed before the next step begins.

[0106] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any modification or substitution that a person skilled in the art could easily conceive within the technical scope disclosed herein should be included within the scope of protection of the present disclosure. Accordingly, the scope of protection of the present disclosure should be the same as the claims. [Explanation of Symbols]

[0107] 001 Light-emitting region 100 Light-emitting substrates 101 circuit board 102 Emitting region 103 Drive Circuit 104 Light-emitting unit 105 First conductive part 106 Second conductive part 107 First Pad 108 Second pad 109 Wiring 110 Flexible circuit board 111 Cascading wiring 112 Buffer Layers 113 First insulating layer 114 Fan-out area 115 Second insulating layer 116 Straight section 117 Folded section 118 First connection section 119 Second connection section 120 binding electrodes

Claims

1. A light-emitting substrate, A substrate including a plurality of light-emitting regions arranged in an array, each of the plurality of light-emitting regions including a drive circuit and at least one light-emitting unit connected to the drive circuit, A first conductive portion located on the substrate and connected to the drive circuit and the at least one light-emitting unit within each light-emitting region, A second conductive portion located on the substrate and including a plurality of pads, The first conductive portion and the second conductive portion are located in the same layer. The second conductive part comprises a plurality of first pads for mounting the drive circuit and a plurality of second pads for mounting the light-emitting unit, the drive circuit is connected to the first conductive part via the first pads, and the light-emitting unit is connected to the first conductive part via the second pads. The plurality of light-emitting regions are arranged in M ​​rows along a first direction and in N columns along a second direction intersecting the first direction, where M and N are both positive integers of 1 or more. The first conductive portion includes N drive voltage signal lines and N common voltage signal lines extending along the first direction, and the light-emitting region of each row includes one drive voltage signal line and one common voltage signal line. Within the light-emitting region of each row, the drive voltage signal line is connected to the first end of each light-emitting unit within the light-emitting region of that row, and the common voltage signal line is connected to each drive circuit within the light-emitting region of that row. Within the light-emitting region of each row, the drive voltage signal line, the light-emitting unit, the drive circuit, and the common voltage signal line are sequentially arranged along the second direction. The orthographic projections of the drive voltage signal line, the light-emitting unit, the drive circuit, and the common voltage signal line on the substrate do not overlap with each other. Each drive circuit is provided with a plurality of terminals arranged in an array, and the plurality of terminals are arranged in at least two rows along the second direction. The plurality of terminals include at least one output terminal and at least one common voltage terminal, and the at least one output terminal and the at least one common voltage terminal are located in different rows of the plurality of terminals. Within the light-emitting region of each row, at least one output terminal of each drive circuit is connected in a one-to-one correspondence to the second end of the at least one light-emitting unit connected to the drive circuit, and at least one common voltage terminal of each drive circuit is connected to the common voltage signal line within the light-emitting region of the row. The aforementioned multiple terminals further include an address terminal, a relay terminal and a power terminal, Each drive circuit within the light-emitting region of each row is sequentially connected in cascaded order, the address terminal of the i-th stage drive circuit is located on the side of the i-th stage drive circuit that is close to the i-1 stage drive circuit, the relay terminal of the i-th stage drive circuit is located on the side of the i-th stage drive circuit that is close to the i+1 stage drive circuit, and 1 < i < M and i is a positive integer. The address terminal is configured to receive an address signal, the relay terminal is configured to output a relay signal, and the power terminal is configured to receive a power supply voltage signal. A light-emitting substrate in which the extending direction of the first conductive portion is parallel to the cascading connection direction of the drive circuit.

2. The light-emitting substrate according to claim 1, wherein a plurality of terminals of the drive circuit are arranged in a first row and a second row along the second direction, and within the light-emitting region of each row, the terminals of the first row of the drive circuit are located on the side adjacent to the drive voltage signal line of the drive circuit, and the terminals of the second row of the drive circuit are located on the side adjacent to the common voltage signal line of the drive circuit.

3. The first conductive portion further includes N power signal lines, each light-emitting region in each row includes one power signal line, each power signal line includes a main body portion and a first connection portion, and the main body portion of the power signal line extends along the first direction. The light-emitting substrate according to claim 2, wherein within the light-emitting region of each row, the power signal line is connected by the first connection to the power terminal of each drive circuit within the light-emitting region of the row, and the orthographic projection of the terminals of the first row on the substrate and the orthographic projection of the terminals of the second row on the substrate are located on opposite sides of the orthographic projection of the power signal line on the substrate.

4. The light-emitting substrate according to claim 3, wherein the first conductive portion further includes N address signal lines extending along the first direction, each light-emitting region of each row includes one address signal line, and within each light-emitting region of each row, the address signal line is connected to the address terminal of the first stage drive circuit.

5. The light-emitting substrate according to claim 4, wherein the first conductive portion further includes cascaded wiring extending along the first direction, the cascaded wiring is located between two adjacent drive circuits that are cascaded together within the light-emitting region of each row, and the relay terminal of the i-th stage drive circuit is connected to the address terminal of the i+1-th stage drive circuit via the cascaded wiring.

6. The light-emitting substrate according to claim 5, wherein the first conductive portion further includes N feedback signal lines extending along the first direction, each light-emitting region of a row includes one feedback signal line, and within each light-emitting region of a row, the feedback signal line is connected to the relay terminal of the final stage drive circuit, and the feedback signal line is at least partially located on the side of the common voltage signal line within the light-emitting region of the row away from the drive circuit.

7. The light-emitting substrate according to claim 6, wherein the orthographic projections of the drive voltage signal line, the address signal line, the cascaded connection wiring, the power signal line, the common voltage signal line, and the feedback signal line on the substrate do not overlap with each other.

8. The plurality of terminals of the drive circuit include the address terminal, the power supply terminal, the common voltage terminal, and the output terminal. The light-emitting substrate according to any one of claims 3 to 7, wherein the first row of terminals includes the output terminal and the address terminal, and the second row of terminals includes the common voltage terminal and the power supply terminal.

9. The light-emitting substrate according to claim 8, wherein the output terminal and the relay terminal of the drive circuit are the same terminal, and the drive circuit is configured to output a relay signal via the output terminal as the address signal of the next stage drive circuit cascaded to the drive circuit within a first time period, and to supply a drive signal via the output terminal to the at least one light-emitting unit connected to the drive circuit within a second time period.

10. The light-emitting substrate according to any one of claims 3 to 7, wherein the plurality of terminals of the drive circuit further include data terminals, and the data terminals and the power terminals are located in different rows of the plurality of terminals.

11. The number of output terminals of the drive circuit is multiple, and the number of common voltage terminals is at least one. The light-emitting substrate according to claim 10, wherein the first row of terminals includes the power terminal and the plurality of output terminals, and the second row of terminals includes the address terminal, the relay terminal, the data terminal and the at least one common voltage terminal.

12. The first conductive portion further includes N data drive signal lines, each light-emitting region of each row includes one data drive signal line, each data drive signal line includes a main body portion and a second connection portion, the main body portion of the data drive signal line extends along the first direction, The light-emitting substrate according to claim 11, wherein within the light-emitting region of each row, the data drive signal line is connected by the second connection to the data terminal of each drive circuit within the light-emitting region of the row, and the orthographic projection of the terminal of the first row on the substrate and the orthographic projection of the terminal of the second row on the substrate are located on opposite sides of the orthographic projection of the data drive signal line on the substrate, and the orthographic projection of the data drive signal line on the substrate does not overlap with the orthographic projection of the power signal line on the substrate.

13. The plurality of output terminals of the drive circuit are connected one-to-one to the second ends of the plurality of light-emitting units connected to the drive circuit. The light-emitting substrate according to claim 11, wherein the drive circuit is configured to output a relay signal via the relay terminal as the address signal for the next stage drive circuit cascaded to the drive circuit within a first time period, and to supply drive signals to the plurality of light-emitting units via the plurality of output terminals within a second time period.

14. The light-emitting substrate according to any one of claims 1 to 13, wherein the distance between the drive voltage signal line and other adjacent signal lines is 0.2 mm or more.

15. It further features multiple flexible circuit boards and a fan-out area. Each signal line of the first conductive part includes a straight portion and a bent portion, the bent portion of each signal line is located within the fan-out region, and each signal line is connected to the plurality of flexible circuit boards by its bent portion, The light-emitting substrate according to any one of claims 1 to 14, wherein the width of the bent portion of each signal line along the second direction is smaller than the width of two adjacent rows of light-emitting regions along the second direction.

16. The light-emitting substrate according to claim 15, wherein the angle between the straight portion and the bent portion of each signal line is 80° to 100°.

17. The light-emitting substrate according to any one of claims 1 to 16, wherein the material of the first conductive portion and the second conductive portion contains copper.

18. The light-emitting substrate according to any one of claims 1 to 17, wherein each light-emitting unit comprises a plurality of light-emitting elements connected to each other, and each of the plurality of light-emitting elements includes a mini light-emitting diode or a micro light-emitting diode.

19. The light-emitting substrate according to any one of claims 1 to 18, further comprising a shielding ring, wherein the shielding ring surrounds the outer periphery of the plurality of light-emitting regions, and the electrical signal received by the shielding ring is the same as the electrical signal received by the common voltage signal line.

20. Further comprising a buffer layer and an insulating layer, The buffer layer is located between the layer on which the first conductive portion and the second conductive portion are located and the substrate. The light-emitting substrate according to any one of claims 1 to 19, wherein the insulating layer is located on the side of the layer in which the first conductive portion and the second conductive portion are located that is away from the substrate.

21. A backlight comprising a light-emitting substrate according to any one of claims 1 to 20.

22. A display device comprising a light-emitting substrate according to any one of claims 1 to 20.

23. A method for manufacturing a light-emitting substrate, To supply circuit boards, A conductive layer is formed on the substrate, and a first conductive portion and a second conductive portion including a plurality of pads are formed simultaneously by patterning the conductive layer. The invention includes forming multiple light-emitting regions arranged in an array by mounting multiple drive circuits and multiple light-emitting units on the substrate, wherein each of the multiple light-emitting regions comprises a drive circuit and at least one light-emitting unit connected to the drive circuit, The first conductive portion is connected to the drive circuit and the at least one light-emitting unit within each light-emitting region. The second conductive part comprises a plurality of first pads for mounting the drive circuit and a plurality of second pads for mounting the light-emitting unit, the drive circuit is connected to the first conductive part via the first pads, and the light-emitting unit is connected to the first conductive part via the second pads. The plurality of light-emitting regions are arranged in M ​​rows along a first direction and in N columns along a second direction intersecting the first direction, where M and N are both positive integers of 1 or more. The first conductive portion includes N drive voltage signal lines and N common voltage signal lines extending along the first direction, and the light-emitting region of each row includes one drive voltage signal line and one common voltage signal line. Within the light-emitting region of each row, the drive voltage signal line is connected to the first end of each light-emitting unit within the light-emitting region of that row, and the common voltage signal line is connected to each drive circuit within the light-emitting region of that row. Within the light-emitting region of each row, the drive voltage signal line, the light-emitting unit, the drive circuit, and the common voltage signal line are sequentially arranged along the second direction. The orthographic projections of the drive voltage signal line, the light-emitting unit, the drive circuit, and the common voltage signal line on the substrate do not overlap with each other. Each drive circuit is provided with a plurality of terminals arranged in an array, and the plurality of terminals are arranged in at least two rows along the second direction. The plurality of terminals include at least one output terminal and at least one common voltage terminal, and the at least one output terminal and the at least one common voltage terminal are located in different rows of the plurality of terminals. Within the light-emitting region of each row, at least one output terminal of each drive circuit is connected in a one-to-one correspondence to the second end of the at least one light-emitting unit connected to the drive circuit, and at least one common voltage terminal of each drive circuit is connected to the common voltage signal line within the light-emitting region of the row. The aforementioned multiple terminals further include an address terminal, a relay terminal and a power terminal, Each drive circuit within the light-emitting region of each row is sequentially connected in cascaded order, the address terminal of the i-th stage drive circuit is located on the side of the i-th stage drive circuit that is close to the i-1 stage drive circuit, the relay terminal of the i-th stage drive circuit is located on the side of the i-th stage drive circuit that is close to the i+1 stage drive circuit, and 1 < i < M and i is a positive integer. The address terminal is configured to receive an address signal, the relay terminal is configured to output a relay signal, and the power terminal is configured to receive a power supply voltage signal. A method for manufacturing a light-emitting substrate, wherein the extending direction of the first conductive portion is parallel to the cascading connection direction of the drive circuit.

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