Power converter, method for controlling a power converter, semiconductor device, and method for controlling a semiconductor device

Abstract

A power conversion device according to the present invention converts power using a semiconductor device, and is characterized by comprising: a MOS control diode 1 that has an n+ layer 11, an n- layer 12, a p- layer 13, a p+ layer 14, a cathode electrode 21, anode electrodes 22, 220, and a gate electrode 23; and a voltage imparting means that applies a forward bias voltage across the anode electrodes 22, 220 and the cathode electrode 21 during forward bias, applies a reverse bias voltage across the anode electrodes 22, 220 and the cathode electrode 21 during reverse recovery, and, before the reverse recovery, sets the potential of the gate electrode 23 to a potential for forming an inversion layer in a third semiconductor layer relative to the potential of the anode electrodes 22, 220. The present invention thereby provides a power conversion device, a control method for the power conversion device, a semiconductor device, and a control method for the semiconductor device that are capable of further reducing power loss.

Description

[Technical Field]

[0001] The present invention relates to a power converter, a control method for a power converter, a semiconductor device, and a control method for a semiconductor device. In particular, the present invention relates to a power converter, etc., suitable for switching control of large currents. [Background technology]

[0002] Currently, power conversion devices such as inverters and converters are widely used in a variety of applications, from home appliances such as air conditioners, refrigerators, and induction cooktops, to industrial and automotive equipment such as electric vehicles, uninterruptible power supplies, solar power generation, and wind power generation, as well as high-voltage, high-power equipment in railways, construction machinery, steel, and power grids. Power conversion devices are essential devices for achieving energy conservation and new energy sources, and are, for example, key components in realizing a decarbonized society. Therefore, it is necessary to widely disseminate power conversion devices, and for this purpose, it is desirable that they be low-cost and compact enough to be installed anywhere.

[0003] In recent years, technological development has been progressing to surpass the low-loss limits of conventional IGBTs and pn diodes by integrating power semiconductors using silicon (Si), which has low material costs and allows the use of the vast assets cultivated in LSIs, with the control of power conversion devices, and through ingenious control methods. Even in flywheel diodes, which are a major component of power conversion devices, a MOS (Metal Oxide Semiconductor) gate has been added to the conventional pn diode, and a MOS-controlled diode has been announced in which the gate is controlled to achieve low loss.

[0004] Patent Document 1 describes a semiconductor device. In this semiconductor device, the semiconductor substrate side of the gate electrode, which is provided on the surface of the anode electrode 22 side of a silicon semiconductor substrate, is surrounded by a p layer, an n layer, and another p layer via a gate insulating film. The anode electrode also contacts the p layer with low resistance and also contacts either the n layer or a p layer, and a Schottky diode is formed between the anode electrode and the n layer or p layer. Non-patent document 1 describes a MOS-controlled diode in which a MOS (Metal Oxide Semiconductor) gate is added to a conventional pn diode and the gate is controlled to achieve low loss. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2019-149511 [Non-Patent Document 1] ISPSD(International Symposium on Power Semiconductor Devices & IC's), 2008, p.40-43 [Overview of the project] [Problems that the invention aims to solve]

[0006] Power converters experience power loss when controlling high-voltage, high-current power. This often leads to larger cooling systems and higher costs. Therefore, reducing power loss is a crucial issue for the widespread adoption of power converters. Until now, reducing power loss in power conversion devices has been primarily achieved by reducing the losses of the power semiconductors used in them. However, the reduction of losses in IGBTs (Insulated Gate Bipolar Transistors) and pn diodes used for flywheel diodes, which are currently the mainstream power semiconductors and use silicon (Si), is reaching its limits. There are power conversion devices that use MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and Schottky diodes, which have lower losses than Si, but the price of SiC material itself is high. As a result, widespread adoption in the various power conversion devices necessary for a decarbonized society has not progressed. The present invention aims to provide a power converter, a control method for the power converter, a semiconductor device, and a control method for the semiconductor device that can further reduce power loss. [Means for solving the problem]

[0007] To solve the above problems, the present invention provides a power conversion device that converts power using a semiconductor device, comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a first conductivity type provided on one surface side of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided in contact with the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer; a cathode electrode provided on the other surface side of the first semiconductor layer; and a protrusion provided on one surface side of the third semiconductor layer and in contact with the fourth semiconductor layer. The present invention provides a power conversion device comprising: a semiconductor device having an anode electrode and a gate electrode provided with a protrusion sandwiched in a direction intersecting the direction in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked, and which contacts the third semiconductor layer via a gate insulating film; and a voltage application means that applies a forward voltage between the anode electrode and the cathode electrode when in forward direction, and applies a reverse voltage between the anode electrode and the cathode electrode when in reverse recovery, and before reverse recovery, sets the potential of the gate electrode to a potential relative to the potential of the anode electrode that forms an inversion layer in the third semiconductor layer.

[0008] Furthermore, the present invention relates to a method for controlling a power converter that converts power using a semiconductor device, the method comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a first conductivity type provided on one surface side of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided in contact with the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer; a cathode electrode provided on the other surface side of the first semiconductor layer; and a projection provided on one surface side of the third semiconductor layer and having contact with the fourth semiconductor layer. This invention provides a control method for a power converter, characterized in that, for a semiconductor device having an anode electrode and a gate electrode provided with a protrusion sandwiched in a direction intersecting the stacking direction of the first, second, and third semiconductor layers, and in contact with the third semiconductor layer via a gate insulating film, the power converter is operated by performing the following control: applying a forward voltage between the anode electrode and the cathode electrode during forward operation, and applying a reverse voltage between the anode electrode and the cathode electrode during reverse recovery, and before reverse recovery, setting the potential of the gate electrode to a potential that forms an inversion layer in the third semiconductor layer relative to the potential of the anode electrode.

[0009] Furthermore, the present invention provides a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a first conductivity type provided on one surface side of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided in contact with the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer; a cathode electrode provided on the other surface side of the first semiconductor layer; an anode electrode provided on one surface side of the third semiconductor layer and having a protrusion that contacts the fourth semiconductor layer; and a gate electrode provided in a direction intersecting the direction in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked, with the protrusion in between, and contacting the third semiconductor layer via a gate insulating film.

[0010] Furthermore, the present invention provides a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a first conductivity type provided on one surface side of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided in contact with the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer; a cathode electrode provided on the other surface side of the first semiconductor layer; an anode electrode provided on one surface side of the third semiconductor layer and in contact with the fourth semiconductor layer; and a gate electrode provided adjacent to the anode electrode and the fourth semiconductor layer.

[0011] Furthermore, the present invention comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type provided on one surface side of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on one surface side of the second semiconductor layer, a fourth semiconductor layer of a second conductivity type provided in contact with the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer, a cathode electrode provided on the other surface side of the first semiconductor layer, an anode electrode provided on one surface side of the third semiconductor layer and having a protrusion that contacts the fourth semiconductor layer, and the first semiconductor layer. The present invention provides a control method for a semiconductor device comprising a gate electrode provided with a protrusion sandwiched between it in a direction intersecting the stacking direction of the second and third semiconductor layers, and which contacts the third semiconductor layer via a gate insulating film, wherein during forward movement, a forward voltage is applied between the anode electrode and the cathode electrode, and during reverse recovery, a reverse voltage is applied between the anode electrode and the cathode electrode, and before reverse recovery, the potential of the gate electrode is set to a potential relative to the potential of the anode electrode that forms an inversion layer in the third semiconductor layer. [Effects of the Invention]

[0012] According to the present invention, it is possible to provide a power converter, a control method for a power converter, a semiconductor device, and a control method for a semiconductor device that can further reduce power loss compared to cases where this configuration is not adopted. [Brief explanation of the drawing]

[0013] [Figure 1] This figure shows an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to the first embodiment of the present invention. [Figure 2] (a) is a diagram showing an example of the equivalent circuit of the MOS-controlled diode in Figure 1, using newly created symbols. (b) is a diagram showing the equivalent circuit of a conventionally proposed MOS-controlled diode. [Figure 3] This figure shows an example of the circuit symbol for a MOS-controlled diode having the equivalent circuit shown in Figure 2(a). [Figure 4] This figure shows the gate voltage dependence of the forward characteristics of the MOS-controlled diode according to the first embodiment. [Figure 5] This figure shows an example of the gate voltage dependence of the amount of stored charge inside a MOS-controlled diode according to the first embodiment. [Figure 6] This figure shows an example of the circuit configuration of a power conversion device to which the MOS-controlled diode according to this embodiment is applied. [Figure 7] Figure 6 shows examples of the operating waveforms of the MOS control diode and IGBT in the power converter during reverse recovery. [Figure 8] This figure shows the gate voltage dependence of the reverse recovery characteristics in the MOS-controlled diode of this embodiment. [Figure 9] This figure shows an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a second embodiment of the present invention. [Figure 10] This figure shows an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a third embodiment of the present invention. [Figure 11] This figure shows an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a fourth embodiment of the present invention. [Figure 12] This figure shows an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a fifth embodiment of the present invention. [Figure 13]This figure shows an example of measured output characteristics of a MOS-controlled diode mounted in a power conversion device according to the fifth embodiment of the present invention. [Figure 14] This figure shows an example of the circuit configuration of a power conversion device according to the sixth embodiment of the present invention. [Figure 15] This figure shows an example of the circuit configuration of a power conversion device according to the seventh embodiment of the present invention. [Figure 16] This figure shows an example of a cross-sectional structure of a dual-gate IGBT. [Figure 17] Figure 16 shows an example of a circuit symbol representing a dual-gate IGBT. [Figure 18] Figure 15 shows an example of a drive waveform (or drive signal) illustrating the control method for the two Gc gates and Gs gates of the dual-gate IGBT and the Gd gate (gate electrode) of the MOS-controlled diode in the upper and lower arms of the power converter.

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings, from the first to the seventh embodiment. Note that in these drawings, n - , n, n + The notation indicates that the semiconductor layer is n-type, and that the impurity concentration is relatively high in this order. - , p, p + The notation indicates that the semiconductor layer is p-type, and that the impurity concentration is relatively higher in this order. In addition, common components in each drawing are denoted by the same reference numeral, and redundant explanations are omitted.

[0015] ≪First Embodiment≫ First, the MOS-controlled diode 1 according to the first embodiment will be described. In the first embodiment, when the MOS-controlled diode 1 is made into an equivalent circuit, the MOS-controlled diode 1 is configured such that a pn diode and an n-channel MOSFET are connected in parallel between the anode (A) and the cathode (K). In addition, a pn diode with a low impurity concentration is used in the source (S) of the MOSFET. -Use layer 130. In the first embodiment, a first example of this configuration will be described.

[0016] FIG. 1 is a diagram showing an example of a cross-sectional structure of a MOS-controlled diode 1 mounted on a power conversion device according to a first embodiment of the present invention. The illustrated MOS-controlled diode 1 is an example of a semiconductor device. In FIG. 1, the upward direction in the figure is taken as one surface side, and the downward direction in the figure is taken as the other surface side. This is based on considering a pair of main surfaces of the laminate in which the respective layers described below are laminated, with one main surface side being one surface side and the other main surface side being the other surface side. Further, the left-right direction in the figure is taken as the direction intersecting the lamination direction in which the respective layers are laminated. The intersecting direction is, for example, a direction orthogonal to the lamination direction.

[0017] As shown in FIG. 1, the semiconductor substrate of the MOS-controlled diode 1 has a layer structure composed of an n + layer 11, an n - layer 12, p - layers 13, 130, and a p + layer 14. The MOS-controlled diode 1 also includes, as electrodes, a cathode electrode 21, anode electrodes 22, 220, and a gate electrode 23.

[0018] n + layer 11 is an example of a first semiconductor layer of a first conductivity type. n - layer 12 is provided on one surface side of the n + layer 11 and is an example of a second semiconductor layer of a first conductivity type having a lower impurity concentration than the n + layer 11. <00​​​​​​​​​​​​​​​- It is provided within layer 130, p - This is an example of a fourth semiconductor layer of the second conductivity type, with a higher impurity concentration than layers 13 and 130. Here, n-type is referred to as the first conductivity type, and p-type as the second conductivity type.

[0019] The cathode electrode 21 is n + It is provided on the other surface side of layer 11. The cathode electrode 21 is n + Layer 11 is in contact with the electrical element with low resistance. Anode electrodes 22 and 220 are p - It is provided on one surface side of layers 13 and 130. The anode electrodes 22 and 220 consist of anode electrode 22 and anode electrode 220. Anode electrode 22 is connected to p through the insulating film 31. - This is a layered portion provided on one surface side of layers 13 and 130. The anode electrode 220 is an example of a protruding portion, and is located from the layered anode electrode 22 to p - P is prominent in layer 130. + It contacts layer 14. Also, in the case of Figure 1, the anode electrode 220 is p - It also comes into contact with layer 130. In this case, p + Layer 14 is p - It can also be said that it is positioned within layer 130 and in contact with the tip of the anode electrode 220. The anode electrode 220 is p + Layer 14 is in contact with the electrical element with low resistance.

[0020] The gate electrode 23 is n + layer 11, n - Layer 12 and p - In a direction intersecting the direction in which layers 13 and 130 are stacked, p - It is surrounded by layers 13 and 130 and is provided with the anode electrode 220 in between. Also, the gate electrode 23 is connected via the gate insulating film 32 - It contacts layers 13 and 130. That is, the gate electrode 23 is connected to the gate insulating film 32 by p - It is insulated from layers 13 and 130. Also in this case, the gate electrode 23 is insulated from the anode electrode 220 and p +It can also be said that it is provided adjacent to layer 14. Furthermore, in this case, it can also be said that the gate electrode 23 and the gate insulating film 32 form a trench structure. And the gate electrode 23 and p - Layers 13 and 130 function as n-channel MOSFETs (metal-oxide-semiconductor field-effect transistors).

[0021] Furthermore, the insulating film 31 and the gate insulating film 32 are formed as a single unit. Also, in Figure 1, the gate insulating film 32 is formed from the insulating film 31 to p - The distance protruding to layers 13 and 130 is defined as depth D. And p + Layer 14 is provided so as to fit within depth D. This is p + It can also be said that layer 14 is formed inside the recess formed by the gate electrode 23 and the gate insulating film 32. + Layer 14 can also be said to be sandwiched between two adjacent trench structures formed by the gate electrode 23 and the gate insulating film 32, and formed within this space.

[0022] Also, as shown in Figure 1, p + Let the distance A be the length between the gate insulating films 32 having layer 14, and p + Distance B is defined as the length between gate insulating films 32 that lack layer 14. In this case, a structure that falls within the combined range of a pair of distances A and B in the intersecting direction in the figure is called a unit cell or basic cell. The MOS control diode 1 shown in the figure has a structure in which these unit cells are repeatedly arranged in the intersecting direction (left-right direction, lateral direction) in the figure. Also, in the depth direction of Figure 1, the shown structure continues in a straight line. In other words, if the MOS control diode 1 is cut in the same direction as in Figure 1, the structure will be the same as in Figure 1 no matter where it is cut.

[0023] In the MOS-controlled diode 1, a forward voltage is applied between the anode electrodes 22 and 220 and the cathode electrode 21 during forward operation by a voltage application means (not shown). That is, a positive potential is applied to the anode electrodes 22 and 220 of the MOS-controlled diode 1, and a negative potential is applied to the cathode electrode 21. And in this case, even if the potential of the gate electrode 23 is the same as the potential of the anode electrodes 22 and 220, p + Layer 14 and p - Layer 13 and n - Layer 12 is forward-biased. Therefore, p + From layer 14 to p - via layer 13 - A large number of holes are injected into layer 12. That is, gate electrode 23 and p - Even if the MOSFET consisting of layers 13 and 130 is not operating, p + From layer 14 to p - The hole is injected directly through layer 13. Then, this hole contacts the cathode electrode 21. + Layers 11 to n - This promotes the injection of a large amount of electrons into layer 12, n - Layer 12 becomes a state where a large amount of holes and electrons are accumulated. These electrons are p - It flows into layer 13, p + This facilitates further hole injection from layer 14. As a result, n - Layer 12 is conduction-modulated to low resistance, causing the forward voltage of the MOS control diode 1 to decrease.

[0024] In the MOS-controlled diode 1 of this embodiment, the current is p + Layer 14→p - Layer 13→n - Layer 12→n + The current flows through layers 11 in order, forming a current path. In the MOS-controlled diode 1, no MOSFET is connected in series with this current path. Therefore, compared to conventional MOS-controlled diodes in which a MOSFET is connected in series with the current path, the forward voltage is lower and conduction losses are further reduced. +By providing the layer 14 to be within the depth D, this effect becomes even more prominent. Also, by providing the region of distance B, the n in the region of distance A + Not only the electrons injected from the layer 11, but also the n in the region of distance B + The electrons injected from the layer 11 also flow into the anode electrode 220 in the region of distance A, and the p + Hole injection from the layer 14 is further promoted. To lower the forward voltage, it is preferable to make the distance B larger than the distance A (A < B). As a result, conductivity modulation is further promoted and the forward voltage is reduced. This is a p provided between two gate electrodes 23 and a gate insulating film 32 adjacent to each other across the anode electrode 220 which is a protrusion. - It can also be said that the distance A in the crossing direction of the layer 13 is smaller than the distance B between two gate electrodes 23 and a gate insulating film 32 adjacent to each other without sandwiching the anode electrode 220.

[0025] On the other hand, when a forward current is passed through the MOS controlled diode 1 and then the MOS controlled diode 1 is reverse recovered to the blocking state, a negative potential is applied to the anode electrodes 22, 220 by voltage applying means not shown, and a positive potential is applied to the cathode electrode 21. That is, during reverse recovery, a reverse voltage is applied between the anode electrodes 22, 220 and the cathode electrode 21. And in the present embodiment, the potential of the gate electrode 23 is made a positive potential with respect to the potential of the anode electrodes 22, 220 immediately before reverse recovery. Immediately before reverse recovery is the time before starting the reverse recovery operation. As a result, an n inversion layer is formed at the interface of the p - layers 13, 130 in contact with the gate insulating film 32. This n inversion layer has electrons flowing more easily than the p - layer 13. Therefore, the n - electrons injected from the layer 12 into the p - layer 13 flow around the p + layer 14 and into the n inversion layer, and flow into the anode electrode 220 via the p - layer 130. As a result, the injection of holes from the p + layer 14 is suppressed, and the n -The accumulated charge of holes and electrons in layer 12 is drastically reduced. Therefore, when the MOS controlled diode 1 is reverse-recovered afterward, the reverse recovery current decreases, and the reverse recovery loss is also reduced. Note that the control of setting the potential of the gate electrode 23 to a positive potential relative to the potentials of the anode electrodes 22 and 220 may be continued even during reverse recovery. Furthermore, unlike conventional MOS control diodes, the MOS control diode 1 has n on the anode electrode side. + Because there is no layer, the parasitic NPN transistor effect is suppressed. Therefore, the reverse recovery safe operating region can be enlarged. In addition, by making the gate electrode 23 the trench structure described above, the width of the trench bottom, which is the bottom of this trench structure, is reduced. As a result, the channel length of the n inversion layer can be shortened, and it also has the advantage of being less prone to the parasitic NPN transistor effect.

[0026] Figure 2(a) is a diagram showing an example of the equivalent circuit of the MOS-controlled diode 1 in Figure 1, using newly created symbols. Note that the numbers shown in Figure 2(a) correspond to the symbols in Figure 1. In this case, the pn diode and the n-channel MOSFET are connected in parallel between the anode (A) and the cathode (K). In this case, the pn diode is n + layer 11, n - Layer 12, p - Layer 13 and p + This corresponds to layer 14. Also, the n-channel MOSFET has a gate electrode 23 and p - This corresponds to layer 130. Furthermore, the anode (A) corresponds to anode electrodes 22 and 220. The cathode (K) corresponds to cathode electrode 21. Finally, the gate (G) corresponds to gate electrode 23. The drain (D) of an n-channel MOSFET is p - The connection starts midway through layer 13, and the source (S) is p - It connects to the anode (A) via layer 130. - In order to divert the current from the middle of layer 13 to train (D), p + From layer 14 to p - The amount injected into layers 13 and 130 can be controlled by the gate (G), and the electrical conductivity of the MOS control diode 1 can be adjusted during forward and reverse recovery.

[0027] On the other hand, FIG. 2(b) is a diagram showing an equivalent circuit of a conventionally proposed MOS controlled diode. In the MOS controlled diode of FIG. 2(b), a pn diode and a p-channel MOSFET are connected in series. That is, a p-channel MOSFET is added in series to the pn diode current path. In this case, in the forward direction, the forward voltage increases more than that of the MOS controlled diode 1 shown in FIG. 2(a), and the conduction loss is large. Further, during reverse recovery, the reverse recovery current increases more than that of the MOS controlled diode 1 shown in FIG. 2(a), and the reverse recovery loss is also large. This means that the MOS controlled diode 1 shown in FIG. 2(a) has a smaller forward voltage and smaller conduction loss than the conventionally proposed MOS controlled diode in the forward direction. Also, the MOS controlled diode 1 shown in FIG. 2(a) can be said to have a smaller reverse recovery current and smaller reverse recovery loss than the conventionally proposed MOS controlled diode during reverse recovery.

[0028] FIG. 3 is a diagram showing an example of a circuit symbol of the MOS controlled diode 1 having the equivalent circuit of FIG. 2(a). This circuit symbol is newly created for the convenience of explaining the embodiment. Note that this circuit symbol is used not only for the MOS controlled diode 1 shown in FIG. 1, for example, but also in the embodiments described later.

[0029] FIG. 4 is a diagram showing the gate voltage dependence of the forward characteristics of the MOS controlled diode 1 according to the first embodiment. In FIG. 4, the horizontal axis represents the forward voltage, and the vertical axis represents the forward current. As shown in FIG. 4, even when the gate voltage (V GA ) between the gate and the anode is not applied and is 0V, conductivity modulation is promoted, and the forward voltage when the forward current is 200 A becomes 3.5 V. On the other hand, when the gate voltage (V GA ) is +15V, the n-channel MOSFET operates, and the conductivity modulation decreases. As a result, the forward voltage when the forward current is 200 A rises to 12 V. The gate voltage (V GAThe gate power supply that drives the diode (V) with 0V and +15V can be the same power supply as that used for the IGBT described later. Therefore, the MOS control diode 1 of this embodiment has the advantage of reducing the number of power supplies compared to conventional technology which requires a third -15V, thus simplifying and miniaturizing the gate circuit. Note that the gate voltage (V) in the forward direction is GA It is also possible to set the voltage to -15V. In this case, the p in contact with the gate insulating film 32 - A p-accumulation layer is formed at the interface of layers 13 and 130. As a result, the forward voltage is further reduced, as shown in Figure 4. This control may be performed not only during forward operation but also during reverse blocking after reverse recovery. Therefore, in this embodiment, it can be said that, at least during forward operation and during reverse blocking after reverse recovery, control is performed to set the potential difference between the gate electrode 23 and the anode electrodes 22 and 220 to 0V, or to set the potential of the gate electrode 23 to a potential opposite to the potential of the anode electrodes 22 and 220 that is the potential for forming an inversion layer in the third semiconductor layer. In this case, this opposite potential is a negative potential (in the above case, -15V).

[0030] Figure 5 shows an example of the gate voltage dependence of the amount of stored charge inside the MOS-controlled diode 1 according to the first embodiment. In Figure 5, the horizontal axis represents depth, and the vertical axis represents the amount of stored charge. The accumulated charge shown in Figure 5 is the hole concentration, and it is a value obtained by simulation calculation with a forward current of 200A. From Figure 5, the gate voltage is +15V (V GA By doing this, it can be seen that the amount of accumulated charge, especially on the anode side, is reduced by about an order of magnitude compared to when the gate voltage is 0V and -15V. In other words, in the conduction state the gate voltage (V GA By setting the gate voltage (V) to 0V or -15V and lowering the forward voltage, conduction losses can be reduced. On the other hand, during reverse recovery, the gate voltage (V) should be set immediately before it. GA By switching the voltage to +15V and reducing the amount of stored charge, the reverse recovery current can be reduced, thereby lowering the reverse recovery loss.

[0031] FIG. 6 is a diagram showing an example of a circuit configuration of a power conversion device 80 to which a MOS controlled diode 82 according to this embodiment is applied. Here, the MOS controlled diode 82 is represented by the circuit symbol of the MOS controlled diode shown in FIG. 3. Also, the MOS controlled diode 82 has the same configuration as the above-described MOS controlled diode 1.

[0032] As shown in FIG. 6, in the power conversion device 80, a MOS controlled diode 82 and an IGBT 81 are connected in series as an upper arm and a lower arm, respectively. Also, the power conversion device 80 connects a load inductance 83 in parallel to the MOS controlled diode 82 as a chopper circuit. The power conversion device 80 adjusts the current flowing through the load inductance 83 and the power output by turning on and off the gate voltage (V GE ) of the IGBT 81.

[0033] Here, when the gate voltage (V GE ) of the IGBT 81 is turned on, the current supplied from the power supply (Vcc) flows through the load inductance 83 and a current (I C ) flows through the IGBT 81. Then, when this current (I C ) reaches a desired value, the IGBT 81 is turned off. Then, the current (I C ) flows as a current (I A ) into the MOS controlled diode 82. This current (I A ) is consumed by the loss of the MOS controlled diode 82 and the parasitic resistance existing in the circuit, and gradually decreases. Then, when the current (I A ) reaches the lower limit of the desired value, the IGBT 81 is turned on again to increase the current supplied to the load inductance 83 and maintain the current amount within the desired range.

[0034] FIG. 7 is an example of the operation waveforms during reverse recovery of the MOS controlled diode 82 and the IGBT 81 of the power conversion device 80 in FIG. 6. Here, it is assumed that the IGBT 81 in the lower arm turns on at time t0. In this case, the MOS control diode 82 of the upper arm has a gate voltage V at time t1, which is earlier than time t0 by the charge extraction period td_rr1. GA The gate voltage (V) is switched from 0V or -15V to +15V, reducing the accumulated charge inside the MOS control diode 82. This corresponds to the operation described above, "setting the potential of the gate electrode 23 to a positive potential relative to the potentials of the anode electrodes 22 and 220 immediately before reverse recovery." GA With the voltage remaining at +15V, the IGBT 81 on the lower arm is turned on at time t0, and the MOS control diode 82 on the upper arm is reverse-recovered. At this time, the gate voltage of the MOS control diode 82 on the upper arm is V GA The voltage remains at +15V. This corresponds to the operation described above, "during reverse recovery, the potential of the gate electrode 23 is set to a positive potential relative to the potentials of the anode electrodes 22 and 220."

[0035] Next, after time t0 has passed and a reverse bias has begun to be applied to the MOS control diode 82, at any time t2, the gate voltage (V) of the MOS control diode 82 is set. GA The voltage is switched back from +15V to 0V or -15V. The MOS control diode 82 stands by to respond when the IGBT 81 on the lower arm turns off and current is commutated to the MOS control diode 82.

[0036] Furthermore, when IGBT81 is turned on, the gate voltage (V) of MOS control diode 82 is turned on. GA The minimum recovery period td_rr2, which is the time it takes for the voltage to return to 0V or -15V, can be shortened until a reverse bias begins to be applied to the MOS control diode 82. By shortening this time, the n-inverting layer of the n-channel MOSFET can be eliminated before a large reverse bias voltage is applied, thereby eliminating the parasitic npn transistor effect. As a result, the reverse recovery safe operating region can be further increased.

[0037] Figure 8 shows the gate voltage dependence of the reverse recovery characteristics in the MOS-controlled diode 82 of this embodiment. In Figure 8, the horizontal axis represents time, and the vertical axis represents voltage. In Figure 8, the voltage (V) between the cathode (K) and anode (A) is shown. KA ) and anode current (I A This shows the gate voltage (V) explained in Figures 6 and 7. GA The solid line shows the case where the voltage is controlled from 0V to +15V at time t1 immediately before reverse recovery. The dashed line shows the case where this control is not performed and reverse recovery occurs while the voltage remains at 0V without switching. By controlling the gate voltage from 0V to +15V, the amount of stored charge decreases, as shown in Figure 5. As a result, the reverse recovery current decreases significantly, as shown by the solid line. Furthermore, it can be seen that the reverse recovery loss is dramatically reduced by 15% compared to when reverse recovery is performed with the voltage at 0V (dashed line).

[0038] ≪Second Embodiment≫ Next, the MOS-controlled diode 2 according to the second embodiment will be described. In the second embodiment, as in the first embodiment, the MOS-controlled diode 2 is configured such that the pn diode and the n-channel MOSFET are connected in parallel between the anode (A) and the cathode (K) in the equivalent circuit. In addition, a pn diode with a low impurity concentration is used in the source (S) of the MOSFET. - Layer 130 is used. Then, in the second embodiment, a second example of this configuration will be described.

[0039] Figure 9 shows an example of the cross-sectional structure of a MOS control diode 2 mounted in a power conversion device according to a second embodiment of the present invention. The MOS control diode 2 according to the second embodiment is similar to the first embodiment in that n + Layer 11 and n - Layer 12 and p - Layers 13, 130, and p + It has a layer structure consisting of layer 14. Furthermore, the MOS control diode 2, similar to the first embodiment, includes a cathode electrode 21, anode electrodes 22 and 220, and gate electrode 23 as electrodes. On the other hand, the MOS control diode 2 is p -A p-layer 15 is formed in at least a portion of layer 130. The p-layer 15 is an example of a fifth semiconductor layer of the second conductivity type. The p-layer 15 sandwiches the anode electrode 220 in the intersecting direction described above, and p - It is provided in layer 130. Also, if shown in the figure, by providing layer p 15, p - Layer 130 is divided into two layers, upper and lower, in the diagram. That is, in this case, n + layer 11, n - Layer 12, p - Layer 13, p - Layer 130, p + Layer 14 and p-layer 15, p - Layers 130 are stacked in that order. Then, p - Layer 130 is located on one surface side p - Layer 130 and p located on the other surface side - It will be two layers of layer 130. The impurity concentration of layer p15 is p - Layers 13 and 130 are higher, p + It is lower than layer 14. This means that when a forward current flows, p - Layer 13 to p - The electron current flowing to layer 130 is suppressed by the p layer 15, + Hole injection from layer 14 and p-layer 15 is increased. As a result, the forward voltage is further reduced.

[0040] Figure 2(a) also shows the p-layer 15. In the equivalent circuit shown in Figure 2(a), the p-layer 15 functions as follows. That is, p - Layer 13 to p - Inserting the p layer 15 increases the barrier for electrons flowing into layer 130. The height of this barrier (potential difference) is then applied to the p layer 15 and the p layer 15. + The forward bias effect of layer 14 increases, and p layer 15 and p + Hole injection from layer 14 is facilitated. As a result, the forward voltage is further reduced. Furthermore, by adjusting the density of the p-layer 15, the gate threshold voltage of the n-channel MOSFET can be adjusted to a desired value.

[0041] p layer 15 -Layer 13 to p - To enhance the suppression effect of the electron current flowing to layer 130, the p layer 15 is made p + It is preferable to form the p layer 15 so as to span from layer 14 to the gate insulating film 32. + It can also be said that it is preferable to form the layer 14 and the gate insulating film 32 to be connected. - Layer 13 and p - Because bypassing electron current can be suppressed across the entire boundary region of layer 130, the forward voltage is further reduced.

[0042] The impurity concentration of the p layer 15 is determined by the gate voltage (V) applied to the gate electrode 23, for example, +15V. GA When the charge is added, it is desirable that an n-inversion layer is formed at the interface of the gate insulating film 32 in contact with the p-layer 15. This way, the reduction of accumulated charge immediately before reverse recovery and the reduction of reverse recovery loss during reverse recovery are not compromised.

[0043] Furthermore, the structure of the gate electrode 23 of MOS-controlled diode 2 differs from that of MOS-controlled diode 1. In this case, the gate electrode 23 becomes thicker in the direction of the intersection as it moves toward the other surface. This can also be described as the gate electrode 23 becoming thicker in the direction from one surface to the other. As a result, the gate capacitance is reduced, for example, by half, making it easier to drive MOS-controlled diode 2. This gate structure is called a sidewall gate structure. Needless to say, this sidewall gate structure can also be used for MOS-controlled diode 1. On the other hand, the gate structure of MOS-controlled diode 1 is called a trench gate structure. That is, in the trench gate structure, the thickness of the gate electrode is almost constant in the vertical direction in the figure. And of course, the trench gate structure of MOS-controlled diode 1 can also be applied to MOS-controlled diode 2.

[0044] ≪Third Embodiment≫ Next, a MOS-controlled diode 3 according to the third embodiment will be described. In the third embodiment, as in the first and second embodiments, the MOS-controlled diode 3 is configured such that a pn diode and an n-channel MOSFET are connected in parallel between the anode (A) and the cathode (K) in the equivalent circuit. Furthermore, an n-layer 131 with a low impurity concentration is used for the source (S) of the MOSFET. Then, in the third embodiment, a third example of this configuration will be described.

[0045] Figure 10 shows an example of the cross-sectional structure of a MOS control diode 3 mounted in a power conversion device according to a third embodiment of the present invention. The MOS control diode 3 according to the third embodiment is similar to the first and second embodiments, n + Layer 11 and n - Layer 12 and p - Layer 13 and p + It has a layered structure consisting of layer 14. Furthermore, the MOS control diode 3, as in the first and second embodiments, includes a cathode electrode 21, anode electrodes 22 and 220, and gate electrode 23 as electrodes. On the other hand, in the MOS control diode 3 according to the third embodiment, compared to the MOS control diode 2, the p layer located on one surface side of the p layer 15 - Instead of layer 130, n layer 131 is formed. In this case, it can also be said that n layer 131 is formed on one surface side relative to p layer 15. That is, in this case, n + layer 11, n - Layer 12, p - Layer 13, p + Layers 14 and p-layer 15, and n-layer 131 are stacked in that order. n-layer 131 is an example of a sixth semiconductor layer of the first conductivity type. As a result, electrons flowing from the n-inversion layer immediately before and during reverse recovery are p - Compared to the case of layer 130, electrons flow more easily to the n layer 131, where they are the majority carriers. As a result, in the forward direction, n - The charge accumulated in layer 12 decreases, further reducing the reverse recovery loss.

[0046] The impurity concentration in n layer 131 is p- Higher than layer 13, p + It is lower than layer 14. Furthermore, it is preferable that the impurity concentration of n layer 131 is lower than that of p layer 15. This results in n layer 131, p layer 15, p - Layer 13, n - layer 12, n + The current amplification factor of the parasitic NPN transistor consisting of layer 11 is reduced, which prevents a decrease in the reverse recovery safe operating region due to the operation of the parasitic NPN transistor.

[0047] ≪Fourth Embodiment≫ Next, the MOS-controlled diode 4 according to the fourth embodiment will be described. In the fourth embodiment, as in the first to third embodiments, the MOS-controlled diode 4 is configured such that in the equivalent circuit, the pn diode and the n-channel MOSFET are connected in parallel between the anode (A) and the cathode (K). In addition, the source (S) of the MOSFET has a low impurity concentration p - Layer 130 is used. Then, in the fourth embodiment, a fourth example of this configuration will be described.

[0048] Figure 11 shows an example of the cross-sectional structure of a MOS control diode 4 mounted in a power conversion device according to the fourth embodiment of the present invention. The MOS control diode 4 in the fourth embodiment is similar to the first to third embodiments, n + Layer 11 and n - Layer 12 and p - Layer 13 and p + It has a layered structure consisting of layer 14. Furthermore, the MOS control diode 4, as in the first to third embodiments, includes a cathode electrode 21, anode electrodes 22 and 220, and gate electrode 23 as electrodes. On the other hand, the MOS control diode 4, relative to the MOS control diode 3 in Figure 10, has a gate electrode 23 and the other surface side p - The layer 13 includes a p-layer 151. The p-layer 151 is an example of a seventh semiconductor layer of the second conductivity type. The impurity concentration of the p-layer 151 is p - It is higher than layer 13. This means that during reverse recovery, n layer 131 (or p -The electron current that has come through layer 130) and the n inversion layer is p - It becomes possible to suppress injection into layer 13. In other words, n inversion layer, p - Layer 13, n - Parasitic NPN transistors consisting of layer 12 become less likely to operate, and the reverse recovery safe operating region is significantly improved. In this embodiment, p layer 151 and p layer 15 can be formed simultaneously with the same ion implantation, eliminating the need to add a new manufacturing process for forming p layer 151.

[0049] p shown in MOS control diodes 1-4 - The junction between layer 130 (or n-layer 131) and the anode electrode 220 is preferably a Schottky junction. p - In the case of layer 130, p - The layer 130 and the anode electrode 220 form a p-type Schottky junction, and when reducing the accumulated charge immediately before reverse recovery, the electrons are p due to the height of the barrier. - This makes it easier for the fluid to flow smoothly from layer 130 to the anode electrode 220. As a result, n - The conductivity modulation of layer 12 can be further reduced. On the other hand, in the case of the n layer 131, the n layer 131 and the anode electrode 220 form an n-type Schottky junction, and the height of this barrier reduces the flow of electrons to the n layer 131, thereby suppressing parasitic NPN transistor operation during reverse recovery. As a result, the reverse recovery safe operating region can be improved. In this embodiment, the p layer 151 and the p layer 15 can also be formed simultaneously with the same ion implantation, eliminating the need to add a new manufacturing process for forming the p layer 151.

[0050] ≪Fifth Embodiment≫ Figure 12 shows an example of the cross-sectional structure of a MOS control diode 3 mounted in a power conversion device according to the fifth embodiment of the present invention. In the fifth embodiment, the MOS control diode 3 replaces the n layer 131 shown in the third and fourth embodiments with an n layer 15 having a higher impurity concentration than the p layer 15. + Layer 132 is formed. In this case, n is located on one surface side relative to the p layer 15.+ It can also be said that layer 132 is formed. + Layer 132 is also an example of a sixth semiconductor layer of the first conductivity type. n + Even when layer 132 is ohmic-junctioned with the anode electrode 220, it makes contact with lower resistance than when it is junctioned with a Schottky electrode. In other words, the n layer, which is located on one surface side of the p layer 15, makes contact with the anode electrode 220 with lower resistance than when it is junctioned with a Schottky electrode. + It can also be said that it has layer 132. + When layer 132 makes contact with the anode electrode 220 with lower resistance than in the case of a Schottky junction, it reduces the accumulated charge immediately before reverse recovery, p - Electrons flowing through the n inversion layer formed on the gate electrode 23 side surface of layer 13 and p layer 15 are n + The charge can flow smoothly to the anode electrode 220 via layer 132. As a result, more accumulated charge is reduced, and the output characteristics of the MOS diode 3 can be controlled more precisely by the gate voltage. Consequently, reverse recovery losses are further reduced. Furthermore, n layer 131 has a higher impurity concentration than n + By making it layer 132, n + layer 132, p layer 15 / p - Layer 13, n - The parasitic NPN transistor consisting of layer 12 is more likely to operate during reverse recovery, but n + Miniaturization of layer 132, and p layer 15, p - By appropriately increasing the concentration of impurities in layer 13, the operation of parasitic NPN transistors can be prevented.

[0051] Figure 13 shows a measured example of the output characteristics of a MOS-controlled diode 3 mounted in a power converter according to the fifth embodiment of the present invention shown in Figure 12. Gate voltage V GA It can be seen that the output characteristics of the MOS-controlled diode 3 can be controlled by changing V. GA The output characteristics of -15V and 0V are almost the same, and the MOS control diode 3 is V GA = -15V and +15V, as well as V GA Output characteristics can also be controlled at 0V and +15V, VGA It has the advantage of eliminating the need for a gate power supply for -15V.

[0052] ≪Sixth Embodiment≫ Next, a sixth embodiment will be described. In the sixth embodiment, a power converter 1000 will be described as a first example of a power converter using the MOS control diode 82 described above.

[0053] Figure 14 is a diagram showing an example of the circuit configuration of a power converter 1000 according to the sixth embodiment of the present invention. The illustrated power converter 1000 comprises a DC-AC conversion circuit and a MOS control diode 82. This MOS control diode 82 can be any of the MOS control diodes 1 to 4 described above, and is simply referred to as MOS control diode 82. The DC-AC conversion circuit is composed of multiple IGBTs 81 (two in Figure 14) connected in series between a pair of DC terminals 1010 and 1020 to switch the current on and off. AC terminals 1030, 1040, and 1050 are connected between the multiple IGBTs 81. Furthermore, in the power converter 1000, a MOS control diode 82 is connected in antiparallel to each of the multiple IGBTs 81. The MOS control diode 82 of the power converter 1000 according to this embodiment may be any of the MOS control diodes 1 to 4 having the structures shown in Figures 1 and 9 to 11. In Figure 14, the MOS control diode 82 is represented by the circuit symbol shown in Figure 3.

[0054] In the power converter 1000, the incorporation of the MOS-controlled diode 82 reduces conduction losses and reverse losses compared to using a conventional pn diode. Furthermore, the reduction in reverse recovery current also reduces the turn-on current of the IGBT 81. As a result, the inverter's losses are reduced, and thus the power converter 1000 achieves higher efficiency.

[0055] ≪Seventh Embodiment≫ Next, a seventh embodiment will be described. In the seventh embodiment, a power converter 1100 will be described as a second example of a power converter using the MOS control diode 82 described above.

[0056] Figure 15 is a diagram showing an example of the circuit configuration of a power converter 1100 according to the seventh embodiment of the present invention. The power converter 1100 according to this embodiment is the same as the power converter 1000 according to the sixth embodiment shown in Figure 14, but with the IGBT 81 replaced by a dual-gate IGBT 810. Here, a dual-gate IGBT 810 refers to an IGBT having two gates that can be driven with a time difference. That is, the dual-gate IGBT 810 has two gates, a first gate and a second gate, which can be controlled on and off independently of each other.

[0057] Figure 16 shows an example of the cross-sectional structure of a dual-gate IGBT810. The illustrated dual-gate IGBT810 consists of a p-layer 41, an n-layer 42, and n - Layer 43, p-layer 44, and n + It has a layered structure consisting of layer 45. The dual-gate IGBT 810 also includes a cathode electrode 51, anode electrodes 52 and 520, and gate electrodes Gc gate 231 and Gs gate 232. The anode electrodes 52 and 520 consist of anode electrode 52 and anode electrode 520. The anode electrode 22 is connected to an insulating film 311 via n - This is a layered portion provided on one surface side of layer 43. The anode electrode 520 protrudes from the anode electrode 52 into the p layer 44 and the n + It makes contact with layer 45.

[0058] Gc gate 231 and Gs gate 232 are located in p layer 41, n layer 42, n - The anode electrode 520 is provided in a direction intersecting the stacking direction of layer 43 and p layer 44. In addition, the Gc gate 231 and Gs gate 232 are connected via the gate insulating film 321. -layer 43, p layer 44, n + It makes contact with layer 45. Gc gate 231 corresponds to the first gate, and Gs gate 232 corresponds to the second gate.

[0059] In the dual-gate IGBT810 having the cross-sectional structure shown in Figure 16, the gate electrode in a unit cell is divided into two gates, a Gc gate 231 and a Gs gate 232, and these are driven separately. By driving the Gc gate 231 and the Gs gate 232 with a time difference, turn-off losses and turn-on losses can be reduced. The timing of the time-difference driving of the Gc gate 231 and the Gs gate 232 will be explained separately using Figure 18.

[0060] The cross-sectional structure of the dual-gate IGBT810 shown in Figure 16, particularly the cross-sectional structures of the Gc gate 231 and Gs gate 232, is similar to the structure of the gate electrode 23 of the MOS-controlled diode 2 shown in Figure 10. However, in the MOS-controlled diode 2, the bottom of the gate insulating film 32 surrounding the gate electrode 23 is covered by the p-layer 13 and does not contact the n-layer 12. As a result, the gate voltage (V GA It also exhibits stable blocking characteristics even when the voltage is +15V.

[0061] Figure 17 shows an example of a circuit symbol representing the dual-gate IGBT810 shown in Figure 16. This circuit symbol was newly created for the convenience of explaining this embodiment. Note that the cross-sectional structure of the dual-gate IGBT810 shown in the circuit symbol of Figure 17 is not limited to the cross-sectional structure of Figure 16, and may have other cross-sectional structures.

[0062] ≪Seventh Embodiment≫ Next, a seventh embodiment will be described. In the seventh embodiment, the control of the power converter 1100 will be described.

[0063] Figure 18 shows an example of a drive waveform (or drive signal) illustrating the control method for the Gc gate 231 and Gs gate 232 of the dual-gate IGBT 810 and the Gd gate (gate electrode 23) of the MOS control diode 82 in the upper and lower arms of the power converter 1100 shown in Figure 15. These drive waveforms are generated by a control circuit (not shown) such as a microcontroller, based on a pulse width A PWM signal generated by that control circuit, while taking into account the dead time (DT), etc. For reference, Figure 18 also shows the gate (G) drive waveform in a conventional IGBT.

[0064] As shown in Figure 18, when the control circuit turns off the dual-gate IGBT 810, it turns off the Gc gate drive signal by time td_off before the Gs gate drive signal. For example, it changes it from +15V to 0V (or -15V). This reduces the charge accumulated inside the dual-gate IGBT 810. Then, after time td_off has elapsed, the control circuit turns off the Gs gate drive signal, which allows for fast interruption of the current in the dual-gate IGBT 810 because the accumulated charge is small, thereby reducing the turn-off loss of the dual-gate IGBT 810.

[0065] On the other hand, when turning on the dual-gate IGBT810, the control circuit turns on the Gs gate drive signal by time td_on before the Gc gate drive signal. That is, it turns the voltage from 0V (or -15V) to +15V. This makes it possible to slowly switch the dual-gate IGBT810 using only the Gc gate, thereby adjusting the dv / dt to a small value. In other words, the voltage change during turn-on can be made smaller. Next, by turning on the Gc gate drive signal, the control circuit can improve the conductivity modulation of the dual-gate IGBT810 and reduce conduction loss (on-voltage). However, if the Gc gate is driven alone, the switching is slow and the turn-on loss increases. In that case, the turn-on loss can be reduced by driving the Gs gate and Gc gate simultaneously.

[0066] Here, the relationship between the Gc gate drive signal and Gs gate drive signal of the dual-gate IGBT810 and the Gd gate drive signal of the MOS control diode 82 is as follows. Here, the transition period is defined as the period from when the Gd gate drive signal is switched from 0V (or -15V) to +15V, maintained at +15V, and then returned from +15V to 0V (or -15V).

[0067] In Figure 18, before the Gs gate drive signal of the dual-gate IGBT 810 of the arm itself turns on, the Gd gate drive signal of the MOS control diode 82 of the opposing arm, which is connected in series, is set to +15V. Then, the Gc and Gs gate drive signals of the dual-gate IGBT 810, which is connected in parallel to this MOS control diode 82, are turned off. This makes it possible to reproduce the pulse width A of the PWM signal. With this control method, the Gd gate drive signal, Gs gate drive signal, and Gc gate drive signal can be generated consistently from the PWM signal, just as in the conventional method. Even if the circuits of the upper arm and the lower arm each consist of three circuits, as shown in Figure 15, the ability to consistently generate the Gd gate drive signal, Gs gate drive signal, and Gc gate drive signal for each circuit from the PWM signal remains unchanged.

[0068] The MOS-controlled diode 82 described above, like conventional diodes, n - By reducing the lifetime of minority carriers in layer 12, the reverse recovery current can be reduced, thereby reducing reverse recovery losses. Furthermore, in the case where the MOS control diode 82 is configured by connecting in parallel a first MOS control diode (an example of a first semiconductor device) with a longer lifetime and reduced forward voltage, and a second MOS control diode (an example of a second semiconductor device) with a shorter lifetime and reduced reverse recovery current (reverse recovery loss), conduction losses can also be reduced.

[0069] With this configuration, during forward operation, the gate electrodes 23 of the first and second MOS control diodes remain at 0V (or -15V), and current is mainly supplied to the first MOS control diode, thereby reducing conduction losses. Furthermore, during reverse recovery, immediately before reverse recovery, the gate electrode 23 of the first MOS control diode is raised to +15V, transferring the main current flow to the second MOS control diode, and then the second MOS control diode is raised to +15V. In this way, the accumulated charge of the second MOS control diode is reduced, and the reverse recovery loss can be reduced due to the short lifetime of the second MOS control diode. This configuration and effect are a new benefit of the MOS control diode 82 in this embodiment, which can control the diode current with its gate electrode.

[0070] Therefore, by connecting the first MOS control diode and the second MOS control diode in parallel as described above, it is possible to realize a composite MOS control diode that simultaneously utilizes the low conduction loss of the first MOS control diode and the low reverse recovery loss of the second MOS control diode.

[0071] Furthermore, it is possible to integrate the MOS control diode 82 and the dual-gate IGBT 810 into a single semiconductor chip. By integrating them into a single semiconductor substrate, the overall mounting area of ​​the MOS control diode 82 and the dual-gate IGBT 810 can be reduced, thus enabling miniaturization of the power conversion device 1100.

[0072] In particular, the MOS control diodes 2, 3, and 4 shown in Figures 9-11 (MOS control diode 82) and the dual-gate IGBT 810 shown in Figure 16 all have similar side-gate structures. Therefore, combining them makes it easy to integrate them into a single semiconductor chip. Of course, even a conventional single-gate IGBT 81 can be integrated into the same semiconductor chip as the MOS control diode 82 in this embodiment.

[0073] As shown in Figure 2(b), one of the conventionally proposed MOS-controlled diodes is one in which a p-channel MOSFET is connected in series with the p-layer of a pn diode. In this MOS-controlled diode, during forward operation, a negative gate voltage lower than the threshold voltage (e.g., -15V) is applied to the p-channel MOSFET to turn it on, thereby allowing forward current to flow through the pn junction. On the other hand, during reverse recovery, the gate voltage is applied in advance to a value higher than the threshold voltage (e.g., 0V or +15V) just before the reverse recovery, turning the p-channel MOSFET off and reducing the excess charge accumulated in the pn diode during forward operation before reverse recovery. However, this MOS-controlled diode requires a negative gate voltage (for example, -15V) when forward. This means that a new negative gate power supply is needed. To operate this MOS-controlled diode, a new -15V power supply is required, resulting in three power supplies. As a result, costs increase and the gate circuit becomes larger. In addition, because a p-channel MOSFET is connected in series with the pn diode, the on-resistance of the p-channel MOSFET is superimposed on the forward voltage drop of the pn diode when forward, increasing the conduction loss of the MOS-controlled diode.

[0074] In contrast, in the MOS-controlled diode 82 of this embodiment, the pn diode and the n-channel MOSFET are connected in parallel between the anode (A) and cathode (K) in the equivalent circuit. In this case, the MOS-controlled diode 82 does not necessarily require a negative gate voltage. In other words, a negative gate voltage is not necessarily required for the gate power supply of the IGBT connected in parallel in the power converter. Therefore, it can be driven with the same binary gate power supply of 0V and +15V as the IGBT81 and dual-gate IGBT810. That is, the number of gate power supply voltages can be reduced. As a result, it has the advantage of being easier to control and allowing for a simplified and miniaturized gate circuit compared to cases where a negative gate voltage is required.

[0075] Furthermore, some conventionally proposed MOS-controlled diodes use the same n-channel MOSFET as IGBTs. In this case, the gate power supply voltage only needs to be set to the same value as an IGBT: 0V for forward rotation and +15V for reverse recovery. Additionally, this MOS-controlled diode forms an n-channel MOSFET in parallel with the pn diode, and in forward rotation, the on-resistance of the n-channel MOSFET is not superimposed on the forward voltage drop of the pn diode, thus making it easier to obtain a low forward voltage drop.

[0076] However, this MOS-controlled diode has a high impurity concentration in the source (S) of the n-channel MOSFET. + A layer is used. Furthermore, immediately before and during reverse recovery, the gate voltage needs to be above the threshold voltage of the n-channel MOSFET (for example, +15V). For this reason, an n+ inversion layer is also formed at the Si interface of the MOS gate surface of the n-channel MOSFET, and together with the high-density n+ layer of the source (S), a parasitic npn transistor with a wide n+ layer is formed. This parasitic npn transistor is prone to operation at high voltages, high currents, and high temperatures, and has the problem of reducing the reverse recovery safe operating region, which is the switching withstand capability during reverse recovery.

[0077] In contrast, in the MOS-controlled diode 82 of this embodiment, the source (S) of the n-channel MOSFET has a low impurity concentration p - Layer 130 is used. As a result, the forward voltage drop is small and the reverse recovery safe operating area is large.

[0078] Furthermore, the dual-gate IGBT 810 and MOS-controlled diode 82 described above can be easily manufactured using semiconductor manufacturing processes that utilize silicon. For example, the drive shown in Figure 18 allows for safe and low-loss operation of power conversion devices 1100, such as inverters, with high efficiency. As a result, it is possible to improve the efficiency of power consumption in power conversion devices 1100, such as inverters, without using high-cost SiC. Therefore, the widespread adoption of power conversion devices 1100 can be promoted, contributing to energy conservation and the development of new energy sources toward a decarbonized society. The same can be said for power conversion devices 1000 using IGBT 810 and MOS-controlled diode 82.

[0079] It should be noted that the present invention is not limited to the embodiments and examples described above, and includes various further modifications. For example, the embodiments and examples described above are described in detail for the purpose of clearly explaining the present invention, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace a part of the configuration of one embodiment or example with the configuration of another embodiment or example, and it is also possible to add the configuration of another embodiment or example to the configuration of one embodiment or example. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment or example with a configuration included in another embodiment or example. [Explanation of Symbols]

[0080] 1, 2, 3, 4, 82...MOS control diode, 11...n + layer, 12…n - Layer, 13, 130…p - layer, 14…p + Layer, 15, 151...p layer, 21...cathode electrode, 22, 220...anode electrode, 23...gate electrode, 31, 31...insulating film, 32...gate insulating film, 131...n layer, 132...n + Layer, 81...IGBT, 231...Gc gate, 232...Gs gate, 810...Dual gate IGBT, 1000, 1100...Power converter

Claims

1. A power conversion device that converts power using a semiconductor device, A first semiconductor layer of the first conductivity type, A second semiconductor layer of a first conductivity type is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer. A third semiconductor layer of a second conductivity type is provided on one surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer, A cathode electrode provided on the other surface side of the first semiconductor layer, An anode electrode provided on one surface side of the third semiconductor layer and having a protrusion that contacts the fourth semiconductor layer, A gate electrode is provided on either side of the protrusion in a direction intersecting the stacking direction of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and contacts the third semiconductor layer via a gate insulating film, A fifth semiconductor layer of second conductivity type is provided within the third semiconductor layer, sandwiching the protrusion in the aforementioned intersecting direction, and having an impurity concentration higher than that of the third semiconductor layer and lower than that of the fourth semiconductor layer. A semiconductor device having, During forward rotation, a forward voltage is applied between the anode electrode and the cathode electrode, and during reverse recovery, a reverse voltage is applied between the anode electrode and the cathode electrode. Before the aforementioned reverse recovery, a voltage application means is provided to set the potential of the gate electrode to a potential relative to the potential of the anode electrode to form an inversion layer in the third semiconductor layer, A power conversion device characterized by being equipped with the following features.

2. A DC-AC converter circuit is configured by connecting a pair of DC terminals and a plurality of insulated-gate bipolar transistors that switch current on and off in series between the pair of DC terminals, AC terminals connected between multiple insulated gate bipolar transistors, Furthermore, The power conversion device according to claim 1, characterized in that the semiconductor device is connected in antiparallel to each of the multiple insulated gate bipolar transistors.

3. The power conversion device according to claim 2, characterized in that the insulated gate bipolar transistor has a first gate and a second gate as the gate electrode, which can be independently controlled on and off.

4. The power conversion device according to any one of claims 1 to 3, characterized in that the semiconductor device has a configuration in which a first semiconductor device with a longer lifetime and reduced forward voltage and a second semiconductor device with a shorter lifetime and reduced reverse recovery current are connected in parallel.

5. A method for controlling a power conversion device that converts power using a semiconductor device, when the power conversion device is operated, A first semiconductor layer of the first conductivity type, A second semiconductor layer of a first conductivity type is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer. A third semiconductor layer of a second conductivity type is provided on one surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer, A cathode electrode provided on the other surface side of the first semiconductor layer, An anode electrode provided on one surface side of the third semiconductor layer and having a protrusion that contacts the fourth semiconductor layer, A gate electrode is provided on either side of the protrusion in a direction intersecting the stacking direction of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and contacts the third semiconductor layer via a gate insulating film, A fifth semiconductor layer of second conductivity type is provided within the third semiconductor layer, sandwiching the protrusion in the aforementioned intersecting direction, and having an impurity concentration higher than that of the third semiconductor layer and lower than that of the fourth semiconductor layer. For a semiconductor device having, During forward rotation, a forward voltage is applied between the anode electrode and the cathode electrode, and during reverse recovery, a reverse voltage is applied between the anode electrode and the cathode electrode. Before the aforementioned reverse recovery, the potential of the gate electrode is set to a potential relative to the potential of the anode electrode to form an inversion layer in the third semiconductor layer. A control method for a power converter, characterized by performing control to operate the power converter.

6. The aforementioned power converter is A DC-AC converter circuit is configured by connecting a pair of DC terminals and a plurality of insulated-gate bipolar transistors that switch current on and off in series between the pair of DC terminals, AC terminals connected between multiple insulated gate bipolar transistors and Furthermore, Each of the multiple insulated-gate bipolar transistors is connected in antiparallel to the semiconductor device. Each of the insulated-gate bipolar transistors has two gates, a first gate and a second gate. The control method for a power converter according to claim 5, characterized in that the first gate and the second gate are controlled to be turned on and off independently of each other.

7. The control method for a power converter according to claim 6, characterized in that when turning off the insulated gate bipolar transistor, the drive signal for the first gate is turned off before the drive signal for the second gate, and when turning on the insulated gate bipolar transistor, the drive signal for the second gate is turned on before the drive signal for the first gate.

8. The control method for a power converter according to claim 6, characterized in that the first gate and the second gate are driven simultaneously when the insulated gate bipolar transistor is turned on.

9. A first semiconductor layer of the first conductivity type, A second semiconductor layer of a first conductivity type is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer. A third semiconductor layer of a second conductivity type is provided on one surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer, A cathode electrode provided on the other surface side of the first semiconductor layer, An anode electrode provided on one surface side of the third semiconductor layer and having a protrusion that contacts the fourth semiconductor layer, A gate electrode is provided on either side of the protrusion in a direction intersecting the stacking direction of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and contacts the third semiconductor layer via a gate insulating film, A fifth semiconductor layer of second conductivity type is provided within the third semiconductor layer, sandwiching the protrusion in the aforementioned intersecting direction, and having an impurity concentration higher than that of the third semiconductor layer and lower than that of the fourth semiconductor layer. A semiconductor device characterized by comprising the following features.

10. The semiconductor device according to claim 9, characterized in that the fifth semiconductor layer is provided so as to extend from the fourth semiconductor layer to the gate insulating film.

11. The semiconductor device according to claim 9 or 10, characterized in that it comprises a sixth semiconductor layer of a first conductivity type located on one surface side with respect to the fifth semiconductor layer, and having a higher impurity concentration than the fifth semiconductor layer.

12. The semiconductor device according to claim 9 or 10, further comprising a sixth semiconductor layer of a first conductivity type located on one surface side with respect to the fifth semiconductor layer, and which makes contact with the protruding portion of the anode electrode with lower resistance than in the case of a Schottky junction.

13. The semiconductor device according to claim 9 or 10, further comprising a sixth semiconductor layer of first conductivity type located on one surface side of the fifth semiconductor layer, wherein the impurity concentration is higher than that of the third semiconductor layer and lower than that of the fourth semiconductor layer.

14. The semiconductor device according to claim 13, characterized in that the sixth semiconductor layer has a lower impurity concentration than the fifth semiconductor layer.

15. The semiconductor device according to claim 13 or 14, characterized in that at least one of the third semiconductor layer and the sixth semiconductor layer and the protruding portion of the anode electrode are joined by a Schottky bond.

16. The semiconductor device according to any one of claims 9 to 15, further comprising a seventh semiconductor layer of second conductivity type, which is located within the third semiconductor layer and provided on the other surface side of the gate electrode, and having a higher impurity concentration than the third semiconductor layer.

17. The semiconductor device according to any one of claims 9 to 16, characterized in that the gate electrode becomes thicker with respect to the intersecting direction as it moves toward the other surface side.

18. The semiconductor device according to any one of claims 9 to 17, characterized in that the fourth semiconductor layer is provided such that the gate insulating film is located within a distance that protrudes from the third semiconductor layer.

19. The semiconductor device according to any one of claims 9 to 18, characterized in that the distance in the intersecting direction of the third semiconductor layer provided between two adjacent gate electrodes and gate insulating films with the protrusion in between is smaller than the distance between two adjacent gate electrodes and gate insulating films without the protrusion in between.

20. The semiconductor device according to claim 9, characterized in that the gate electrode and the third semiconductor layer function as a metal oxide semiconductor field-effect transistor.

21. The semiconductor device according to claim 20, characterized in that, when the semiconductor device is considered as an equivalent circuit, the pn diode composed of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and the metal oxide film semiconductor field-effect transistor are connected in parallel between the anode electrode and the cathode electrode.

22. The gate electrode and the third semiconductor layer function as a metal-oxide-semiconductor field-effect transistor. The semiconductor device according to claim 20, characterized in that, when the semiconductor device is considered as an equivalent circuit, the pn diode composed of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and the metal oxide film semiconductor field-effect transistor are connected in parallel between the anode electrode and the cathode electrode.

23. A first semiconductor layer of the first conductivity type, A second semiconductor layer of a first conductivity type is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer. A third semiconductor layer of a second conductivity type is provided on one surface side of the second semiconductor layer, A fourth semiconductor layer of second conductivity type is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer, A cathode electrode provided on the other surface side of the first semiconductor layer, An anode electrode provided on one surface side of the third semiconductor layer and having a protrusion that contacts the fourth semiconductor layer, A gate electrode is provided on either side of the protrusion in a direction intersecting the stacking direction of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and contacts the third semiconductor layer via a gate insulating film, A fifth semiconductor layer of second conductivity type is provided within the third semiconductor layer, sandwiching the protrusion in the aforementioned intersecting direction, and having an impurity concentration higher than that of the third semiconductor layer and lower than that of the fourth semiconductor layer. For this semiconductor device, During forward rotation, a forward voltage is applied between the anode electrode and the cathode electrode, and during reverse recovery, a reverse voltage is applied between the anode electrode and the cathode electrode. Before the aforementioned reverse recovery, the potential of the gate electrode is set to a potential relative to the potential of the anode electrode to form an inversion layer in the third semiconductor layer. A control method for a semiconductor device, characterized by performing control.

24. The semiconductor device control method according to claim 23, characterized in that, even during the reverse recovery, the potential of the gate electrode is set to a potential relative to the potential of the anode electrode to form an inversion layer in the third semiconductor layer.

25. A method for controlling a semiconductor device according to claim 23 or 24, characterized in that, at least during the forward direction and during reverse blocking after reverse recovery, the potential difference between the gate electrode and the anode electrode is set to 0V, or the potential of the gate electrode is set to a potential opposite to the potential of the anode electrode that is the potential for forming an inversion layer in the third semiconductor layer.

26. The semiconductor device control method according to claim 25, characterized in that a voltage of a magnitude that causes a storage layer to form on the third semiconductor layer is applied during at least one of the forward direction and reverse blocking after reverse recovery.

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