Memory system, control method
The memory system addresses data loss by delaying the power disable signal response, ensuring data backup and integrity through controlled power management, thus preventing data loss during power transitions.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2022-09-14
- Publication Date
- 2026-06-01
Smart Images
Figure 0007867929000001 
Figure 0007867929000002 
Figure 0007867929000003
Abstract
Description
[Technical Field]
[0001] This embodiment relates to a memory system and a control method. [Background technology]
[0002] For example, PCIe (PCI Express) and NVMe (Non-Volatile Memory Express) are well-known interface standards for memory systems such as SSD memory. NVMe is a protocol standard for storage using non-volatile memory.
[0003] PCIe defines a signal called the Power Disable signal (hereinafter referred to as the PWRDIS (Power DISable) signal). The PWRDIS signal is a request signal to turn off the output of the power management IC (hereinafter referred to as the PMIC (Power Management IC)) used in the memory system for a predetermined period of time. For example, the PWRDIS signal is used when temporarily turning off the power to the memory system while the power supply from the host continues, and then restarting the SSD memory system.
[0004] When restarting an SSD memory system, the memory controller must respond to the PWRDIS signal sent from the host. Furthermore, if the PWRDIS signal sent from the host is directly supplied to the PMIC, and the PMIC controls the power output to turn off in response to the PWRDIS signal, the memory controller will be unable to save data, resulting in an improper power outage. This can cause data loss in the memory system. [Prior art documents] [Patent Documents]
[0005] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0318815 [Patent Document 2] U.S. Patent No. 10,551,897 [Patent Document 3] U.S. Patent No. 2020 / 0411068 [Overview of the project] [Problems that the invention aims to solve]
[0006] The memory system of this embodiment aims to provide a memory system that can perform data backup when it receives a request signal to disable the power supply. [Means for solving the problem]
[0007] The memory system of the embodiment is The device comprises a non-volatile memory capable of storing data, a memory controller capable of executing commands to the memory, a power supply circuit that generates a second power supply to the memory and the memory controller using a first power supply supplied from an external source, a connection line that transmits a request signal to the power supply circuit to disable the supply of the second power supply for a first period of time, and a switching element that opens and closes the connection line. The memory controller receives the request signal, closes the switching element and supplies the request signal to the power supply circuit after a second period shorter than the first period has elapsed since the receipt of the request signal, the power supply circuit disables the supply of the second power supply in response to the receipt of the request signal, and the memory controller resumes the supply of the second power supply by the power supply circuit after the first period has elapsed since the receipt of the request signal. [Brief explanation of the drawing]
[0008] [Figure 1] This is a block diagram showing an overall overview of the information processing system including the memory system and host device according to the first embodiment. [Figure 2] This is a circuit diagram showing the configuration of the memory system according to the first embodiment. [Figure 3] This is a timing chart showing the operation of the memory system according to the first embodiment. [Figure 4] This is a flowchart showing the operation of the memory system according to the first embodiment. [Figure 5] This is a circuit diagram showing the configuration of the memory system according to the second embodiment. [Figure 6] This is a timing chart showing the operation of the memory system according to the second embodiment. [Figure 7] This is a flowchart showing the operation of the memory system according to the second embodiment. [Figure 8] This is a circuit diagram showing the configuration of the memory system according to the third embodiment. [Figure 9] This is a timing chart showing the operation of the memory system according to the third embodiment. [Figure 10] It is a flowchart showing the operation of the memory system according to the third embodiment.
Mode for Carrying Out the Invention
[0009] (First Embodiment) FIG. 1 is a block diagram showing an overview of the entire information processing system including the memory system 1 and the host device 2 of the first embodiment. As shown in FIG. 1, the memory system 1 can be connected to the host device 2. The memory system 1 is, for example, an SSD (Solid State Drive) or a UFS (Universal Flash Storage) device. The host device 2 is, for example, a server, a personal computer, an in-vehicle device, or a mobile information processing device. The memory system 1 functions as an external storage device of the host device 2. The host device 2 can issue requests to the memory system 1. The requests include read requests and write requests.
[0010] The memory system 1 includes, for example, a NAND type flash memory (hereinafter also referred to as a NAND memory) 10, a memory controller (hereinafter sometimes referred to as a SoC (System-On-a-Chip)) 20, and a power supply circuit 30 such as a PMIC. The NAND memory 10 includes one or more memory chips. The memory chips include a plurality of memory cell transistors and can store data non-volatilely. The memory chips of the NAND memory 10 are connected to the memory controller 20.
[0011] Memory controller 20 performs program processing, read processing, erase processing, etc. on NAND memory 10. Memory controller 20 is a semiconductor circuit configured as, for example, a SoC. Memory controller 20 may be configured as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). Memory controller 20 may be composed of a plurality of chips. Each function of memory controller 20 can be realized by a CPU that executes software (firmware), dedicated hardware, or a combination thereof.
[0012] Power supply circuit 30 supplies power to each circuit element provided in memory system 1 such as NAND memory 10 and memory controller 20. Power supply circuit 30 is exemplified by, for example, a PMIC. Power supply circuit 30 receives the supply of power VIN (first power supply) from host device 2 or outside of memory system 1 via connector 35 and generates one or more constant voltages. Power supply circuit 30 generates and supplies the power VCC (second power supply) of a constant voltage corresponding to a plurality of supply destinations (Ch*). The plurality of supply destinations are, for example, NAND memory 10 and memory controller 20. Generate and supply. The plurality of supply destinations are, for example, NAND memory 10 and memory controller 20.
[0013] Power supply circuit 30 further receives a PWRDIS signal from host device 2 via connector 35. The PWRDIS signal is a request signal for disabling the power supply to memory system 1 from host device 2 for a predetermined time. The PWRDIS signal is, for example, a signal that becomes High (H) for 5 seconds. However, if power supply circuit 30 controls the on / off of power VCC according to the PWRDIS signal, data loss may occur in NAND memory 10.
[0014] Therefore, in the memory system 1 of this embodiment, when the memory controller 20 receives the PWRDIS signal, it sends a control signal CTRL to the power supply circuit 30 to delay the timing of turning off the power supply VCC. With this configuration, the memory controller 20 and the NAND memory 10 can obtain time to save data for storage.
[0015] Figure 2 is a circuit diagram showing in more detail the configuration of the memory system 1 according to the first embodiment, which is included in the information processing system shown in Figure 1. As shown in Figure 2, the memory system 1 of the first embodiment receives the power supply VIN and the PWRDIS signal via the connector 35. The signal line of the PWRDIS signal is connected to the corresponding input terminal PWRDIS_SoC of the memory controller 20. The PWRDIS signal is a request signal from the host device 2 to the memory system 1 to turn off the power supply VCC output of the power supply circuit 30 for a predetermined period (first period).
[0016] Meanwhile, the signal line of the PWRDIS signal is also connected to the corresponding input terminal PWRDIS_PMIC of the power supply circuit 30 via the switching element Q. In other words, the memory system 1 comprises the switching element Q, a resistor R, and a capacitor C.
[0017] In the example shown in Figure 2, the switching element Q is a P-MOSFET, but it is not limited to this. The switching element Q may also be an N-MOSFET. The source of the switching element Q is connected to the signal line of the PWRDIS signal, and the drain of the switching element Q is connected to ground via a resistor R. The gate of the switching element Q is connected to a general-purpose input / output terminal (hereinafter referred to as a GPIO (General-Purpose Input / Output) terminal) which is the terminal of the control signal CTRL of the memory controller 20. The drain terminal of the switching element Q is further connected to the PWRDIS signal input terminal PWRDIS_PMIC in the power supply circuit 30.
[0018] The power supply VIN, received via connector 35, is connected to the input terminal VIN of the power supply circuit 30. The connection line of power supply VIN is bypassed to ground by capacitor C.
[0019] The power supply circuit 30 generates power supply VCC to supply to the NAND memory 10 and memory controller 20 based on the given power supply VIN. On the other hand, the power supply circuit 30 shown in Figure 2 is equipped with a PWRDIS_PMIC terminal that receives the PWRDIS signal, and is capable of receiving the PWRDIS signal as a power supply circuit 30. When the input terminal PWRDIS_PMIC of the power supply circuit 30 receives the PWRDIS signal, it controls the output of power supply VCC to be turned off for a predetermined period of time according to the PWRDIS signal.
[0020] In this embodiment of the memory system 1, the memory controller 20 includes a PWRDIS_SoC terminal for receiving the PWRDIS signal, a general-purpose input / output terminal GPIO, a VCC terminal for receiving the power supply VCC, and a CPU for controlling the output of the control signal CTRL. The NAND memory 10 also has a VCC terminal for receiving the power supply VCC.
[0021] Next, the operation of the memory system of the first embodiment will be described with reference to Figures 3 and 4.
[0022] Figure 3 is a time chart showing the relationship between the voltage level of the power supply VIN supplied to the power supply circuit 30, the voltage level of the power supply VCC output from the power supply circuit 30, the voltage level of the PWRDIS signal sent from the host device 2, the voltage level of the general-purpose input / output terminal GPIO of the memory controller 20, and the voltage level of the PWRDIS_PMIC terminal of the power supply circuit 30, and the passage of time t. Figure 4 is a flowchart showing the operation of the memory system 1.
[0023] As shown in Figure 3, when the power supply circuit 30 receives power supply VIN via connector 35 at time t1, power supply VIN reaches a predetermined voltage level. In response to the supply of power supply VIN, the power supply circuit 30 generates power supply VCC corresponding to each Ch* at time t2 (S100 in Figure 4; the same applies hereafter).
[0024] As shown in Figure 3, in the initial state, the host device 2 does not transmit the PWRDIS signal, and the voltage level of the PWRDIS signal is low ("L") at time t2. Therefore, the power supply circuit 30 supplies the generated power supply VCC to the memory controller 20 and the NAND memory 10 (S105).
[0025] When the CPU of the memory controller 20 receives power supply VCC, it performs an initialization operation and sets the voltage level of the general-purpose input / output terminal GPIO to a high level ("H") at time t3 (S110). Thereafter, the memory controller 20 waits for the reception of the PWRDIS signal (No. in S115).
[0026] When the host device 2 sets the PWRDIS signal level to "H" at time t4, and the PWRDIS_SoC terminal of the memory controller 20 also reaches "H" (Yes in S115), the memory controller 20 maintains the level of the general-purpose input / output terminal GPIO at "H" until the writing of the data being processed to the NAND memory 10 is complete (data save time) (No in S120). In the example shown in Figure 3, the voltage level of the general-purpose input / output terminal GPIO is maintained at "H" until time t5. During this data save time, the memory controller 20 can perform processes such as writing to the NAND memory 10, flashing, and saving unsaved data.
[0027] The data save time (second period) from time t4 to t5 is arbitrarily determined within a range that does not exceed the minimum value of 5 seconds specified as the PWRDIS signal. The data save time may be designed in advance based on the time required for writing operations to the NAND memory 10, or it may be determined experimentally by actual measurement. As shown in Figure 3, the data save time (second period) is shorter than the period during which the power supply VCC required by the PWRDIS signal is turned off (first period).
[0028] When the data saving time has elapsed at time t5 (Yes in S120), the CPU of the memory controller 20 sets the level of the general-purpose input / output terminal GPIO to "L" at time t6 (S125).
[0029] When the level of the general-purpose input / output terminal GPIO changes from "H" to "L" at time t6, the switching element Q in Figure 2 turns on (S130), and the potential of the PWRDIS_PMIC terminal changes from "L" to "H" (S135), becoming the same potential as the PWRDIS_SoC terminal.
[0030] At time t6, the power supply circuit 30 turns off the output of the power supply VCC according to the definition of the PWRDIS signal (S140). In other words, it disables the supply of power supply VCC. At this time, the supply of power supply VCC to the memory controller 20 is stopped, so the level of the general-purpose input / output terminal GPIO remains "L".
[0031] Since the switching element Q remains on when the level of the general-purpose input / output terminal GPIO is "L", when the level of the PWRDIS signal becomes "L" at time t8 (Yes in S145), the level of the PWRDIS_PMIC terminal of the power supply circuit 30 becomes low level "L" (S150).
[0032] The power supply circuit 30 turns on the output of power supply VCC at time t9 in response to the change in the PWRDIS signal (S155). In other words, the supply of power supply VCC is resumed.
[0033] The memory controller 20 performs an initialization operation when the power supply VCC is supplied again, and the CPU of the memory controller 20 performs an initialization operation over time t 10 In this process, the level of the general-purpose input / output terminal GPIO is set to "H" (S160), the switching element Q is turned off (S165), and the level of the PWRDIS_SoC terminal is monitored.
[0034] According to this embodiment, when the memory controller 20 detects a change in the PWRDIS signal, it transmits the level of the PWRDIS signal to the power supply circuit 30 via the switching element Q after the data save time in the NAND memory 10 has elapsed. In other words, when the host device 2, memory controller 20, and power supply circuit 30 respond to the PWRDIS signal, data save time can be secured with a simple configuration.
[0035] (Second Embodiment) Next, with reference to Figure 5, the memory system of the second embodiment will be described. In this embodiment, the memory system 1a is configured so that the transmission control of the PWRDIS signal to the power supply circuit 30 is directly performed by the memory controller 20. In the following description, elements and operations common to the first embodiment are denoted by the same reference numerals, and redundant explanations are omitted.
[0036] As shown in Figure 5, the memory system 2 of this embodiment accepts power supply VIN and the PWRDIS signal via connector 35. The signal line of the PWRDIS signal is connected to the corresponding input terminal PWRDIS_SoC of the memory controller 21. Similarly, the signal line of the PWRDIS signal is also connected to the corresponding input terminal PWRDIS_PMIC of the power supply circuit 30.
[0037] In this embodiment of the memory system 1a, the memory controller 21 includes an input terminal PWRDIS_SoC for receiving the PWRDIS signal, an output terminal Ex_PWR as a terminal for the control signal CTRL for controlling the external power supply, a VCC terminal for receiving the power supply VCC, and a CPU for controlling the output of the Ex_PWR terminal. The NAND memory 10 also has a VCC terminal for receiving the power supply VCC.
[0038] The power supply circuit 31 shown in Figure 5 is equipped with an input terminal PWRDIS_PMIC for receiving the PWRDIS signal, and is capable of receiving the PWRDIS signal as a power supply circuit 31. In addition, the power supply circuit 31 has an input terminal Ex_PWR that enables control of the output of the power supply VCC.
[0039] Next, the operation of the memory system 1a of the second embodiment will be described with reference to Figures 6 and 7.
[0040] Figure 6 is a time chart showing the relationship with the passage of time t for each of the following: the voltage level of the power supply VIN supplied to the power supply circuit 31, the voltage level of the power supply VCC output from the power supply circuit 31, the voltage level of the PWRDIS signal sent from the host device 2, the voltage level of the output terminal Ex_PWR of the memory controller 21 that controls the external power supply, and the control state of the power supply VCC. Figure 7 is a flowchart showing the operation of the memory system 1a.
[0041] As shown in Figure 6, when the power supply circuit 31 receives power supply VIN via connector 35 at time t1, power supply VIN reaches a predetermined voltage level. In response to the supply of power supply VIN, the power supply circuit 31 generates power supply VCC corresponding to each Ch* at time t2 (S100 in Figure 7).
[0042] As shown in Figure 6, in the initial state, the host device 2 does not transmit the PWRDIS signal, and the voltage level of the PWRDIS signal is "L" at time t2. Therefore, the power supply circuit 31 supplies the generated power supply VCC to the memory controller 21 and the NAND memory 10 (S105).
[0043] The CPU of the memory controller 21 performs an initialization operation when it receives power supply VCC, and for a time t 3a The signal at the output terminal Ex_PWR is set to a high level "H" (S111). Thereafter, the memory controller 21 waits for the reception of the PWRDIS signal (No. in S115).
[0044] When the host device 2 sets the PWRDIS signal to "H" at time t4, and the level of the PWRDIS_SoC terminal of the memory controller 21 becomes "H" (Yes in S115), the memory controller 21 maintains the level of the output terminal Ex_PWR to "H" (No in S120) until the writing of the data being processed to the NAND memory 10 is completed (data save time). In the example shown in Figure 6, at time t 5aThe voltage level of the output terminal Ex_PWR is maintained at "H" until this time. During this data save time, the memory controller 21 can perform operations such as writing to the NAND memory 10, flashing, and saving unsaved data.
[0045] In the second embodiment, the power supply circuit 31 monitors the level of the PWRDIS signal and the level of the input terminal Ex_PWR, and controls the output of the power supply VCC from on to off when the level of the PWRDIS_PMIC terminal is "H" and the level of the input terminal Ex_PWR is "L".
[0046] From time t4 to time t 5a Once the data backup time has elapsed (Yes in S120), the CPU of the memory controller 21 will execute the command t 6a In this configuration, the level of the output terminal Ex_PWR is changed from "H" to "L" (S126).
[0047] When the level of the output terminal Ex_PWR of the memory controller 21 is "L", that is, when the level of the input terminal Ex_PWR of the power supply circuit 31 is "L", the level of the PWRDIS_PMIC terminal is "H". As a result, the power supply circuit 31 controls the output of the power supply VCC from on to off at time t7 (S141). In other words, it disables the supply of power supply VCC.
[0048] The power supply circuit 31 responds to the change in the level of PWRDIS_PMIC at time t8 (Yes in S145), at time t 9a The output of the power supply VCC is turned on (S155). In other words, the supply of power supply VCC is resumed.
[0049] The memory controller 21 performs an initialization operation when the power supply VCC is supplied again, and the CPU of the memory controller 21 performs an initialization operation over time t 10 In this configuration, the level of the output terminal Ex_PWR is set to "H" (S161).
[0050] According to this embodiment, when the memory controller 21 detects a change in the PWRDIS signal, after the data save time in the NAND memory 10 has elapsed, it directly transmits the level of the Ex_PWR signal, which controls the output of the power supply VCC, to the power supply circuit 31. In other words, data save time can be secured with a simple configuration without adding external circuits or the like.
[0051] (Third embodiment) Next, with reference to Figure 8, the memory system of the third embodiment will be described. In this embodiment, the memory system 3 controls the transmission of the PWRDIS signal to the power supply circuit 32 using a power loss notification signal (hereinafter referred to as the PLN (Power Loss Notification) signal) and a power loss confirmation signal (hereinafter referred to as the PLA (Power Loss Acknowledge) signal). In the following description, elements and operations common to the first and second embodiments will be denoted by the same reference numerals, and redundant explanations will be omitted.
[0052] As shown in Figure 8, the memory system 1b of this embodiment accepts power supply VIN and the PWRDIS signal via connector 35. The signal line of the PWRDIS signal is connected to the corresponding input terminal PWRDIS_PMIC of the power supply circuit 32.
[0053] In this embodiment of the memory system 1b, the memory controller 22 includes a PLN terminal for receiving the PLN signal, a PLA terminal for transmitting the PLA signal as a control signal CTRL, a VCC terminal for receiving the power supply VCC, and a CPU for controlling the PLN signal and the PLA signal. The NAND memory 10 also has a VCC terminal for receiving the power supply VCC.
[0054] The PLN terminal provides a function to notify of power loss. The PLA terminal provides a function to return a confirmation signal in response to a signal input to the PLN terminal.
[0055] The power supply circuit 32 shown in Figure 8 is equipped with a PWRDIS_PMIC terminal for receiving the PWRDIS signal, and is capable of receiving the PWRDIS signal as a power supply circuit 32. The power supply circuit 32 also has an input terminal Ex_PWR that enables control of the output of the power supply VCC. Furthermore, the power supply circuit 32 has an OMP terminal (OMP; Off Module Power Loss Protection) that can send a power loss protection signal.
[0056] Next, the operation of the memory system 1b of the third embodiment will be described with reference to Figures 9 and 10.
[0057] Figure 9 is a time chart showing the relationship with the passage of time t for each of the following: the voltage level of the power supply VIN supplied to the power supply circuit 32, the voltage level of the power supply VCC output from the power supply circuit 32, the voltage level of the PWRDIS signal sent from the host device 2, the voltage level at the OMP terminal of the power supply circuit 32 (PLN terminal of the memory controller 22), the voltage level at the input terminal Ex_PWR of the power supply circuit 32 (PLA terminal of the memory controller 22), and the control state of the power supply VCC. Figure 10 is a flowchart showing the operation of the memory system 1b.
[0058] As shown in Figure 9, when the power supply circuit 32 receives power supply VIN via connector 35 at time t1, power supply VIN becomes a predetermined voltage level. In response to the supply of power supply VIN, the power supply circuit 32 generates power supply VCC corresponding to each Ch* at time t2 (S100 in Figure 10).
[0059] As shown in Figure 9, in the initial state, the host device 2 does not transmit the PWRDIS signal, and the voltage level of the PWRDIS signal is "L" at time t2. Therefore, the power supply circuit 32 supplies the generated power supply VCC to the memory controller 22 and the NAND memory 10 (S105).
[0060] When the power supply circuit 32 receives power supply VIN, time t 3bSet the level of the OMP terminal to "H" (S112). Since the OMP terminal of the power supply circuit 32 is connected to the PLN terminal of the memory controller 22, the level of the PLN terminal becomes "H". When the CPU of the memory controller 22 receives the power supply VCC, it performs an initialization operation, sets the PLN terminal to the input mode, and at time t 3c set the PLA terminal to the "H" level in the output mode. Since the PLA terminal of the memory controller 22 is connected to the Ex_PWR terminal of the power supply circuit 32, the level of the Ex_PWR terminal also becomes "H" (S113). Thereafter, the power supply circuit 32 waits for the reception of the PWRDIS signal (No in S115).
[0061] In this embodiment, the power supply circuit 32 monitors the level of the PWRDIS signal and the level of the input terminal Ex_PWR. When the level of the PWRDIS_PMIC terminal is "H" and the level of the input terminal Ex_PWR changes from "L" to "H", the output of the power supply VCC is controlled from on to off.
[0062] When the host device 2 sets the PWRDIS signal to "H" at time t4 and the level of the PWRDIS_PMIC terminal of the power supply circuit 32 becomes "H" (Yes in S115), the power supply circuit 32 sets the level of the OPM terminal to "L" at time t 4a Since the OPM terminal is connected to the PLN terminal, when the level of the OPM terminal becomes "L", the level of the PLN terminal also becomes "L". According to the operation programmed in the memory controller 22, when the writing (data backup) of the data being processed to the NAND memory 10 is started, at time t 4b set the level of the PLA terminal to "L", and the level of the Ex_PWR terminal of the power supply circuit 32 also becomes "L" (S116).
[0063] The memory controller 22 sets the level of the PLA terminal to "L" and maintains the level of the Ex_PWR terminal at "L" until the writing of the data being processed to the NAND memory 10 is completed (data backup time) (No in S120). In the example shown in FIG. 9, at time t 5bThe voltage level of the Ex_PWR terminal is maintained at "L" until this time. During this data save time, the memory controller 22 can perform operations such as writing to the NAND memory 10, flashing, and saving unsaved data.
[0064] From time t4 to time t 5b Once the data backup time has elapsed (Yes in S120), the CPU of the memory controller 22 will time t 6b During the period from t7, the level of the PLA terminal is temporarily changed from "L" to "H" (S121). As a result, the level of the input terminal Ex_PWR of the power supply circuit 32 also changes from "L" to "H" (S122).
[0065] When the level of the input terminal Ex_PWR of the power supply circuit 32 becomes "H", the level of the PWRDIS_PMIC terminal is "H". As a result, the power supply circuit 32 controls the output of the power supply VCC from on to off at time t7 (S140). In other words, it disables the supply of power supply VCC.
[0066] The power supply circuit 32 monitors the level of the PWRDIS_PMIC terminal (No in S146). When the level of the PWRDIS_PMIC terminal changes from "H" to "L" at time t8 (Yes in S146), the power supply circuit 32 9b At this point, the output of the power supply VCC is turned on (S155), and time t 9c At this point, the level of the OMP terminal is changed from "L" to "H" (S166). Since the OMP terminal of the power supply circuit 32 is connected to the PLN terminal of the memory controller 22, the level of the PLN terminal becomes "H". The CPU of the memory controller 22 operates at time t 9b When power supply VCC is received, an initialization operation is performed, and time t 10a In this configuration, the PLN terminal is set to input mode and the PLA terminal to output mode, both at a "H" level. Since the PLA terminal of the memory controller 22 is connected to the Ex_PWR terminal of the power supply circuit 32, the level of the Ex_PWR terminal is also set to "H" (S167).
[0067] According to this embodiment, since the output of the power supply VCC is controlled using existing PLN terminals or PLA terminals, data save time can be secured with a simple configuration without adding external circuits or the like.
[0068] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]
[0069] 1...Memory system, 2...Host device, 10...NAND memory, 20...Memory controller, 30...Power supply circuit, 35...Connector, Q...Switching element.
Claims
1. A non-volatile memory capable of storing data, A memory controller capable of executing commands on the aforementioned memory, A power supply circuit that generates a second power supply to be supplied to the memory and the memory controller using a first power supply supplied from an external source, The device comprises a connection line that transmits a request signal to the power supply circuit to disable the supply of the second power supply for a first period of time, and a switching element that opens and closes the connection line. The aforementioned memory controller Upon receiving the aforementioned request signal, After a second period shorter than the first period has elapsed since the reception of the request signal, the switching element is closed and the request signal is supplied to the power supply circuit. The aforementioned power supply circuit is In response to the receipt of the request signal, the supply of the second power source is disabled. The aforementioned memory controller The power supply circuit restarts the supply of the second power after the first period has elapsed since the receipt of the request signal. A memory system characterized by the following:
2. A non-volatile memory capable of storing data, A memory controller capable of executing commands on the aforementioned memory, The system includes a power supply circuit that generates a second power supply to be supplied to the memory and the memory controller using a first power supply supplied from an external source, The aforementioned memory controller A request signal is received to disable the supply of the second power source for a first period of time. After a second period shorter than the first period has elapsed since the receipt of the request signal, a deactivation signal is transmitted to the power supply circuit. The aforementioned power supply circuit is Upon receiving the aforementioned request signal, Based on the request signal and the deactivation signal, the supply of the second power supply is deactivated. The aforementioned memory controller The power supply circuit restarts the supply of the second power after the first period has elapsed since the receipt of the request signal. A memory system characterized by the following:
3. A non-volatile memory capable of storing data, A memory controller capable of executing commands on the aforementioned memory, The system includes a power supply circuit that generates a second power supply to be supplied to the memory and the memory controller using a first power supply supplied from an external source, The aforementioned power supply circuit is A request signal is received to disable the supply of the second power source for a first period of time. In response to receiving the aforementioned request signal, a power loss signal is transmitted to the memory controller to notify of the power loss. The aforementioned memory controller Upon receiving the aforementioned power loss signal, After a second period shorter than the first period has elapsed since the reception of the power loss signal, a power loss confirmation signal is transmitted to the power supply circuit to confirm the power loss. The aforementioned power supply circuit is Upon receiving the aforementioned power loss confirmation signal, Based on the request signal and the power loss confirmation signal, the supply of the second power source is disabled. The aforementioned memory controller The power supply circuit restarts the supply of the second power after the first period has elapsed since the receipt of the request signal. A memory system characterized by the following:
4. The memory system according to any one of claims 1 to 3, characterized in that the request signal is a PWRDIS signal sent from a host device.
5. Non-volatile memory for storing data, A memory controller capable of executing commands on the aforementioned memory, A power supply circuit that generates a second power supply to be supplied to the memory and the memory controller using a first power supply supplied from an external source, A control method for a memory system comprising a connection line that transmits a request signal to the power supply circuit to disable the supply of the second power supply for a first period of time, and a switching element that opens and closes the connection line, The aforementioned memory controller Upon receiving the aforementioned request signal, After a second period shorter than the first period has elapsed since the reception of the request signal, the switching element is closed and the request signal is supplied to the power supply circuit. The aforementioned power supply circuit In response to the receipt of the request signal, the supply of the second power source is disabled. The aforementioned memory controller The power supply circuit restarts the supply of the second power after the first period has elapsed since the receipt of the request signal. A control method characterized by the following.