Packaged transistor and its mounting process using channel-forming die attach material

Abstract

The package includes a circuit including at least one active area and at least one sub-device area, a support configured to support the circuit, and a die attach material, the circuit being mounted to the support using the die attach material, the die attach material including at least one channel configured to allow escape of gas generated during curing of the die attach material from the die attach material.

Description

Technical Field

[0001] Cross - reference to Related Applications This application is a continuation - in - part of U.S. Patent Application No. 16 / 868,639, filed on May 7, 2020, the entire content of which is incorporated herein by reference. This application also claims the benefit of U.S. Provisional Patent Application No. 63 / 055,541, filed on July 23, 2020, the entire content of which is incorporated herein in its entirety without omission.

[0002] The present disclosure relates to semiconductor die attach materials having at least one channel. The present disclosure further relates to radio frequency (RF) packages having semiconductor dies, such as Group III nitride dies, having die attach materials with at least one channel that unrestrictedly includes multiple channels or grooves, such as a mesh configuration, intersecting channels or grooves, and / or channels or grooves of different shapes.

Background Art

[0003] One of the latest and most important die attach materials for low-cost packaging, replacing AuSn (gold-tin solder), is a material called silver sintered die attach material. These materials consist of 75-90% small silver particles by bulk mass, with the remainder being volatile organic compounds. These materials are extruded from needles, screen printed, or by inkjet printing. Die attach materials provide a high thermal conductivity path for high-power heat dissipation through the material and a strong mechanical bond between the die and the package to which it is attached. After extrusion or screen printing onto a support such as a lead frame or submount, and placement of the die on top, the material is cured and solidified. In the curing of die attach materials composed of metal particles and volatile organic compounds such as plastics, polymers, or resins, the volatile organic compounds escape as gas. That is, bubbles are created in the die attach material that remain unchanged during solidification. In high-power heat dissipation applications on large-area semiconductor dies, such as Group III nitride microwave monolithic integrated circuits or large-area Group III nitride GaN HEMTs, voids formed during the curing or mounting process can be located beneath the transistor area of ​​the semiconductor die, potentially hindering heat conduction from the transistors. Because the location of generated gases is partially random and sintered materials are generally viscous, there is little void aggregation or void bubbles "retreating" to the edges of the material before complete solidification. Generally, as semiconductor dies become larger, such as in MMICs, the concentration of voids in the central area of ​​the semiconductor die increases, making it more likely that voids will form beneath critical active transistor areas.

[0004] Mounting a Group III nitride die, such as an MMIC, to a support structure (metal lead frame, metal flange, or other suitable submount or support structure, etc.) is part of the packaging process. The package often includes protective material formed on or around the die, which adheres to various parts of the die and / or support structure. However, the protective material may not reliably adhere to various parts of the die and / or support structure, which can cause package defects. In particular, protective packaging materials such as plastics, synthetic materials, or other suitable materials may not reliably adhere to various metal parts of the support structure.

[0005] Therefore, there is a need for equipment and processes that limit the formation of voids in the die attach material of semiconductor dies. Furthermore, there is a need for equipment and processes that improve the adhesion of protective materials to the semiconductor die package. [Overview of the project]

[0006] One aspect of the present disclosure includes a semiconductor device comprising: a semiconductor die; a support portion; and a die attach material having at least one channel, wherein at least a portion of the at least one channel is positioned between the semiconductor die and the support portion, and gas generated when the semiconductor die is attached to the support portion can be released from the die attach material.

[0007] One aspect of the present disclosure includes a semiconductor device mounting process comprising: providing a semiconductor die; providing a support; and forming a die attach material having at least one channel, wherein at least a portion of the at least one channel is positioned between the semiconductor die and the support, and gas generated during the attachment of the semiconductor die to the support can be released from the die attach material.

[0008] One aspect of the present disclosure includes a semiconductor device comprising: a semiconductor die including at least one sub-device area; a support portion; and a die attach material having at least one channel, wherein at least a portion of the at least one channel is positioned between the at least one sub-device area of ​​the semiconductor die and the support portion, and gas generated during attachment of the semiconductor die to the support portion can be released from the die attach material.

[0009] One aspect of the present disclosure includes a semiconductor device comprising: a semiconductor die; a support portion; a die attach material having at least one channel; and an overmolded configuration enclosing at least the semiconductor die and at least a portion of which is attached to the die attach material.

[0010] Additional features, advantages, and aspects of this disclosure may be specified or clarified by the following detailed description, drawings, and review of the claims. Furthermore, the above summary of this disclosure and the following detailed description are illustrative and not intended to limit the scope of this disclosure in terms of the claims, and it should be understood that additional explanations are provided.

[0011] The accompanying drawings, included for a deeper understanding of this disclosure, are incorporated herein and constitute part of it, illustrating aspects of this disclosure and, together with the detailed description, are useful in explaining the principles of this disclosure. No attempt has been made to provide structural details of this disclosure beyond what is necessary for a basic understanding of this disclosure and the various ways in which it may be implemented. [Brief explanation of the drawing]

[0012] [Figure 1] This is a perspective view of the package related to this disclosure. [Figure 2] Figure 1 is a partial top view of the package. [Figure 3A] This is a partial cross-sectional view of the package along line III-III in Figure 2. [Figure 3B] This is a partial cross-sectional view of another aspect of Figure 3A. [Figure 4]It is a partial view of FIG. 3A. [Figure 5] It is a diagram showing an exemplary layout of a die attach material according to the present disclosure. [Figure 6] It is a diagram showing various exemplary dimensions of channels of a die attach material according to the present disclosure. [Figure 7] It is a diagram showing an exemplary layout of a die attach material according to the present disclosure. [Figure 8] It is a diagram showing an exemplary layout of a die attach material according to the present disclosure. [Figure 9] It is a diagram showing an exemplary layout of a die attach material according to the present disclosure. [Figure 10] It is a diagram showing an exemplary layout of a die attach material according to the present disclosure. [Figure 11] It is a partial top view of the package according to FIG. 1. [Figure 12] It is a partial top view of the package according to FIG. 11. [Figure 13] It is a partial top view of the package according to FIG. 11. [Figure 14] It is a partial top view of the package according to FIG. 13. [Figure 15A] It is a partial cross-sectional view of the package along line XV-XV of FIG. 14. [Figure 15B] It is a partial cross-sectional view of another aspect of FIG. 15A. [Figure 16] It is a partial top view of the package according to FIG. 11. [Figure 17] It is a diagram showing various exemplary dimensions of channels of a die attach material according to the present disclosure. [Figure 18] It is a partial cross-sectional view of the package along line XV-XV of FIG. 14. [Figure 19] It is a partial top view of the package according to FIG. 11. [Figure 20] It is a partial top view of the package according to FIG. 11. [Figure 21] It is a diagram showing a process for constructing a package according to the present disclosure. [Figure 22] The top view of an exemplary embodiment of a package according to FIG. 1. [Figure 23] An enlarged schematic view of a subset of unit cell transistors of the transistor amplifier of FIG. 22. [Figure 24] A schematic cross-sectional view taken along line XXIV-XXIV of FIG. 23. [Figure 25] A partial top view of a package according to the present disclosure.

MODE FOR CARRYING OUT THE INVENTION

[0013] Aspects of the present disclosure and its various features and advantageous details will be described in more detail with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and elaborated in the following description. Note that the features shown in the drawings are not necessarily drawn to scale, and as will be appreciated by those skilled in the art, features of one aspect may be adopted in other aspects even without explicit indication herein. Descriptions of well-known components and processing techniques may be omitted so that the aspects of the present disclosure are not needlessly obscured. The examples used herein are merely intended to facilitate understanding of how the present disclosure may be implemented and to enable those skilled in the art to implement aspects of the present disclosure. Therefore, the examples and aspects herein should not be construed as limiting the scope of the present disclosure, which is defined only by the appended claims and the applicable law. Further, it should be noted that throughout the plurality of drawings and the various embodiments of the disclosure, the same reference numerals represent similar parts.

[0014] In this specification, terms such as first, second, etc., may be used to represent various elements, but it should be understood that these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any combination of one or more of the relevant list items.

[0015] When an element such as a layer, region, or substrate is mentioned as existing "on top of" another element, or as extending "on top of" another element, it is understood that the element may exist directly on the other element, or extend directly onto the other element, or an intervening element may be present. In contrast, when an element is mentioned as existing "directly on top of" another element, or as extending "directly on top of" another element, there is no intervening element. Similarly, when an element such as a layer, region, or substrate is mentioned as existing "above" another element, or as extending "above" another element, it is understood that the element may exist directly above the other element, or extend directly above the other element, or an intervening element may be present. In contrast, when an element is mentioned as existing "directly above" another element, or extending "directly above" another element, there is no intervening element. Furthermore, when an element is described as being "connected" or "joined" to another element, it is understood that the element may be directly connected or joined to the other element, or that an intermediary element may be present. In contrast, when an element is described as being "directly connected" or "directly joined" to another element, it is understood that no intermediary element exists.

[0016] In this specification, relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” or “vertical” may be used to describe the relationship between one element, layer, or area and another element, layer, or area, as shown in the drawings. It is understood that these terms and the terms described above are intended to include various orientations of the apparatus, in addition to the orientations shown in the drawings.

[0017] The technical terms used herein are intended solely to represent specific aspects and are not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless otherwise explicitly stated in the context. As used herein, the terms “comprise,” “comprising,” and / or “include,” “including,” indicate the presence of the features, integers, steps, actions, elements, and / or components referred to, but do not preclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which this disclosure belongs. Terms used herein should be construed to have meanings consistent with their respective meanings in the context of this specification and the related art, and it should be further understood that, unless explicitly defined herein, they should not be construed in an ideal or overly formal sense.

[0019] Aspects of this disclosure are applicable to low-cost packaging using silver sintered die attach materials. These materials may comprise, for example, small silver particles comprising 75-90% of the bulk mass, and other volatile organic compounds. These materials can be dispensed by needle extrusion, screen printing, inkjet extrusion, and / or similar methods. The die attach material may provide high thermal conductivity pathways for high-power heat dissipation through the material and a strong mechanical bond to the package in which the die is mounted. The material is cured and solidified after extrusion, screen printing, and / or similar methods onto support parts such as lead frames, submounts, and / or similar parts, and after the die is placed on top. In the curing of die attach materials composed of metal particles and volatile organic compounds such as plastics, polymers, or resins, the volatile organic compounds may release gases, creating bubbles that may remain unchanged in the die attach material during solidification.

[0020] For high-power heat dissipation applications on large-area semiconductor dies, such as Group III nitride microwave monolithic integrated circuits or large-area Group III nitride GaN HEMTs, this disclosure provides numerous configurations and processes that ensure the reduction of voids formed during the curing or mounting process and located beneath the transistor area of ​​the semiconductor die, thereby hindering heat conduction from the transistors. Because the location of generated gases is partially random and sintered materials are generally viscous, this disclosure utilizes embodiments that encourage the "relocation" of bubbles to the edges of the material before complete solidification. Generally, as semiconductor dies become larger, such as in MMICs, various embodiments of this disclosure become more beneficial, enabling the reduction and / or removal of voids found in the central area of ​​the semiconductor die, which may be critical active transistor areas.

[0021] In certain embodiments, the die attach material comprises metal particles in an organic material such as a sintered die attach material. In certain embodiments, the sintered die attach material is a silver sintered die attach material or a copper sintered die attach material. This material may consist of small silver particles making up the majority of the bulk mass, and other volatile organic compounds. These materials can be dispensed by needle ejection, screen printing, inkjet ejection, and / or similar methods. The die attach material provides a high thermal conductivity path for high-power heat dissipation through the die attach material and a strong mechanical bond between the die and the package to which it is internally mounted.

[0022] The die attach material is extruded or screen printed onto a substrate or lead frame, and after the die is placed on top, it is cured and solidified. During curing, volatile organic compounds (VOCs) in the die attach material escape. In particular, the VOCs create small bubbles of a shape that remain unchanged in the die attach material during solidification. For high-power heat dissipation applications on large-area integrated circuits such as monolithic integrated circuits, monolithic microwave integrated circuits (MMICs), multi-cell transistor integrated circuits, integrated circuits with arrays of field-effect transistors (FETs), multi-transistor integrated circuits, multi-circuit integrated circuits, multi-unit integrated circuits, multi-area integrated circuits, multi-active-area integrated circuits, compound semiconductor devices, high-power compound semiconductor devices, high-frequency compound semiconductor devices, and / or similar circuits, it is important that voids formed during curing do not form beneath the active parts such as the transistor sections of the integrated circuit. Similarly, for discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-area discrete devices, and / or similar devices, it is important that voids formed during curing do not form beneath the active parts such as the transistor sections of the discrete devices. This is because voids obstruct heat transfer from active areas, such as the area where transistors are mounted. Generally, the location of the generated gases is partially random, and since sintered materials are generally highly viscous, there is little void aggregation during hardening, nor are there many void bubbles that "retreat" to the edges of the die material before complete solidification. Generally, the larger the integrated circuit, the higher the void density. Furthermore, high-density voids can be observed in the central area of ​​the integrated circuit. Such voids can be detected by X-rays.

[0023] In some embodiments, this disclosure relates to intentionally configured channels (for example, channels configured using screen printing stencils) that allow gas escape voids to be relocated to an area near, but not directly beneath, an active area such as an active transistor. Note that sintered materials such as silver sintered materials behave considerably differently from conventional solders. Therefore, the application of the channel formation void reduction technique described in this disclosure using sintered die attach materials results in the unexpected outcome of improved cooling and / or robustness. Furthermore, the application of the channel formation void reduction technique described in this disclosure to Group III nitride semiconductor dies such as GaN or its alloy-based HEMTs and MMICs using sintered die attach materials results in the unexpected outcome of improved cooling and / or robustness. Furthermore, the application of the channel formation void reduction technique described in this disclosure to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-area discrete devices, and / or similar devices using sintered die attach materials results in the unexpected outcome of improved cooling and / or robustness. In particular, the applicant tested many different processes for reducing voids and found that the channel formation method of this disclosure presents and provides the best results.

[0024] In this industry, silver sintered die attach materials are primarily used for mounting discrete transistors. Generally, discrete transistors have an elongated form factor (e.g., a path of less than 0.6 mm) and generally do not experience the same void problems because voids can be relocated to the free edge. As the industry moves towards larger dies with higher power and higher integration, particularly towards more MMIC-based mountings, the problem of die attach void formation due to inevitable gas leakage is becoming more significant. One way to address this problem is to X-ray inspect all devices as a "screening" procedure during manufacturing and discard devices that have significant voids formed directly beneath the active transistor area. According to the disclosed technology, void formation beneath the active transistor area can be reduced to near zero, eliminating the need for "screening". Therefore, the technology presented in this disclosure offers the advantage of improved yield, as well as the possibility of implementing the technology for current and future low-cost, high-power GaN MMIC-based solutions. Furthermore, the technology presented in this disclosure requires little to no additional processing or screening steps in manufacturing. While generally more advantageous in the context of larger MMICs, the present invention can also improve the die-attachment of discrete transistors, such as Group III nitride-based HEMTs and their packaging. In particular, the present invention can also improve the die-attachment of discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-area discrete devices, and / or similar devices.

[0025] This technology has many potential embodiments. In this regard, this disclosure describes a process and apparatus utilizing silver sintered die attach material. However, the process and apparatus of this disclosure may also be applicable to future die attach materials, such as copper sintered material currently under development. Furthermore, this disclosure indicates many potential channel locations. However, this disclosure is not limited to these potential locations, and any number of potential embodiments are conceivable regarding locations where channels can be installed and / or positioned. In certain embodiments utilizing monolithic integrated circuits such as MMICs, there may be an elongated active area, such as a transistor area, and a widened passive area, such as a matching component, such as resistors, capacitors, inductors, and / or similar components. In certain embodiments, this disclosure considers placing an elongated channel below the passive area near the active area. In some embodiments of this disclosure, it is possible to place a single channel on one side of some active area, place channels on both sides of the active area, and / or similar configurations. In various embodiments of this disclosure, the channel does not need to be linear. In particular, channels can be angled, curved, and / or similar configurations to reduce targeted voids and avoid affected areas.

[0026] Furthermore, this disclosure considers the formation of channels by screen printing using a die attach material. However, die attach materials having channels can also be mounted using other die attach methods such as needle extrusion and jet extrusion. The applicant has found many beneficial applications by implementing the process and apparatus of this disclosure. For example, the process and apparatus of this disclosure are implemented with sintered die attach material on GaN-on-SiC (silicon carbide). However, it is believed that similar beneficial applications can be realized for GaN-on-Si, LDMOS (laterally diffused metal oxide semiconductor), and / or similar materials by using sintered die attach material. In particular, the applicant notes that high-power applications in particular may benefit from the process of this disclosure. For example, the applicant considers the use of the process of this disclosure for MMICs or any other type of apparatus of the disclosure configured using the above-described technology. The applicant also notes that custom stencils for screen printing sintered die attach material containing gas escape channels are very inexpensive for various applications such as MMIC die attach.

[0027] The applications of this disclosure may also relate to sintered die attach materials such as sintered silver, sintered copper, and / or similar materials. It is expected that the formation of gas voids will be virtually impossible to eliminate. In this regard, this disclosure provides a process that prevents the formation and encapsulation of these voids directly beneath high-temperature active areas such as transistor areas in MMIC dies, multi-cell transistor integrated circuit dies, integrated circuit dies having arrays of field-effect transistors (FETs), multi-transistor integrated circuit dies, multi-circuit integrated circuit dies, multi-unit integrated circuit dies, multi-area integrated circuit dies, multi-active-area integrated circuit dies, compound semiconductor devices, high-power compound semiconductor devices, high-frequency compound semiconductor devices, and / or similar devices, by means of escape paths or predetermined collection areas for these voids. This disclosure is also applicable to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-area discrete devices, and / or similar devices. However, the process of this disclosure is particularly useful in die attaching integrated circuits such as MMICs, as these utilize much larger areas and include vast passive areas.

[0028] Figure 1 is a perspective view of the package relating to this disclosure.

[0029] Figure 2 is a partial top view of the package relating to Figure 1.

[0030] Figure 3A is a partial cross-sectional view of the package along line III-III in Figure 2.

[0031] In particular, Figures 1, 2, and 3A show an exemplary embodiment of package 100, which may include one or more arbitrary features, components, configurations, etc., as described herein. Specifically, Figures 1, 2, and 3A show package 100 that can be implemented as a power package, power amplifier package, microwave power package, microwave power amplifier package, radio frequency (RF) package, RF amplifier package, RF power amplifier package, RF power transistor package, RF power amplifier transistor package, and / or similar, as described herein. Referring to Figure 1, package 100 may have one or more input / output pins 134.

[0032] Referring to Figures 2 and 3A, the package 100 may comprise a semiconductor die 200 having one or more active areas 400. In this regard, the package 100 shown in Figures 2 and 3A shows two of the one or more active areas 400. However, the package 100 may contain any number of one or more active areas 400. The semiconductor die 200 may be coupled to one or more input / output pins 134 via one or more interconnects 120, one or more interconnects 190, and / or other connections.

[0033] One or more interconnects 120 and / or one or more interconnects 190 may utilize one or more wires, leads, vias, edge plating, circuit traces, tracks, ball bonding, wedge bonding, compliant bonding, ribbon bonding, metal clip attachments, and / or similar. In one embodiment, one or more interconnects 120 and / or one or more interconnects 190 may utilize the same type of connection. In one embodiment, one or more interconnects 120 and / or one or more interconnects 190 may utilize different types of connections.

[0034] One or more interconnects 120 and / or one or more interconnects 190 may contain various metallic materials, including one or more of aluminum, copper, silver, gold, and / or similar metals. In one embodiment, one or more interconnects 120 and / or one or more interconnects 190 may utilize the same type of metal. In one embodiment, one or more interconnects 120 and / or one or more interconnects 190 may utilize different types of metals.

[0035] One or more interconnections 120 and / or one or more interconnections 190 may be connected by adhesive, soldering, sintering, eutectic bonding, thermal compression bonding, ultrasonic bonding / welding, clip components, and / or similar, as described herein. In one embodiment, the same type of connection may be used for these connections. In one embodiment, different types of connections may be used for these connections.

[0036] One or more active areas 400 may be any heat-generating area within the semiconductor die 200 and / or any area that may benefit from heat flux, heat transfer, cooling, and / or similar effects. One or more active areas 400 may be an area where one or more transistors are located, an area where one or more transistor amplifiers are located, an area where one or more transformers are located, an area where one or more voltage regulators are located, an area where one or more heat-generating devices are located, an area where one or more devices that benefit from low-temperature operation are located, an area where one or more semiconductor devices are located, and / or a combination thereof.

[0037] One or more active areas 400 may be any area on which one or more semiconductor devices are located. One or more semiconductor devices may be wide bandgap semiconductor devices, ultra-wideband devices, GaN-based devices, GaN-on-SiC devices, GaN-on-Si devices, metal-semiconductor field-effect transistors (MESFETs), metal oxide field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), lateral diffusion metal oxide semiconductors (LDMOSs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide bandgap (WBG) semiconductors, field-effect transistors (FETs), etc., and / or combinations thereof.

[0038] One or more semiconductor devices may implement components such as amplifiers, radar amplifiers, radar components, microwave radar amplifiers, power modules, gate drivers, general-purpose broadband components, telecommunications components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, Doherty configurations, and / or similar. The L-band is the IEEE designation for various frequencies in the radio spectrum from 1 to 2 gigahertz (GHz). The S-band is the IEEE designation for a portion of the microwave band in the electromagnetic spectrum covering frequencies from 2 to 4 GHz. The X-band is the designation for frequency bands in the microwave radio domain of the electromagnetic spectrum, indeterminately set at approximately 7.0 to 11.2 GHz. The C-band is the designation given to radio frequencies from 500 to 1000 MHz. The Ku-band is a portion of the electromagnetic spectrum in the microwave frequency range from 12 to 18 GHz.

[0039] The semiconductor die 200 may further include at least one sub-device area 300. At least one sub-device area 300 may be defined as a passive area. At least one sub-device area 300 may be implemented as an RF device as described herein. At least one sub-device area 300 may support various functional technologies as inputs, outputs, and / or intra-stage functions, and / or similar functions to package 100 by implementing resistors, inductors, capacitors, metal oxide silicon (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power couplers, power distributors, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, fundamental frequency matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), matching networks, and / or similar, and / or combinations thereof, one or more of these.

[0040] The package 100 may include a support portion 102. The support portion 102 may be implemented as a support portion, surface, package support portion, package surface, package support surface, metal submount, flange, metal flange, heat sink, common source support portion, common source surface, common source package support portion, common source package surface, common source package support surface, common source flange, common source heat sink, lead frame, metal lead frame, and / or similar, and / or combination thereof. The support portion 102 may include a metallic material, insulating material, dielectric material, etc., and / or combination thereof. The support portion 102 may isolate and protect the semiconductor die 200, one or more active areas 400, and / or similar from the external environment, while simultaneously dissipating the heat generated by the semiconductor die 200, one or more active areas 400, at least one sub-device area 300, and / or similar.

[0041] Referring to Figure 3A, the semiconductor die 200 may be mounted on the support 102 using a die attach material 124. The die attach material 124 may comprise one or more channels 122. In particular, one or more channels 122 may be positioned vertically downward along the Y-axis with respect to one or more active areas 400, but not directly below the one or more active areas 400. In other words, one or more channels 122 may be positioned vertically downward along the Y-axis with respect to one or more active areas 400 and offset from the active areas 400 along the X-axis, as otherwise described herein. In one or more embodiments, the die attach material 124 may not form an electrical connection with the semiconductor die 200. More specifically, the die attach material 124 may be used solely for attaching the semiconductor die 200 to the support 102. Therefore, in this respect, the bottom of the semiconductor die 200 has no electrical contacts. In one or more embodiments, the die attach material 124 may form a single electrical connection with the semiconductor die 200. More specifically, the die attach material 124 may be used as a single electrical connection to the support portion 102 of the semiconductor die 200. In this respect, the bottom of the semiconductor die 200 may form a single electrical connection.

[0042] One or more channels 122 may be located below at least one sub-device area 300. In certain embodiments, one or more channels 122 may be located directly below at least one sub-device area 300 along the Y-axis. For example, one or more channels 122 may be located below or directly below at least one sub-device area 300, flux pad, and / or similar along the Y-axis and X-axis.

[0043] The die attach material 124 may include one or more metallic materials and one or more non-metallic materials. The one or more metallic materials may include silver, copper, gold, tin, lead, etc., and / or combinations thereof. The one or more metallic materials may include powdered metallic materials configured to be sintered. In one embodiment, the die attach material 124 may contain metallic particles as metallic material at a ratio of 75% to 90% of its bulk mass, with the remainder being non-metallic materials. In one embodiment, the die attach material 124 includes a sintered material. In one embodiment, the die attach material 124 includes at least one of a silver sintered material or a copper sintered material.

[0044] One or more nonmetallic materials may include organic materials, volatile organic materials, epoxy materials, epoxy, binder materials, gas-generating materials, etc., and / or combinations thereof. In one embodiment, the die attach material 124 may include silver, silver configured to be sintered, silver sintered material, etc., and / or combinations thereof. In one embodiment, the die attach material 124 may contain 75% to 90% silver particles as metallic material, with the remainder being nonmetallic material. In one embodiment, the die attach material 124 may contain 75% to 90% silver particles as metallic material, with volatile organic materials being other nonmetallic materials.

[0045] Furthermore, within the package 100, the semiconductor die 200 may be positioned on the support portion 102. Referring to Figure 1, the package 100 may comprise an overmolding 130 and / or similar. The overmolding 130 may substantially enclose the semiconductor die 200, one or more active areas 400, and / or other components of the package 100. The overmolding 130 may be formed of plastic material, molding compound, synthetic material, plastic polymer material, etc., and / or a combination thereof, and may provide protection from the external environment by injection molding or compression molding around the support portion 102 and the semiconductor die 200.

[0046] Alternatively, the package 100 may be implemented to include an open cavity configuration suitable for use with the semiconductor die 200. In particular, the open cavity configuration may utilize an open cavity package design. In some embodiments, the open cavity configuration may include an enclosure such as a lid to protect interconnects, circuit components, the semiconductor die 200, and / or similar components. The package 100 may comprise a ceramic body, a lid, and / or one or more metal contacts.

[0047] Package 100 may be implemented as an MMIC RF package and house an RF device. The RF device may be configured and implemented in at least part of at least one sub-device area 300. In particular, the RF device may be configured and implemented in at least one sub-device area 300 and support various functional technologies as inputs, outputs, and / or intra-stage functions, and / or similar functions to package 100 by implementing one or more of the following: resistors, inductors, capacitors, metal oxide silicon (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power couplers, power distributors, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, fundamental frequency matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), matching networks, and / or similar, and / or combinations thereof. Package 100 implemented as an MMIC package may further include one or more active areas 400. Package 100, implemented as an MMIC package, may further implement one or more active areas 400 and at least one sub-device area 300 configured to include, connect, support, etc., radar transmitters, radar transmitter functions, microwave radar transmitters, microwave radar transmitter functions, radar receivers, radar receiver functions, microwave radar receiver functions, and / or similar devices.

[0048] Package 100 may be implemented as a power package, power amplifier package, microwave power package, microwave power amplifier package, radio frequency (RF) package, RF amplifier package, RF power amplifier package, RF power transistor package, RF power amplifier transistor package, and / or similar, and at least one sub-device area 300 and one or more active areas 400 may be implemented as a radio frequency device as described herein, and may include, connect, support, etc., a transmitter, transmitter function, receiver, receiver function, transceiver, transceiver function, matched network function, harmonic termination circuit, integrated passive device (IPD), etc., and / or combinations thereof. At least one sub-device area 300 and / or one or more active areas 400 implemented as a radio frequency device may be configured to carry, or support, data such as permissible transmitter power output, harmonics, band edge requirements, etc., and / or combinations thereof, by transmitting and modulating radio waves as described herein. At least one sub-device area 300 and / or one or more active areas 400 implemented as radio frequency devices may be configured to receive and demodulate radio waves, or to support such reception and demodulation. At least one sub-device area 300 and / or one or more active areas 400 implemented as radio frequency devices may be configured to transmit and modulate radio waves, or to support such transmission and demodulation, or to receive and demodulate radio waves, or to support such reception and demodulation.

[0049] Figure 3B is a partial cross-sectional view of another aspect of Figure 3A.

[0050] In particular, Figure 3B shows one embodiment of a package 100 on which multiple semiconductor dies 200 are mounted. Various embodiments, configurations, components, processes, and / or similars may be implemented in conjunction with the embodiment of Figure 3B, as described herein. Further reference to Figure 3B, one or more of the semiconductor dies 200 may be configured to be mounted as one embodiment of at least one sub-device area 300, and one or more of the semiconductor dies 200 may be configured to be mounted as one embodiment of an active area 400. In certain embodiments, one or more of the multiple semiconductor dies 200 may be mounted as individual devices. In certain embodiments, each of the multiple semiconductor dies 200 may be mounted as an individual device.

[0051] Referring to Figure 3B, a plurality of semiconductor dies 200 may be mounted on a support 102 using a die attach material 124. The die attach material 124 may comprise one or more channels 122. In particular, one or more channels 122 are positioned vertically downward along the Y-axis with respect to one or more semiconductor dies 200 mounted as active areas 400, but not directly below the one or more active areas 400. In other words, one or more channels 122 are positioned vertically downward along the Y-axis with respect to one or more semiconductor dies 200 mounted as active areas 400, and may be offset from the active areas 400 along the X-axis as otherwise described herein.

[0052] Referring further to Figure 3B, one or more channels 122 may be located beneath the semiconductor die 200, which is implemented as at least one sub-device area 300. In certain embodiments, one or more channels 122 may be located directly beneath the semiconductor die 200, which is implemented as at least one sub-device area 300, along the Y-axis. For example, one or more channels 122 may be located beneath or directly beneath the semiconductor die 200, which is implemented as at least one sub-device area 300, flux pad, and / or similar, along the Y-axis and X-axis.

[0053] Figure 4 is a partial view of Figure 3A.

[0054] Figure 5 shows an exemplary layout of the die attach material relating to this disclosure.

[0055] In particular, Figure 4 is a detail view of one or more channels 122 shown in Figure 3A and applicable to any embodiment described herein. Referring to Figure 4, one or more channels 122 may be defined by the lower surface 280 of the semiconductor die 200 and the upper surface 180 of the support portion 102. In one embodiment, the lower surface 280 of the semiconductor die 200 may extend substantially parallel to the X-axis, as shown in Figure 4, the upper surface 180 of the support portion 102 may extend substantially parallel to the X-axis, as shown in Figure 4, and one or more side edges 128 may extend substantially parallel to the Y-axis, as shown in Figure 4. In this regard, substantially parallel may be defined as 0°~15°, 0°~2°, 2°~4°, 4°~6°, 6°~8°, 8°~10°, 10°~12°, or 12°~15°. In other embodiments, one or more channels 122 may be composed of and defined by other components of the package 100.

[0056] However, during the manufacturing of package 100, the shape of one or more channels 122 may change due to expansion, migration, and / or similar changes. Therefore, various embodiments of one or more channels 122 may vary slightly during manufacturing, as described herein.

[0057] Figure 5 shows an exemplary configuration of a die attach material 124 placed on the support portion 102. In particular, the die attach material 124 may comprise one or more channels 122. The one or more channels 122 are positioned vertically below one or more active areas 400 (shown by dashed lines in Figure 5) along the Y-axis, but not directly below the one or more active areas 400. In other words, the one or more channels 122 are positioned vertically below the one or more active areas 400 along the Y-axis and offset from the active areas 400 along the X-axis.

[0058] One or more channels 122 may be located below at least one sub-device area 300. In certain embodiments, one or more channels 122 may be located directly below at least one sub-device area 300 along the Y-axis. For example, one or more channels 122 may be located below or directly below at least one sub-device area 300, flux pad, and / or similar along the Y-axis and X-axis.

[0059] One or more channels 122 may include one or more exhaust ports 126 and one or more side edges 128. One or more channels 122 may be located in the X-axis and Z-axis planes parallel to the upper surface 180 of the support portion 102, and may be rectangular, polygonal, circular, free-form, continuous, discontinuous, and / or combinations thereof.

[0060] One or more channels 122 may divide the die attach material 124 in the X and Z planes parallel to the upper surface 180 of the support portion 102. As shown in Figure 5, two of the one or more channels 122 divide the die attach material 124 into three different parts. The package 100 may include any number of the one or more channels 122 and any number of parts of the die attach material 124.

[0061] One or more side edges 128 of one or more channels 122 may form a surface of the die attach material 124 that allows gases generated during the curing of the die attach material 124 to be released from the die attach material 124. In particular, one or more channels 122 may form a surface that allows gases generated during curing to be released from the die attach material 124 from below the active area 400 by utilizing one or more side edges 128 of the die attach material 124. More specifically, as shown by arrows in Figure 5, part of which are positioned in the die attach material 124, gases generated during curing below the active area 400 may travel toward one or more side edges 128 of one or more channels 122 and enter one or more channels 122. Thus, one or more channels 122, together with one or more side edges 128, help suppress void formation below the active area 400 by providing a place for gases generated during the curing process to retreat from below the active area 400 into one or more channels 122.

[0062] Subsequently, the gas generated during curing below the active area 400 may enter one or more channels 122. As shown by the arrows positioned within one or more channels 122 as in Figure 5, once the gas is taken into one or more channels 122, it may travel along one or more channels 122 and be discharged from one or more channels 122 through the exhaust port 126.

[0063] In this regard, one or more channels 122 allow for the release of gas generated during curing below the active area 400, thereby suppressing void formation below the active area 400. Thus, one or more channels 122 enhance the cooling function of the support 102 below the active area 400 by increasing the ability of heat generated by the active area 400 to be transferred from the semiconductor die 200 to the support 102. Furthermore, the implementation of one or more channels 122 within the die attach material 124 may be even more beneficial in dealing with various temperature extremes, which are considered more likely in high-power applications of the package 100. In this regard, it is very beneficial to ensure higher performance, higher reliability, and / or similar characteristics by keeping the active area 400 within 5°C of the desired operating temperature range.

[0064] Referring further to Figure 5, one or more channels 122 may have a substantially straight and / or linear configuration 122-1. The substantially straight and / or linear configuration 122-1 may include a first exhaust port 126 at one end and a second exhaust port 126 at the other end. However, the substantially straight and / or linear configuration 122-1 may include only one exhaust port 126 at one end.

[0065] One or more channels 122 may have a plurality of connection sections 122-2 in a substantially straight and / or linear configuration. Each of these sections may be connected at any angle. These angles may include 1° to 359°, 1° to 40°, 40° to 80°, 80° to 120°, 120° to 160°, 160° to 200°, 200° to 240°, 240° to 280°, 280° to 320°, or 320° to 359°. As shown in Figure 5, the plurality of connection sections 122-2 in a substantially straight and / or linear configuration are connected at an angle of approximately 90°. The plurality of connection sections 122-2 in a substantially straight and / or linear configuration may also include a first exhaust port 126 at one end and a second exhaust port 126 at the other end. However, a plurality of connection sections 122-2 having a roughly straight and / or linear configuration may include only one exhaust port 126 at one end.

[0066] One or more channels 122 may result in improved robustness of the die attach material 124, extended lifespan of the die attach material 124, and / or other beneficial improvements. In this regard, it is known that large-area die attach regions are susceptible to various failure mechanisms, such as delamination, cracking, and / or similar phenomena. These various failure mechanisms are thought to be the result of thermal expansion of the materials associated with the die attach material 124, the semiconductor die 200, the support 102, and / or similar components. In this regard, the materials associated with the die attach material 124, the semiconductor die 200, the support 102, and / or similar components may be different materials and may have different coefficients of thermal expansion. Therefore, different materials that may have different coefficients of thermal expansion may result in different expansion when the semiconductor die 200 operates at different temperature extremes. As a result, the package 100, the semiconductor die 200, the die attach material 124, and / or similar components are more likely to experience one of the failure mechanisms.

[0067] One or more channels 122 can reduce the large-area die-attach region. In particular, one or more channels 122 can divide the large-area die-attach region into one or more small-area die-attach regions. Specifically, as shown in Figure 5, two of the one or more channels 122 divide the die-attach material 124 into three different small parts. Therefore, different materials with different thermal expansion coefficients, which can result in different expansions when the semiconductor die 200 operates at various temperature extremes, have smaller portions of die-attach material 124, thus suppressing the amount of expansion. As a result, the likelihood of one of the failure mechanisms occurring in the package 100 is reduced.

[0068] The die attach material 124 may be applied using a screen printing process, a preform process, a needle ejection system, an inkjet ejection system, a masking process, a photogravure process, a transparent film printing process, a photomask process combined with an etching process, a photosensitization process, a laser resist ablation process, a milling process, a laser etching process, a direct metal printing process, a combination thereof, and / or similar processes.

[0069] In one embodiment, the die attach material 124 may be applied using a screen printing process. In this regard, a stencil may be formed having openings that match various configurations of the die attach material 124 and portions that do not allow application of the die attach material 124, matching various positions of one or more channels 122. The stencil may then be applied to the upper surface 180 of the support 102, and the die attach material 124 may be applied to the stencil. By applying a squeegee to the entire stencil, the die attach material 124 may be pressed through the stencil against the upper surface 180 of the support 102, thereby forming the die attach material 124 and one or more channels 122.

[0070] In one embodiment, the die attach material 124 may be formed using a preforming process. In this regard, a preform may be formed that has portions of the die attach material 124 that are absent, in accordance with various configurations of the die attach material 124 and in accordance with various positions of one or more channels 122. The preform may then be applied to the upper surface 180 of the support portion 102 to form the die attach material 124 and one or more channels 122.

[0071] In one embodiment, the die attach material 124 may be applied using a needle dispensing system. In this regard, the needle dispensing system may be configured to operate in a manner that applies the die attach material 124 to the upper surface 180 of the support portion 102, but does not apply the die attach material 124 to the upper surface 180 of the support portion 102 that is aligned with various positions of one or more channels 122.

[0072] In one embodiment, the die attach material 124 may be applied using an inkjet ejection system. In this regard, the inkjet ejection system may be configured to operate in a manner that applies the die attach material 124 to the upper surface 180 of the support portion 102, but does not apply the die attach material 124 to the upper surface 180 of the support portion 102 that is aligned with various positions of one or more channels 122.

[0073] In one embodiment, the die attach material 124 may be applied using a masking process. In this regard, a mask may be formed that has openings that match various configurations of the die attach material 124 and portions that do not allow application of the die attach material 124 to various positions of one or more channels 122.

[0074] Figure 6 shows various exemplary dimensions of the channel of the die attach material relating to this disclosure.

[0075] In particular, the position of one or more channels 122 relative to the active area 400 can be optimized to maximize heat transfer from the active area 400 to the support 102. Also, the position of one or more channels 122 relative to the active area 400 can be optimized to maximize void suppression and / or gas escape from below the active area 400 of gases generated during the curing process. More specifically, the width of one or more channels 122 is shown and specified as distance D1 along the X axis, the distance from the active area 400 to one or more channels 122 is specified as distance D2 along the X axis, the overall length of the die attach material 124 is specified as distance D3 along the X axis, and the width of the active area 400 is specified as distance D4 along the X axis.

[0076] For example, distance D1 may be related to distance D2 as the relationship between the width of one or more channels 122 and the distance from one or more side edges 128 of one or more channels 122 to the edge of the active area 400. Distance D1 may be 20% to 300% of distance D2, 20% to 60% of distance D2, 60% to 100% of distance D2, 100% to 140% of distance D2, 140% to 180% of distance D2, 180% to 220% of distance D2, 220% to 260% of distance D2, or 260% to 300% of distance D2.

[0077] For example, distance D1 may be related to distance D4 as the relationship between the width of one or more channels 122 and the width of the active area 400. Distance D1 may be 20% to 300% of distance D4, 20% to 60% of distance D4, 60% to 100% of distance D4, 100% to 140% of distance D4, 140% to 180% of distance D4, 180% to 220% of distance D4, 220% to 260% of distance D4, or 260% to 300% of distance D4.

[0078] For example, distance D1 may be related to distance D3 as the relationship between the width of one or more channels 122 and the width of the die attach material 124. Distance D1 may be 2% to 40% of distance D3, 2% to 10% of distance D3, 10% to 20% of distance D3, 20% to 30% of distance D3, or 30% to 40% of distance D3.

[0079] The various distances D1, D2, D3, and D4 may also be similarly defined along the Z-axis for the configuration of one or more channels 122, active areas 400, and / or similar formed along the Z-axis.

[0080] Figure 7 shows an exemplary layout of the die attach material relating to this disclosure.

[0081] In particular, Figure 7 shows alternative embodiments of one or more channels 122 that constitute many parts of the die attach material 124. Various embodiments, configurations, components, processes, etc., as described herein, may be implemented in conjunction with the layout of Figure 7. As shown in Figure 7, various embodiments of one or more channels 122 may be connected to constitute various parts of the die attach material 124. In this respect, one or more channels 122 may be connected to form an intersection 170. In one embodiment, one or more channels 122 include a plurality of channels. In one embodiment, one or more channels 122 include at least two intersecting channels. In one embodiment, one or more channels 122 include three or more intersecting channels. In one embodiment, one or more channels 122 may constitute a channel mesh.

[0082] Figure 8 shows an exemplary layout of the die attach material relating to this disclosure.

[0083] In particular, Figure 8 shows alternative embodiments of one or more channels 122 that constitute many parts of the die attach material 124. Various embodiments, configurations, components, processes, etc., as described herein, may be implemented in conjunction with the layout of Figure 8. As shown in Figure 8, various embodiments of one or more channels 122 may be arranged on both sides 172 of one or more active areas 400 to constitute various parts of the die attach material 124. Also, Figure 8 shows one or more channels 122 of a curved configuration 122-3.

[0084] Figure 9 shows an exemplary layout of the die attach material relating to this disclosure.

[0085] In particular, Figure 9 shows alternative embodiments of one or more channels 122 that constitute many parts of the die attach material 124. Various embodiments, configurations, components, processes, etc., as described herein, may be implemented in conjunction with the layout of Figure 9. As shown in Figure 9, various embodiments of one or more channels 122 may be connected to constitute various parts of the die attach material 124. Also, Figure 9 shows alternative embodiments of one or more channels 122 having configurations 122-4 that are angled with respect to both the Z and X axes. In one embodiment, one or more channels 122 include a plurality of channels. In one embodiment, one or more channels 122 include at least two intersecting channels. In one embodiment, one or more channels 122 include three or more intersecting channels. In one embodiment, one or more channels 122 may constitute a channel mesh.

[0086] Figure 10 shows an exemplary layout of the die attach material relating to this disclosure.

[0087] In particular, Figure 10 shows alternative embodiments of one or more channels 122 that constitute many parts of the die attach material 124. As described herein, various embodiments, configurations, components, processes, etc., may be implemented in conjunction with the layout of Figure 10. As shown in Figure 10, various embodiments of one or more channels 122 may be connected to constitute various parts of the die attach material 124. Also, Figure 10 shows the formation of one or more channels 122 that define a die attach material 124 in which one or more embodiments of active areas 400 are absent. For example, one or more channels 122 are formed in adjacent parts of the die attach material 124 that define a die attach material 124 in which one or more embodiments of active areas 400 are absent. Furthermore, there are several advantages to a larger portion of the die attach material 124. In this regard, during manufacturing, the thickness of the die attach material 124 may vary within a particular area, and if the area of ​​the die attach material 124 is large, a certain degree of self-leveling during the curing process may enable a more uniform thickness and / or a more uniform connection. In one embodiment, one or more channels 122 include a plurality of channels. In one embodiment, one or more channels 122 include at least two intersecting channels. In one embodiment, one or more channels 122 include three or more intersecting channels. In one embodiment, one or more channels 122 may constitute a channel mesh.

[0088] As described herein, the various configurations of one or more channels 122 and die attach material 124 shown in Figures 5 to 10 can be used in combination or selectively in package 100. More specifically, package 100 can utilize any number or configuration of one or more channels 122 as illustrated and described herein. Similarly, any number or configuration of die attach material 124 can be used as illustrated and described herein.

[0089] Figure 11 is a partial top view of the package relating to Figure 1.

[0090] In particular, Figure 11 shows an exemplary embodiment of package 100, which may include one or more arbitrary features, components, configurations, etc., as described herein. More specifically, Figure 11 shows package 100 with many components omitted for ease of understanding. Referring to Figure 11, package 100 may comprise a support portion 102. In one embodiment, the support portion 102 may be mounted as a paddle. The support portion 102 mounted as a paddle may contain a metallic material such as copper and / or similar metals. Furthermore, the support portion 102 mounted as a paddle may contain a metallizing material. The metallizing material may contain any metallic material such as silver. In one embodiment, the support portion 102 is mounted as a paddle and contains copper along with a metallizing material containing silver. The support portion 102 may be connected to and / or supported by a lead frame 192. The lead frame 192 may comprise one or more input / output pins 134, or may be connected to one or more input / output pins 134.

[0091] Furthermore, the support portion 102 may be mounted as a surface, package support portion, package surface, package support surface, metal submount, flange, metal flange, heat sink, common source support portion, common source surface, common source package support portion, common source package surface, common source package support surface, common source flange, common source heat sink, lead frame, metal lead frame, etc., and / or combinations thereof. The support portion 102 may include metal materials, insulating materials, dielectric materials, etc., and / or combinations thereof.

[0092] Figure 12 is a partial top view of the package relating to Figure 11.

[0093] In particular, Figure 12 shows package 100 with many components omitted for ease of understanding. Further reference to Figure 12, package 100 is shown by an exemplary configuration of die attach material 124 placed on the support 102. The die attach material 124 may be placed at many specific locations throughout the support 102, as otherwise described herein. The arrangement of the die attach material 124 may result in the formation and / or provision of one or more channels 122. In one embodiment, the die attach material 124 may constitute a mesh of one or more channels 122. Note that the configurations shown in the drawings include many parts of the die attach material 124 and one or more channels 122, but for ease of illustration, each may not have a reference number.

[0094] In one embodiment, the die attach material 124 may constitute a mesh of one or more channels 122, and may be arranged in a square and / or rectangular shape. However, the die attach material 124 may be configured in any shape. The size, arrangement, location, number, and / or similar characteristics of the die attach material 124 shown in Figure 12 and anywhere in this disclosure are examples only. Other configurations of the die attach material 124 are similarly conceivable. In one embodiment, one or more channels 122 include multiple channels. In one embodiment, one or more channels 122 include at least two intersecting channels. In one embodiment, one or more channels 122 include three or more intersecting channels. In one embodiment, one or more channels 122 may constitute a mesh of channels.

[0095] Figure 13 is a partial top view of the package relating to Figure 11.

[0096] In particular, Figure 13 shows a package 100 with many components removed for ease of understanding. Referring to Figure 13, the package 100 may comprise a semiconductor die 200 having one or more active areas 400. In this regard, the package 100 shown in Figure 13 shows two of the one or more active areas 400. However, the package 100 may contain any number of one or more active areas 400. The semiconductor die 200 may also be attached to the package 100 and the support portion 102 by a die attach material 124.

[0097] Figure 14 is a partial top view of the package relating to Figure 13.

[0098] In particular, Figure 14 is a transparent view of the semiconductor die 200 of the package 100 to illustrate the arrangement of one or more active areas 400 on the die attach material 124. This arrangement will be discussed in more detail elsewhere in this specification.

[0099] Figure 15A is a partial cross-sectional view of the package along line XV-XV in Figure 14.

[0100] Referring to Figure 15A, the semiconductor die 200 may be mounted on the support 102 using a die attach material 124. The arrangement of the die attach material 124 may result in the formation of a mesh of one or more channels 122 and / or the provision of one or more channels 122. As otherwise described herein, the arrangement and position of the die attach material 124 in combination with one or more channels 122 may be specific to one or more active areas 400. In particular, one or more channels 122 may be positioned vertically downward along the Y-axis with respect to one or more active areas 400, but not directly below one or more active areas 400. In other words, one or more channels 122 may be positioned vertically downward along the Y-axis with respect to one or more active areas 400 and offset from the active areas 400 along the X-axis, as otherwise described herein.

[0101] One or more channels 122 may be located below at least one sub-device area 300. In certain embodiments, one or more channels 122 may be located directly below at least one sub-device area 300 along the Y-axis. For example, one or more channels 122 may be located below or directly below at least one sub-device area 300, flux pad, and / or similar along the Y-axis and X-axis.

[0102] Figure 15B is a partial cross-sectional view of another aspect of Figure 15A.

[0103] In particular, Figure 15B shows one embodiment of a package 100 on which multiple semiconductor dies 200 are mounted. Various embodiments, configurations, components, processes, and / or similars may be implemented in conjunction with the embodiment of Figure 15B, as described herein. Further reference to Figure 15B, one or more of the semiconductor dies 200 may be configured to be mounted as one embodiment of at least one sub-device area 300, and one or more of the semiconductor dies 200 may be configured to be mounted as one embodiment of an active area 400. In certain embodiments, one or more of the multiple semiconductor dies 200 may be mounted as individual devices. In certain embodiments, each of the multiple semiconductor dies 200 may be mounted as an individual device.

[0104] Referring to Figure 15B, a plurality of semiconductor dies 200 may be mounted on a support 102 using a die attach material 124. The die attach material 124 may comprise one or more channels 122. In particular, one or more channels 122 are positioned vertically downward along the Y-axis with respect to one or more semiconductor dies 200 mounted as active areas 400, but not directly below the one or more active areas 400. In other words, one or more channels 122 are positioned vertically downward along the Y-axis with respect to one or more semiconductor dies 200 mounted as active areas 400, and may be offset from the active areas 400 along the X-axis as otherwise described herein.

[0105] Referring further to Figure 15B, one or more channels 122 may be located beneath the semiconductor die 200, which is implemented as at least one sub-device area 300. In certain embodiments, one or more channels 122 may be located directly beneath the semiconductor die 200, which is implemented as at least one sub-device area 300, along the Y-axis. For example, one or more channels 122 may be located beneath or directly beneath the semiconductor die 200, which is implemented as at least one sub-device area 300, flux pad, and / or similar, along the Y-axis and X-axis.

[0106] Figure 16 is a partial top view of the package relating to Figure 11.

[0107] In particular, Figure 16 shows an exemplary configuration of a die attach material 124 disposed on the support portion 102. Specifically, the die attach material 124 may comprise one or more channels 122. The one or more channels 122 are positioned vertically below one or more active areas 400 (shown by dashed lines in Figure 16) along the Y-axis, but not directly below the one or more active areas 400. In other words, the one or more channels 122 are positioned vertically below the one or more active areas 400 along the Y-axis and offset from the active areas 400 along the X-axis.

[0108] One or more channels 122 may be located below at least one sub-device area 300. In certain embodiments, one or more channels 122 may be located directly below at least one sub-device area 300 along the Y-axis. For example, one or more channels 122 may be located below or directly below at least one sub-device area 300, flux pad, and / or similar along the Y-axis and X-axis.

[0109] One or more channels 122 may include one or more exhaust ports 126 and one or more side edges 128. One or more channels 122 may be located in the X-axis and Z-axis planes parallel to the upper surface 180 of the support portion 102, and may be rectangular, polygonal, circular, free-form, continuous, discontinuous, and / or combinations thereof.

[0110] One or more channels 122 may divide the die attach material 124 in the X and Z planes parallel to the upper surface 180 of the support portion 102. As shown in Figure 16, a majority of the one or more channels 122 divide the die attach material 124 into a number of different parts. The package 100 may include any number of the one or more channels 122 and any number of parts of the die attach material 124.

[0111] One or more side edges 128 of one or more channels 122 may form a surface of the die attach material 124 that allows gases generated during the curing of the die attach material 124 to be released from the die attach material 124. In particular, one or more channels 122 may form a surface that allows gases generated during curing to be released from the die attach material 124 from below the active area 400 by utilizing one or more side edges 128 of the die attach material 124. More specifically, as shown by arrows in Figure 16, some of which are positioned in the die attach material 124, gases generated during curing below the active area 400 may travel toward one or more side edges 128 of one or more channels 122 and enter one or more channels 122. Thus, one or more channels 122, together with one or more side edges 128, help suppress void formation below the active area 400 by providing a place for gases generated during the curing process to retreat from below the active area 400 into one or more channels 122.

[0112] Subsequently, the gas generated during curing below the active area 400 may enter one or more channels 122. Once the gas is taken into one or more channels 122, as indicated by the arrows positioned within one or more channels 122 as shown in Figure 16, it may travel along one or more channels 122 and be discharged from one or more channels 122 through the exhaust port 126.

[0113] In this regard, one or more channels 122 allow for the release of gas generated during curing below the active area 400, thereby suppressing void formation below the active area 400. Thus, one or more channels 122 enhance the cooling function of the support 102 below the active area 400 by increasing the ability of heat generated by the active area 400 to be transferred from the semiconductor die 200 to the support 102. Furthermore, the implementation of one or more channels 122 within the die attach material 124 may be even more beneficial in dealing with various temperature extremes, which are considered more likely in high-power applications of the package 100. In this regard, it is very beneficial to ensure higher performance, higher reliability, and / or similar characteristics by keeping the active area 400 within 5°C of the desired operating temperature range.

[0114] Referring further to Figure 16, one or more channels 122 may have a substantially straight and / or linear configuration. The substantially straight and / or linear configuration may include a first exhaust port 126 at one end and a second exhaust port 126 at the other end. However, the substantially straight and / or linear configuration may include only one exhaust port 126 at one end.

[0115] One or more channels 122 may have multiple connections in a substantially straight and / or linear configuration. These connections may be at any angle. These angles may include 1° to 359°, 1° to 40°, 40° to 80°, 80° to 120°, 120° to 160°, 160° to 200°, 200° to 240°, 240° to 280°, 280° to 320°, or 320° to 359°. As shown in Figure 16, the multiple connections in a substantially straight and / or linear configuration are connected at an angle of approximately 90°. The multiple connections in a substantially straight and / or linear configuration may also include a first exhaust port 126 at one end and a second exhaust port 126 at the other end. However, the multiple connections in a substantially straight and / or linear configuration may include only one exhaust port 126 at one end.

[0116] One or more channels 122 may result in improved robustness of the die attach material 124, extended lifespan of the die attach material 124, and / or other beneficial improvements. In this regard, it is known that large-area die attach regions are susceptible to various failure mechanisms, such as delamination, cracking, and / or similar phenomena. These various failure mechanisms are thought to be the result of thermal expansion of the materials associated with the die attach material 124, the semiconductor die 200, the support 102, and / or similar components. In this regard, the materials associated with the die attach material 124, the semiconductor die 200, the support 102, and / or similar components may be different materials and may have different coefficients of thermal expansion. Therefore, different materials that may have different coefficients of thermal expansion may result in different expansion when the semiconductor die 200 operates at different temperature extremes. As a result, the package 100, the semiconductor die 200, the die attach material 124, and / or similar components are more likely to experience one of the failure mechanisms.

[0117] One or more channels 122 can reduce the large-area die-attach region. In particular, one or more channels 122 can divide the large-area die-attach region into one or more small-area die-attach regions. Specifically, as shown in Figure 16, a majority of the one or more channels 122 divide the die-attach material 124 into many different small parts. Therefore, different materials with different thermal expansion coefficients, which can result in different expansions when the semiconductor die 200 operates at various temperature extremes, have smaller portions of die-attach material 124, thus suppressing the amount of expansion. As a result, the likelihood of one of the failure mechanisms occurring in the package 100 is reduced.

[0118] The die attach material 124 may be applied using a screen printing process, a preform process, a needle ejection system, an inkjet ejection system, a masking process, a photogravure process, a transparent film printing process, a photomask process combined with an etching process, a photosensitization process, a laser resist ablation process, a milling process, a laser etching process, a direct metal printing process, a combination thereof, and / or similar processes, as described herein.

[0119] Figure 17 is a diagram showing various exemplary dimensions of the channel of the die attach material relating to this disclosure.

[0120] In particular, the position of one or more channels 122 relative to the active area 400 can be optimized to maximize heat transfer from the active area 400 to the support 102. Also, the position of one or more channels 122 relative to the active area 400 can be optimized to maximize void suppression and / or gas escape from below the active area 400 of gases generated during the curing process. More specifically, the width of one or more channels 122 is shown and specified as distance D5 along the X axis, the distance from the active area 400 to one or more channels 122 is specified as distance D6 along the X axis, the overall length of the die attach material 124 is specified as distance D7 along the X axis, and the width of the active area 400 is specified as distance D8 along the X axis.

[0121] For example, distance D5 may be related to distance D6 as the relationship between the width of one or more channels 122 and the distance from one or more side edges 128 of one or more channels 122 to the edge of the active area 400. Distance D5 may be 20% to 300% of distance D6, 20% to 60% of distance D6, 60% to 100% of distance D6, 100% to 140% of distance D6, 140% to 180% of distance D6, 180% to 220% of distance D6, 220% to 260% of distance D6, or 260% to 300% of distance D6.

[0122] For example, distance D5 may be related to distance D8 as the relationship between the width of one or more channels 122 and the width of the active area 400. Distance D5 may be 20% to 300% of distance D8, 20% to 60% of distance D8, 60% to 100% of distance D8, 100% to 140% of distance D8, 140% to 180% of distance D8, 180% to 220% of distance D8, 220% to 260% of distance D8, or 260% to 300% of distance D8.

[0123] For example, distance D5 may be related to distance D7 as the relationship between the width of one or more channels 122 and the width of the die attach material 124. Distance D5 may be 2% to 40%, 2% to 10%, 10% to 20%, 20% to 30%, or 30% to 40% of distance D7.

[0124] The various distances D5, D6, D7, and D8 may also be similarly defined along the Z-axis due to the configuration of one or more channels 122, active areas 400, and / or similar formed along the Z-axis.

[0125] Figure 18 is a partial cross-sectional view of the package along line XV-XV in Figure 14.

[0126] Figure 19 is a partial top view of the package relating to Figure 11.

[0127] Referring to Figure 1, the package 100 may include an overmolding 130 and / or similar. The overmolding 130 may be formed of a plastic material, a synthetic material, a plastic polymer material, etc., and / or a combination thereof, and may provide protection from the external environment by injection molding around the support portion 102 and the semiconductor die 200. The overmolding 130 may substantially surround the semiconductor die 200, one or more active areas 400, and / or other components of the package 100.

[0128] Referring to Figures 18 and 19, there are portions of the die attach material 124 that can extend beyond the semiconductor die 200 covering the support portion 102. These portions of the die attach material 124 can improve the overmolding plastic adhesion of the overmolded package 100's overmolded 130 to the support portion 102. Furthermore, these portions of the die attach material 124 can avoid selective plating of the support portion 102. Also, this configuration allows for the use of a single common package lead frame for all die sizes of the semiconductor die 200 used in a given package type.

[0129] In one embodiment where a portion of the die attach material 124 that can extend beyond the semiconductor die 200 is mounted, the overmolding 130 may adhere to the die attach material 124 and the side edges of the semiconductor die 200 in portion 502. The overmolding 130 may also adhere to the upper surface of the semiconductor die 200 in portion 504. The overmolding 130 may also adhere to the side edges of the semiconductor die 200 in portion 506. Furthermore, the overmolding 130 may adhere to one or more upper surfaces of the die attach material 124 and may extend and adhere to a portion of one or more channels 122 in portion 508. In this respect, the composite material can be reliably attached by one or more channels 122 and the die attach material 124, thereby reducing package failure. In particular, the overmolding 130 positioned on the die attach material 124 and / or one or more channels 122 can promote the adhesion of the molded compound to the semiconductor die 200 within the package 100. Furthermore, the package 100 may undergo a cleaning process, such as a plasma cleaning process, prior to the installation and / or placement of the overmolding 130 on the semiconductor die 200. In this regard, the cleaning process may physically alter the die attach material 124. In particular, the cleaning process may create pores or increase the porosity of the die attach material 124. This physical alteration may further promote the adhesion of the molded compound of the overmolding 130 to the semiconductor die 200 within the package 100.

[0130] Alternatively, the package 100 may be implemented to include an open cavity configuration suitable for use with the semiconductor die 200. In particular, the open cavity configuration may utilize an open cavity package design. In some embodiments, the open cavity configuration may include an enclosure such as a lid to protect interconnects, circuit components, the semiconductor die 200, and / or similar components. The package 100 may comprise a ceramic body, a lid, and one or more metal contacts.

[0131] Figure 20 is a partial top view of the package relating to Figure 11.

[0132] In particular, Figure 20 shows alternative embodiments of the die attach material 124 and one or more channels 122 having various configurations. Specifically, the die attach material 124 may have a circular, triangular, free-form, and / or similar shape. Also, one or more channels 122 may differ in size and shape, as shown in Figure 20.

[0133] Figure 21 shows the process for implementing the package related to this disclosure.

[0134] In particular, Figure 21 shows the package assembly process (box 600) relating to the mounting, configuration, manufacturing, formation, and / or similar operations of package 100 as described herein. It should be noted that embodiments of the package assembly process (box 600) may be performed in a different order consistent with the embodiments described herein. Furthermore, the package assembly process (box 600) may be modified to have more or fewer processes consistent with the various embodiments disclosed herein.

[0135] First, the package mounting process (box 600) may include a process (box 602) for forming the support portion 102. More specifically, the support portion 102 may be configured, set up, and / or positioned as described herein.

[0136] In particular, the support portion 102 may be mounted as a paddle. The support portion 102 mounted as a paddle may contain a metallic material such as copper and / or a similar metal. Furthermore, the support portion 102 mounted as a paddle may contain a metal plating material. The metal plating material may contain any metallic material such as silver. In one embodiment, the support portion 102 is mounted as a paddle and contains copper along with a metal plating material containing silver. The support portion 102 may be connected to and / or supported by the lead frame 192. The lead frame 192 may have one or more input / output pins 134, or may be connected to one or more input / output pins 134. Alternatively, the support portion 102 may be formed as a support portion, surface, package support portion, package surface, package support surface, metal submount, flange, metal flange, heat sink, common source support portion, common source surface, common source package support portion, common source package surface, common source package support surface, common source flange, common source heat sink, lead frame, metal lead frame, etc., and / or combinations thereof. The support portion 102 may be formed from a metal material, insulating material, dielectric material, etc., and / or combinations thereof.

[0137] Furthermore, the package mounting process (box 600) may include forming the die attach material 124 and one or more channels 122 (box 604). More specifically, the die attach material 124 and one or more channels 122 may be configured, set, and / or positioned on at least a portion of the support 102 as described herein.

[0138] In particular, the die attach material 124 and one or more channels 122 may be formed using a screen printing process, a preform process, a needle ejection system, an inkjet ejection system, a masking process, a photogravure process, a transparent film printing process, a photomask process combined with an etching process, a photosensitization process, a laser resist ablation process, a milling process, a laser etching process, a direct metal printing process, a combination thereof, and / or similar processes, as described herein.

[0139] The package mounting process (box 600) may also include placing the semiconductor die 200 on the support 102, the die attach material 124, and one or more channels 122 (box 606). More specifically, the semiconductor die 200 may be configured, set up, and / or placed as described herein. The semiconductor die 200 may then be placed on the support 102, the die attach material 124, and one or more channels 122 as described herein.

[0140] More specifically, arranging the semiconductor die 200 on the support portion 102, the die attach material 124, and one or more channels 122 (box 606) may include placing the semiconductor die 200 on the support portion 102 by using and / or implementing a pick-and-place assembly.

[0141] Furthermore, the package mounting process (box 600) may include curing the die attach material 124 (box 608) as described herein. In particular, the semiconductor die 200, support portion 102, die attach material 124, one or more channels 122, and / or similar components may be placed in a high-temperature environment such as an oven. In this regard, one or more side edges 128 of one or more channels 122 may form a surface of the die attach material 124 that allows gases generated during the curing of the die attach material 124 to be released from the die attach material 124. In particular, one or more channels 122 may form a surface that allows gases generated during curing to be released from the die attach material 124 from below the active area 400 by utilizing one or more side edges 128 of the die attach material 124.

[0142] Furthermore, the package mounting process (box 600) may include forming one or more interconnects 120 and one or more interconnects 190 (box 610). More specifically, one or more interconnects 190 may be configured, set up, and / or positioned as described herein. In one embodiment, the process of forming one or more interconnects may include forming one or more interconnects 120 and one or more interconnects 190 by forming one or more wires, leads, vias, edge plating, circuit traces, tracks, and / or similar. In one embodiment, forming one or more interconnects 120 and one or more interconnects 190 (box 610) may include connecting one or more interconnects 120 and one or more interconnects 190 by adhesive, soldering, sintering, eutectic bonding, ultrasonic welding, clip components, and / or similar as described herein.

[0143] Furthermore, the package assembly process (box 600) may include enclosing the package 100 (box 612). More specifically, the package 100 may be configured, set up, and / or positioned as described herein. In one embodiment, the process of enclosing the package 100 (box 612) may include forming an open cavity configuration, an overmolded configuration, and the like.

[0144] Figure 22 is a top view of an exemplary embodiment of the package shown in Figure 1.

[0145] In particular, Figure 22 is a top view of an exemplary embodiment of package 100, in which at least a portion is implemented as an MMIC transistor amplifier. In this regard, package 100 may be implemented using many types of device technologies, device topologies, semiconductor types, transistor types, embodiments of semiconductor die 200, embodiments of at least one sub-device area 300, embodiments of one or more active areas 400, etc., as described herein. Therefore, Figure 22 is merely an example.

[0146] As shown in Figure 22, the MMIC transistor amplifier comprises a semiconductor die 200 contained in a package 100. The package 100 may include input leads 112 and output leads 118. The input leads 112 may be attached to the input lead pads 114 by means of, for example, adhesive, soldering, sintering, eutectic bonding, thermal compression bonding, ultrasonic bonding / welding, clip components, and / or similar. One or more interconnects 120, such as input bonding wires, may electrically connect the input lead pads 114 to the input bonding pads 232 on the semiconductor die 200. The first ends of one or more interconnects 120 may be directly connected to the input lead pads 114, or the second ends of each of the one or more interconnects 120 may be connected to the input bonding pads 232.

[0147] The semiconductor die 200 may further comprise a supply network 238 which may include an input splitting node 236 that can be connected to an input bonding pad 232 by a transmission line 234, the first sub-device area of ​​at least one sub-device area 300 may be implemented as an input impedance matching network 350, the first active area of ​​one or more active areas 400 may be implemented as a first transistor stage 460, the second sub-device area of ​​at least one sub-device area 300 may be implemented as an intermediate impedance matching network 340, the second active area of ​​one or more active areas 400 may be implemented as a second transistor stage 462, and the third sub-device area of ​​at least one sub-device area 300 may be implemented as an output impedance matching network 370.

[0148] The semiconductor die 200 may further comprise an output bonding pad 288 and an output coupling node 285. The output leads 118 may be connected to the output lead pad 116 by means of, for example, adhesive, soldering, sintering, eutectic bonding, thermal compression bonding, ultrasonic bonding / welding, clip components, and / or similar. One or more interconnects 190, such as output bonding wires, may electrically connect the output lead pad 116 to the output bonding pad 288. The first end of each of the one or more interconnects 190 may be directly connected to the output lead pad 116, or the second end of the one or more interconnects 190 may be connected to the output bonding pad 288. A transmission line 287 may connect the output bonding pad 288 to an integrated supply network 282.

[0149] The input impedance matching network 350 may include reactive components such as capacitors, inductive elements, and / or similars that can improve impedance matching between the input lead 112 and the first transistor stage 460, as described herein. Similarly, the output impedance matching network 370 may include reactive components such as capacitors, inductive elements, and / or similars that can be used to match the output impedance of the second transistor stage 462 to the output lead 118 of the package 100, as described herein.

[0150] The intermediate impedance matching network 340 may include, as described herein, reactive components such as capacitors, inductive elements, and / or similar elements that can help improve the impedance at the output of the first transistor stage 460 relative to the impedance at the input of the second transistor stage 462.

[0151] The first transistor stage 460 and the second transistor stage 462 may include multiple unit cell transistors arranged in electrical parallel. The first transistor stage 460 and the second transistor stage 462 may be provided in an MMIC amplifier to increase the gain. Naturally, in other cases, only a single transistor stage may be provided, or three or more transistor stages may be provided, and the number of impedance matching stages may be adjusted accordingly.

[0152] As further shown in Figure 22, both the input splitting node 236 and the output coupling node 285 may reside on the semiconductor die 200. Therefore, one or more interconnects 120 and one or more interconnects 190 may reside outside the loop defined by the parallel amplification path included in the MMIC amplifier extending between the input splitting node 236 and the output coupling node 285.

[0153] Figure 23 is an enlarged schematic diagram of a subset of the unit cell transistors of the transistor amplifier shown in Figure 22.

[0154] As shown in Figure 23, one or more active areas 400 may include a gate bus 402 connected to a plurality of gate fingers 406 extending parallel to a first direction (for example, the X direction shown in Figure 23). A source bus 410 is connected to a plurality of parallel source contacts 416. The source bus 410 may be connected to a ground voltage node on the back surface of the semiconductor die 200. A drain bus 420 may also be connected to a plurality of drain contacts 426.

[0155] As shown in Figure 23, each gate finger 406 extends along the X direction between an adjacent pair of source contacts 416 and drain contacts 426. The semiconductor die 200 may comprise a plurality of unit cells 430, each containing an individual transistor. In Figure 23, one of the plurality of unit cells 430 is shown by a dashed box and includes a gate finger 406 extending between adjacent source contacts 416 and drain contacts 426. "Gate width" represents the distance that the gate finger 406 overlaps with its associated source contacts 416 and drain contacts 426 in the X direction. That is, the "width" of the gate finger 406 represents the dimension (distance along the Z direction) of the gate finger 406 extending parallel to the adjacent source contacts 416 / drain contacts 426. Each of the plurality of unit cells 430 may share one of its source contacts 416 and / or drain contacts 426 with one or more adjacent unit cells 430. Figure 23 shows a specific number of the multiple unit cells 430, but naturally, the semiconductor die 200 may have more or fewer unit cells 430 than this.

[0156] Figure 24 is a schematic cross-sectional view along line XXIV-XXIV in Figure 23.

[0157] Referring to Figure 24, the semiconductor die 200 and / or active area 400 may include a semiconductor structure 440 including a substrate 202 which may contain, for example, 4H-SiC or 6H-SiC. The channel layer 490 may be located between the substrate 202 and the barrier layer 470, with the channel layer 490 located on the substrate 202 and the barrier layer 470 located on the channel layer 490. The channel layer 490 and the barrier layer 470 may contain group III nitride materials, and the material of the barrier layer 470 has a wider band gap than the material of the channel layer 490. For example, the channel layer 490 may contain GaN while the barrier layer 470 contains AlGaN.

[0158] Due to the difference in band gap between the barrier layer 470 and the channel layer 490, and the piezoelectric effect at the interface between the barrier layer 470 and the channel layer 490, a two-dimensional electron gas (2DEG) is induced in the channel layer 490 at the junction between the channel layer 490 and the barrier layer 470. The 2DEG acts as a highly conductive layer that enables conduction between the source and drain regions of the device, which may be located directly beneath the source contact 416 and the drain contact 426, respectively. The source contact 416 and the drain contact 426 may be located on the barrier layer 470. The gate finger 406 may be located on the barrier layer 470 between the source contact 416 and the drain contact 426. In Figure 23, the gate finger 406, source contact 416, and drain contact 426 are all shown to have the same "length," but naturally, in practice, the length of the gate finger 406 may be substantially shorter than the lengths of the source contact 416 and the drain contact 426, and naturally, the source contact and drain contact 426 do not need to have the same length.

[0159] The material of the gate finger 406 may be selected based on the composition of the barrier layer 470. However, in certain embodiments, Ni, Pt, NiSi xMaterials capable of forming Schottky contacts with nitride-based semiconductor materials such as Cu, Pd, Cr, W, and / or WSiN may be used. The source contact 416 and drain contact 426 may contain metals such as TiAlN that can form ohmic contacts with GaN.

[0160] The input lead pad 114, input bonding pad 232, output bonding pad 288, output lead pad 116, and any other bonding pad areas may be formed of a metal surface and may also contain metallic materials such as copper, gold, nickel, palladium, silver, and combinations thereof.

[0161] The semiconductor die 200 may have a metallization layer disposed on the underside of the substrate 202. The metallization layer may be arranged in a plane substantially parallel to the Z-axis and / or X-axis. In one embodiment, the metallization layer may be realized as a full-surface metal layer on the underside of the substrate 202. As an addition or alternative, the semiconductor die 200 may be single-sided (one metal layer), double-sided (two metal layers on both sides of one substrate layer), or multilayer (outer and inner layers of aluminum, copper, silver, gold, and / or similar metals alternating with the substrate layer). The semiconductor die 200 may include features such as separate conductive lines, tracks, circuit traces, connection pads, vias, and solid conductive areas for EM shielding, etc., connecting the layers of aluminum, copper, silver, gold, and / or similar metals. In one or more embodiments, the die attach material 124 may not form an electrical connection with the semiconductor die 200. More specifically, the die attach material 124 may be used solely for attachment to the support portion 102 of the semiconductor die 200. In this respect, the bottom of the semiconductor die 200 has no electrical contacts. In one or more embodiments, the die attach material 124 may form a single electrical connection with the semiconductor die 200. More specifically, the die attach material 124 may be used as a single electrical connection to the support portion 102 of the semiconductor die 200. In this respect, the bottom of the semiconductor die 200 has no electrical contacts. Thus, in these embodiments, the configuration of the package 100 of the present disclosure differs from the multi-connection circuits used in flip chips, C4 (Controlled Collapse Chip Connection), and / or similar devices.

[0162] Figure 25 is a partial top view of the package relating to this disclosure.

[0163] In particular, Figure 25 shows an exemplary embodiment of package 100, which may include one or more arbitrary features, components, configurations, etc., as described herein. More specifically, Figure 25 shows package 100 on which semiconductor 200 is mounted as a large-area integrated circuit, monolithic integrated circuit, monolithic microwave integrated circuit (MMIC), multi-cell transistor integrated circuit, integrated circuit having an array of field-effect transistors (FETs), multi-transistor integrated circuit, multi-circuit integrated circuit, multi-unit integrated circuit, multi-area integrated circuit, multi-active-area integrated circuit, compound semiconductor device, high-power semiconductor device, high-frequency semiconductor device, high-power / high-frequency semiconductor device, compound high-power semiconductor device, compound high-frequency semiconductor device, compound high-power / high-frequency semiconductor device, compound semiconductor device, high-power compound semiconductor device, high-frequency compound semiconductor device, and / or similar. For example, the present disclosure may be used for high-power and / or high-frequency compound semiconductor devices such as Group III nitride transistors such as GaN-based FETs, HEMTs, and / or similar transistors, or MMICs incorporating these. Furthermore, this disclosure may be used in multi-stage FET topologies, multi-path FET topologies, and / or similar topologies (including Doherty configurations) using MMICs and / or discrete components. In addition, this disclosure is applicable to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-area discrete devices, and / or similar.

[0164] In one or more embodiments, the package 100 of Figure 25 shows that various embodiments of the present disclosure can be used for any embodiment of the semiconductor die 200 that includes one or more active areas 400 and at least one embodiment of an area of ​​the semiconductor die 200 on which one or more active areas 400 are not mounted. For example, an area on which one embodiment of at least one sub-device area 300 is mounted.

[0165] As a specific example, the package 100 shown in Figure 25 may include an embodiment in which at least one embodiment of one or more active areas 400 is a Doherty circuit including a carrier amplifier and a peaking amplifier. In particular, the package 100 may comprise a carrier amplifier and a peaking amplifier configured to power couple the output. In one embodiment, the two amplifiers may have different biases. In one embodiment, the carrier amplifier may be configured to operate in a typical class AB or class B. In one embodiment, the peaking amplifier may be configured to operate in class C. Other operating classes are similarly conceivable.

[0166] Accordingly, this disclosure discloses apparatus and processes for implementing intentionally configured channels or meshes of one or more channels that allow gas escape voids to be relocated to areas near, but not directly beneath, the active area of ​​an active transistor or the like. Thus, the application of the channel formation void reduction technique described in this disclosure using sintered die attach materials yields the unexpected result of improved cooling and / or robustness. Furthermore, the application of the channel formation void reduction technique described in this disclosure for GaN packaging using sintered die attach materials yields the unexpected result of improved cooling and / or robustness. In particular, the applicant has tested many different processes for void reduction and found that the channel formation method of this disclosure presents and provides the best results. In particular, this disclosure may be used in large-area integrated circuits, monolithic integrated circuits, monolithic microwave integrated circuits (MMICs), multi-cell transistor integrated circuits, integrated circuits having arrays of field-effect transistors (FETs), multi-transistor integrated circuits, multi-circuit integrated circuits, multi-unit integrated circuits, multi-area integrated circuits, multi-active-area integrated circuits, compound semiconductor devices, high-power semiconductor devices, high-frequency semiconductor devices, high-power / high-frequency semiconductor devices, compound high-power semiconductor devices, compound high-frequency semiconductor devices, compound high-power / high-frequency semiconductor devices, compound semiconductor devices, high-power compound semiconductor devices, high-frequency compound semiconductor devices, and / or similar devices. For example, this disclosure may be used in high-power and / or high-frequency compound semiconductor devices such as Group III nitride transistors such as GaN-based FETs, HEMTs, and / or similar transistors, or in MMICs incorporating these. This disclosure may also be used in multi-stage FET topologies, multi-path FET topologies, and / or similar topologies (including Doherty configurations) using MMICs and / or individual components. Furthermore, this disclosure is also applicable to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-area discrete devices, and / or similar.

[0167] Furthermore, this disclosure discloses apparatus and processes for mounting a die attach material 124 and / or an overmold 130 positioned on one or more channels 122, which can facilitate the adhesion of a molded compound to a semiconductor die 200 within a package 100. In this regard, there are portions of the die attach material 124 that can extend beyond the semiconductor die 200 covering the support portion 102. These portions of the die attach material 124 can improve the adhesion of the overmold plastic of the overmold 130 of the package 100 to the support portion 102. Moreover, these portions of the die attach material 124 can avoid selective plating of the support portion 102. In addition, this configuration may allow the use of a single common package lead frame for all die sizes of the semiconductor die 200 used in a given package type. In this regard, the various embodiments of mounting the overmold 130 of the package 100 to the support portion 102 as described herein allow for great versatility in the size and embodiment of the semiconductor die 200.

[0168] Furthermore, this disclosure discloses equipment and processes that result in lower manufacturing costs. It also discloses equipment and processes that can implement various component configurations for reduced packaging costs, reduced packaging manufacturing costs, reduced manufacturing complexity, reduced yield losses, and / or similar effects.

[0169] The adhesives of this disclosure may be used in adhesive bonding processes that may include joining surfaces to be joined by the application of an intermediate layer. The adhesive may be organic or inorganic, and may be deposited on one side or both sides of the surfaces to be joined. The adhesive may be used in adhesive bonding processes that may include applying the adhesive material over a specific processing time at a specific coating thickness and a specific bonding temperature in an environment that may include applying a specific tool pressure. In one embodiment, the adhesive may be a conductive adhesive, an epoxy adhesive, a conductive epoxy adhesive, and / or an adhesive similar to these.

[0170] The solders of this disclosure may be used to construct solder interfaces that may contain solder and / or solder interfaces that may be formed by solder. The solder may be any fused metal that can be used to form a joint between surfaces to be connected. The solder may be lead-free solder, lead solder, eutectic solder, etc. Lead-free solder may contain tin, copper, silver, bismuth, indium, zinc, antimony, trace amounts of other metals and / or similar metals. Lead solder may contain lead, tin, silver and other metals and / or similar metals. The solder may further contain flux as needed.

[0171] The sintering process described herein may utilize a process for compressing and forming a solid mass of material by heat and / or pressure. This sintering process may operate without melting the material to its liquefaction temperature. This sintering process may include sintering of metal powder. This sintering process may include sintering in a vacuum. This sintering process may include sintering using a protective gas.

[0172] The eutectic joining of this disclosure may utilize a joining process involving an intermediate metal layer capable of forming a eutectic system. The eutectic system may be used between the surfaces to be joined. The eutectic joining may utilize a eutectic metal, which may be an alloy that changes from solid to liquid or liquid to solid at a specific composition and temperature without undergoing two-phase equilibrium. The eutectic alloy may be deposited by sputtering, binary deposition, electroplating, and / or similar methods.

[0173] The ultrasonic welding described herein may utilize a process in which high-frequency ultrasonic vibrations are locally applied to integrally held components under pressure. This ultrasonic welding may form a solid weld between the surfaces of the objects to be joined. In one embodiment, this ultrasonic welding may include the application of ultrasonic resolving force.

[0174] While the present disclosure has been described in terms of exemplary embodiments, those skilled in the art will recognize that the present disclosure can be implemented with improvements included in the spirit and scope of the attached claims. The examples given above are illustrative and do not encompass all conceivable designs, embodiments, applications, or improvements of the present disclosure.

Claims

1. Semiconductor die and Support part and A die attach material configured to attach the lower surface of the semiconductor die to the upper surface of the support portion, Equipped with, The die attach material is structured and arranged on the support portion and comprises at least one channel, The semiconductor die is positioned on at least a portion of the at least one channel that is positioned on the support portion, The at least one channel is positioned vertically below the active area of ​​the semiconductor die and is offset laterally from the active area. The at least one channel is configured such that gas generated during the curing of the die attach material when the semiconductor die is attached to the support can be released from the die attach material. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the semiconductor die is a Group III nitride-based HEMT (high electron mobility transistor).

3. The semiconductor device according to claim 1, wherein the semiconductor die is a Group III nitride-based MMIC (monolithic microwave integrated circuit).

4. The semiconductor device according to claim 3, wherein the group III nitride-based MMIC comprises a plurality of group III nitride-based HEMTs (high electron mobility transistors) and at least one sub-device area.

5. The semiconductor device according to claim 1, further comprising at least one sub-device area on the support portion, wherein the die attach material includes at least a portion of the at least one channel disposed between the at least one sub-device area and the support portion.

6. The semiconductor device according to claim 1, further comprising an overmolding on the support portion, wherein the die attach material includes at least a portion of the at least one channel disposed between the overmolding and the support portion.

7. The semiconductor device according to claim 1, wherein the at least one channel includes a plurality of channels.

8. The semiconductor device according to claim 1, wherein the at least one channel includes at least two intersecting channels.

9. The semiconductor device according to claim 1, wherein three or more of the at least one channel intersect.

10. The semiconductor device according to claim 1, wherein the at least one channel constitutes a mesh.

11. The semiconductor device according to claim 1, wherein the die attach material contains metal particles in an organic material.

12. The semiconductor device according to claim 1, wherein the die attach material includes a sintered material.

13. The semiconductor device according to claim 1, wherein the die attach material includes at least one of a silver sintered material or a copper sintered material.

14. The semiconductor device according to claim 1, wherein the semiconductor die comprises an integrated circuit.

15. The at least one channel is located below at least one sub-device area. The semiconductor device according to claim 1, wherein the semiconductor die comprises a monolithic microwave integrated circuit (MMIC).

16. The semiconductor device according to claim 1, wherein the at least one channel includes at least one exhaust port and at least one side edge.

17. The semiconductor device according to claim 1, wherein the at least one channel includes at least one of the following shapes: rectangular, polygonal, circular, free-form, continuous, discontinuous, and combinations thereof.

18. The semiconductor device according to claim 1, wherein the at least one channel divides the die attach material.

19. The semiconductor device according to claim 1, wherein at least one side edge of the at least one channel is configured to form a surface of the die attach material that allows gas generated during the curing of the die attach material to be released from the die attach material.

20. The semiconductor device according to claim 1, wherein the at least one channel is configured to receive gas generated during curing from below at least one active area, and once the gas is taken into the at least one channel, the gas can travel along the at least one channel and be discharged from the at least one channel through an exhaust port.

21. The semiconductor device according to claim 1, wherein the die attach material is constructed using one of the following processes: a screen printing process, a preform process, a needle ejection process, and an inkjet ejection process.

22. The semiconductor device according to claim 1, wherein the die attach material is constructed using a screen printing process with a stencil having an opening that matches the configuration of the die attach material and a portion that does not allow application of the die attach material that matches the position of the at least one channel.

23. The package is further enhanced, The package includes at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a radio frequency (RF) amplifier package, a radio frequency (RF) power amplifier package, a radio frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, a radio frequency (RF) power amplifier transistor package, an L-band component package implementing various frequencies in the 1-2 gigahertz (GHz) radio spectrum, an S-band component package covering frequencies from 2-4 GHz, an X-band component package implementing various frequencies in the 7.0-11.2 GHz radio spectrum, a C-band component package implementing various frequencies in the 500-1000 MHz radio spectrum, a Ku-band component package for the electromagnetic spectrum in the 12-18 GHz microwave frequency range, a satellite communication component package, and a Doherty configuration package. The semiconductor device according to claim 1, wherein the semiconductor die comprises an integrated circuit.

24. The semiconductor device according to claim 1, wherein the semiconductor die includes at least one active area which includes at least one of the following: an area on which one or more transistors are located; an area on which one or more transistor amplifiers are located; an area on which one or more transformers are located; an area on which one or more voltage regulators are located; an area on which one or more heat-generating devices are located; an area on which one or more devices that benefit from low-temperature operation are located; and an area on which one or more semiconductor devices are located.

25. The semiconductor die includes at least one active area which is an area on which one or more radio frequency (RF) semiconductor devices are arranged. The semiconductor die comprises at least one of a GaN-based field-effect transistor (FET) and a GaN-based high-electron-mobility transistor (HEMT), The semiconductor device according to claim 1, wherein the semiconductor die includes at least one sub-device area which includes one or more portions of an impedance matching circuit, a matching circuit, an input matching circuit, an output matching circuit, an intermediate matching circuit, a harmonic termination section, a harmonic termination circuit, and a matching circuit network.

26. The semiconductor die includes at least one active area which is an area on which one or more semiconductor devices are arranged. The semiconductor device according to claim 1, wherein the semiconductor die comprises at least one of a wide bandgap semiconductor device, an ultra-wideband device, a GaN-based device, a GaN-on-SiC device, a GaN-on-Si device, a metal-semiconductor field-effect transistor (MESFET), a metal oxide field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), a lateral diffusion metal oxide semiconductor (LDMOS), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), and a wide bandgap (WBG) semiconductor.

27. The semiconductor device according to claim 1, wherein the semiconductor die includes at least one subdevice area comprising one or more of the following: resistors, inductors, capacitors, silicon oxide (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power couplers, power distributors, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, fundamental frequency matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), and matching circuit networks.

28. The semiconductor device according to claim 1, wherein the support portion includes at least one of a paddle, a surface, a package support portion, a package surface, a package support surface, a metal submount, a flange, a metal flange, a heat sink, a common source support portion, a common source surface, a common source package support portion, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a lead frame, and a metal lead frame.

29. The semiconductor device according to claim 1, wherein the die attach material comprises one or more metallic materials and one or more non-metallic materials.

30. The invention further comprises at least an overmolding configuration surrounding the semiconductor die, The semiconductor device according to claim 1, wherein the die attach material includes at least a portion of at least one channel disposed between the overmolded structure and the support portion.

31. To prepare a semiconductor die, To prepare a support structure, A die attach material is formed on the support portion, configured to attach the lower surface of the semiconductor die to the upper surface of the support portion. Includes, Forming the die attach material includes forming at least one channel in the die attach material on the support portion, The at least one channel is positioned vertically below the active area of ​​the semiconductor die and is offset laterally from the active area. The at least one channel is configured such that gas generated during the curing of the die attach material when the semiconductor die is attached to the support can be released from the die attach material. Semiconductor device assembly process.

32. The semiconductor device mounting process according to claim 31, wherein the semiconductor die is a Group III nitride-based HEMT (high electron mobility transistor).

33. The semiconductor device mounting process according to claim 31, wherein the semiconductor die is a Group III nitride-based MMIC (monolithic microwave integrated circuit).

34. The semiconductor device packaging process according to claim 33, wherein the group III nitride-based MMIC comprises a plurality of group III nitride-based HEMTs (high electron mobility transistors) and at least one sub-device area.

35. The semiconductor device mounting process according to claim 31, further comprising at least one sub-device area on the support portion, wherein the die attach material includes at least a portion of the at least one channel disposed between the at least one sub-device area and the support portion.

36. The semiconductor device mounting process according to claim 31, further comprising an overmolding on the support portion, wherein the die attach material includes at least a portion of the at least one channel disposed between the overmolding and the support portion.

37. The semiconductor device mounting process according to claim 31, wherein the at least one channel includes a plurality of channels.

38. The semiconductor device mounting process according to claim 31, wherein the at least one channel includes at least two intersecting channels.

39. The semiconductor device mounting process according to claim 31, wherein three or more of the at least one channel intersect.

40. The semiconductor device mounting process according to claim 31, wherein the at least one channel constitutes a mesh.

41. The semiconductor device mounting process according to claim 31, wherein the die attach material comprises metal particles in an organic material.

42. The semiconductor device mounting process according to claim 31, wherein the die attach material includes a sintered material.

43. The semiconductor device mounting process according to claim 31, wherein the die attach material includes at least one of a silver sintered material or a copper sintered material.

44. The semiconductor device mounting process according to claim 31, wherein the semiconductor die comprises an integrated circuit.

45. The method further includes locating the at least one channel below at least one sub-device area. The semiconductor device mounting process according to claim 31, wherein the semiconductor die comprises a monolithic microwave integrated circuit (MMIC).

46. The semiconductor device mounting process according to claim 31, further comprising configuring at least one exhaust port and at least one side edge portion in the at least one channel.

47. The semiconductor device mounting process according to claim 31, wherein the at least one channel includes at least one of rectangular, polygonal, circular, free-form, continuous, discontinuous, and combinations thereof.

48. The semiconductor device mounting process according to claim 31, wherein the at least one channel divides the die attach material.

49. The semiconductor device mounting process according to claim 31, further comprising configuring at least one side edge portion in the at least one channel to form a surface of the die attach material that allows gas generated during the curing of the die attach material to be released from the die attach material.

50. The at least one channel is configured to receive gas generated during curing from below at least one active area, The at least one channel is configured such that once the gas is taken into the at least one channel, the gas can travel along the at least one channel and be discharged from the at least one channel through an exhaust port. The semiconductor device mounting process according to claim 31, further comprising:

51. The semiconductor device mounting process according to claim 31, wherein forming the die attach material includes utilizing one of a screen printing process, a preform process, a needle ejection process, and an inkjet ejection process.

52. The semiconductor device mounting process according to claim 31, wherein forming the die attach material involves utilizing a screen printing process using a stencil having an opening that matches the configuration of the die attach material and a portion that does not allow application of the die attach material that matches the position of the at least one channel.

53. The semiconductor device mounting process according to claim 31, further comprising mounting a package, which includes mounting at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a radio frequency (RF) amplifier package, a radio frequency (RF) power amplifier package, a radio frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, a radio frequency (RF) power amplifier transistor package, an L-band component package mounting various frequencies of the radio spectrum from 1 to 2 gigahertz (GHz), an S-band component package covering frequencies from 2 to 4 GHz, an X-band component package mounting various frequencies of the radio spectrum from 7.0 to 11.2 GHz, a C-band component package mounting various frequencies of the radio spectrum from 500 to 1000 MHz, a Ku-band component package for the electromagnetic spectrum in the microwave frequency range of 12 to 18 GHz, a satellite communication component package, and a Doherty configuration package.

54. The semiconductor device mounting process according to claim 31, wherein at least one active area includes at least one of the following: an area where one or more transistors are located; an area where one or more transistor amplifiers are located; an area where one or more transformers are located; an area where one or more voltage regulators are located; an area where one or more heat-generating devices are located; an area where one or more devices that benefit from low-temperature operation are located; and an area where one or more semiconductor devices are located.

55. The system comprises at least one active area, which is an area in which one or more radio frequency (RF) semiconductor devices are arranged, The one or more radio frequency (RF) semiconductor devices are configured as at least one of a GaN-based field-effect transistor (FET) and a GaN-based high electron-mobility transistor (HEMT), To constitute at least one sub-device area as one or more parts of an impedance matching circuit, a matching circuit, an input matching circuit, an output matching circuit, an intermediate matching circuit, a harmonic termination section, a harmonic termination circuit, and a matching circuit network, The semiconductor device mounting process according to claim 31, further comprising:

56. The system comprises at least one active area, where one or more semiconductor devices are arranged, The semiconductor device is configured as at least one of the following: wide bandgap semiconductor device, ultra-wideband device, GaN-based device, GaN-on-SiC device, GaN-on-Si device, metal-semiconductor field-effect transistor (MESFET), metal oxide field-effect transistor (MOSFET), junction field-effect transistor (JFET), bipolar junction transistor (BJT), lateral diffusion metal oxide semiconductor (LDMOS), insulated gate bipolar transistor (IGBT), high electron mobility transistor (HEMT), and wide bandgap (WBG) semiconductor. The semiconductor device mounting process according to claim 31, further comprising:

57. The semiconductor device mounting process according to claim 31, further comprising configuring at least one subdevice area as one or more of resistors, inductors, capacitors, metal oxide silicon (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power couplers, power distributors, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, fundamental frequency matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), and matching network.

58. The semiconductor device mounting process according to claim 31, wherein the support portion includes at least one of a paddle, a surface, a package support portion, a package surface, a package support surface, a metal submount, a flange, a metal flange, a heat sink, a common source support portion, a common source surface, a common source package support portion, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a lead frame, and a metal lead frame.

59. The semiconductor device mounting process according to claim 31, wherein the die attach material comprises one or more metallic materials and one or more non-metallic materials.

60. The invention further comprises at least an overmolding configuration surrounding the semiconductor die, The semiconductor device mounting process according to claim 31, wherein the die attach material includes at least a portion of at least one channel disposed between the overmolding configuration and the support portion.

61. A semiconductor die including at least one subdevice area, Support part and A die attach material configured to attach the lower surface of the semiconductor die to the upper surface of the support portion, Equipped with, The die attach material is structured and arranged on the support portion and comprises at least one channel, The semiconductor die is positioned on at least a portion of the at least one channel that is positioned on the support portion, The at least one channel is positioned vertically below the active area of ​​the semiconductor die and is offset laterally from the active area. At least a portion of the at least one channel is positioned between the at least one sub-device area of ​​the semiconductor die and the support portion, and gas generated during the curing of the die attach material can be released from the die attach material when the semiconductor die is attached to the support portion. Semiconductor equipment.

62. The semiconductor device according to claim 61, wherein the semiconductor die is a Group III nitride-based HEMT (high electron mobility transistor).

63. The semiconductor device according to claim 61, wherein the semiconductor die is a Group III nitride-based MMIC (monolithic microwave integrated circuit).

64. The semiconductor device according to claim 63, wherein the group III nitride-based MMIC comprises a plurality of group III nitride-based HEMTs (high electron mobility transistors) and at least one sub-device area.

65. The semiconductor device according to claim 61, further comprising an overmolding on the support portion, wherein the die attach material includes at least a portion of the at least one channel disposed between the overmolding and the support portion.

66. The semiconductor device according to claim 61, wherein the at least one channel includes a plurality of channels.

67. The semiconductor device according to claim 61, wherein the at least one channel includes at least two intersecting channels.

68. The semiconductor device according to claim 61, wherein three or more of the at least one channel intersect.

69. The semiconductor device according to claim 61, wherein the at least one channel constitutes a mesh.

70. The semiconductor device according to claim 61, wherein the die attach material comprises metal particles in an organic material.

71. The semiconductor device according to claim 61, wherein the die attach material includes a sintered material.

72. The semiconductor device according to claim 61, wherein the die attach material includes at least one of a silver sintered material or a copper sintered material.

73. The semiconductor device according to claim 61, wherein the semiconductor die comprises an integrated circuit.

74. The at least one channel is located below the at least one sub-device area. The semiconductor device according to claim 61, wherein the semiconductor die comprises a monolithic microwave integrated circuit (MMIC).

75. The semiconductor device according to claim 61, wherein the at least one channel includes at least one exhaust port and at least one side edge.

76. The semiconductor device according to claim 61, wherein the at least one channel includes at least one of the following shapes: rectangular, polygonal, circular, free-form, continuous, discontinuous, and combinations thereof.

77. The semiconductor device according to claim 61, wherein the at least one channel divides the die attach material.

78. The semiconductor device according to claim 61, wherein at least one side edge of the at least one channel is configured to form a surface of the die attach material that allows gas generated during the curing of the die attach material to be released from the die attach material.

79. The semiconductor device according to claim 61, wherein the at least one channel is configured to receive gas generated during curing from below at least one active area, and once the gas is taken into the at least one channel, the gas can travel along the at least one channel and be discharged from the at least one channel through an exhaust port.

80. The semiconductor device according to claim 61, wherein the die attach material is constructed using one of the following processes: a screen printing process, a preform process, a needle ejection process, and an inkjet ejection process.

81. The semiconductor device according to claim 61, wherein the die attach material is constructed using a screen printing process with a stencil having an opening that matches the configuration of the die attach material and a portion that does not allow application of the die attach material that matches the position of the at least one channel.

82. The package is further enhanced, The package includes at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a radio frequency (RF) amplifier package, a radio frequency (RF) power amplifier package, a radio frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, a radio frequency (RF) power amplifier transistor package, an L-band component package implementing various frequencies in the 1-2 gigahertz (GHz) radio spectrum, an S-band component package covering frequencies from 2-4 GHz, an X-band component package implementing various frequencies in the 7.0-11.2 GHz radio spectrum, a C-band component package implementing various frequencies in the 500-1000 MHz radio spectrum, a Ku-band component package for the electromagnetic spectrum in the 12-18 GHz microwave frequency range, a satellite communication component package, and a Doherty configuration package. The semiconductor device according to claim 61, wherein the semiconductor die comprises an integrated circuit.

83. The semiconductor device according to claim 61, wherein the semiconductor die includes at least one active area which includes at least one of the following: an area on which one or more transistors are located; an area on which one or more transistor amplifiers are located; an area on which one or more transformers are located; an area on which one or more voltage regulators are located; an area on which one or more heat-generating devices are located; an area on which one or more devices that benefit from low-temperature operation are located; and an area on which one or more semiconductor devices are located.

84. The semiconductor die includes at least one active area which is an area on which one or more radio frequency (RF) semiconductor devices are arranged. The semiconductor die comprises at least one of a GaN-based field-effect transistor (FET) and a GaN-based high-electron-mobility transistor (HEMT), The semiconductor device according to claim 61, wherein the at least one sub-device area includes one or more portions of an impedance matching circuit, a matching circuit, an input matching circuit, an output matching circuit, an intermediate matching circuit, a harmonic termination section, a harmonic termination circuit, and a matching circuit network.

85. The semiconductor die includes at least one active area which is an area on which one or more semiconductor devices are arranged. The semiconductor device according to claim 61, wherein the semiconductor die comprises at least one of a wide bandgap semiconductor device, an ultra-wideband device, a GaN-based device, a GaN-on-SiC device, a GaN-on-Si device, a metal-semiconductor field-effect transistor (MESFET), a metal oxide field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), a lateral diffusion metal oxide semiconductor (LDMOS), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), and a wide bandgap (WBG) semiconductor.

86. The semiconductor device according to claim 61, wherein the semiconductor die includes at least one subdevice area comprising one or more of the following: resistors, inductors, capacitors, silicon oxide (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power couplers, power distributors, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, fundamental frequency matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), and matching circuit networks.

87. The semiconductor device according to claim 61, wherein the support portion includes at least one of a paddle, a surface, a package support portion, a package surface, a package support surface, a metal submount, a flange, a metal flange, a heat sink, a common source support portion, a common source surface, a common source package support portion, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a lead frame, and a metal lead frame.

88. The semiconductor device according to claim 61, wherein the die attach material comprises one or more metallic materials and one or more non-metallic materials.

89. The invention further comprises at least an overmolding configuration surrounding the semiconductor die, The semiconductor device according to claim 61, wherein the die attach material includes at least a portion of at least one channel disposed between the overmolded structure and the support portion.

90. Semiconductor die and Support part and A die attach material having at least one channel, An overmolding configuration that surrounds the semiconductor die and has at least a portion attached to the die attach material, Equipped with, The semiconductor die is positioned on at least a portion of the at least one channel that is positioned on the support portion, The at least one channel is positioned vertically below the active area of ​​the semiconductor die and is offset laterally from the active area. The at least one channel is configured such that gas generated during the curing of the die attach material when the semiconductor die is attached to the support can be released from the die attach material. Semiconductor equipment.

91. The semiconductor device according to claim 90, wherein the semiconductor die is a Group III nitride-based HEMT (high electron mobility transistor).

92. The semiconductor device according to claim 90, wherein the semiconductor die is a Group III nitride-based MMIC (monolithic microwave integrated circuit).

93. The semiconductor device according to claim 92, wherein the group III nitride-based MMIC comprises a plurality of group III nitride-based HEMTs (high electron mobility transistors) and at least one sub-device area.

94. The semiconductor device according to claim 90, further comprising at least one sub-device area on the support portion, wherein the die attach material includes at least a portion of the at least one channel disposed between the at least one sub-device area and the support portion.

95. The semiconductor device according to claim 90, wherein the die attach material includes at least a portion of the at least one channel disposed between the overmolded structure and the support portion.

96. The semiconductor device according to claim 90, wherein the at least one channel includes a plurality of channels.

97. The semiconductor device according to claim 90, wherein the at least one channel includes at least two intersecting channels.

98. The semiconductor device according to claim 90, wherein three or more of the at least one channel intersect.

99. The semiconductor device according to claim 90, wherein the at least one channel constitutes a mesh.

100. The semiconductor device according to claim 90, wherein the die attach material comprises metal particles in an organic material.

101. The semiconductor device according to claim 90, wherein the die attach material includes a sintered material.

102. The semiconductor device according to claim 90, wherein the die attach material includes at least one of a silver sintered material or a copper sintered material.

103. The semiconductor device according to claim 90, wherein the semiconductor die comprises an integrated circuit.

104. The at least one channel is located below at least one sub-device area. The semiconductor device according to claim 90, wherein the semiconductor die comprises a monolithic microwave integrated circuit (MMIC).

105. The semiconductor device according to claim 90, wherein the at least one channel includes at least one exhaust port and at least one side edge.

106. The semiconductor device according to claim 90, wherein the at least one channel includes at least one of rectangular, polygonal, circular, free-form, continuous, discontinuous, and combinations thereof.

107. The semiconductor device according to claim 90, wherein the at least one channel divides the die attach material.

108. The semiconductor device according to claim 90, wherein at least one side edge of the at least one channel is configured to form a surface of the die attach material that allows gas generated during the curing of the die attach material to be released from the die attach material.

109. The semiconductor device according to claim 90, wherein the at least one channel is configured to receive gas generated during curing from below at least one active area, and once the gas is taken into the at least one channel, the gas can travel along the at least one channel and be discharged from the at least one channel through an exhaust port.

110. The semiconductor device according to claim 90, wherein the die attach material is constructed using one of the following processes: a screen printing process, a preform process, a needle ejection process, and an inkjet ejection process.

111. The semiconductor device according to claim 90, wherein the die attach material is constructed using a screen printing process with a stencil having an opening that matches the configuration of the die attach material and a portion that does not allow application of the die attach material that matches the position of the at least one channel.

112. The package is further enhanced, The package includes at least one of the following: a power amplifier package, a microwave power package, a microwave power amplifier package, a radio frequency (RF) amplifier package, a radio frequency (RF) power amplifier package, a radio frequency (RF) power transistor package, a monolithic microwave integrated circuit (MMIC) package, a radio frequency (RF) power amplifier transistor package, an L-band component package implementing various frequencies in the 1-2 gigahertz (GHz) radio spectrum, an S-band component package covering frequencies from 2-4 GHz, an X-band component package implementing various frequencies in the 7.0-11.2 GHz radio spectrum, a C-band component package implementing various frequencies in the 500-1000 MHz radio spectrum, a Ku-band component package for the electromagnetic spectrum in the 12-18 GHz microwave frequency range, a satellite communication component package, and a Doherty configuration package. The semiconductor device according to claim 90, wherein the semiconductor die comprises an integrated circuit.

113. The semiconductor device according to claim 90, wherein the semiconductor die includes at least one active area which includes at least one of the following: an area on which one or more transistors are located; an area on which one or more transistor amplifiers are located; an area on which one or more transformers are located; an area on which one or more voltage regulators are located; an area on which one or more heat-generating devices are located; an area on which one or more devices that benefit from low-temperature operation are located; and an area on which one or more semiconductor devices are located.

114. The semiconductor die includes at least one active area which is an area on which one or more radio frequency (RF) semiconductor devices are arranged. The semiconductor die comprises at least one of a GaN-based field-effect transistor (FET) and a GaN-based high-electron-mobility transistor (HEMT), The semiconductor device according to claim 90, wherein the semiconductor die includes at least one sub-device area which includes one or more portions of an impedance matching circuit, a matching circuit, an input matching circuit, an output matching circuit, an intermediate matching circuit, a harmonic termination section, a harmonic termination circuit, and a matching circuit network.

115. The semiconductor die includes at least one active area which is an area on which one or more semiconductor devices are arranged. The semiconductor device according to claim 90, wherein the semiconductor die comprises at least one of a wide bandgap semiconductor device, an ultra-wideband device, a GaN-based device, a GaN-on-SiC device, a GaN-on-Si device, a metal-semiconductor field-effect transistor (MESFET), a metal oxide field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), a lateral diffusion metal oxide semiconductor (LDMOS), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), and a wide bandgap (WBG) semiconductor.

116. The semiconductor device according to claim 90, wherein the semiconductor die includes at least one subdevice area comprising one or more of the following: resistors, inductors, capacitors, silicon oxide (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power couplers, power distributors, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, fundamental frequency matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), and matching circuit networks.

117. The semiconductor device according to claim 90, wherein the support portion includes at least one of a paddle, a surface, a package support portion, a package surface, a package support surface, a metal submount, a flange, a metal flange, a heat sink, a common source support portion, a common source surface, a common source package support portion, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a lead frame, and a metal lead frame.

118. The semiconductor device according to claim 90, wherein the die attach material comprises one or more metallic materials and one or more non-metallic materials.

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