Input / Output Control Device
The input/output control device synchronizes the operating frequencies of verification circuits and semiconductor memory devices by delaying transactions and responses, ensuring accurate performance verification without the frequency mismatch and cost issues of DRAM or SRAM.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2022-10-18
- Publication Date
- 2026-06-02
AI Technical Summary
The performance verification of electronic circuits using FPGAs is compromised when connected to DRAM due to frequency mismatch, and SRAM-based verification is costly.
An input/output control device is used to delay read transactions and responses between a verification circuit and a semiconductor memory device, simulating latency to match operating frequencies.
This approach maintains accuracy in performance verification by synchronizing the operating frequencies of the verification circuit and the semiconductor memory device, reducing the frequency mismatch and associated verification costs.
Smart Images
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Abstract
Description
Technical Field
[0001] This disclosure relates to an input / output control device.
Background Art
[0002] Conventionally, in the development of electronic circuits, for the verification of the performance and functions of electronic circuits, a technique of mounting an electronic circuit to be verified on an FPGA (Field Programmable Gate Array) for verification is known. According to such a verification method, verification can be performed in a shorter time compared to software-based verification.
Prior Art Documents
Non-Patent Documents
[0003]
Non-Patent Document 1
Non-Patent Document 2
Summary of the Invention
Problems to be Solved by the Invention
[0004] When the electronic circuit being tested requires a large amount of memory, verification is sometimes performed by connecting DRAM (Dynamic Random Access Memory) to an FPGA. However, since the operating frequency of DRAM is significantly faster than that of FPGAs, there is a problem in that the performance of the electronic circuit cannot be properly verified. There is also a method of verification using SRAM (Static Random Access Memory), which has a slower operating frequency than DRAM, but SRAM is more expensive than DRAM, which increases the verification cost. [Means for solving the problem]
[0005] This disclosure can be implemented in the following forms:
[0006] According to one embodiment of the present disclosure, an input / output control device (200) is provided. This input / output control device is connected between a verification circuit (100) and a semiconductor memory device (320) and controls the input and output of data, and includes a first port (210) for receiving a read transaction from the verification circuit requesting the reading of data from the semiconductor memory device and outputting a read response received from the semiconductor memory device in response to the read transaction to the verification circuit, and a second port (240) for outputting the read transaction to the semiconductor memory device and receiving the read response output from the semiconductor memory device in response to the read transaction, The input / output control device is equipped with, The following are performed: delay the output of the read transaction to the semiconductor memory device, and delay the output of the read response to the verification circuit in order to simulate the latency when the semiconductor memory device is connected to the electronic circuit simulated by the verification circuit. .
[0007] According to this type of input / output control device, at least one of the output of a read transaction to the semiconductor memory device and the output of a read response to the verification circuit is delayed, thereby suppressing the difference between the operating frequency of the verification circuit and the operating frequency of the semiconductor memory device, and thus suppressing a decrease in the accuracy of performance verification of the verification circuit. [Brief explanation of the drawing]
[0008] [Figure 1] This is a block diagram showing the schematic configuration of the input / output control device of the first embodiment. [Figure 2] This flowchart shows the procedure for transaction output processing in the first embodiment. [Figure 3] This flowchart shows the procedure for processing the response output in this embodiment. [Figure 4] This is a block diagram showing the schematic configuration of the input / output control device of the second embodiment. [Figure 5] This flowchart shows the procedure for transaction output processing in the second embodiment. [Figure 6] This is a flowchart showing the procedure for setting the target bandwidth in the second embodiment. [Figure 7] This is an explanatory diagram illustrating an example of the relationship between the average amount of bank access data and the target bandwidth. [Modes for carrying out the invention]
[0009] A. First Embodiment: A-1.Device configuration: As shown in Figure 1, the input / output control device 200 is connected between the verification circuit 100 and the memory system 300, and controls the input and output of data between the verification circuit 100 and the memory system 300. More specifically, the input / output control device 200 delays the output of read transactions from the verification circuit 100 to the memory system 300 and the output of read responses from the memory system 300 to the verification circuit 100 by a predetermined number of cycles.
[0010] In this embodiment, the verification circuit 100 is implemented using an FPGA (Field Programmable Gate Array) and comprises an arithmetic unit 110 and a bus 120. The arithmetic unit 110 is connected to the input / output control device 200 via the bus 120 and outputs transactions requesting data access to the memory system 300 to the input / output control device 200. In the following description, a transaction requesting to read data from the memory system 300 is referred to as a "read transaction". In this embodiment, the read transaction output from the arithmetic unit 110 has at least an ID, a data amount, and the address of the target to be accessed.
[0011] The memory system 300 comprises a memory controller 310 and a semiconductor memory device 320. The memory controller 310 converts transactions output from the input / output control device 200 into protocols for processing by the semiconductor memory device 320 and outputs them to the semiconductor memory device 320. The memory controller 310 also converts data output from the semiconductor memory device 320 into read responses for processing by the arithmetic unit 110 according to the protocol and outputs them to the input / output control device 200 via the bus 10. The read responses have the same ID as the corresponding read transactions.
[0012] The semiconductor memory device 320 is configured to allow reading and writing of data to any storage unit specified by the protocol output from the memory controller 310. In this embodiment, the semiconductor memory device 320 is configured as a DRAM having banks B0 and B1. The semiconductor memory device 320 may have only one bank or three or more banks.
[0013] The input / output control device 200 includes a slave port 210, a bandwidth counter device 220, elapsed cycle counters 231 to 234, a master port 240, and a buffer device 250.
[0014] The slave port 210 is connected to the verification circuit 100 and receives transactions from the verification circuit 100 and outputs read responses to the verification circuit 100. The slave port 210 corresponds to the "first port" in the present disclosure.
[0015] The bandwidth counter device 220 counts the access data volume and holds back the output of the read transaction to the memory system 300 when the access data volume within a preset time exceeds the preset target bandwidth. "Access data volume" means the total value per unit time of the data volume of the read transaction output to the memory system 300. "Target bandwidth" means a value that determines the target of the usage bandwidth of the bus 10. Also, when the access data volume becomes less than or equal to the target bandwidth, the bandwidth counter device 220 outputs the read transaction to the memory system 300 via the master port 240. The specific processing by the bandwidth counter device 220 will be described in the transaction output processing described later.
[0016] The elapsed cycle counters 231 to 234 hold the number of elapsed cycles since the read transaction was output to the memory system 300 for each read transaction. Also, each of the elapsed cycle counters 231 to 234 has a parameter (hereinafter also referred to as "busy") indicating whether or not it is counting and holding the number of elapsed cycles. Busy "0" indicates that the number of elapsed cycles is not being held, that is, not being counted, and busy "1" indicates that the number of elapsed cycles is being held, that is, being counted. The specific processing by the elapsed cycle counters 231 to 234 will be described in the transaction output processing and response output processing described later.
[0017] In the input / output control device 200 of the present embodiment, it is preferable that the number of elapsed cycle counters provided is the same as the maximum number of outstanding read transactions. The "maximum number of outstanding" means the maximum number of read transactions that the arithmetic unit 110 can continuously output without receiving a read response. With such a configuration, the input / output control device 200 can process the read transactions continuously output from the arithmetic unit 110 in parallel without excess or deficiency.
[0018] The master port 240 is connected to the memory system 300 and performs output of transactions to the memory system 300 and reception of read responses from the memory system 300. The master port 240 corresponds to the "second port" in the present disclosure.
[0019] The buffer device 250 holds the read response when the number of elapsed cycles is less than a preset threshold. In the present embodiment, the buffer device 250 holds the read response in a FIFO (First-In First-Out) format. Further, when the number of elapsed cycles becomes equal to or more than the threshold, the buffer device 250 outputs the read response to the verification circuit 100 via the slave port 210. Specific processing by the buffer device 250 will be described in the response output processing described later.
[0020] A-2. Transaction output processing: When the input / output control device 200 outputs a read transaction to the memory system 300, it executes the transaction output processing shown in FIG. 2. When a read transaction is output from the verification circuit 100, the bandwidth counter device 220 determines whether the access data amount is below the target bandwidth (step S110).
[0021] If it is determined that the amount of access data is less than or equal to the target bandwidth (step S110: Yes), the input / output control device 200 determines whether at least one of the elapsed cycle counters 231 to 234 is busy (step S120). If it is determined that at least one of the elapsed cycle counters 231 to 234 is busy (step S120: Yes), the input / output control device 200 receives the read transaction via the slave port 210 (step S130).
[0022] On the other hand, if it is determined that the amount of access data exceeds the target bandwidth (step S110: No), or if all of the elapsed cycle counters 231 to 234 are busy (step S120: No), the input / output control device 200 stops receiving read transactions on the slave port 210. In this embodiment, while the reception of read transactions is stopped, the read transactions are held in the verification circuit 100.
[0023] In step S140, the bandwidth counter device 220 adds the amount of data from the received read transaction (hereinafter also referred to as "received data amount") to the amount of access data it holds, and sets this value as the new access data amount. In step S150, the bandwidth counter device 220 also records the time when the received data amount was added to the access data amount.
[0024] In step S160, the bandwidth counter device 220 outputs the read transaction via the master port 240.
[0025] In step S170, the busy status of one of the elapsed cycle counters 231 to 234 (hereinafter also referred to as the "selected counter") that is currently 0 is changed to "1", and the ID and data amount of the output transaction are recorded. Also, in step S180, the selected counter starts counting the number of elapsed cycles. After each cycle, the selected counter adds "1" to the number of elapsed cycles it currently holds and stores a new value.
[0026] The input / output control device 200 repeatedly executes steps S110 to S180 described above each time a read transaction is output from the verification circuit 100.
[0027] In parallel with steps S110 to S180 described above, the bandwidth counter device 220 subtracts the amount of data that has been added and for which a predetermined time has elapsed from the amount of access data (step S190). In this embodiment, the bandwidth counter device 220 can count and maintain the amount of access data within a predetermined time frame by repeatedly performing this step.
[0028] A3. Response output processing: When the input / output control device 200 outputs a read response to the verification circuit 100, it performs the response output processing shown in Figure 3. When the input / output control device 200 receives a read response via the master port 240 (step S210: Yes), the buffer device 250 holds the received read response (step S220). The buffer device 250 repeatedly executes steps S210 and S220.
[0029] In parallel with steps S210 and S220, the buffer device 250 determines whether the number of elapsed cycles of the corresponding counter is equal to or greater than a preset threshold (step S230). The "corresponding counter" refers to the elapsed cycle counter among the elapsed cycle counters 231 to 234 whose recorded ID matches the ID of the first data in the buffer device 250. If it is determined that the number of elapsed cycles of the corresponding counter is less than the threshold (step S230: No), the buffer device 250 waits with the data in abeyance.
[0030] If it is determined that the number of elapsed cycles of the corresponding counter is greater than or equal to a threshold (step S230: Yes), the buffer device 250 outputs the first data via the slave port 210 (step S240). This threshold is set as a value determined in advance through experiments, etc., to simulate the latency when the memory system 300 is connected to the electronic circuit simulated by the verification circuit 100.
[0031] In step S250, the buffer device 250 determines whether the amount of data recorded in the corresponding counter has been output (step S250). If it is determined that the amount of data recorded in the corresponding counter has not been output (step S250: No), the buffer device 250 repeatedly executes steps S240 and S250 until the amount of data recorded in the corresponding counter has been output.
[0032] If it is determined that the amount of data recorded in the corresponding counter has been output (step S250: Yes), the buffer device 250 resets the busy state of the corresponding counter to "0" and erases the recorded ID and amount of data (step S260). After this step, the corresponding counter becomes capable of counting the number of elapsed cycles of other read transactions again. The input / output control device 200 repeatedly executes steps S230 to S260.
[0033] According to the input / output control device 200 described above, the output of read transactions to the memory system 300 and the output of read responses to the verification circuit 100 are delayed, thereby suppressing the difference between the operating frequency of the verification circuit 100 and the operating frequency of the memory system 300, and thus suppressing a decrease in the accuracy of performance verification of the verification circuit 100.
[0034] B. Second Embodiment: The input / output control device 200A of the second embodiment differs from the input / output control device 200 of the first embodiment in that it includes a target bandwidth generation device 260, as shown in Figure 4, and that it executes a target bandwidth setting process (step S1400) after step S140 in the transaction output processing, as shown in Figure 5. The other device configurations and other procedures in the transaction output processing of the input / output control device 200A of the second embodiment are the same as those of the input / output control device 200 of the first embodiment, so the same reference numerals are used for the same configurations and procedures, and their detailed descriptions are omitted.
[0035] As shown in Figure 4, the target bandwidth generation device 260 includes bank access counter devices 261 and 262 and a bandwidth setting unit 263. The bank access counter devices 261 and 262 count and store the amount of bank access data for banks B0 and B1, respectively, and record the last accessed page for each bank. "Bank access data amount" means the total amount of data for read transactions issued consecutively for the same page in each bank. "Last accessed page" means the page address that was the target of the last output read transaction in each bank. The number of bank access counter devices in the target bandwidth generation device 260 is the same as the number of banks in the semiconductor memory device 320. The processing in the bank access counter devices 261 and 262 will be explained in the target bandwidth setting process described later.
[0036] The bandwidth setting unit 263 calculates the average value of the bank access data volume held in the bank access counter devices 261 and 262, respectively. The bandwidth setting unit 263 then uses the calculated average value of the bank access data volume to set the target bandwidth.
[0037] As shown in Figure 5, the target bandwidth generation device 260 performs a target bandwidth setting process after step S140 (step S1400) and updates the target bandwidth referenced in step S110 described above.
[0038] In the target bandwidth setting process shown in Figure 6, the target bandwidth generator 260 determines whether the bank address accessed by the read transaction is "0" or "1" (step S1410). If it is determined that the bank address accessed is "0", it determines whether the page address accessed by the received read transaction (hereinafter also referred to as the "currently accessed page") is the same as the previously accessed page in bank B0 (step S1420).
[0039] If the currently accessed page is the same as the previously accessed page (step S1420: Yes), the bank access counter device 261 sets the amount of received data to be the sum of the amount of bank access data held (step S1430).
[0040] If the accessed page this time is different from the accessed page last time (step S1420: No), the bank access counter device 261 sets the received data amount as the new bank access data amount and records the accessed page this time (step S1432).
[0041] On the other hand, if the target bank address is determined to be "1", it is determined whether the currently accessed page is the same as the previously accessed page in bank B1 (step S1422).
[0042] If the accessed page is the same as the previously accessed page (step S1422: Yes), the bank access counter device 262 sets the amount of received data to be the sum of the amount of bank access data held (step S1434).
[0043] If the accessed page this time is different from the accessed page last time (step S1422: No), the bank access counter device 262 sets the received data amount as the new bank access data amount and records the accessed page this time (step S1436).
[0044] In step S1440, the bandwidth setting unit 263 calculates the average value of the bank access data amounts counted and held by the bank access counter devices 261 and 262, respectively, and sets the target bandwidth from the calculated average value. In this embodiment, the bandwidth setting unit 263 sets the target bandwidth using the table shown in Figure 7, which shows the relationship between the average value of the bank access data amount and the target bandwidth. In this embodiment, the table has a relationship in which the target bandwidth increases as the average value of the bank access data amount increases. More specifically, the table has a relationship in which the slope of the increase in the target bandwidth decreases as the average value of the bank access data amount increases. With this, the target bandwidth generation device 260 completes the target bandwidth setting process.
[0045] According to the input / output control device 200A of the second embodiment described above, the target bandwidth is set according to the average value of the amount of bank access data counted and held in each of the bank access counter devices 261 and 262. Therefore, the output of read transactions to the memory system 300 can be delayed in accordance with changes in the amount of access data, and the decrease in the accuracy of performance verification of the verification circuit 100 can be further suppressed.
[0046] C. Other embodiments: (C1) In the above embodiment, the number of elapsed cycle counters is the same as the number of maximum outstanding numbers, but the disclosure is not limited thereto. The number of elapsed cycle counters may be less than the number of maximum outstanding numbers. This configuration also produces the same effects as the above embodiment.
[0047] (C2) In the above embodiment, the input / output control device 200 includes a buffer device 250 and a bandwidth counter device 220, but the disclosure is not limited thereto. The input / output control device 200 may include only the buffer device 250 among the buffer device 250 and the bandwidth counter device 220. In this configuration as well, the input / output control device 200 can delay the output of the read response to the verification circuit 100, thereby suppressing the difference between the operating frequency of the verification circuit and the operating frequency of the semiconductor memory device 320, and suppressing a decrease in the accuracy of performance verification of the verification circuit 100.
[0048] (C3) In the above embodiment, the table has a relationship in which the slope of the increase in target bandwidth decreases as the average value of the bank access data increases, but the disclosure is not limited thereto. The table may have a relationship in which the target bandwidth increases linearly as the average value increases. This form also produces the same effects as the above embodiment.
[0049] The input / output control device 200 and its method described herein may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. Alternatively, the input / output control device 200 and its method described herein may be implemented by a dedicated computer provided by configuring a processor by one or more dedicated hardware logic circuits. Alternatively, the input / output control device 200 and its method described herein may be implemented by one or more dedicated computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured by one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium.
[0050] This disclosure is not limited to the embodiments described above, and can be implemented in various configurations without departing from its spirit. For example, the technical features in each embodiment corresponding to the technical features in the embodiments described in the summary of the invention can be replaced or combined as appropriate in order to solve some or all of the above-described problems, or to achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be deleted as appropriate. [Form 1] An input / output control device (200) is connected between a verification circuit (100) and a semiconductor memory device (320) and controls the input and output of data, A first port (210) receives a read transaction from the verification circuit requesting the reading of data from the semiconductor memory device, and outputs a read response received from the semiconductor memory device in response to the read transaction to the verification circuit, A second port (240) for outputting the read transaction to the semiconductor memory device and receiving the read response output from the semiconductor memory device in response to the read transaction, A buffer device (250) for delaying at least one of the output of the read transaction to the semiconductor memory device and the output of the read response to the verification circuit, Equipped with, Input / output control device. [Form 2] An input / output control device as described in Embodiment 1, The device further includes elapsed cycle counters (231, 232, 233, 234) that count the number of elapsed cycles since the read transaction was output to the semiconductor memory device for each read transaction. The buffer device holds the read response when the number of elapsed cycles is less than a preset threshold, and outputs the read response to the verification circuit via the first port when the number of elapsed cycles becomes equal to or greater than the threshold. Input / output control device. [Form 3] An input / output control device according to Embodiment 2, The number of elapsed cycle counters is equal to the maximum number of outstanding read transactions. Input / output control device. [Form 4] An input / output control device according to any one of the three embodiments, The semiconductor memory device is equipped with a bandwidth counter device (220) that counts the amount of access data, which is the total amount of data from the read transactions output to the semiconductor memory device. The bandwidth counter device withholds output of the read transaction to the semiconductor memory device via the second port when the amount of access data exceeds the set target bandwidth, and outputs the read transaction to the semiconductor memory device via the second port when the amount of access data falls below the target bandwidth. Input / output control device. [Form 5] An input / output control device according to Embodiment 4, The bandwidth counter device suspends the output of the read transaction to the semiconductor memory device if the amount of access data within a predetermined time exceeds the predetermined target bandwidth. Input / output control device. [Form 6] An input / output control device according to Embodiment 4, The system further comprises a target bandwidth generation device (260) that generates the target bandwidth of the bandwidth counter device, The aforementioned target bandwidth generating device is Multiple bank access counter devices (261, 262) are provided in the same number as the number of banks in the semiconductor memory device, and each counts the bank access data amount, which is the sum of the data amounts of the read transactions issued consecutively for the same page in each of the banks, targeting different banks. A bandwidth setting unit (263) calculates the average value of the amount of bank access data counted by each bank access counter device and sets the target bandwidth using a pre-set table that shows the relationship between the calculated average value and the target bandwidth, Equipped with, Each bank access counter device, in each bank, if the current access page, which is the target of the received read transaction, and the previous access page, which is the target of the previously outputted read transaction, are the same, then the new access data amount is the sum of the bank access data amount and the data amount of the read transaction; and if the current access page and the previous access page are different, then the new bank access data amount is the data amount of the read transaction. Input / output control device. [Form 7] An input / output control device according to Embodiment 6, The table is set such that the target bandwidth increases as the average value increases. Input / output control device. [Explanation of symbols]
[0051] 100…Verification circuit, 200…Input / output control device, 210…Slave port, 240…Master port, 250…Buffer device, 320…Semiconductor memory device
Claims
1. An input / output control device (200) is connected between a verification circuit (100) and a semiconductor memory device (320) and controls the input and output of data, A first port (210) receives a read transaction from the verification circuit requesting the reading of data from the semiconductor memory device, and outputs a read response received from the semiconductor memory device in response to the read transaction to the verification circuit, The device includes a second port (240) for outputting the read transaction to the semiconductor memory device and receiving the read response output from the semiconductor memory device in response to the read transaction, The aforementioned input / output control device is Delaying the output of the read transaction to the semiconductor memory device, The output of the read response to the verification circuit is delayed in order to simulate the latency that would occur if the semiconductor memory device were connected to the electronic circuit simulated by the verification circuit. Perform at least one of the following: Input / output control device.
2. An input / output control device according to claim 1, For each of the aforementioned read transactions, there are elapsed cycle counters (231, 232, 233, 234) that count the number of elapsed cycles since the read transaction was output to the semiconductor memory device, The system further comprises a buffer device for holding the read response, The buffer device holds the read response when the number of elapsed cycles is less than a preset threshold, and outputs the read response to the verification circuit via the first port when the number of elapsed cycles becomes equal to or greater than the threshold. Input / output control device.
3. An input / output control device according to claim 2, The number of elapsed cycle counters is equal to the maximum number of outstanding read transactions. Input / output control device.
4. An input / output control device according to any one of claims 1 to 3, The semiconductor memory device is equipped with a bandwidth counter device (220) that counts the amount of access data, which is the total amount of data from the read transactions output to the semiconductor memory device. The bandwidth counter device withholds output of the read transaction to the semiconductor memory device via the second port when the amount of access data exceeds the set target bandwidth, and outputs the read transaction to the semiconductor memory device via the second port when the amount of access data falls below the target bandwidth. Input / output control device.
5. An input / output control device according to claim 4, The bandwidth counter device suspends the output of the read transaction to the semiconductor memory device if the amount of access data within a predetermined time exceeds the predetermined target bandwidth. Input / output control device.
6. An input / output control device according to claim 4, The system further comprises a target bandwidth generation device (260) that generates the target bandwidth of the bandwidth counter device, The aforementioned target bandwidth generating device is Multiple bank access counter devices (261, 262) are provided in the same number as the number of banks in the semiconductor memory device, and each counts the bank access data amount, which is the sum of the data amounts of the read transactions issued consecutively for the same page in each of the banks, targeting different banks. A bandwidth setting unit (263) calculates the average value of the amount of bank access data counted by each of the bank access counter devices, and sets the target bandwidth using a pre-set table that shows the relationship between the calculated average value and the target bandwidth, Equipped with, Each bank access counter device, in each bank, if the current access page, which is the target of the received read transaction, and the previous access page, which is the target of the previously outputted read transaction, are the same, then the new access data amount is the sum of the bank access data amount and the data amount of the read transaction; and if the current access page and the previous access page are different, then the new bank access data amount is the data amount of the read transaction. Input / output control device.
7. An input / output control device according to claim 6, The table is set such that the target bandwidth increases as the average value increases. Input / output control device.