SoC module
The SoC module addresses complex access management in shared cache memory by prioritizing processor cores and using access suppression units to reduce contention and software development costs, enhancing efficiency and power management.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2023-04-24
- Publication Date
- 2026-06-02
AI Technical Summary
In SoC modules with shared cache memory, complex control is necessary to manage access timings and addresses for multiple processors, leading to increased software development costs.
An SoC module with processor cores having predetermined priorities, a profile acquisition unit to monitor access patterns, and an access conflict adjustment unit to determine a preferred core, along with access suppression units to manage access conflicts, thereby simplifying control and reducing contention.
Suppresses contention between processor cores with simpler control, reducing software development costs and latency, while minimizing power consumption.
Smart Images
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Abstract
Description
Technical Field
[0001] This disclosure relates to a SoC module.
Background Art
[0002] Conventionally, a SoC module including a plurality of processors has been known (Patent Document 1). In such a SoC module, in order to reduce the area of the module, it has been desired to share a cache memory among a plurality of processors. For reducing the area of the module, the storage capacity of such a cache memory becomes smaller than the total capacity of the cache memories provided for each of the conventional processors.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] In such a cache memory, in order to suppress competition between processors for access to the cache memory, if access timings and accessible addresses are defined in advance for each processor, complicated control becomes necessary, and an increase in the cost of software development becomes a problem.
Means for Solving the Problems
[0005] This disclosure can be realized in the following forms.
[0006] According to one embodiment of this disclosure, an SoC module (100) is provided. This SoC module includes a plurality of processor cores (111, 112), each with a predetermined priority for arithmetic processing; a cache memory (120) accessed by the plurality of processor cores to read and write data; a profile acquisition unit (130) that acquires access profile information showing the time change of the access destination address of the cache memory by each of the plurality of processor cores; and a function that uses the access profile information to determine whether the access to the cache memory by at least two of the plurality of processor cores conflicts with each other; and among the plurality of conflicting processor cores that are competing with each other, the other The system includes an access conflict adjustment unit (140) that determines a preferred core, which is a competing core that will execute the access with priority over competing cores, and a plurality of access suppression units (151, 152) provided corresponding to each of the plurality of processor cores, which control the execution and cessation of the access to the cache memory by each of the processor cores, wherein the access conflict adjustment unit determines the competing core with the higher priority among the plurality of competing cores as the preferred core, and the access suppression unit provided corresponding to the non-preferred core, which is a competing core that is not the preferred core among the plurality of competing cores, stops the access by the non-preferred core.
[0007] This type of SoC module allows for the suppression of contention between processor cores by determining the core with the higher priority among multiple competing cores as the preferred core and preventing non-priority cores from accessing the cache memory. Therefore, contention between processor cores can be suppressed with simpler control compared to configurations where access timing and accessible addresses are predetermined for each processor core, thereby reducing the increase in software development costs. [Brief explanation of the drawing]
[0008] [Figure 1]This is an explanatory diagram showing the schematic configuration of the SoC module of this embodiment. [Figure 2] This chart shows an example of the relationship between the accessed address and the timing of the access. [Figure 3] This flowchart shows the access control procedure in this embodiment. [Modes for carrying out the invention]
[0009] A. First Embodiment: A-1.Device configuration: The SoC module 100 accesses data stored in the main memory 200 and sequentially executes predetermined arithmetic processes. In this embodiment, the SoC module 100 performs arithmetic processes using a neural network. As shown in Figure 1, the SoC module 100 of this embodiment includes processor cores 111 and 112, cache memory 120, bus BS, profile acquisition unit 130, access conflict adjustment unit 140, and access suppression units 151 and 152.
[0010] In this embodiment, processor cores 111 and 112 are configured as NPUs (Neural Network Processing Units) that perform computational processing using neural networks. For example, processor cores 111 and 112 perform computational processing to output feature quantities for identifying pedestrians, structures, etc., contained in image data captured by a camera mounted on a vehicle. Processor cores 111 and 112 each operate and perform computational processing according to a clock signal supplied via bus BS from a clock generation circuit CLK located outside the SoC module 100. Note that processor cores 111 and 112 are not limited to computational processing using neural networks, but may also be configured as CPUs (Central Processing Units) that sequentially execute predetermined computational processing. The specific configuration of processor cores 111 and 112 is the same as that of known NPUs, so a detailed explanation is omitted. Note that the number of processor cores in the SoC module 100 is not limited to two, but may be three or more.
[0011] Furthermore, processor cores 111 and 112 each have pre-set processing priorities. In this embodiment, "processing priority" refers to the degree to which the processing of the processing in either processor core 111 or processor core 112 will be given priority. The processing priority is determined according to the type of processing to be performed in each processor core, for example, so that the processor core performing processing that requires more real-time processing has a higher priority. In the following description, we will explain using the case where the priority set for processor core 111 is higher than the priority set for processor core 112 as an example.
[0012] The main memory 200 and the processor cores 111 and 112 are connected to each other via a bus BS. The main memory 200 stores various data that are input and output via the bus BS during arithmetic processing performed by the processor cores 111 and 112, such as image data and coefficients used in arithmetic processing. In this embodiment, the main memory 200 is configured as DRAM (Dynamic Random Access Memory).
[0013] The cache memory 120 is located on the bus BS between the processor cores 111 and 112 and the main memory 200. The cache memory 120 is accessed by the processor cores 111 and 112 to read and write data. More specifically, when data is read from the main memory 200 to the processor core 111 or processor core 112, the cache memory 120 stores that data. When the processor core 111 or processor core 112 requests to read the same data again, the processor core reads the data from the cache memory 120 instead of the main memory 200. This reduces the frequency of access from the processor core to the main memory 200, which takes time to access data, and suppresses a decrease in data access efficiency. In this embodiment, the cache memory 120 is configured as SRAM (Static Random Access Memory) capable of high-speed data reading and writing.
[0014] The profile acquisition unit 130 is located on the bus BS between the processor cores 111 and 112 and the cache memory 120. The profile acquisition unit 130 acquires access profile information for each of the processor cores 111 and 112. "Access profile information" refers to information that shows the time change of the access destination address of the cache memory 120 accessed by each processor core. In this embodiment, the access profile information includes information that shows which processor core accesses which address of the cache memory 120 at which timing.
[0015] In this embodiment, the profile acquisition unit 130 uses the acquired access profile information to create a chart for each processor core showing the relationship between the access destination address and the access timing, as shown in the example in Figure 2. In the chart, the vertical axis represents the access destination address of the cache memory 120 by the processor core. The horizontal axis represents the access timing. "Access timing" refers to the timing at which the processor core accesses the access destination address. The black circles represent access by processor core 111, and the white dots represent access by processor core 112. Note that in Figure 2, for illustrative purposes, the chart showing the relationship between the access destination address and the access timing is schematically represented.
[0016] The access conflict adjustment unit 140 shown in Figure 1 acquires access profile information and determines whether the accesses by each processor core are in conflict with each other. "Conflict" means that multiple processor cores are accessing the same address in the cache memory 120. In the example shown in Figure 2, conflicts occur at access timings t1, t2, and t3. The access conflict adjustment unit 140 also determines a priority core when a conflict occurs. A "priority core" is a conflict core that is given priority over other conflict cores among multiple conflicting processor cores (hereinafter also referred to as "conflict cores"). The access conflict adjustment unit 140 uses the priority set in advance for each conflict core to determine the conflict core with the higher priority as the priority core. In the following explanation, among multiple conflict cores, those that are not priority cores are also referred to as "non-priority cores".
[0017] The access control units 151 and 152 shown in FIG. 1 are provided corresponding to the processor cores 111 and 112 respectively. Each access control unit controls the execution or stop of access by each processor core to the cache memory 120. Also, each access control unit controls the execution or stop of the supply of a clock signal to each processor core. Specific control by each access control unit will be described in the access control described later.
[0018] A-2. Access Control: As shown in FIG. 3, the SoC module 100 of this embodiment executes access control for controlling access from each processor core to the cache memory 120. The access control starts when the SoC module 100 is activated and is repeatedly executed during the activation of the SoC module 100. As shown in FIG. 2, the SoC module 100 executes the control of steps S10 and S20 and the control from step S30 to step S90 in parallel in the access control.
[0019] In step S10, the profile acquisition unit 130 acquires access profile information for each processor core. In this embodiment, the profile acquisition unit 130 can acquire access profile information by monitoring the usage status of the bus BS by each processor core.
[0020] In step S20, the profile acquisition unit 130 creates a chart showing the relationship between the access destination address and the access timing for each processor core using the acquired access profile information. The profile acquisition unit 130 repeatedly executes steps S10 and S20 at a predetermined time interval during the execution of the access control.
[0021] In step S30, the access conflict adjustment unit 140 determines whether the accesses by each processor core conflict with each other by using the created chart. More specifically, the access conflict adjustment unit 140 determines that the accesses by each processor core conflict with each other when a plurality of processor cores request access to the same address of the cache memory 120 at the same timing.
[0022] When a conflict occurs (step S30: Yes), the access conflict adjustment unit 140 determines a priority core (step S40). As described above, the access conflict adjustment unit 140 determines, as the priority core, a processor core having a higher preset priority among the plurality of processor cores. As described above, in this embodiment, since a higher priority than that of the processor core 112 is set for the processor core 111, the processor core 111 is determined as the priority core.
[0023] On the other hand, when no conflict occurs (step S30: No), the access conflict adjustment unit 140 repeatedly executes the determination in step S30. When the accesses by each processor core do not conflict with each other, each access suppression unit may cause the arithmetic processing by each processor core to be executed at an arbitrary timing.
[0024] In step S50, the access suppression unit 152 stops access by the non-priority core, the processor core 112. If access by the non-priority core is not stopped, it is possible that immediately after data is read from the main memory 200 to the cache memory 120 based on access by the priority core, different data may be read from the main memory 200 to the same address in the cache memory 120 based on access by the non-priority core. In such a case, even if the priority core reads the data it has already read, that data has been overwritten by access by the non-priority core, so it will have to read the data from the main memory 200 to the cache memory 120 again, increasing latency. To avoid such an increase in latency, the access suppression unit stops access by the non-priority core.
[0025] In step S60, the access suppression unit 152 stops supplying the clock signal to the processor core 112, which is a non-priority core. As a result, the operation of the non-priority core is stopped, and the operating power of the non-priority core is suppressed.
[0026] In step S70, the access conflict adjustment unit 140 determines whether the progress rate of access by the priority core is above a predetermined threshold. The "progress rate" refers to the ratio of already completed arithmetic operations to the total amount of arithmetic operations scheduled to be executed by the processor core. The access conflict adjustment unit 140 can grasp the progress rate of access by the priority core by referring to a chart showing the relationship between the access destination address and the access timing.
[0027] While the progress rate is below a predetermined percentage (step S70: No), the access conflict adjustment unit 140 repeatedly performs the determination in step S70 and maintains a state in which access by non-priority cores and the supply of clock signals to non-priority cores are stopped.
[0028] If the progress rate is above a predetermined percentage (step S70: Yes), the access suppression unit 152 resumes supplying the clock signal to the non-priority core processor core 112 (step S80). In step S90, the access suppression unit 152 also resumes access by the non-priority core processor core 112. This is because, for processor cores whose progress rate exceeds a threshold, the frequency of access to the cache memory 120 decreases compared to the peak, thus suppressing the frequency of the latency increase described above. The SoC module 100 repeatedly executes steps S30 to S90 as described above.
[0029] According to the SoC module 100 of the embodiment described above, among multiple competing cores, the competing core with the higher set priority is determined as the priority core, and access to the cache memory 120 by non-priority cores is stopped, thereby suppressing contention between processor cores. For this reason, contention between processor cores can be suppressed with simpler control compared to a configuration in which access timing and accessible addresses are predetermined for each processor core, and the increase in software development costs can be suppressed.
[0030] Furthermore, access by non-priority cores is resumed when the progress rate of access by priority cores exceeds a preset threshold. This allows access by non-priority cores to resume when the frequency of access to cache memory 120 by priority cores has decreased compared to its peak. As a result, the increase in latency caused by contention can be suppressed.
[0031] Furthermore, while access by non-priority cores is stopped, the supply of clock signals to non-priority cores is also stopped, thus halting the operation of non-priority cores and suppressing their operating power consumption.
[0032] B. Other embodiments: (B1) In the above embodiment, when a conflict occurs, the access suppression unit corresponding to the non-priority core stops the access by the non-priority core and stops supplying a clock signal to the non-priority core, but the disclosure is not limited thereto. The access suppression unit may continue supplying a clock signal to the non-priority core and stop only the execution of access by the non-priority core. Even with such a configuration, the occurrence of conflicts in access to the cache memory 120 by multiple processor cores can be suppressed. In addition, since the access suppression unit 151 only needs to control the execution and stopping of access by the processor core, the complexity of the configuration of the access suppression unit can be suppressed.
[0033] (B2) In the above embodiment, the access conflict adjustment unit 140 determines whether accesses are conflicting with each other for each processor core, but the disclosure is not limited thereto. The access conflict adjustment unit 140 may also determine whether accesses are conflicting with each other for each of the multiple instructions that implement the arithmetic processing executed in each processor. In this case, it is desirable that the priority of the arithmetic processing is also set for each instruction. An SoC module 100 with such a configuration will also have the same effects as the above embodiment. In addition, since it is possible to determine whether a conflict is occurring at an instruction level smaller than the processor core level, for example, while one processor core is executing arithmetic processing, another processor core can execute an instruction that targets an address that the said processor core does not access, thereby suppressing a decrease in the efficiency of the arithmetic processing.
[0034] (B3) In the above embodiment, when a conflict occurs, only the access suppression unit 151 and 152 provided for the non-priority core stops access by the non-priority core. However, the disclosure is not limited thereto. When a conflict occurs, all access suppression units may temporarily stop access by all processor cores and then resume access in order from the processor core with the highest set priority. An SoC module 100 with such a configuration will also have the same effects as the above embodiment.
[0035] (B4) In the above embodiment, the access suppression units 151 and 152 resume access by non-priority cores when the progress rate of access by priority cores exceeds a preset threshold, but the disclosure is not limited thereto. The access suppression units 151 and 152 may also resume access by non-priority cores after a predetermined time has elapsed since stopping access by non-priority cores. With such a configuration, the SoC module 100 can also resume access by non-priority cores when the frequency of access to the cache memory 120 by priority cores has decreased compared to the peak time. This makes it possible to suppress the increase in latency caused by contention.
[0036] This disclosure is not limited to the embodiments described above, and can be implemented in various configurations without departing from its spirit. For example, the technical features in each embodiment corresponding to the technical features in the embodiments described in the summary of the invention can be replaced or combined as appropriate in order to solve some or all of the above-described problems, or to achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be deleted as appropriate.
[0037] The SoC module 100 and its method described herein may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. Alternatively, the SoC module 100 and its method described herein may be implemented by a dedicated computer provided by configuring a processor by one or more dedicated hardware logic circuits. Alternatively, the SoC module 100 and its method described herein may be implemented by one or more dedicated computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured by one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium. [Explanation of symbols]
[0038] 100…SoC module, 111, 112…Processor cores, 120…Cache memory, 130…Profile acquisition unit, 140…Access contention adjustment unit, 151, 152…Access suppression unit
Claims
1. SoC module (100), Multiple processor cores (111, 112), each with a pre-set processing priority, A cache memory (120) that is accessed by the aforementioned multiple processor cores to read and write data, A profile acquisition unit (130) acquires access profile information showing the time change of the destination address of the cache memory accessed by each of the plurality of processor cores, An access conflict adjustment unit (140) that uses the access profile information to determine whether access to the cache memory by at least two of the plurality of processor cores conflicts with each other, and determines a preferred core among the plurality of conflicting processor cores that are competing with each other, which is the conflicting core that will execute the access with priority over the other conflicting cores, A plurality of access suppression units provided corresponding to each of the plurality of processor cores, the plurality of access suppression units (151, 152) that control the execution and cessation of the access to the cache memory by each of the processor cores, Equipped with, The access conflict adjustment unit determines, among the plurality of conflicting cores, the conflicting core with the higher priority as the priority core. The access suppression unit provided in response to a non-priority core, which is a competing core among the plurality of competing cores that is not the priority core, stops the access by the non-priority core. SoC module.
2. The SoC module according to claim 1, The access suppression unit restarts the access by the non-priority core when the progress rate of the access by the priority core exceeds a preset threshold. SoC module.
3. An SoC module according to claim 1 or claim 2, The access suppression unit stops supplying a clock signal to the non-priority core while the access by the non-priority core is stopped. SoC module.