Digital filter circuits, methods, and programs

Abstract

To provide a digital filter circuit, a method, and a program for amplifying, smoothing, and emphasizing stream data signals such as audio and images.SOLUTION: A digital filter circuit includes short-term memory means for capturing stream data as a digital signal, cyclically operating the first phase and the second phase, and storing local state variables, and long-term storage means for storing global state variables, and further includes first phase synthesis means for outputting, in the first phase, a digital signal under the influence of a local state variable stored in a short-term memory means, and second phase synthesis means for outputting, in the second phase, a digital signal under the influence of a global state variable stored in a long-term storage means. The output from the first phase synthesis means and the output from the second phase synthesis means produce an interference pattern due to a phase shift.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a digital filter circuit, method, and program.

Background Art

[0002] Conventionally, various digital filters have been developed.

[0003] For example, in the digital filter described in Patent Document 1, since a non-linear conversion means is inserted into the feedback loop, a distortion component due to the non-linear conversion means is generated cumulatively, a harmonic component is added to the signal in the feedback loop, and it is disclosed that thus, a rich-sounding musical tone like an analog filter can be generated.

[0004] Also, in Patent Document 2, in a state-variable type multi-mode digital filter, by inserting a non-linear circuit with soft limiter characteristics into an accumulator (integrator) composed of an adder and a delay circuit that delays by one sample period, it is disclosed that even if the adder is overflow-limited, the input signal is given an appropriate distortion without being abruptly clipped.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] As mentioned above, the state-variable multimode digital filter with a nonlinear circuit inserted into the accumulator (integrator) focuses on limiting the oscillation level. While it operates very stably even when oscillating, it does not exhibit much emphasis on amplifying or sharpening the input signal.

[0007] In view of the problems of the conventional type described above, the present invention aims to provide a digital filter circuit, method, and program that can enhance an input signal by amplifying, smoothing, or sharpening it to suitably (desired response and characteristics) in a cyclic state variable type digital filter circuit. [Means for solving the problem]

[0008] To achieve the above objective, one embodiment of the present invention is a digital filter circuit that takes stream data as a digital signal and operates a first phase and a second phase cyclically, comprising: a short-term memory means for storing local state variables; a long-term memory means for storing global state variables; a first-phase combining means for outputting the digital signal in the first phase under the influence of the local state variables stored in the short-term memory means; and a second-phase combining means for outputting the digital signal in the second phase under the influence of the global state variables stored in the long-term memory means, wherein the output from the first-phase combining means and the output from the second-phase combining means are interfered with by a phase shift.

[0009] Furthermore, an embodiment of the present invention is characterized in that, as described above, the short-term storage means stores the superimposed charge states of each cell constituting the digital filter circuit over a short period of time as the local state variable.

[0010] Furthermore, an embodiment of the present invention is characterized in that, in the above, the long-term storage means stores the superimposed charge states of each cell constituting the digital filter circuit over a long period of time as the global state variable.

[0011] Furthermore, in the embodiments of the present invention, the first phase synthesis means is characterized in that, in the first phase, when the superposition of the digital signal and the local state variable exceeds a predetermined threshold, it fires and outputs.

[0012] Furthermore, in the embodiments of the present invention, the second-phase synthesis means is characterized in that, in the second phase, it fires and outputs when the superposition of the digital signal and the global state variable exceeds a predetermined threshold.

[0013] Furthermore, embodiments of the present invention are characterized in that, in the above, the stream data is image data, sound data, thermal data, chemical substance data, gravity data, pressure data, vibration data, magnetic data, electromagnetic wave data, radiation data, attribute value pairs, language data, or biological data.

[0014] Furthermore, an embodiment of the present invention is characterized in that, in the above, the interference patterns output from the first phase synthesis means and the second phase synthesis means are images, sounds, videos, actuator control signals, and device control signals. [Brief explanation of the drawing]

[0015] [Figure 1] Figure 1 is a diagram showing the configuration of a digital filter according to the first embodiment of the present invention. [Figure 2] Figure 2 schematically illustrates a case in which a matrix (such as a digital image signal) is input as an input digital signal from an external sensor to an element unit of a digital filter circuit, and an interference pattern is output as an output matrix to an external action destination. [Figure 3] Figure 3 is a diagram showing an implementation example of a digital filter circuit unit that shows the interaction relationships between cells and the processing in each time slit. [Figure 4] Figure 4 is a diagram showing transition examples in time slits 1 to 8 of an input matrix input from an external sensor. [Figure 5] Figure 5 is a diagram showing an electroencephalogram-like waveform in a time-series display by superimposing the charging states of cells in each time slit. [Figure 6] Figure 6 is a diagram showing an output example output by the digital filter circuit of the present embodiment for 5×5 matrix data input from an external sensor. [Figure 7] Figure 7 is a diagram showing waveform data reproduced from what corresponds to the neural circuit data of a nematode heart. [Figure 8] Figure 8 is a diagram showing the application fields of the digital filter circuit of the present invention. [Figure 9] Figure 9 is a diagram showing the data flow of the present embodiment. [Figure 10] Figure 10 is a diagram showing the data structure of the data used in the present embodiment L4t4. [Figure 11] Figure 11 is a diagram showing data examples such as interaction rules. [Figure 12] Figure 12 is a diagram showing the calculation flow of each data. [Figure 13] Figure 13 is a diagram showing the content of each applied data. [Figure 14] Figure 14 is a diagram showing the applied data content and an output data example.

Embodiments for Carrying Out the Invention

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0017] Figure 1 shows the configuration of a digital filter according to a first embodiment of the present invention. This digital filter is a digital filter circuit that takes stream data as a digital signal and operates a first phase and a second phase cyclically, and comprises a first phase combining unit 101 and a second phase combining unit 102, and the output from the first phase combining unit 101 and the output from the second phase combining unit 102 cause interference due to a phase difference. Furthermore, the digital filter according to this embodiment includes an adjustment unit 103.

[0018] Of these, the first-phase combining unit 101 is a first-phase combining means that, in the first phase, outputs a digital signal under the influence of local state variables stored in a short-term memory means. The short-term memory means may be provided by the first-phase combining unit 101 itself, or by other components of the digital filter circuit. This short-term memory means stores the superposition of the charge states of each cell constituting the digital filter circuit over a short period of time as local state variables. Furthermore, in the first phase, the first-phase combining unit 101 fires and outputs when the superposition of the digital signal and the local state variables exceeds a predetermined threshold.

[0019] Furthermore, the second-phase combining unit 102 is a second-phase combining means that outputs a digital signal in the second phase under the influence of a global state variable stored in a long-term memory means. The long-term memory means may be provided by the second-phase combining unit 102 itself or by other components of the digital filter circuit. This long-term memory means stores the superposition of the charge states of each cell constituting the digital filter circuit over a long period of time as a global state variable. In addition, the second-phase combining unit 102 fires and outputs when the superposition of the digital signal and the global state variable exceeds a predetermined threshold in the second phase.

[0020] The input signal is arbitrary, but as an example, the input stream data (also called data stream) may be time-series data such as wave data, and may be image data, sound data, thermal data, chemical data, gravity data, pressure data, vibration data, magnetic data, electromagnetic wave data, radiation data, attribute value pairs, language data, or biological data. The output signal is also arbitrary depending on the input signal, but as an example, the interference patterns output from the first-phase synthesis unit 101 and the second-phase synthesis unit 102 may be image, sound, video, actuator control signals, or device control signals.

[0021] As a further example, in this embodiment, the first-phase synthesis unit 101, the second-phase synthesis unit 102, and the adjustment unit 103 are composed of cells (F1-6, B1,2,4,6, L1,7) as shown in the figure. The cells simulate living cells; for example, a cell simulating a nerve cell fires when the superposition of a digital signal on the input side connected like a synapse and a state variable indicating the charge state exceeds a predetermined threshold, and outputs a signal to the output side connected like a synapse. Note that in Figure 1, the connection lines for each part (first-phase synthesis unit 101, second-phase synthesis unit 102, adjustment unit 103) or each cell (F1-6, B1,2,4,6, L1,7) may be omitted, but each part and / or each cell can be configured to be connected with any connection lines as needed.

[0022] The digital filter circuit according to this embodiment is a semiconductor element unit devised based on the operating principles of biological neural circuits. As shown in Figure 1, one unit of the digital filter circuit consists of 10 unique cells (F1-6, B1,2,4,6) and 2 shared cells (L1,7). Multiple units of the same type of digital filter circuit may be combined to form a pseudo-organ, or different types of organs may be linked to form a pseudo-neural network.

[0023] As shown in Figure 1, the element unit of the digital filter circuit consists of 10 reaction cells (F1-6, B1,2,4,6) and 2 state-holding cells (L1,7). As shown in the figure, each cell is called F3, F1, F2, F4, F5, F6, B1, B2, B4, B6, L1, and L7. This configuration is specifically called the L4t4 (Layered Elements: 4 feedforward and time-sliced ​​4 feedback) model, and is an intelligent model consisting of a collection of elements in 7 layers (the numbers attached to the names of each cell represent the layer number), with 4 feedforward cells (F3, F1, F2, F4) and 4 feedback cells (F5, B1, B2, B4) each having 4 types of elements that are time-divided and operate in synchronization with the surrounding interaction cells (F6, B6). According to the device, method, program, and data structure that implement the L4t4 model, simulation results that could not be obtained with conventional artificial intelligence can be obtained, as will be described later. Although not shown in the diagram, the input side may also include a group of cells that detect changes in the external environment (external sensors), and the output side may include a group of external action target cells (actuator devices, etc.). These cells operate cyclically in synchronization and cooperation with each other. As an example, the external sensors digitize stream data from one or more external sources and take it into the system. The external action target cell group may render the output (internal digital data) of the first phase synthesis unit 101 (F4) and the second phase synthesis unit 102 (B4) into stream data (wave data, etc.) and output it for display or other purposes, or it may act on servo motors or actuators corresponding to muscle fibers in a living organism with output signals, as in robot control. Multiple element units of the digital filter circuit may be connected together.

[0024] Each unit's operation cycle is divided into two phases. F3, F1, F2, and F4, which constitute the first phase synthesis unit 101, are mainly involved in the first phase, while F5, B1, B2, and B4, which constitute the second phase synthesis unit 102, are mainly involved in the second phase.

[0025] Of these, L1 is a cell responsible for local memory, and in this embodiment, it is a short-term memory means that short-term stores local state variables that affect the response of F4. That is, L1 stores the superposition of the charge states of each cell constituting the digital filter circuit over a short period of time as local state variables.

[0026] Furthermore, F3 is the input cell, receiving input from external sensors (external sources), and if there is a connected unit on the network, it can also receive output from internal units superimposed on it.

[0027] Furthermore, F1 is a cell that plays a role in Phase 1 intervention, mediating signal transduction between F3, F2, and F4 cells.

[0028] Furthermore, F2 is the cell responsible for first-phase synchronization, primarily controlling the timing between internal cells related to the output of the F4 cell in the first phase.

[0029] Furthermore, F4 is a cell responsible for the output of the first phase, and outputs a digital value obtained from the superposition of input waveform data, which depends on the state of L1. In other words, in the first phase, F4 of the first phase synthesis unit 101 fires and outputs when the superposition of the digital signal transmitted through F3, F1, and F2 and the local state variable stored in L1, which acts as a short-term memory means, exceeds a predetermined threshold.

[0030] Furthermore, F6 is the cell responsible for the in-clock, and receives a signal from the connected unit on the input side indicating the timing of the start of the first phase.

[0031] Furthermore, B6 is the cell responsible for the out clock, and it sends a start timing signal to the connected unit on the output side.

[0032] Furthermore, F5 is the cell responsible for the pool, accumulating the values ​​from the F4 cells of each unit. In other words, F5 stores the values ​​output from the F4 of the connected unit on the input (in) side.

[0033] Furthermore, B1 is a cell that intervenes in the second phase, mediating signal transduction between F5, B2, and B4 cells.

[0034] Furthermore, B2 is the cell responsible for synchronizing the second phase, primarily controlling the timing between internal cells related to the B4 output of the second phase.

[0035] Furthermore, B4 is a cell responsible for the output of the second phase, and depending on the state of L7, it determines and outputs the digital value of its own unit according to the value accumulated (summed) in F5. In other words, B4 of the second phase synthesis unit 102 fires and outputs when the superposition of the digital signal transmitted through F5, B2, and B1 and the global state variable stored in L7, which is a long-term memory means, exceeds a predetermined threshold.

[0036] Furthermore, L7 is a cell responsible for global memory, and in this embodiment, it is a long-term memory means that stores global state variables that affect the reaction of B4. In other words, L7 stores the superimposed charge states of each cell constituting the digital filter circuit over a long period of time as global state variables.

[0037] Figure 2 schematically illustrates a case where a matrix (such as a digital image signal) is input as an input digital signal from an external sensor to the element unit of a digital filter circuit, and an interference pattern is output as an output matrix to an external action destination.

[0038] As shown in Figure 2, F3, F1, F2, and F4, which constitute the first phase synthesis unit 101, perform processing related to the first phase, and F5, B1, B2, and B4, which constitute the second phase synthesis unit 102, perform processing related to the second phase, and this processing of the first and second phases is repeated cyclically. The processing of one cycle performed by each cell is divided into 10 sections, and in more detail, processing is performed in 64 time slits.

[0039] Figure 3 shows an example of a digital filter circuit unit implementation illustrating the interaction relationships between cells and the processing at each time slit. This implementation example is merely one example, and the present invention is not limited to this example. It can be implemented in various embodiments as long as it achieves the objectives and effects of the present invention. The interaction rule table defines the communication between cells. The circuit diagram labeled L4t4 shows the signal exchange. The type of connection signal is distinguished and represented according to the direction and number of signals. Connection lines corresponding to gap junctions are indicated by thick arrows, and connection lines corresponding to chemical junctions are indicated by thin arrows. The transmitting side (filled in) and the receiving side (not filled in) are distinguished by the difference in terminals. There are three types of signals depending on the number of signals: a signal with one occurrence is issued as a reset signal, signals with 2 to 12 occurrences are issued periodically as a synchronous trigger signal or reset signal, and signals with 12 or more occurrences are issued as a timer signal (continuous pulse signal).

[0040] As described above, in the L4t4 implementation example of this embodiment, the timing control consists of 68 time slits and 10 sections in total, with each section having a time slit width of 7 (except for section 10, which has a time slit width of 5). The first phase corresponds to sections 1 to 5, and the second phase corresponds to sections 6 to 10. This L4t4 digital filter circuit has three inhibitory cells, F6, F2, and B2. These emit reset and synchronization signals according to a specified interaction rule table. Meanwhile, the other excitable cells transmit continuous pulse signals to each other. Depending on the signal intensity and the state of charge accumulated over a certain period (charge state), the synchronization signal triggers periodic hyperpolarization and depolarization of the cells. In the first section, the cycle (first and second phases) is initialized by processing the reset signal. Sections 2 through 4 generate waveforms that indicate the firing state of F4, section 6 performs the reset process of the second phase, and sections 7 through 9 generate waveforms that mainly reflect the firing of B4.

[0041] As described above, in the first phase, F4 outputs a digital value obtained from the superposition of input waveform data, depending on the local state variable stored in L1, while in the second phase, B4 determines and outputs its own digital value according to the value accumulated (summed) in F5, depending on the global state variable stored in L7. Therefore, the signals output from these two phases with a time difference interfere with each other due to the phase difference, forming an output matrix that creates an interference pattern.

[0042] Therefore, the factors that affect the output value of this digital filter circuit unit are the wave pattern of the F3 input, interference due to the phase difference between F4 and B4, fluctuations in the state values ​​of L1 and L7, and fluctuations in the pool value of F5.

[0043] An example of the element unit of the digital filter circuit implemented in this way (simulation results) is described below. Figure 4 shows an example of the transitions in time slits 1 to 8 of the input matrix input from an external sensor. As shown in Figure 4, the input signal is input to F3 as time-transforming stream data (wave data, etc.).

[0044] Figure 5 shows an electroencephalogram-like waveform displayed over time by superimposing the charge states of each cell in each time slit. Each cell is either excitatory or inhibitory, and the firing of an action potential is determined by whether the sum of the excitatory / inhibitory signals of the input reaches a specific value (threshold).

[0045] Figure 6 shows an example of the output produced by the digital filter circuit of this embodiment in response to 5x5 matrix data input from an external sensor. As shown in Figure 6, the image (pattern) of the changes in the external environment is reproduced as an internal image. This indicates that the L4t4 circuit has the function of an autoencoder.

[0046] Figure 7 shows waveform data reconstructed from neural circuit data of a nematode heart. This demonstrates that the electrical signals of the heart can be reconstructed from the neural circuit data of a nematode heart. This allows for the reproduction and output of electrical signals in devices such as artificial hearts. This indicates the presence of a digital filter circuit capable of amplifying, smoothing, or sharpening the input signal to suitably match the heartbeat (desired response and characteristics).

[0047] Figure 8 shows the application fields of the digital filter circuit of the present invention. As shown in the figure, the present invention can be applied in various fields such as the medical field, nursing care field, agriculture field, transportation field, production field, disaster prevention and safety field, and chemical field.

[0048] The data and programs used in the above-described embodiment will now be explained. Figure 9 shows the data flow of this embodiment. Assume that stream data from an external sensor is input as the value of element Sen(x,y) in an n×m matrix. The destination of the external action is output as the value of element Out(x,y). The set of L4t4 circuits is referenced by each element as a change in the variable (e1,e2) of element Cells(x,y,pre / post). Furthermore, the R2r type rule of the interaction rule table is referenced as the variable n0 of element R2r(c1,c2,c3). Similarly, the R2p type rule of the interaction rule table is referenced as the variable n0 of element R2p(c1,c2,c3). Here, the phase, section, and slit of the clock signal are represented by variables c1, c2, and c3, respectively. Interaction application is applied by elements R2rfunc(c1,c2) ​​and R2pfunc(c1,c2). Here, variables v1 and v2 represent the firing weight values ​​determined at the timing of each slit. Furthermore, state transition management reflects the variable e11 or variable e22, obtained by applying the element Syn(from1, c3, to1, c3+1) based on the interaction applied variable v1 or variable v2, into the element Cells.

[0049] Figure 10 shows the data structure of the data used in this embodiment L4t4. Figure 11 shows an example of data such as interaction rules. As shown in Figure 10, the interaction rule table R2r is, for example, an array of size r1r × r2r (8 × 4). The state transition management table Syn Times is, for example, an array of size (t1 × t2) × (r1r + r1p) * 2. The interaction rule table r2p is, for example, an array of size r1p = 11, r2p = 19. The external sensor matrix consists of, for example, q0 arrays of size s1 × s2 (size n × m). The L4t4 circuit matrix is, for example, an array of size x0 × y0 (size n × m), where k0 = 1 to 12 (corresponding to L1 to L7). The clock signal is, for example, an array of t2 slits × t1 time sections. Furthermore, the target of the external action is, for example, a matrix s1×s2 (size n×m) array data consisting of q0 frames.

[0050] Figure 12 shows the calculation flow for each data point. As shown in Figure 12, interaction rule tables R2r and R2p are applied to the x and y input matrices, respectively, and this process is repeated for each time slit and each time section.

[0051] Figure 13 shows the content of each applied data. Figure 14 shows the applied data content and an example of the output data. As a result of applying the interaction rule tables R2r and R2p shown in Figure 13, the output Out shown in the graph was obtained for the sensor input Sen shown in Figure 14. This confirmed that the L4t4 circuit outputs the result of phase difference interaction. Furthermore, by cyclically changing the state variable, the input signal can be amplified, smoothed, or sharpened to the intended output signal. For example, if the original data is sound wave data, if the first and second phases are shifted by 1 / 2 wavelength, smoothing often occurs, and if they are shifted by 1 wavelength, amplification and sharpening often occur. Therefore, the cyclic period of the first and second phases can be set according to the frequency to be amplified or smoothed. Also, by setting the length of the long-term and short-term memory, similar to a moving average for waves, it is possible to adjust whether the response to changes in waves is sensitive or coarse.

[0052] While it is obvious that the digital filter circuit of the present invention can be implemented in hardware, it may also be realized by having an MPU (CPU) or DSP of a computer execute a filtering program. Furthermore, the digital filter circuit of the present invention is not limited to the L4t4 described above, but can be applied to any digital filter that can produce a phase difference output between the first and second phases.

Claims

1. A digital filter circuit that takes stream data as a digital signal and operates the first and second phases cyclically, A first storage means for storing a local state variable that indicates the state of the stream data for the most recent predetermined first period, A second storage means for storing a global state variable that indicates a state longer than the first period of the most recent stream data, In the first phase, a first phase synthesis means outputs the digital signal based on local state variables stored in the first storage means, In the second phase, a second-phase synthesis means outputs the digital signal based on global state variables stored in the second storage means, Equipped with, A digital filter circuit characterized in that the output from the first-phase combining means and the output from the second-phase combining means can produce interference due to a phase difference.

2. The first storage means is The state of each cell constituting the digital filter circuit is superimposed during the first period and stored as the local state variable. The digital filter circuit according to claim 1, characterized by the following:

3. The second storage means is The state of each cell constituting the digital filter circuit is superimposed over a period longer than the first period and stored as the global state variable. The digital filter circuit according to claim 2, characterized by the above.

4. The first phase synthesis means is In the first phase, if the superposition of the digital signal and the local state variable exceeds a predetermined threshold, the device fires and outputs an output. A digital filter circuit according to any one of claims 1 to 3, characterized by the above.

5. The second phase synthesis means is In the second phase, if the superposition of the digital signal and the global state variable exceeds a predetermined threshold, the device fires and outputs an output. A digital filter circuit according to any one of claims 1 to 3, characterized by the above.

6. The data of the aforementioned stream is Image data, sound data, thermal data, chemical data, gravity data, pressure data, vibration data, magnetic data, electromagnetic wave data, radiation data, attribute value pairs, language data, or biometric data. A digital filter circuit according to any one of claims 1 to 3, characterized by the above.

7. The interference patterns output from the first phase synthesis means and the second phase synthesis means are It must be an image, sound, video, actuator control signal, or device control signal. A digital filter circuit according to any one of claims 1 to 3, characterized by the above.

8. A digital filtering method performed in a digital filter circuit comprising: a first storage means for storing a local state variable indicating the state of the stream data for the most recent predetermined first period, which is used to acquire stream data as a digital signal and to operate a first phase and a second phase cyclically; and a second storage means for storing a global state variable indicating the state of the stream data for a period longer than the most recent first period, wherein In the first phase, the first phase synthesis step involves outputting the digital signal based on local state variables stored in the first storage means, In the second phase, a second-phase synthesis step is performed in which the digital signal is output based on global state variables stored in the second storage means, By repeatedly executing this, A digital filter method characterized in that the output of the first phase synthesis step and the output of the second phase synthesis step can interfere with each other due to a phase difference.

9. A program for a digital filter circuit to be executed, comprising: a first storage means for storing a local state variable indicating the state of the stream data for the most recent predetermined first period, and a second storage means for storing a global state variable indicating the state of the stream data for a period longer than the most recent first period, the program taking stream data as a digital signal and operating a first phase and a second phase cyclically; In the first phase, the first phase synthesis step involves outputting the digital signal based on local state variables stored in the first storage means, In the second phase, a second-phase synthesis step is performed in which the digital signal is output based on global state variables stored in the second storage means, By repeatedly executing this process, A program characterized in that the output from the first-phase synthesis means and the output from the second-phase synthesis means can interfere with each other due to a phase difference.

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