Method for manufacturing silicon carbide-based semiconductor structures and intermediate composite structures

Abstract

The present invention relates to a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a temporary substrate of a material having a thermal expansion coefficient close to that of silicon carbide, b) forming an intermediate layer of graphite on the front side of the temporary substrate, c) depositing on the intermediate layer a support layer of polycrystalline silicon carbide with a thickness in the range of 10 microns to 200 microns, d) transferring, directly or via an additional layer, a useful layer of monocrystalline silicon carbide to the support layer to form a composite structure, said transfer being carried out by molecular adhesion bonding, e) forming an active layer on the useful layer, and f) removing at the interface or at the intermediate layer to form a semiconductor structure comprising the active layer, the useful layer and the support layer and to form a temporary substrate. The present invention further relates to a composite structure obtained in the intermediate steps of this method.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor materials for miniature electronic components. In particular, the present invention relates to a method for producing a semiconductor structure comprising an active layer made of high-quality single-crystal silicon carbide, which is intended to include or house electronic components, wherein the active layer is disposed on a support layer made of polycrystalline silicon carbide. The present invention further relates to an intermediate composite structure obtained by the above method. [Background technology]

[0002] Silicon carbide (SiC) semiconductor materials have seen a significant increase in interest in recent years due to their ability to enhance energy processing capabilities. SiC is increasingly being used to manufacture innovative power devices, particularly to meet the demands of growing areas of electronic technology such as electric vehicles.

[0003] Power devices and integrated power supply systems based on single-crystal silicon carbide can achieve significantly higher power densities than their conventional silicon equivalents while maintaining relatively smaller active region dimensions. To further limit the dimensions of power devices using SiC, it is advantageous to manufacture components in a longitudinal direction rather than a transverse direction. For this to work, vertical electrical conduction between electrodes positioned at the front and rear of the component assembly must be permitted by the assembly.

[0004] However, bulk substrates made from single-crystal SiC for the microelectronics industry remain expensive, and sourcing large sizes is difficult. Furthermore, when manufactured on bulk substrates, assemblies of electronic components often need to have the back surface of the substrate thinned to approximately 100 microns to reduce vertical electrical resistivity and / or to meet space and miniaturization specifications.

[0005] Therefore, to manufacture composite structures that typically include a thin layer made of single-crystal SiC on a relatively low-cost support substrate, and where this thin layer is used to form electronic components, it is advantageous to use a thin-layer transfer solution. A well-known thin-layer transfer solution is the Smart Cut™ method, which is based on assembly by light ion implantation and direct bonding. Such a method makes it possible to manufacture composite structures that include a thin layer made of c-SiC, obtained from a donor substrate made of single-crystal SiC (c-SiC), enabling perpendicular electrical conduction, by directly contacting a support substrate made of polycrystalline SiC (p-SiC), for example. The support substrate must be thick enough to be compatible with the formation of the components, and ultimately thinned to obtain an assembly of electronic components ready for integration. Even if the quality of the support substrate is relatively low, the thinning step and material loss are still preferable cost factors to be eliminated.

[0006] U.S. Patent No. 8,436,363 is also known, which describes a method for manufacturing a composite structure comprising a thin layer made of c-SiC placed on a metal-supported substrate, the coefficient of thermal expansion of which matches the coefficient of thermal expansion of the thin layer. This manufacturing method involves the following steps: The steps include forming an embedded brittle surface on a donor substrate made of c-SiC, and defining a thin layer between the embedded brittle surface and the front surface of the donor substrate, For example, a metal layer made of tungsten or molybdenum is deposited on the front surface of a donor substrate to form a support substrate that is thick enough to serve as a reinforcing material. The process involves separating along the embedded weak surface to form a composite structure on one side, including a metal support substrate and a thin layer made of c-SiC, and on the other side, forming the remaining portion of the donor substrate made of c-SiC. Includes.

[0007] A drawback of this method is that the metal support substrate may not always fit into the production line for electronic components. Furthermore, the support substrate may need to be thinner depending on the application. [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention relates to an alternative solution to a prior art solution and aims to overcome all or part of the aforementioned drawbacks. In particular, the present invention relates to a method for manufacturing a semiconductor structure for electronic components, preferably for vertical components, which is manufactured on and / or within an active layer made of high-quality single-crystal silicon carbide, arranged in a support layer made of polycrystalline silicon carbide. The present invention further relates to a composite structure obtained in an intermediate step of the manufacturing method. [Means for solving the problem]

[0009] The present invention is a method for manufacturing a semiconductor structure, a) The coefficient of thermal expansion is 3.5 × 10 -6 / ℃~5×10 -6 A step of setting up a temporary substrate made from a material in the range of / ℃, b) The step of forming an intermediate layer made of graphite on the front surface of this temporary substrate, c) A step of depositing a support layer made of polycrystalline silicon carbide with a thickness in the range of 10 microns to 200 microns onto this intermediate layer, d) A step of transferring a useful layer made from single-crystal silicon carbide to a support layer, either directly or via an additional layer, to form a composite structure, wherein the transfer includes a step of performing molecular adhesion bonding. e) The step of forming an active layer on this useful layer, f) On the one hand, a semiconductor structure including an active layer, a useful layer, and a support layer is obtained, and on the other hand, a removal step at the interface of the intermediate layer or in the intermediate layer is performed to obtain a temporary substrate. Regarding methods including

[0010] According to further advantageous and non-limiting features of the present invention, when grouped individually or in any technically feasible combination, they are as follows.

[0011] The thickness of the intermediate layer is in the range of 1 micron to 100 microns.

[0012] The average grain size of the graphite in the intermediate layer is in the range of 1 micron to 50 microns.

[0013] The porosity of the graphite in the intermediate layer is in the range of 6% to 17%.

[0014] The coefficient of thermal expansion of the graphite in the intermediate layer is 4×10 -6 / °C to 5×10 -6 / °C.

[0015] In step b), the intermediate layer is also formed on the peripheral edge of the temporary substrate, and / or a second intermediate layer is formed on the back surface of the temporary substrate.

[0016] In step c), the support layer is further deposited directly on the intermediate layer present on the peripheral edge of the temporary substrate and / or on the peripheral edge of the temporary substrate.

[0017] The transfer step d) injecting light species into a donor substrate made of single-crystalline silicon carbide to form an embedded weak surface that defines a useful layer together with the front surface of the donor substrate, assembling the front surface of the donor substrate to the support layer by molecular adhesion bonding directly or through an additional layer, separating along the embedded weak surface to transfer the useful layer to the support layer and includes.

[0018] Separation occurs while heat-treating at a temperature in the range of 800°C to 1,200°C.

[0019] Step e) includes epitaxially growing at least one additional layer made from doped single-crystal silicon carbide onto the useful layer, wherein the additional layer forms all or part of the active layer.

[0020] Step e) includes heat treatment at a temperature of 1,600°C or higher for the purpose of activating the dopant in the active layer.

[0021] This method includes step e') manufacturing all or part of an electronic component on and / or within the active layer, wherein step e') is placed between step e) and step f).

[0022] Prior to removal step f), a removable handle is assembled on the free surface of the active layer, or, if any, the free surface of the electronic component, all or part of the free surface of the active layer or the electronic component.

[0023] The removal in step f) occurs after applying mechanical stress, either at the interface of the intermediate layer or by allowing cracks to propagate within the intermediate layer.

[0024] The removal in step f) includes lateral chemical etching of all or part of the intermediate layer.

[0025] The removal process in step f) involves thermal damage to the graphite in the intermediate layer.

[0026] The removal in step f) is achieved by cutting the intermediate layer of graphite using a diamond wire saw.

[0027] This method includes the step of reusing the temporary substrate produced in step f).

[0028] Step c) involves depositing a second support layer made of polycrystalline silicon carbide on a second intermediate layer located on the rear surface of the temporary substrate, the thickness of the second support layer being in the range of 10 microns to 200 microns.

[0029] Step d) includes transferring a second useful layer, made from single-crystal silicon carbide, to a second support layer, either directly or via an additional layer, wherein the transfer carries out molecular adhesion bonding.

[0030] Step e) includes forming a second active layer on the second useful layer.

[0031] Step f) includes removing at the interface of the second intermediate layer or in the second intermediate layer to obtain another semiconductor structure comprising a second active layer, a second useful layer, and a second support layer.

[0032] The present invention further, A temporary substrate made from a material having a thermal expansion coefficient close to that of silicon carbide, At least an intermediate layer made of graphite, placed on the front of the temporary substrate, A support layer made of polycrystalline silicon carbide, with a thickness ranging from 10 to 200 microns, is placed in the intermediate layer. A useful layer made from single-crystal silicon carbide is placed in the support layer. Regarding composite structures including...

[0033] A further advantageous and non-limiting feature of the present invention, when combined individually or in any technically feasible combination, is as follows:

[0034] The temporary substrate is made from single-crystal silicon carbide or polycrystalline silicon carbide.

[0035] The thickness of the useful layer is in the range of 100 nm to 1,500 nm.

[0036] Further features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings. [Brief explanation of the drawing]

[0037] [Figure 1]This figure shows an assembly of electronic components manufactured by the manufacturing method according to the present invention. [Figure 2a] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2b] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2c] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2d] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2e] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2e-1] This figure shows the steps of the manufacturing method according to the present invention. [Figure 2f] This figure shows the steps of the manufacturing method according to the present invention. [Figure 3a] This figure shows the steps of a specific embodiment of the manufacturing method according to the present invention. [Figure 3b] This figure shows the steps of a specific embodiment of the manufacturing method according to the present invention. [Figure 3c] This figure shows the steps of a specific embodiment of the manufacturing method according to the present invention. [Figure 3d] This figure shows the steps of a specific embodiment of the manufacturing method according to the present invention. [Figure 4a] This figure shows the transfer step d) of the manufacturing method according to the present invention. [Figure 4b] This figure shows the transfer step d) of the manufacturing method according to the present invention. [Figure 4c] This figure shows the transfer step d) of the manufacturing method according to the present invention. [Modes for carrying out the invention]

[0038] In each figure, the same reference numeral may be used for elements of the same type. Each figure is a schematic diagram and is not proportional to the actual size for the sake of readability. In particular, the thickness of each layer along the z axis is not proportional to the lateral dimensions along the x and y axes, and the relative thickness of each layer relative to each other is not necessarily considered in each figure.

[0039] The present invention relates to a method for manufacturing a semiconductor structure 100 (Figure 1). The semiconductor structure 100 is understood to mean a stack of layers 4, 3, 2 intended to house at least a plurality of micro-electronic components, which is further understood to mean a stack of layers 4, 3, 2 having the electronic components 40, resulting from collective manufacturing on and / or within the active layer 4 held in wafer form by a support layer 2, and ready to undergo a unification step before being packaged.

[0040] This manufacturing method is advantageous because it can be applied to vertically-oriented miniature electronic components that require vertical electrical conduction through a support layer 2 that forms a mechanical support for the component 40.

[0041] Firstly, this manufacturing method has a thermal expansion coefficient close to that of silicon carbide (SiC), i.e., 3.5 × 10⁻⁶. -6 / ℃~5×10 -6 The process includes step a) providing a temporary substrate 1 made from a material in the range of / °C (between ambient temperature and 1,000°C) and having a front surface 1a, a rear surface 1b, and a peripheral edge 1c (Figure 2a). Therefore, it is preferable that the temporary substrate 1 is made from polycrystalline or single-crystal SiC with low crystal quality, and that the role of this temporary substrate 1 is essentially mechanical.

[0042] Other materials that meet the specified constraints of thermal expansion coefficient can be used. These materials also need to be able to withstand very high temperatures, i.e., up to approximately 1,850°C, taking into account the subsequent heat treatment performed in this method.

[0043] Next, the manufacturing method includes step b) forming an intermediate layer 12 made of graphite. This intermediate layer 12 can be manufactured, for example, by plasma deposition of resin, ion jetting, cathode arc deposition, laser graphite evaporation, carbonization, and / or thermal decomposition.

[0044] It is advantageous to select several physical properties of the graphite described below to provide a good seed for depositing a layer made of polycrystalline silicon carbide (p-SiC), which will be referred to as the support layer 2 below, with reference to step c) of this method. In particular, the graphite having a polycrystalline structure has a grain size in the range of 1 micron to 50 microns, especially an average grain size, i.e., in the plane of surfaces 1a and 1b, it falls on the same order as the average grain size expected for the support layer 2.

[0045] It should be noted that the average particle size corresponds to the arithmetic mean of particles larger than 100 nm. These particle sizes can be measured, for example, by scanning microscopy (SEM), X-ray diffraction (particularly from the full width at half maximum of the X-ray diffraction signal), or electron backscatter diffraction (EBSD).

[0046] Since the grain size of the support layer 2 does not become too small, the thermal conductivity of the support layer 2 is ensured in this way. Furthermore, even if the grain size increases when the support layer 2 is deposited, the range of the graphite grain size is defined, so it remains within a controlled grain size range, thereby limiting the roughness of the free surface of the deposited support layer 2.

[0047] The porosity of graphite ranges from 6% to 17%, which is a limited range that allows for control of the surface roughness of the support layer 2 after deposition. Typically, the surface roughness is limited to less than 1 micron RMS, or even less than 10 nm RMS, to reduce any smoothing treatment required after the support layer 2 is deposited.

[0048] The thermal expansion coefficient of the intermediate layer 12 is set to match that of silicon carbide, so that it is 4 × 10⁻⁶. -6 / ℃~5×10 -6 The mechanical stress is limited within the range of / °C (between ambient temperature and 1,000°C) while performing high-temperature processing (which will be described later in this method).

[0049] The temporary substrate 1 with the intermediate layer 12 can withstand temperatures up to 1,450°C when the atmosphere is controlled, i.e., in the absence of oxygen. In practice, when exposed to air, the graphite in the intermediate layer 12 begins to burn in a lower temperature range, typically 400°C to 600°C. The intermediate layer 12, made of graphite, is protected by a protective layer that completely encapsulates it, so it can withstand even very high temperatures exceeding 1,450°C.

[0050] According to a particular embodiment of this method, step b) further includes forming an intermediate layer 12 on the peripheral edge 1c of the temporary substrate 1 (Figure 3b). Step b) may further include a second intermediate layer 12' made of graphite on the rear surface 1b of the temporary substrate 1 (Figures 3a, 3b), with or without the intermediate layer 12 on the peripheral edge 1c.

[0051] Further reference to the outline of this method, step c) is performed, in which a support layer 2 made of polycrystalline silicon carbide (p-SiC) is deposited on the intermediate layer 12 (Figure 2c). In particular, the support layer 2 is deposited directly on the intermediate layer 12, i.e., no additional layer is inserted between layers 2 and 12, which are in contact with each other. It is also advantageous that the support layer 2 is further deposited on the peripheral edge 1c of the temporary substrate 1 to encapsulate and protect the intermediate layer 12 for subsequent steps of this method.

[0052] This deposition can be carried out at a temperature of approximately 1,100°C to 1,400°C using any known technique, particularly by chemical vapor deposition (CVD). For example, thermal CVD techniques such as atmospheric pressure CVD (APCVD) or low-pressure CVD (LPCVD) can be used, and the precursor can be selected from methylsilane, dimethyldichlorosilane, or even dichlorosilane + i-butane. For example, plasma-enhanced CVD (PECVD) techniques can also be used with silicon tetrachloride and methane as precursors, and the frequency of the source used to generate the plasma discharge is approximately 3.3 MHz, and more generally, preferably in the range of 10 kHz to 100 GHz.

[0053] Prior to deposition, a conventional cleaning sequence can be applied to the temporary substrate 1 on which the intermediate layer 12 is provided, in order to remove all or part of any potentially present particulate matter, metal, or organic contaminants on the free surfaces 1a and 1b of the temporary substrate 1.

[0054] The thickness of the support layer 2, made from p-SiC, is in the range of 10 to 200 microns. This thickness is selected according to the expected thickness specifications in the semiconductor structure 100. In this structure 100, the support layer 2 is assumed to act as a mechanical substrate and, potentially, must ensure vertical electrical conductivity. To guarantee the aforementioned electrical conductivity characteristics (low resistivity), it is advantageous for the support layer 2 to be doped with n-type or p-type as required.

[0055] In the specific embodiments described above, as shown in Figure 3c, the deposition in step c) can be further carried out on a second intermediate layer 12' to form a second support layer 2' and / or on the peripheral edge 1c of the temporary substrate 1. The role of the second support layer 2' deposited on the rear surface 1b of the temporary substrate 1 is to enable the following steps of this method to be carried out on the two surfaces 1a, 1b of the substrate 1.

[0056] Generally, after the deposit of support layer 2 (and, optionally, a second support layer 2'), surface treatment is performed to improve the surface roughness of support layer 2 and / or the quality of the structural edges for the subsequent thin-layer transfer step.

[0057] Conventional chemical etching (wet or dry), and / or mechanical grinding and / or chemical mechanical polishing techniques can be employed to achieve a surface roughness of approximately 0.5 nm RMS, preferably less than 0.3 nm RMS, for example, by measuring roughness using atomic force microscopy (AFM) with a 20 micron × 20 micron scan. Nevertheless, the aforementioned characteristics of the graphite in the intermediate layer 12 make it possible to limit the surface treatments that can be applied.

[0058] Next, the manufacturing method according to the present invention includes step d) transferring a useful layer 3 made from single-crystal silicon carbide (c-SiC) to a support layer 2 directly or via an additional layer to form a composite structure 10 (Figure 2d). This transfer carries out molecular adhesion bonding, resulting in the formation of a bonding interface 5. Additional layers can be formed on the sides of the useful layer 3 and / or the sides of the support layer 2 to facilitate the bonding.

[0059] Conveniently, and as is known in relation to the Smart Cut (trademark) Act, transcription step d) is, Lightweight species are injected into a donor substrate 30 made from single-crystal silicon carbide to form an embedded fragile surface 31 that defines the useful layer 3 together with the front surface 30a of the donor substrate 30 (Figure 4a), The front surface 30a of the donor substrate 30 is assembled to the support layer 2 along the bonding interface 5 by molecular adhesion bonding, either directly or via an additional layer (Figure 4b), The useful layer 3 is separated along the embedded weak surface 31 and transferred to the support layer 2 (Figure 4c). Includes.

[0060] The light species are preferably hydrogen, helium, or a co-injection of these two species, and are implanted into the donor substrate 30 at a determined depth that matches the thickness of the target useful layer 3 (Fig. 4a). These light species will form microvoids dispersed as a thin layer parallel to the free surface 30a of the donor substrate 30, parallel to the (x, y) plane in each figure, around the determined depth. For the sake of brevity, this thin layer is called the embedded weak plane 31.

[0061] The implantation energy of the light species is selected to reach the determined depth. For example, hydrogen ions are in the energy level range of 10 keV to 250 keV, and are implanted at an irradiation dose level in the range of 5 E 16 / cm 2 ~1 E 17 / cm 2 to define a useful layer 3 with a thickness of approximately 100 nm to 1,500 nm. It should be noted that a protective layer can be deposited on the front surface 30a of the donor substrate 30 prior to the ion implantation step. This protective layer can be composed of materials such as silicon oxide or silicon nitride, for example. This protective layer can be retained in the next step or removed as well.

[0062] The donor substrate 30 is assembled to the support layer 2 at their respective front / free surfaces to form a joined stack along the joining interface 5 (Fig. 4b). As is well known in itself, molecular adhesion bonding does not require an adhesive because atomic-level bonding is established between the assembled surfaces. There are several types of molecular adhesion bonding, and differences occur particularly with respect to temperature, pressure, atmospheric conditions, or the treatment before contacting the surfaces. Examples include bonding at ambient temperature with or without prior plasma activation of the assembled surfaces, atomic diffusion bonding (ADB), surface activation bonding (SAB), etc.

[0063] The assembly step may include conventional cleaning, surface activation, or other surface treatment sequences that are likely to enhance the quality of the bond interface 5 (low defect density, good adhesion quality) before the surfaces to be assembled are brought into contact.

[0064] As already mentioned, the front surface 30a of the donor substrate 30 and / or the free surface of the support layer 2 may optionally include additional layers, such as a metal layer (such as tungsten) or a doped semiconductor layer (such as silicon) to promote vertical electrical conductivity, or an insulating layer (such as silicon oxide or silicon nitride) for applications that do not require vertical electrical conductivity. The additional layers are particularly likely to promote molecular adhesion bonding by eliminating residual roughness or surface defects present on the surface to be assembled. These additional layers may be subjected to planarization or smoothing treatments to achieve a roughness of less than 1 nm RMS, or even less than 0.5 nm RMS, which is favorable for bonding.

[0065] Separation along the embedded weak surface 31 is typically achieved by heat treatment at temperatures in the range of 800°C to 1200°C (Figure 4c). Such heat treatment creates cavities and microcracks in the embedded weak surface 31, which are then pressurized by lightweight species present in gaseous form, after which fracture propagates along the weak surface 31. Alternatively, or in conjunction with, mechanical stress can be applied to the joined assembly, particularly the embedded weak surface 31, to transmit or facilitate the mechanical propagation of fracture leading to separation. Once this separation is complete, a composite structure 10 is obtained on the one hand, comprising a temporary substrate 1, an intermediate layer 12 made of graphite, a support layer 2 made of p-SiC, and a transferred useful layer 3 made of c-SiC, and on the other hand, the remaining 30' of the donor substrate is obtained. The thickness of the useful layer 3 is typically between 100 nm and 1,500 nm. The level and type of doping of the useful layer 3 are determined by the selection of each characteristic of the donor substrate 30, or can be subsequently adjusted by known techniques for doping semiconductor layers.

[0066] The free surface of the useful layer 3 is typically rough after separation, for example, in the range of 5 nm to 100 nm RMS (AFM, scanned at 20 microns × 20 microns). A good surface finish (typically less than a few angstroms RMS roughness, scanned at 20 microns × 20 microns AFM) can be restored by adding a cleaning step and / or a smoothing step.

[0067] Alternatively, the free surface of the useful layer 3 may remain rough after separation if the following steps of this method allow for this roughness.

[0068] In a particular embodiment where a second intermediate layer 12' and a second support layer 2' are mounted on the rear surface 1b of the temporary substrate 1, step d) may further include transferring a second useful layer 3' made of c-SiC to the second support layer 2' via a second bonding interface 5' (Figure 3d).

[0069] Next, the manufacturing method according to the present invention includes step e) forming an active layer 4 on the useful layer 3 (Figure 2e).

[0070] This active layer 4 is advantageously manufactured by epitaxially growing an additional layer made from doped single-crystal silicon carbide onto the useful layer 3. This epitaxial growth occurs within the conventional temperature range, i.e., between 1,500°C and 1,900°C, forming an additional layer with a thickness of approximately 1 micron to several tens of microns, depending on the target electronic component.

[0071] In the composite structure 10, a protective layer is required at each edge of the intermediate layer 12 made of graphite in order to prevent damage to the graphite due to the aforementioned very high temperature treatment. As mentioned above, this protective layer can be made of, for example, a layer made of polycrystalline silicon carbide (for example, deposited simultaneously with the support layer 2), or an amorphous layer.

[0072] The manufacturing method according to the present invention may further include step e') manufacturing all or part of the electronic components 40 on and / or within the active layer 4 (Figure 2e-1). The electronic components 40 may consist of, for example, a transistor or other high-voltage and / or high-frequency components.

[0073] Conventional steps such as washing, deposition, lithography, injection, etching, planarization, and heat treatment are performed to produce these on and / or within the active layer 4. In particular, some of the aforementioned heat treatments are aimed at activating dopants locally injected into the active layer 4 (or useful layer 3), and are usually performed at temperatures of 1,600°C or higher.

[0074] In a particular embodiment in which a second support layer 2' is mounted on the rear surface of the temporary substrate 1, step e) may further include forming a second active layer on the second useful layer 3', and it should be noted that step e') may include fabricating all or some of the second electronic components on and / or in the second active layer.

[0075] Ultimately, the manufacturing method according to the present invention includes, on the one hand, a semiconductor structure 100 comprising an active layer 4, a useful layer 3, and a support layer 2, and on the other hand, a step f) removing at the interface of the intermediate layer 12 and / or in the intermediate layer 12 in order to form a temporary substrate 1 (Figure 2f(i)) and potentially electronic components 40 (Figure 2f(ii)).

[0076] In this step, several alternative embodiments can be implemented for removal in the intermediate layer 12 (and possibly in the second intermediate layer 12' in certain embodiments).

[0077] According to the first alternative embodiment, step f) includes mechanically removing the intermediate layer 12 and / or the interface between the intermediate layer 12 and the support layer 2, and / or between the intermediate layer 12 and the temporary substrate 1, by allowing a crack to propagate. This crack propagates substantially parallel to the plane of the intermediate layer 12 after mechanical stress is applied. For example, by inserting a chamfering tool on the opposite side of the intermediate layer 12, an opening is initiated and propagates at the fragile interface, and it is preferable that the crack develops in the intermediate layer 12 or the interface until complete separation exists between the semiconductor structure 100 and the temporary substrate 1, since graphite has a relatively low cohesive energy along the z axis. The protective layer present at the edge 1c of the temporary substrate 1 is advantageously removed, for example, by dry etching or wet etching, in order to facilitate the initiation of cracks in the graphite.

[0078] According to a second alternative embodiment, step f) includes chemical removal between the semiconductor structure 100 and the temporary substrate 1 by lateral chemical etching. To allow access to the graphite, the protective layer (p-SiC) located on the peripheral edge 1c of the temporary substrate 1 in the composite structure 10 (particularly the edge of the intermediate layer 12) must be removed chemically or mechanically. The lateral chemical etching of the intermediate layer 12 can then be carried out with a solution based on nitric acid and / or sulfuric acid, such as a solution of concentrated sulfuric acid and potassium dichromate, or a solution of sulfuric acid, nitric acid, and potassium chlorate. Chemical etching using an alkaline solution (of the type of potassium hydroxide (KOH) or sodium hydroxide (NaOH)) can also be utilized.

[0079] Of course, great care will be taken to protect the free surfaces and edges of the active layer 4, as well as the electronic components 40 if present, and / or limit the contact time with the etching solution, so as not to damage them during this chemical removal.

[0080] According to a third alternative embodiment, step f) includes mechanical removal of the graphite forming the intermediate layer 12 by thermal damage. Here again, it is necessary to remove the protective layer present at least at the edges of the temporary substrate 1 to allow access to the intermediate layer 12.

[0081] Removal due to thermal damage may occur at temperatures in the range of 600°C to 1,000°C in the presence of oxygen, after which the graphite of the intermediate layer 12 burns and crumbles into pieces, thus separating the semiconductor structure 100 from the temporary substrate 1.

[0082] Of course, if the electronic component 40 is manufactured in step e', this alternative embodiment of removal can only be applied if the component 40 is suitable for the applied temperature.

[0083] According to a fourth alternative embodiment, step f) is performed by cutting the graphite of the intermediate layer 12 with a wire saw. In particular, this wire contains diamond particles.

[0084] It should be noted that the aforementioned alternative embodiments can be combined at will by any technically feasible means.

[0085] Regardless of the alternative embodiment implemented, the removal of the temporary substrate 1 may leave residue 12r of the intermediate layer 12 on the rear surface 2b of the support layer 2 and / or on the front surface of the temporary substrate 1. These residues can be removed by mechanical grinding, chemical mechanical polishing, chemical etching, and / or thermal damage.

[0086] Following the removal of the residue 12r, if necessary, chemical mechanical polishing or chemical etching techniques may also be performed to reduce the roughness of the rear surface 2b of the support layer 2.

[0087] In the particular embodiment described above, where the second active layer is located on the rear surface 1b side of the temporary substrate 1, step f) removing the temporary substrate 1 also makes it possible to form a second semiconductor structure including the second active layer, the second useful layer 3', and the second support layer 2'.

[0088] During and after the removal of the temporary substrate 1, the semiconductor structure 100 must be processed. If the total thickness of the semiconductor structure is insufficient to mechanically hold it during this processing, a removable handle can be considered. The handle is placed, for example, on the active layer 4 or component 40 and temporarily fixed therein to perform the processing until the unification step.

[0089] The semiconductor structure 100 obtained upon completion of the manufacturing method according to the present invention includes an active layer 4 which is advantageous to complete with electronic components 40 and is placed on the support layer 2 at a thickness suitable for this application. Mechanical thinning, which would result in significant material loss, is not required. The support layer 2 is made from high-quality p-SiC (because it is deposited at a relatively high temperature), which is less expensive than bulk substrates of single-crystal or polycrystalline SiC, and would have had to be significantly thinned before the components 40 could be unified. The temporary substrate 1, after removal, is recovered for reuse, which is also an economic advantage.

[0090] The intermediate layer 12, made of graphite, allows for easy removal of the composite structure 10 after the active layer 4 (and preferably all or part of the components) has been formed, and ensures the mechanical stability of the composite structure 10 during the very high-temperature heat treatment used to manufacture the active layer 4.

[0091] By selecting the physical characteristics (average particle size, porosity, and thermal expansion coefficient) of the intermediate layer 12 made from graphite, the formation of the support layer 2 can be ensured, resulting in a robust and high-quality composite structure 10, and thus a reliable and high-performance semiconductor structure 100. The performance of the component 40, in particular, stems from the fact that the composite structure 10 allows for processing at very high temperatures to form the active layer 4.

[0092] The present invention further relates to a composite structure 10 corresponding to the intermediate structure obtained in the manufacturing method described above (Figures 2d, 3d).

[0093] The composite structure 10 is A temporary substrate 1 made from a material having a thermal expansion coefficient close to that of silicon carbide, An intermediate layer 12 made of graphite is placed at least on the front surface 1a of the temporary substrate 1, A support layer 2 made of polycrystalline silicon carbide, with a thickness ranging from 10 microns to 200 microns, is placed in the intermediate layer 12. This support layer 2 is arranged in a useful layer 3 made from single-crystal silicon carbide and Includes.

[0094] The graphite in the intermediate layer 12 has a particle size in the range of 1 micron to 50 microns, a porosity in the range of 6% to 17%, and / or a coefficient of thermal expansion of 4 × 10⁻⁶. -6 / ℃~5×10 -6 It is preferable that the temperature be within the range of / °C. The advantages associated with these characteristics have been described above.

[0095] The thickness of the useful layer 3 is preferably in the range of 100 nm to 1,500 nm. The thickness of the intermediate layer 12 is in the range of 1 micron to 100 microns, or in the range of 10 microns to 100 microns, and the thickness of the temporary substrate 1 is in the range of 300 microns to 800 microns.

[0096] In applications involving vertically mounted miniature electronic components, the support layer 2 has good conductivity, i.e., 0.015 ohms-cm to 0.03 ohms-cm, high thermal conductivity, i.e., 200 W / mK or higher, and a thermal expansion coefficient similar to that of the useful layer 3, i.e., typically 3.8 × 10⁻¹⁰ at ambient temperature. -6 / ℃~4.2×10 -6 Having a temperature range of / ℃ is advantageous.

[0097] The intermediate layer 12 and / or temporary substrate 1 have a thermal conductivity in the range of 5 W / mK to 500 W / mK, which is advantageous because it allows for a uniform temperature to be achieved on the temporary substrate 1 during the very high-temperature heat treatment step of the manufacturing method. In particular, this improves the uniformity of the deposited layer and the reproducibility of the physical characteristics of the manufactured layer and components.

[0098] Finally, as described with reference to the manufacturing method according to the present invention, the composite structure 10 can be "double-sided," that is, A second intermediate layer 12' made of graphite is placed on the rear surface 1b of the temporary substrate 1, A second support layer 2' made of polycrystalline silicon carbide, with a thickness in the range of 10 microns to 200 microns, is placed in this second intermediate layer 12, This second support layer 2' is arranged in a second useful layer 3' made of single-crystal silicon carbide and It can include (Figure 3d).

[0099] With such a composite structure 10, two active layers 40 can be formed on the first useful layer 3 and the second useful layer 3', and when the manufacturing method according to the present invention is completed, two semiconductor structures 100 can be obtained from a single temporary substrate 1.

[0100] Of course, the present invention is not limited to the embodiments and examples described, and alternative embodiments may be added without departing from the scope of the invention as defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure (100), a) The coefficient of thermal expansion is 3.5 × 10 －６ / ℃~5×10 －６ The steps include: providing a temporary substrate (1) made from a material in the range of / ℃, b) The step of forming an intermediate layer (12) made of graphite on the front surface (1a) of the temporary substrate (1), c) A step of depositing a support layer (2) made of polycrystalline silicon carbide having a thickness in the range of 10 microns to 200 microns on the intermediate layer (12), d) A step of transferring a useful layer (3) made from single-crystal silicon carbide to the support layer (2) directly or via an additional layer to form a composite structure (10), wherein the transfer is a step of performing molecular adhesion bonding. e) The step of forming an active layer (4) on the useful layer (3), f) On the one hand, to obtain the semiconductor structure (100) including the active layer (4), the useful layer (3), and the support layer (2), and on the other hand, to obtain the temporary substrate (1), a removal step at the interface of the intermediate layer (12) or in the intermediate layer (12), Methods that include...

2. The manufacturing method according to claim 1, wherein the thickness of the intermediate layer (12) is in the range of 1 micron to 100 microns.

3. The manufacturing method according to claim 1 or 2, wherein the average particle size of the graphite in the intermediate layer (12) is in the range of 1 micron to 50 microns.

4. The manufacturing method according to any one of claims 1 to 3, wherein the porosity of the graphite in the intermediate layer (12) is in the range of 6% to 17%.

5. The thermal expansion coefficient of the graphite in the intermediate layer (12) is 4 × 10 －６ / ℃~5×10 －６ A manufacturing method according to any one of claims 1 to 4, wherein the temperature is within the range of / °C.

6. In step b), the intermediate layer (12) is also formed on the peripheral edge (1c) of the temporary substrate (1), and / or The manufacturing method according to any one of claims 1 to 5, wherein a second intermediate layer (12') is formed on the rear surface (1b) of the temporary substrate (1).

7. In step b), the intermediate layer (12) is also formed on the peripheral edge (1c) of the temporary substrate (1), and in step c), the support layer (2) is further deposited on the intermediate layer (12) present on the peripheral edge (1c) of the temporary substrate (1), or The manufacturing method according to any one of claims 1 to 6, wherein in step b), the intermediate layer (12) is not formed on the peripheral edge (1c) of the temporary substrate (1), and in step c), the support layer (2) is further deposited directly on the peripheral edge (1c) of the temporary substrate (1).

8. The aforementioned transfer step d) A lightweight species is injected into a donor substrate (30) made from single-crystal silicon carbide to form an embedded fragile surface (31) that defines the useful layer (3) together with the front surface (30a) of the donor substrate (30), The front surface (30a) of the donor substrate (30) is assembled to the support layer (2) by molecular adhesion bonding, either directly or via an additional layer. Separating along the embedded weak surface (31) and transferring the useful layer (3) to the support layer (2), A manufacturing method according to any one of claims 1 to 7, including

9. The manufacturing method according to any one of claims 1 to 8, wherein step e) includes epitaxially growing at least one additional layer made of doped single-crystal silicon carbide on the useful layer (3), the additional layer forming all or part of the active layer (4).

10. The manufacturing method according to claim 9, wherein step e) includes heat treatment at a temperature of 1,600°C or higher for the purpose of activating the dopant in the active layer (4).

11. The manufacturing method according to any one of claims 1 to 10, comprising step e') of manufacturing all or part of an electronic component (40) on and / or within the active layer (4), wherein step e') is positioned between step e) and step f).

12. The manufacturing method according to claim 11, wherein, prior to the removal step f), a removable handle is assembled on the free surface of the active layer (4) or on all or part of the free surface of the electronic component (40).

13. The removal in step f) occurs after applying mechanical stress, at the interface of the intermediate layer (12), or by propagating a crack in the intermediate layer (12), and / or The removal in step f) includes and / or, lateral chemical etching of all or part of the intermediate layer (12). The removal in step f) includes thermal damage to the graphite of the intermediate layer (12) and / or, The manufacturing method according to any one of claims 1 to 12, wherein the removal in step f) is performed by cutting the graphite of the intermediate layer (12) using a diamond wire saw.

14. In step b), the second intermediate layer (12') is formed on the rear surface (1b) of the temporary substrate (1), Step c) includes depositing a second support layer (2') made of polycrystalline silicon carbide on the second intermediate layer (12') present on the rear surface (1b) of the temporary substrate (1), wherein the thickness of the second support layer (2') is in the range of 10 microns to 200 microns. Step d) includes transferring a second useful layer (3') made from single-crystal silicon carbide to the second support layer (2') either directly or via an additional layer, wherein the transfer carries out molecular adhesion bonding. Step e) includes forming a second active layer on the second useful layer (3'), The manufacturing method according to claim 6, wherein step f) includes removing at the interface of the second intermediate layer (12') or in the second intermediate layer (12') to obtain another semiconductor structure (100) comprising the second active layer, the second useful layer (3'), and the second support layer (2').

15. A temporary substrate (1) made from a material having a thermal expansion coefficient in the range of 3.5 × 10⁻⁶ / °C to 5 × 10⁻⁶ / °C, At least an intermediate layer (12) made of graphite is placed on the front surface of the temporary substrate (1), A support layer (2) made of polycrystalline silicon carbide, having a thickness in the range of 10 microns to 200 microns, is placed in the aforementioned intermediate layer (12), A useful layer (3) made of single-crystal silicon carbide is placed on the support layer (2), A composite structure (10) including the above.

16. The composite structure (10) according to claim 15, wherein the temporary substrate (1) is made of single-crystal silicon carbide or polycrystalline silicon carbide, and the thickness of the useful layer (3) is in the range of 100 nm to 1500 nm.

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