Microelectronics H-frame devices

Abstract

A microelectronic H-frame device includes a stack of two or more substrates, the stack of substrates including a top substrate and a bottom substrate, bonding of the top substrate to the bottom substrate creating a vertical electrical connection between the top substrate and the bottom substrate, a top surface of the top substrate including a top substrate top metallization and a bottom surface of the bottom substrate including a bottom substrate bottom metallization, an intermediate substrate metallization located between the top substrate and the bottom substrate, a micromachined top cover bonded to a top side of the stack of substrates, and a micromachined bottom cover bonded to a bottom side of the stack of substrates.

Description

Technical Field

[0001] The present invention relates to a microelectronic H-frame device.

[0002] Statement Regarding Government Rights The United States Government has rights in this invention pursuant to Government Contract No. 17-C-3186.

[0003] Cross - Reference to Related Applications This application includes subject matter related to the subject matter of the following applications assigned to the same assignee as this application. The applications listed below are hereby incorporated by reference in their entirety.

[0004] "FILTER WITH AN ENCLOSURE HAVING A MICROMACHINED INTERIOR USING SEMICONDUCTOR FABRICATION", Kunkee et al., filed Apr. 28, 2020, Serial No. 16 / 860,642.

[0005] "CHANNELIZED FILTER USING SEMICONDUCTOR FABRICATION", Duan et al., filed Jun. 30, 2020, Serial No. 16 / 916,644.

Summary of the Invention

[0006] A microelectronics H-frame device comprises a stack of two or more substrates, with a microfabricated top cover bonded to the top side of the device and a microfabricated bottom cover bonded to the bottom side of the device, forming an "H-frame" package entirely fabricated using microelectronics technology. "H-frame" refers to a double-sided metal housing in which electronics are packaged to form a "module." Specifically, the letter "H" refers to the shape of the vertical cross-section of the housing. The horizontal bar of the "H" refers to the "central web," or a common shared floor for mounting components. Substrate transmission lines, printed circuit boards, and other electronic components are bonded to both the top and bottom sides of the central web. The vertical bar of the "H" refers to the vertical walls surrounding the housing.

[0007] A microelectronic H-frame device comprises a stack of four or more semiconductor layers. One or more of the top and bottom semiconductors form the housing of the device. The intermediate semiconductor includes a substrate that provides a surface for electrical signal transmission. One or more of the top and bottom semiconductors are microfabricated to form one or more cavities and walls to isolate radio frequency (RF) signals. One or more of the top and bottom semiconductors are then metallized. Metal bumps are added to the bottom of the walls of one or more of the top and bottom semiconductors. The intermediate substrate is processed on a wafer. One or more of the transmission lines, filters, other circuits, ground planes, and bonding bumps are plated onto the intermediate substrate. Electrical connections between all surfaces of the intermediate substrate are provided using one or more of the through-wafer vias and crushed metal bonding bumps between the substrates. This creates an electrical connection between two sides of the H-frame housing. All four semiconductor layers are then aligned and bonded together. The metallized layer between the two intermediate substrates allows signals to escape from the microelectronic H-frame housing without the need to add one or more mechanical holes and connectors within the housing.

[0008] Horizontal surfaces are joined using compression bonding. Alternatively or additionally, wafer-scaled eutectic alloy bonding is used to join stacks of two or more substrates together with upper and lower silicon microfabrication cavities. For example, the upper and lower cavities are joined to the central conductor using one or more of wafer-scaled gold-indium bonds and wafer-scaled gold-gold bonds. For example, horizontal surfaces are joined using gold-gold thermocompression bonding.

[0009] An H-frame device has two chips joined together to create a vertical electrical connection. In an H-frame, a layer of gold may be used to form a conductive artwork and shield electrical signals propagating along the artwork, or it may have features and openings to enable the vertical interconnection.

[0010] The artwork of the upper chip and the artwork of the lower chip may differ. The upper and lower chips may be fabricated on the same wafer, even if they are different. The top surface of the upper chip and the bottom surface of the lower chip are fabricated together on the front surface of the wafer. When the wafer is diced into chips, the upper and lower chips may be joined together at their bottom surfaces. When a large number of chips are desired, for example, more than approximately 20 chips, it is also possible to use a first dedicated wafer for the upper chips and a second dedicated wafer for the lower chips.

[0011] As an example, embodiments of the present invention provide a compact vertical feedthrough transition that allows a spiral inductor to "escape" from a sealed cavity.

[0012] The device includes an intermediate substrate metallization located between the upper and lower substrates. The metallizations in the upper and lower covers, along with through-substrate vias contained within the substrates, together form a continuous metal shield, or "wall," for the package. The through-substrate vias are preferably metallized. An intermediate substrate metallization ("intermediate" metal layer) including one or more of the lower substrate upper metallization and upper substrate lower metallization is sandwiched between two substrates in a new H-frame. Bumps bond these two metallizations together through a bonding process. As used herein, the terms "bump" or "bumps" refer to a metal mound intended to create one or more of electrical and physical connections. For example, one or more of the electrical and physical connections are created using one or more of gold-indium thermocompression and gold-gold thermocompression.

[0013] Passive circuits such as filters, power splitters, and couplers can be patterned directly on the upper side of the substrate. Similarly, pads can be patterned directly on the upper side of the substrate. Pads can be used to mount discrete circuits such as monolithic microwave integrated circuits (MMICs) and capacitors. Radio frequency (RF) transmission lines may include one or more of microstrips, coplanar waveguides (CPWs), and strip lines. RF transmission lines can run on the upper side of the substrate, or even a thin "central web" layer, i.e., an "intermediate" metal layer. RF transmission lines can switch layers by metallized through-substrate vias. RF transmission lines can transition to different line types while maintaining minimal electrical reflection losses in a fully integrated transition including one or more of through-substrate vias, patterned metallization on the substrate, insulating walls consisting of metallized through-substrate vias, and vertical walls included in a cover.

[0014] Alcoves created in one of the covers, positioned at the electrical input and output of the H-frame, have metallized walls and help to gradually change the direction of the electric field from vertical (in microstrip lines) to horizontal (in so-called "vertical coaxial cables" formed by signal vias and surrounding ground vias). This helps to achieve good return loss and suppress radiation leakage, resulting in a transition design with normal RF integrity.

[0015] An alcove is a portion of the outer wall of a cover used to create an escape transition. Alcoves are contoured to facilitate good RF transitions. Alcoves do not break through the wall or introduce holes into the outer wall, thus maintaining the environmental seal provided by the outer wall of the cover.

[0016] A microelectronic H-frame device is a stack of two or more substrates, wherein the stack of substrates includes an upper substrate and a bottom substrate, the bonding of the upper substrate to the bottom substrate creates a vertical electrical connection between the upper substrate and the bottom substrate, the upper surface of the upper substrate includes an upper substrate metallization, and the bottom surface of the bottom substrate includes a bottom substrate metallization; an intermediate substrate metallization located between the upper substrate and the bottom substrate; a microfabricated upper cover bonded to the upper side of the stack of substrates; and a microfabricated bottom cover bonded to the bottom side of the stack of substrates. A method for fabricating a microelectronic H-frame device includes: microfabrication of an upper cover usable in the device; microfabrication of a bottom cover usable in the device; fabrication of an upper surface of an upper substrate usable in the device and a bottom surface of a bottom substrate usable in the device, together on the front surface of a wafer, wherein the upper surface of the upper substrate includes an upper substrate upper metallization and the bottom surface of the bottom substrate includes a bottom surface bottom metallization; fabrication of an intermediate substrate metallization; bonding the upper substrate to the upper cover; bonding the bottom substrate to the bottom cover; bonding the upper substrate to the upper surface of the intermediate substrate metallization and bonding the bottom substrate to the bottom surface of the intermediate substrate metallization, thereby creating a vertical electrical connection between the upper substrate and the bottom substrate.

[0017] A microelectronic H-frame device is a stack of two or more substrates, the stack of substrates comprising an upper substrate and a bottom substrate, the top surface of the upper substrate and the bottom surface of the bottom substrate being fabricated together on the front surface of a wafer, at least one of the upper substrate and the bottom substrate comprising at least one of a transmission line, a filter, a power splitter, a coupler, and another electronic component, the bonding of the upper substrate to the bottom substrate creating a vertical electrical connection between the upper substrate and the bottom substrate, the top surface of the upper substrate comprising an upper substrate upper metallization, the bottom surface of the bottom substrate comprising a bottom substrate bottom metallization, an intermediate substrate metallization located between the upper substrate and the bottom substrate, a microfabricated upper cover bonded to the upper side of the stack of substrates, the upper cover comprising an upper cover metallization, and a microfabricated bottom cover bonded to the bottom side of the stack of substrates, the bottom cover comprising a bottom cover metallization.

[0018] The accompanying drawings are used to more fully illustrate various representative embodiments and provide visual representations that can be used by those skilled in the art to better understand the representative embodiments disclosed herein and their inherent advantages. In these drawings, similar reference numerals identify corresponding elements. [Brief explanation of the drawing]

[0019] [Figure 1A] This is a diagram of a microelectronics H-frame device. [Figure 1B] This is a diagram of a microelectronics H-frame device. [Figure 1C] This is a diagram of a microelectronics H-frame device. [Figure 1D] This is a diagram of a microelectronics H-frame device. [Figure 1E] This is a diagram of a microelectronics H-frame device. [Figure 1F]It is a diagram of a microelectronics H-frame device. [Figure 1G] It is a diagram of a microelectronics H-frame device. [Figure 1H] It is a diagram of a microelectronics H-frame device. [Figure 2A] It is a diagram of a circuit using strip lines and feed-through transitions in a microelectronics H-frame device. [Figure 2B] It is a diagram of a circuit using strip lines and feed-through transitions in a microelectronics H-frame device. [Figure 2C] It is a diagram of a circuit using strip lines and feed-through transitions in a microelectronics H-frame device. [Figure 2D] It is a diagram of a circuit using strip lines and feed-through transitions in a microelectronics H-frame device. [Figure 2E] It is a diagram of a circuit using strip lines and feed-through transitions in a microelectronics H-frame device. [Figure 2F] It is a diagram of a circuit using strip lines and feed-through transitions in a microelectronics H-frame device. [Figure 2G] It is a diagram of a circuit using strip lines and feed-through transitions in a microelectronics H-frame device. [Figure 3A] It is a diagram showing a manufacturing method of a microelectronics H-frame device. [Figure 3B] It is a diagram showing a manufacturing method of a microelectronics H-frame device. [Figure 3C] It is a diagram showing a manufacturing method of a microelectronics H-frame device. [Figure 3D] It is a diagram showing a manufacturing method of a microelectronics H-frame device. [Figure 3E]This figure shows a method for fabricating a microelectronic H-frame device. [Figure 3F] This figure shows a method for fabricating a microelectronic H-frame device. [Figure 4] This is a flowchart of Method 400 for fabricating microelectronic H-frame devices. [Modes for carrying out the invention]

[0020] Figures 1A to 1H are a set of eight drawings of microelectronics H-frame devices.

[0021] Figure 1A shows an exploded view of the microelectronics H-frame device 100.

[0022] The microelectronics H-frame device 100 includes an upper cover 102. For example, the upper cover 102 includes a semiconductor.

[0023] For example, as shown in the figure, the upper cover 102 includes three upper cover cavities 104A to 104C: a first upper cover cavity 104A, a second upper cover cavity 104B, and a third upper cover cavity 104C. The first upper cover cavity 104A includes a partial first upper cover cavity 104A. The second upper cover cavity 104B includes a fully formed second upper cover cavity 104B. The third upper cover cavity 104C includes a partial third upper cover cavity 104C.

[0024] For example, as will be described in more detail below, the upper cover 102 is micro-machined to form one or more of the upper cover cavities 104A to 104C. For example, as will be described in more detail below, the upper cover 102 is plated to form one or more of the upper cover cavities 104A to 104C. For example, the upper cover 102 is plated with gold to form one or more of the upper cover cavities 104A to 104C.

[0025] The microelectronic H-frame device 100 further includes a bottom cover 106. For example, the bottom cover 106 includes a semiconductor. The bottom cover 106 includes one or more bottom cover cavities 108. For example, as shown, the bottom cover 106 includes one bottom cover cavity 108. For example, as will be described in more detail below, the bottom cover 106 is microfabricated to form a bottom cover cavity 108. For example, as will be described in more detail below, the bottom cover 106 is plated to form a bottom cover cavity 108. For example, the bottom cover 106 is plated with gold to form a bottom cover cavity 108.

[0026] The microelectronic H-frame device 100 further includes a substrate 110. While not essential, preferably the substrate 110 is substantially flat. While not essential, preferably the substrate 110 is configured to be encapsulated between a bottom cover 106 and an upper cover 102. For example, the substrate 110 has a thickness of about 200 microns to about 800 microns.

[0027] The substrate 110 includes an upper substrate 112. While not essential, the upper substrate 112 preferably contains silicon carbide (SiC).

[0028] The upper substrate 112 is operably connected to the upper cover 102. Preferably, the upper substrate 112 is bonded to the upper cover 102. The upper substrate 112 includes an upper substrate surface 114. Preferably, the upper substrate surface 114 includes circuit components of the H-frame device 100, such as one or more of transistors, resistors, capacitors, and transmission lines.

[0029] Preferably, the upper substrate surface 114 includes a first bonding interface 114 to which the upper substrate 112 is physically bonded to the upper cover 102. Preferably, the upper substrate 112 is physically bonded to the upper cover 102. For example, the upper substrate 112 is physically bonded to the upper cover 102 at the upper substrate surface 114. For example, gold-gold crimping is used to physically attach the upper substrate 112 to the upper cover 102 at the upper substrate surface 114. For example, a first adhesive (not shown in Figure 1A) physically attaches the upper substrate 112 to the upper cover 102 at the upper substrate surface 114. For example, the first adhesive includes epoxy. For example, the first adhesive includes conductive epoxy. For example, the first adhesive includes gold that can be crimped to gold on the upper cover 102.

[0030] While not mandatory, preferably, the upper surface 114 of the upper substrate is configured to support the upper substrate upper metallization 116. For example, the upper substrate upper metallization 116 has a thickness of about 1 micron to about 13 microns. For example, the upper substrate upper metallization 116 has a thickness of about 3.5 microns. For example, the upper substrate upper metallization 116 has a thickness of about 5.5 microns. The upper substrate upper metallization 116 includes an upper substrate upper ground plane 116A used as one or more of a reference conductor and a "ground conductor" in the H-frame device 100. The upper substrate upper metallization 116B includes a first input / output port 116B, which is described in more detail below in Figure 1C. The upper substrate upper metallization 116C includes a second input / output port 116C, which is also described in more detail below in Figure 1C. The upper substrate upper metallization 116D includes a first upper substrate upper signal line 116D configured to conduct signals.

[0031] The upper substrate upper metallization 116 includes one or more upper substrate upper metallization openings 118A to 118C. For example, as shown in the figure, the upper substrate upper metallization 116 includes three upper substrate upper metallization openings 118A to 118C: a first upper substrate upper metallization opening 118A, a second upper substrate upper metallization opening 118B, and a third upper substrate upper metallization opening 118C. The first upper substrate upper metallization opening 118A includes a partially formed first upper substrate upper metallization opening 118A. The second upper substrate upper metallization opening 118B includes a fully formed second upper substrate upper metallization opening 118B. The third upper substrate upper metallization opening 118C includes a partially formed third upper substrate upper metallization opening 118C.

[0032] As will be described in more detail below, the first upper substrate upper metallization opening 118A is designed to be substantially aligned with the first upper cover cavity 104A. Similarly, as will be described in more detail below, the second upper substrate upper metallization opening 118B is designed to be substantially aligned with the second upper cover cavity 104B. As will be described in more detail below, the third upper substrate metallization opening 118C is designed to be substantially aligned with the third upper cover cavity 104C.

[0033] The upper substrate 112 further includes an upper substrate bottom surface 120. The upper substrate bottom surface 120 includes an upper substrate bottom ground plane 122A which is used as one or more of a reference conductor and a ground conductor in the H-frame device 100.

[0034] While not mandatory, preferably, the upper substrate bottom surface 120 is configured to support the upper substrate bottom metallization 122. For example, the upper substrate bottom metallization 122 has a thickness of about 1 micron to about 13 microns. For example, the upper substrate bottom metallization 122 has a thickness of about 3.5 microns. For example, the upper substrate bottom metallization 122 has a thickness of about 5.5 microns. The upper substrate bottom metallization 122 includes an upper substrate bottom ground plane 122A, a first upper substrate bottom signal line 122B, a circular upper substrate bottom metallization via pad 122C, and a second upper substrate bottom signal line 122D. These three upper substrate bottom metallizations 122B, 122C, and 122D are described in more detail in Figures 2A and 2B.

[0035] The upper substrate bottom metallization 122 includes one or more upper substrate bottom metallization openings 123A to 123C. For example, as shown in the figure, the upper substrate bottom metallization 122 includes three upper substrate bottom metallization openings 123A to 123C: a first upper substrate bottom metallization opening 123A, a second upper substrate bottom metallization opening 123B, and a third upper substrate bottom metallization opening 123C.

[0036] The upper substrate 112 further includes a plurality of metallized upper substrate through substrate vias 124A to 124D, which are configured to provide vertical electrical connections between the upper substrate upper metallization 116 and the upper substrate bottom metallization 122. The bonding of the upper cover 102 to the upper substrate 112 creates a vertical electrical connection between the upper substrate 112 and the upper cover 102.

[0037] As will be described in more detail below, the upper substrate through-substrate signal vias 124A to 124D are preferably hermetically sealed electrical feed through vias. The upper substrate through-substrate vias 124A to 124D are preferably formed by etching through the upper substrate 112 and plating the inner walls of the voids created by the etching, as will be described in more detail below. Preferably, at least one upper surface of the upper substrate through-substrate vias 124A to 124D is sealed. For example, preferably, all upper surfaces of the upper substrate through-substrate vias 124A to 124D are sealed with gold. For example, preferably, all upper surfaces of the upper substrate through-substrate vias 124A to 124D are sealed with gold.

[0038] For example, preferably, the upper surface of at least one of the upper substrate through-substrate vias 124A to 124D is sealed using a solid cap containing gold. The upper substrate through-substrate vias 124A to 124D include a first upper substrate through-substrate via 124A, a second upper substrate through-substrate via 124B, a third upper substrate through-substrate via 124C, and a fourth upper substrate through-substrate via 124D. As will be described in more detail below, the upper substrate through-substrate vias 124A to 124D are preferably hermetically sealed electrical feed through-vias. The upper substrate through-substrate vias 124A to 124D are preferably formed by etching through the upper substrate 112 and plating the inner walls of the voids created by the etching, as will be described in more detail below. Preferably, the upper surface of at least one of the upper substrate through-substrate vias 124A to 124D is sealed. For example, preferably, the upper surface of at least one of the upper substrate through-substrate vias 124A to 124D is sealed with gold. The functions of the second upper substrate through-substrate via 124B and the third upper substrate through-substrate via 124E are described in more detail in Figures 2A and 2B.

[0039] The upper substrate 112 further includes a plurality of upper substrate ground vias 125A to 125O, which are configured to provide electrical grounding. The upper substrate ground vias 125A to 125O include a first upper substrate ground via 125A, a second upper substrate ground via 125F, and a third upper substrate ground via 125K. The functions of the first upper substrate ground via 125A, the second upper substrate ground via 125F, the third upper substrate ground via 125K, and the fourth upper substrate ground via 125M are described in more detail in Figures 1C, 1D, 1E, and 2A.

[0040] The substrate 110 further includes a bottom substrate 126. Therefore, the substrate 110 includes a stack of the top substrate 112 and the bottom substrate 126. More generally, the substrate 110 includes a stack of two or more substrates. The device 100 further includes a metallization located between the top substrate 112 and the bottom substrate 126.

[0041] While not essential, the bottom substrate 126 preferably contains silicon carbide (SiC).

[0042] The bottom substrate 126 is operably connected to the bottom cover 106. Preferably, the bottom substrate 126 is bonded to the bottom cover 106. The bottom substrate 126 includes a bottom substrate bottom surface 128. Preferably, the bottom substrate bottom surface 128 includes circuit components of the H-frame device 100, such as one or more of transistors, capacitors, and transmission lines. Preferably, the bottom substrate bottom surface 128 includes a second bonding interface 128 to which the bottom substrate 126 is physically bonded to the bottom cover 106. Preferably, the bottom substrate 126 is physically bonded to the bottom cover 106. For example, the bottom substrate 126 is physically bonded to the bottom cover 106 at the bottom substrate bottom surface 128. For example, a gold-gold pressure bond is used to physically attach the upper substrate 112 to the bottom cover 106 at the bottom substrate bottom surface 128. For example, a second adhesive (not shown in Figure 1A) physically attaches the bottom substrate 126 to the bottom cover 106 on the bottom surface 128 of the bottom substrate. For example, the second adhesive contains epoxy.

[0043] While not mandatory, preferably, the bottom surface 128 of the bottom substrate is configured to support the bottom substrate metallization 130. For example, the bottom substrate metallization 130 has a thickness of about 1 micron to about 13 microns. For example, the bottom substrate metallization 130 has a thickness of about 3.5 microns. For example, the bottom substrate metallization 130 has a thickness of about 5.5 microns.

[0044] The bottom substrate 126 further includes a bottom substrate upper surface 132. The bottom substrate upper surface 132 is bonded to the top substrate bottom surface 120. As will be described in more detail below, the bottom substrate upper surface 132 is bonded to the top substrate bottom surface 120 using a number of bonding bumps included in both the bottom substrate upper surface 132 and the top substrate bottom surface 120.

[0045] The upper surface 132 of the bottom substrate and the bottom surface 120 of the upper substrate intersect at the third bonding interface 134. While not essential, preferably, the upper surface 132 of the bottom substrate is configured to support the upper metallization 135 of the bottom substrate.

[0046] The bottom substrate upper metallization 135 includes a bottom substrate upper ground plane 135A, a first bottom substrate upper signal line 135B, a circular bottom substrate upper metallization via pad 135C, and a second bottom substrate upper signal line 135D. The first upper substrate bottom signal line 122B and the first bottom substrate upper signal line 135B together form the first intermediate substrate signal line 122B-135B, which is a strip line 122B-135B used by an escape transition (item 210 in Figure 2A, not shown in Figure 1A) to connect the inside and outside of device 100.

[0047] The bottom substrate upper metallization 135 includes one or more bottom substrate upper metallization openings 136A to 136C. For example, as shown in the figure, the bottom substrate upper metallization 135 includes three bottom substrate upper metallization openings 136A to 136C: a first bottom substrate upper metallization opening 136A, a second bottom substrate upper metallization opening 136B, and a third bottom substrate upper metallization opening 136C.

[0048] As will be described in more detail below, the first bottom substrate upper metallization opening 136A is configured to be substantially aligned with the first top substrate bottom cavity 123A. Similarly, the second bottom substrate upper metallization opening 136B is configured to be substantially aligned with the second top substrate bottom cavity 123B. Likewise, the third bottom substrate upper metallization opening 136C is configured to be substantially aligned with the third top substrate bottom cavity 123C. When designing the H-frame device 100, the shape of the first top substrate bottom cavity 123A substantially matches that of the first bottom substrate upper metallization opening 136A. Similarly, when designing the H-frame device 100, the shape of the second top substrate bottom cavity 123B substantially matches that of the second bottom substrate upper metallization opening 136B. Similarly, when designing the H-frame device 100, the shape of the third upper substrate bottom cavity 123C is approximately identical to the shape of the third bottom substrate upper metallization opening 136C.

[0049] For example, the bottom substrate upper metallization 135 has a thickness of about 1 micron to about 13 microns. For example, the bottom substrate upper metallization 135 has a thickness of about 3.5 microns. For example, the bottom substrate upper metallization 135 has a thickness of about 5.5 microns. The bottom substrate upper metallization 135 is preferably in electrical contact with the upper substrate bottom metallization 122, thereby creating a vertical electrical connection between the upper substrate bottom metallization 122 and the bottom substrate upper metallization 135. The bonding of the bottom cover 106 to the bottom substrate 126 creates a first vertical electrical connection between the bottom substrate 126 and the bottom cover 106.

[0050] Using a first vertical electrical connection, the upper substrate upper metallization 116 is electrically connected to the upper substrate bottom metallization 122 outside the upper cover 102. The shape of the upper substrate bottom metallization 122 connects the first vertical electrical connection outside the upper cover 102 to the first vertical electrical connection inside the upper cover 102. Using a first vertical electrical connection, the upper substrate bottom metallization 122 is electrically connected to the upper substrate upper metallization 116 inside the upper cover 102.

[0051] Using a second vertical electrical connection, the bottom substrate bottom metallization 130 is electrically connected to the bottom substrate upper metallization 135 inside the bottom cover 106.

[0052] The bottom substrate bottom metallization 130 further includes bottom substrate bottom signal lines 137 configured to conduct signals.

[0053] The bottom substrate bottom metallization 130 includes one or more bottom substrate bottom metallization openings 138. As shown in the figure, the bottom substrate metallization 130 includes one bottom substrate bottom metallization opening 138. The bottom substrate bottom metallization opening 138 includes a fully formed bottom substrate bottom metallization opening 138.

[0054] As will be described in more detail below, the bottom substrate bottom metallization opening 138 is designed to be approximately aligned with the bottom cover cavity 108.

[0055] The bottom substrate 126 further includes a plurality of bottom substrate through substrate vias 140A to 140B, which are configured to provide a second vertical electrical connection between the bottom substrate upper metallization 135 and the bottom substrate bottom metallization 130. The bonding of the bottom cover 106 to the bottom substrate 126 creates a second vertical electrical connection between the bottom substrate 126 and the bottom cover 106.

[0056] As will be described in more detail below, the bottom substrate through-substrate vias 140A to 140B are preferably hermetically sealed electrical feed through vias. The bottom substrate through-substrate vias 140A to 140B are preferably formed by etching through the upper substrate 112 and plating the inner walls of the voids created by the etching, as will be described in more detail below. Preferably, the upper surface of at least one of the bottom substrate through-substrate vias 140A to 140B is sealed. For example, preferably, the upper surface of at least one of the bottom substrate through-substrate vias 140A to 140B is sealed using gold. For example, preferably, the upper surface of at least one of the bottom substrate through-substrate vias 140A to 140B is sealed using a solid cap containing gold. For example, preferably, the upper surface of at least one of the bottom substrate through-substrate vias 140A to 140B is sealed using a solid cap made of gold.

[0057] The bottom board through-board vias 140A to 140B include a first bottom board signal via 140A and a second bottom board through-board via 140B. These two bottom board through-board vias 140A and 140B are described in more detail in Figures 1H, 2A, and 2G.

[0058] The bottom substrate 126 further includes a plurality of bottom substrate ground vias 141A to 141N, which are configured to provide electrical grounding. The bottom substrate ground vias 141A to 141N include a first bottom substrate ground via 141A, a second bottom substrate ground via 141F, and a third bottom substrate ground via 141H. The functions of the first bottom substrate ground via 141A, the second bottom substrate ground via 141F, and the third bottom substrate ground via 141H are described in more detail in Figures 1H, 2A, and 2B.

[0059] Figure 1B shows a detailed view of the upper cover 102 and the bottom cover 106.

[0060] Similarly, the upper cover 102 includes a first upper cover cavity 104A, a second upper cover cavity 104B, and a third upper cover cavity 104C.

[0061] Similarly, the first upper cover cavity 104A includes a partial first upper cover cavity 104A. The partial first upper cover cavity 104A includes an upper first cavity wall 143A. The upper first cavity wall 143A becomes visible after the upper cover 102 is bonded to the substrate 110, as will be described in more detail below.

[0062] Similarly, the second upper cover cavity 104B includes a fully formed second upper cover cavity 104B. The second upper cover cavity 104B includes a second upper cavity wall 143B.

[0063] Similarly, the third upper cover cavity 104C includes a partial third upper cover cavity 104C. The partial third upper cover cavity 104C includes an upper third cavity wall 143C. The upper third cavity wall 143C becomes visible after the upper cover 102 is bonded to the substrate 110, as will be described in more detail below.

[0064] The upper cover 102 further includes an upper cover metallization 145. The upper cover metallization 145 grounds the upper cover 102. Thus, the upper cover metallization 145 provides an integral part of the overall grounding structure of the microelectronic H-frame device 100. For example, the upper cover metallization 145 includes an upper cover metallization 145 connected independently. For example, as will be described in more detail below, the upper cover metallization 145 is produced by performing gold plating on a microfabricated silicon wafer.

[0065] The upper cover metallization 145 includes a metallized upper cavity floor 146. The second upper cover cavity 104B also includes a metallized upper cavity floor 146. When the upper cover 102 is bonded to the upper substrate 120, the metallized upper cavity floor 146 becomes the upper cover ceiling 146 of the upper cover 102.

[0066] The upper cover metallization 145 further includes a metallized upper cover surface 147. During the fabrication of the device (item 100 in Figure 1A), as will be described in more detail below, the metallized upper cover surface 147 is bonded to a bump on the upper substrate surface 114 to complete the bonding.

[0067] The upper cover metallization 145 further includes a metallized second upper cavity wall 143B. The second upper cover cavity 104B is metallized and includes the second upper cavity wall 143B.

[0068] The bottom cover 106 further includes a bottom cover metallization 149. The bottom cover metallization 149 grounds the top cover 102. Thus, the bottom cover metallization 149 provides an integral part of the overall grounding structure of the microelectronic H-frame device (item 100 in Figure 1A). For example, the bottom cover metallization 149 includes a bottom cover metallization 149 connected independently. For example, as will be described in more detail below, the bottom cover metallization 149 is produced by performing gold plating on a microfabricated silicon wafer.

[0069] The bottom cover metallization 149 includes a metallized bottom cavity floor 150. The bottom cover cavity 108 includes a metallized bottom cavity floor 150. When the bottom cover 106 is bonded to the bottom substrate 126, the metallized bottom cavity floor 150 becomes the floor 150 of the bottom cover 106.

[0070] The bottom cover metallization 149 further includes a metallized bottom cover top surface 151. As will be described in more detail below, during the fabrication of the device (item 100 in Figure 1A), the metallized bottom cover top surface 151 is bonded to a bump on the bottom substrate bottom surface (item 128 in Figure 1A) to complete the bonding.

[0071] The bottom cover metallization 149 further includes a metallized bottom cavity wall 152. The bottom cover cavity 108 also includes a metallized bottom cavity wall 152.

[0072] Figure 1C shows a detailed view of the upper substrate 112. The upper substrate 112 includes the upper substrate top surface 114, the upper substrate upper metallization 116, the upper substrate bottom surface 120, the upper substrate through substrate vias 124A-124D, and the upper substrate ground vias 125A, 125F, 125K, and 125M. Similarly, the upper substrate bottom surface 120 includes the upper substrate bottom metallization 122. (Details of the upper substrate bottom metallization 122 are not visible in Figure 1C, but are explained in more detail in Figures 2A and 2B.)

[0073] Similarly, the upper metallization 116 of the upper substrate includes the upper ground plane 116A of the upper substrate, the first input / output port 116B, the second input / output port 116C, and the first upper signal line 116D of the upper substrate.

[0074] Similarly, the upper board 112 further includes a first input / output port 116B. Preferably, the upper surface 114 of the upper board also includes the first input / output port 116B. The first input / output port 116B is configured to receive input signals and transmit output signals, one or more of these. The first input / output port 116B includes a first ground metal pad 154A of the first port, a first port signal metal pad 154B, and a second ground metal pad 154C of the first port. The signal metal pad of the first port includes a second signal line 154B.

[0075] The first grounding metal pad 154A of the first port is operably connected to the bottom surface 120 of the upper board by one or more of the upper board through-board vias 124A to 124D. The second grounding metal pad 154C of the first port is operably connected to the upper board ground plane 120 by one or more of the upper board through-board vias 124A to 124D.

[0076] The upper board 112 further includes a second input / output port 116C. The upper surface 114 of the upper board, while not mandatory, preferably includes a second input / output port 116C. The second input / output port 116C is configured to receive input signals and transmit output signals, one or more of these. The second input / output port 116C includes a first grounding metal pad 156A of the second port, a second port signaling metal pad 156B, and a second grounding metal pad 156C of the second port. The second port signaling metal pad includes a third signal line 156B.

[0077] The first grounding metal pad 156A of the second port is operably connected to the bottom surface 120 of the upper board by one or more of the upper board through-board vias 124A to 124D. The second grounding metal pad 156C of the second port is operably connected to the bottom surface 120 of the upper board by one or more of the upper board through-board vias 124A to 124D.

[0078] The upper substrate upper metallization 116 further includes one or more upper substrate upper metallization continuous bumps 158A to 158B. As shown in the figure, the upper substrate upper metallization 116 includes two upper substrate upper metallization concentric continuous bumps 158A and 158B, which can be used to bond the upper substrate 112 to the upper cover 102. Preferably, the concentric upper substrate upper metallization continuous bumps 158A and 158B are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0079] The upper substrate upper metallization 116 further includes one or more upper substrate upper metallization individual bumps 160A to 160P, which can be used to bond the upper substrate 112 to the upper cover 102. Preferably, the upper substrate upper metallization individual bumps 160A to 160P are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0080] Preferably, the upper substrate upper metallization continuous bumps 158A, 158B are configured to provide an environmental seal that prevents foreign matter from entering the upper cover 102 after the bond is formed on the upper surface 114 of the upper substrate, thereby protecting the H-frame device 100.

[0081] Preferably, the upper substrate upper metallization individual bumps 160A to 160P are configured to provide an environmental seal that prevents foreign matter from entering the upper cover 102 after the bond is formed on the upper surface 114 of the upper substrate, thereby protecting the H-frame device 100.

[0082] The dotted line 161 in Figure 1C is the boundary of the detailed view of the device, which is provided and described in more detail in Figure 1E.

[0083] Figure 1D shows an exploded view of the upper substrate 112. The upper substrate 112 includes the upper substrate upper metallization 116, the upper substrate bottom metallization 122, and the upper dielectric 162. The upper dielectric 162 includes an electrical insulator 162. Similarly, the upper substrate upper metallization 116 includes upper substrate through substrate vias 124A to 124D, upper substrate ground vias 125F, 125K, and 125M, upper substrate upper metallization continuous bumps 158A to 158B, and upper substrate upper metallization individual bumps 160A to 160P.

[0084] Similarly, the upper surface 114 of the upper board, the lower surface 120 of the upper board, and the through-board vias 124A to 124D of the upper board are also shown.

[0085] The upper metallization 116 of the upper board further includes a first input / output port 116B. The upper metallization 116 of the upper board further includes a second input / output port 116C.

[0086] The upper dielectric 162 includes the upper substrate top surface 114, the upper substrate bottom surface 120, and the upper substrate through substrate vias 124A to 124D.

[0087] Similarly, the first input / output port 116B includes a first ground metal pad 154A of the first port, a first port signal metal pad 154B, and a second ground metal pad 154C of the first port. Similarly, the first ground metal pad 154A of the first port is operably connected to the upper board bottom ground plane 122A by one or more of the upper board through-board vias 124A to 124D. The second ground metal pad 154C of the first port is operably connected to the upper board ground plane 122A by one or more of the upper board through-board vias 124A to 124D.

[0088] Similarly, the second input / output port 116C includes a first ground metal pad 156A of the second port, a second port signal metal pad 156B, and a second ground metal pad 156C of the second port. Similarly, the first ground metal pad 156A of the second port is operably connected to the upper board bottom ground plane 122A by one or more of the upper board through-board vias 124A to 124D. Similarly, the second ground metal pad 156C of the second port is operably connected to the upper board ground plane 122A by one or more of the upper board through-board vias 124A to 124D.

[0089] The upper substrate bottom metallization 122 includes a grounded upper substrate bottom ground plane 122A. The upper substrate bottom metallization 122 includes a first upper substrate bottom signal line 122B configured to conduct signals. Similarly, the upper substrate bottom metallization 122 includes a first upper substrate bottom metallization opening 123A, a second upper substrate bottom metallization opening 123B, and a third upper substrate bottom metallization opening 123C.

[0090] When designing the H-frame device 100, the first upper substrate bottom signal line 122B has a shape that substantially matches the bottom substrate top signal line (item 135B shown in Figure 1A, not shown in Figure 1D). The first upper substrate bottom signal line 122B is bonded to the bottom substrate top signal line (item 135B shown in Figure 1A, not shown in Figure 1D) at a third bonding interface 134 using a number of bonding bumps (not shown in Figure 1D). Together, the first upper substrate bottom signal line 122B and the first bottom substrate top signal line (item 135B shown in Figure 1A, not shown in Figure 1D) form the first intermediate substrate signal lines 122B-135B, which are strip lines 122B-135B used by escape transitions (item 210 in Figure 2A, not shown in Figure 1A) to connect the inside and outside of the device 100.

[0091] When designing the H-frame device 100, the circular upper substrate bottom metallization via pad 122C substantially matches the shape of the circular bottom substrate top metallization via pad (item 135C shown in Figure 1A, not shown in Figure 1D). The circular upper substrate bottom metallization via pad 122C is bonded to the circular bottom substrate top metallization via pad (item 135C shown in Figure 1A, not shown in Figure 1D) at a third bonding interface 134 using a number of bonding bumps (not shown in Figure 1D). Together, the circular upper substrate bottom metallization via pad 122C and the circular bottom substrate top metallization via pad (item 135C shown in Figure 1A, not shown in Figure 1D) form via pads 122C-135C, which helps to provide one or more of electrical connections and electrical fencing.

[0092] Similarly, the upper substrate bottom metallization 122 further includes a circular upper substrate bottom metallization 122C and a second upper substrate bottom signal line 122D.

[0093] The upper substrate bottom metallization 122 further includes one or more upper substrate bottom metallization continuous bumps 163A to 163B. As shown in the figure, the upper substrate bottom metallization 122 includes two concentric upper substrate bottom metallization continuous bumps 163A, 163B which can be used to bond the upper substrate 112 to the bottom substrate 126. Preferably, the concentric upper substrate bottom metallization continuous bumps 163A, 163B are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0094] The upper substrate bottom metallization 122 further includes one or more upper substrate bottom metallization individual bumps 164A to 164P, which can be used to bond the upper substrate 112 to the bottom substrate 126. Preferably, the upper substrate bottom metallization individual bumps 164A to 164P are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0095] Preferably, the upper substrate bottom metallization continuous bumps 163A, 163B are configured to provide an environmental seal that prevents foreign matter from entering the substrate 110 after the bond is formed on the upper substrate bottom surface 120, thereby protecting the H-frame device 100.

[0096] Preferably, the upper substrate bottom metallization individual bumps 164A to 164P are configured to provide an environmental seal that prevents foreign matter from entering the substrate 110 after the bond is formed on the upper substrate bottom surface 120, thereby protecting the H-frame device 100.

[0097] Figure 1E shows a detailed view of a portion 161 of Figure 1C, which is a portion of the upper substrate 112. The dotted line 161 in Figure 1C is the boundary of the detailed view of the device shown in Figure 1E.

[0098] Similarly, the upper substrate 112 includes the upper substrate top surface 114, the upper substrate upper metallization 116A and 116C, the upper substrate bottom surface 120, the upper substrate through substrate vias 124A to 124D, and the upper substrate ground vias 125F, 125K, and 125M.

[0099] Similarly, the upper board 112 further includes a second input / output port 116C. Preferably, though not required, the upper surface 114 of the upper board also includes a second input / output port 116C. Similarly, the second input / output port 116C includes a first ground metal pad 156A for the second port, a second port signal metal pad 156B, and a second ground metal pad 156C for the second port.

[0100] The first ground metal pad 156A of the second port is operably connected to the upper substrate bottom ground plane 122A by the second upper substrate ground via 125F. The second signal metal pad 156B of the second port is operably connected to the second upper substrate bottom signal line 122D by the fourth upper substrate signal via 12D. The fourth upper substrate through-substrate via 124D includes a high-temperature upper substrate through-substrate via 124D that can be used in transitions. The third upper metal pad 156C of the second port is operably connected to the upper substrate bottom ground plane 122A by the third upper substrate ground via 125K. The third upper substrate ground via 125K is configured to provide general ground to one or more of the upper substrate 112 and the H-frame device 100. The fourth upper substrate ground via 125M is configured to provide general ground to one or more of the upper substrate 112 and the H-frame device 100.

[0101] Similarly, the upper substrate upper metallization 116 further includes one or more upper substrate upper metallization continuous bumps 158A-158B. As shown in the figure, the upper substrate upper metallization 116 includes two concentric upper substrate upper metallization continuous bumps 158A, 158B, which can be used to bond the upper substrate 112 to the upper cover 102. Preferably, the upper substrate upper metallization concentric continuous bumps 158A, 158B are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0102] Similarly, the upper substrate upper metallization 116 further includes one or more upper substrate upper metallization individual bumps 160A to 160P, which can be used to bond the upper substrate 112 to the upper cover 102. Preferably, the individual bumps 160A to 160P are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0103] Preferably, the upper substrate upper metallization continuous bumps 158A, 158B are also configured to provide an environmental seal, which prevents foreign matter from entering the upper cover 102 after the bond is formed on the upper surface 114 of the upper substrate, thereby protecting the H-frame device 100.

[0104] Figure 1F shows a detailed view of the bottom substrate 126. Similarly, the bottom substrate 126 includes a bottom substrate bottom surface 128, a bottom substrate top surface 132, a bottom substrate upper metallization 135 (shown in more detail here, and thus four bottom substrate upper metallization regions are shown here), a bottom substrate bottom metallization opening 138, bottom substrate through substrate vias 140A and 140B, and bottom substrate ground vias 141F and 141H. Similarly, the bottom substrate top surface 132 includes the bottom substrate upper metallization 135. Similarly, the bottom substrate upper metallization 135 includes a first metallization opening 136A of the first bottom substrate, a second bottom substrate upper metallization opening 136B, and a third bottom substrate upper metallization opening 136C.

[0105] The bottom substrate upper metallization 135A further includes one or more bottom substrate upper metallization continuous bumps 165A-165B. As shown in the figure, the bottom substrate upper metallization 135A includes two concentric bottom substrate upper metallization continuous bumps 165A, 165B, which can be used to bond the bottom substrate 126 to the upper substrate 112. Preferably, the concentric bottom substrate upper metallization continuous bumps 165A, 165B are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0106] The bottom substrate upper metallization 135A further includes one or more individual bottom substrate upper metallization bumps 166A to 166P, which can be used to bond the bottom substrate 126 to the upper substrate 112. Preferably, the individual bottom substrate upper metallization bumps 166A to 166P are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0107] Preferably, the metallization continuous bumps 165A and 165B on the upper part of the bottom substrate are configured to provide an environmental seal that prevents foreign matter from entering between the upper substrate 112 and the bottom substrate 126 after the bonding on the surface 134, thereby protecting the H-frame device 100.

[0108] Preferably, the bottom substrate upper metallization individual bumps 166A to 166P are configured to provide one or more environmental seals that prevent moisture and foreign matter from entering between the upper substrate 112 and the bottom substrate 126 after the bonding on the top surface 132 of the bottom substrate, thereby protecting the H-frame device 100.

[0109] The dotted line 175 in Figure 1F is the boundary of the detailed view of the device, which is provided and described in more detail in Figure 1H.

[0110] Figure 1G shows an exploded view of the bottom substrate 126. Similarly, the bottom substrate 126 includes a bottom substrate bottom metallization 130, a bottom substrate upper metallization 135, and a bottom substrate bottom metallization opening 138. The bottom substrate bottom metallization 130 includes a bottom substrate bottom signal line 137 configured to conduct signals.

[0111] The bottom substrate 126 further includes a bottom dielectric 179. The bottom dielectric 179 includes an electrical insulator. Similarly, the top metallization 135 of the bottom substrate includes continuous top metallization bumps 165A to 165B and individual top metallization bumps 166A to 166P.

[0112] Similarly, the bottom substrate bottom surface 128, the top substrate surface 132, the bottom substrate through substrate vias 140A and 140B, and the bottom substrate ground vias 141F and 141H are also shown.

[0113] The bottom dielectric 179 includes the bottom substrate bottom surface 128, the bottom substrate top surface 132, and the bottom substrate through substrate vias 140A and 140B.

[0114] The bottom substrate bottom metallization 130 includes a grounded bottom substrate bottom ground plane 180. The bottom substrate bottom metallization 130 includes bottom substrate bottom signal lines 137 configured to conduct signals.

[0115] The bottom substrate bottom metallization 130 further includes one or more bottom substrate bottom metallization continuous bumps 183A to 183B. As shown in the figure, the bottom substrate bottom metallization 130 includes two concentric bottom substrate bottom metallization continuous bumps 183A and 183B, which can be used to bond the bottom substrate 126 to the bottom cover 106. Preferably, the bottom substrate bottom metallization concentric continuous bumps 183A and 183B are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest. Preferably, the bottom substrate bottom metallization individual bumps 185A to 185P are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0116] Preferably, the bottom substrate bottom metallization continuous bumps 183A, 183B are configured to provide an environmental seal that prevents foreign matter from entering the substrate 110 after the bond is formed on the bottom surface 128 of the bottom substrate, thereby protecting the H-frame device 100.

[0117] Preferably, the bottom substrate bottom metallization individual bumps 185A to 185P are configured to provide one or more environmental seals that prevent moisture and foreign matter from entering the bottom cover 106 after the bond is formed on the bottom surface 128 of the bottom substrate, thereby protecting the H-frame device 100.

[0118] Figure 1H shows a detailed view of a portion 175 of Figure 1F, which shows a portion of the bottom substrate 126. The dotted line 175 in Figure 1F is the boundary of the detailed view of the device shown in Figure 1H.

[0119] Similarly, the bottom substrate 126 includes a bottom substrate bottom surface 128, a bottom substrate top surface 132, bottom substrate upper metallizations 135A and 135C-135D, bottom substrate through substrate vias 140A and 140B, bottom substrate upper metallization concentric continuous bumps 165A-165B, bottom substrate upper metallization individual bumps 164A-164P, and a bottom substrate bottom ground plane 180. Preferably, the concentric bottom substrate bottom metallization continuous bumps 165A and 165B are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0120] The bottom substrate 126 includes a second bottom substrate through-substrate via 140B, which includes a second high-temperature bottom substrate through-substrate via 140B usable in the transition. The bottom substrate 126 further includes a second bottom substrate ground via 141F and a third bottom substrate ground via 141H. The second bottom substrate ground via 141F is configured to provide general grounding to one or more of the bottom substrate 126 and the H-frame device 100. Similarly, the third bottom substrate ground via 141H is configured to provide general grounding to one or more of the bottom substrate 126 and the H-frame device 100.

[0121] The bottom substrate bottom metallization 130 further includes one or more individual bumps 185A to 185P, which can be used to bond the bottom substrate 126 to the bottom cover 106. Preferably, the individual bumps 185A to 185P are spaced apart so as to be separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0122] Preferably, the bottom substrate bottom metallization continuous bumps 183A, 183B are configured to provide an environmental seal that prevents foreign matter from entering the bottom cavity (item 108 in Figure 1A, not shown in this figure) after bonding is formed to the bottom cover 106 on the bottom substrate bottom surface 128, thereby protecting the H-frame device 100.

[0123] Figures 2A to 2G are a set of seven diagrams illustrating circuits using strip lines and feedthrough transitions in microelectronics H-frame devices.

[0124] Figure 2A shows the H-frame device 100 and the circuit 205 formed by the H-frame device 100. Similarly, the upper cover 102, the bottom cover 106, the substrate 110, the upper substrate 112, the first bonding interface 114, the first input / output port 116B, the second input / output port 116C, the first upper substrate upper signal line 116D, the upper substrate bottom surface 120, the first upper substrate bottom signal line 122B, the circular upper substrate bottom metallization via pad 122C, the second upper substrate bottom signal line 122D, the first upper substrate through-substrate via 124A, the second upper substrate through-substrate via 124B, the third upper substrate through-substrate via 124C, the fourth upper substrate through-substrate via 124D, and the second upper substrate ground via The following are shown: via A125F, a third upper substrate ground via 125K, a fourth upper substrate ground via 125M, a bottom substrate 126, a second bonding interface 128, a third bonding interface 134, a bottom substrate bottom signal line 137, a first bottom substrate through substrate via 140A, a second bottom substrate through substrate via 140B, a first ground metal pad 154A of the first port, a first port signal metal pad 154B, a second ground metal pad 154C of the first port, a first ground metal pad 156A of the second port, a second port signal metal pad 156B, and a second ground metal pad 156C of the second port. In this example, the typical thickness of the SiC substrate 110 is approximately 200 microns, and the relative dielectric value of the SiC substrate is approximately 9.7.

[0125] Circuit 205 includes a first sub-circuit 210, a second sub-circuit 220, and a third sub-circuit 230. The second sub-circuit 220 is operably connected to the first sub-circuit 210. For example, preferably, the second sub-circuit 220 is electrically connected to the first sub-circuit 210. The third sub-circuit 230 is operably connected to the second sub-circuit 220. For example, preferably, the third sub-circuit 230 is electrically connected to the second sub-circuit 220.

[0126] The first subcircuit 210 includes a first escape transition 210. The first subcircuit 210 includes a first escape transition 210 configured to bring a signal between the outside of one or more of the top cover 102 and the bottom cover 106 and the inside of one or more of the top cover 102 and the bottom cover 106. In this example, the first subcircuit 210 brings a signal from outside the top cover 102 into the inside of the top cover 102. Thus, the first subcircuit 210 includes a first microstrip 210. The first microstrip 210 includes a second signal line 154B extending over the top surface 114 of the top substrate. The first microstrip 210 further includes the bottom surface 120 of the top substrate, which is located between the top substrate 112 and the bottom substrate 126.

[0127] The first subcircuit 210 includes a second signal line 154B, a first upper board through-board via 124A, a first upper board bottom signal line 122B, a second upper board through-board via 124B, and a portion of the first upper board upper signal line 116D. The second signal line 154B is operably connected to the first upper board through-board via 124A. Preferably, as shown in the figure, the second signal line 154B is electrically connected to the first upper board through-board via 124A. The first upper board through-board via 124A is operably connected to the first upper board bottom signal line 122B. Preferably, as shown in the figure, the first upper board through-board via 124A is electrically connected to the first upper board bottom signal line 122B. The first upper board bottom signal line 122B is operably connected to the second upper board through-board via 124B. Preferably, as shown in the figure, the first upper substrate bottom signal line 122B is electrically connected to the second upper substrate signal via 124B. The second upper substrate through substrate via 124B is operably connected to the first upper substrate signal line 116D. Preferably, as shown in the figure, the second upper substrate through substrate via 124B is electrically connected to the first upper substrate upper signal line 116D.

[0128] The second subcircuit 220 includes a vertical feedthrough circuit 220 or a second microstrip 220 that supplies signals from the first subcircuit 210 to the third subcircuit 230. The second microstrip 220 includes a first upper board upper signal line 116D extending over the upper board upper surface 114. The second microstrip 220 further includes an upper board bottom surface 120 positioned between the upper board 112 and the bottom board 126.

[0129] The second subcircuit 220 includes a portion of the first upper board signal line 116D, a third upper board through-board via 124C, a circular upper board bottom metallization via pad 122C, a first bottom board through-board via 140A, and a portion of the bottom board bottom signal line 137. The first upper board signal line 116D is operably connected to the third upper board through-board via 124C. Preferably, as shown in the figure, the first upper board signal line 116D is electrically connected to the third upper board through-board via 124C. The third upper board through-board via 124C is operably connected to the circular upper board bottom metallization via pad 122C.

[0130] Preferably, as shown in the figure, the third upper substrate through-substrate via 124C is electrically connected to the circular upper substrate bottom metallization via pad 122C. The circular upper substrate bottom metallization via pad 122C is operably connected to the first bottom substrate through-substrate via 140A. Preferably, as shown in the figure, the circular upper substrate bottom metallization via pad 122C is electrically connected to the first bottom substrate through-substrate via 140A. The first bottom substrate through-substrate via 140A is operably connected to the bottom substrate bottom signal line 137. Preferably, as shown in the figure, the first bottom substrate through-substrate via 140A is electrically connected to the bottom substrate bottom signal line 137.

[0131] The third subcircuit 230 includes a second escape transition 230. The third subcircuit 230 includes a second escape transition 230 configured to bring a signal between the outside of one or more of the top cover 102 and the bottom cover 106 and the inside of one or more of the top cover 102 and the bottom cover 106. In this example, the third subcircuit 230 brings a signal from inside the bottom cover 106 to the outside of the bottom cover 106. Thus, the third subcircuit 230 includes a second microstrip 230. The third microstrip 230 includes a third signal line 156B extending over the top surface 114 of the top substrate. The third microstrip 230 further includes the bottom surface 120 of the top substrate, which is located between the top substrate 112 and the bottom substrate 126.

[0132] The third subcircuit 230 includes a portion of the bottom board bottom signal line 137, a second bottom board through-board via 140B, a second top board bottom signal line 122D, a fourth top board through-board via 124D, and a second port signal metal pad 156B. The bottom board signal line 137 is operably connected to the second bottom board through-board via 140B. Preferably, as shown in the figure, the bottom board signal line 137 is electrically connected to the second bottom board through-board via 140B. The second bottom board through-board via 140B is operably connected to the second top board bottom signal line 122D. Preferably, as shown in the figure, the second bottom board through-board via 140B is electrically connected to the second top board bottom signal line 122D. The second upper substrate bottom signal line 122D is operably connected to the fourth upper substrate through-board via 124D. Preferably, as shown in the figure, the second upper substrate bottom signal line 122D is electrically connected to the fourth upper substrate through-board via 124D. The fourth upper substrate through-board via 124D is operably connected to the second port signal metal pad 156B. Preferably, as shown in the figure, the fourth upper substrate signal via 124D is electrically connected to the second port signal metal pad 156B.

[0133] Figure 2B shows a diagram of the signal path of circuit 205. Similarly, circuit 205 includes a first sub-circuit 210, a second sub-circuit 220, and a third sub-circuit 230. Similarly, the second sub-circuit 220 is operably connected to the first sub-circuit 210. For example, preferably, similarly, the second sub-circuit 220 is electrically connected to the first sub-circuit 210. Similarly, the third sub-circuit 230 is operably connected to the second sub-circuit 220. For example, preferably, similarly, the third sub-circuit 230 is electrically connected to the second sub-circuit 220.

[0134] Similarly, the first upper board upper signal line 116D, the first input / output port 154B, the second input / output port 156B, the first upper board upper signal line 116D, the first upper board bottom signal line 122B, the circular upper board bottom metallization via pad 122C, the second upper board bottom signal line 122D, the first upper board through-board via 124A, the second upper board through-board via 124B, the third upper board through-board via 124C, the fourth upper board through-board via 124D, the third upper board ground via 125H, the fourth upper board ground via 125K, the first bottom board through-board via 140A, the second bottom board through-board via 140B, and the bottom board bottom signal line 137 are shown.

[0135] Similarly, the first subcircuit 210 includes a second signal line 154B, a first upper board through-board via 124A, a first upper board bottom signal line 122B, a second upper board through-board via 124B, and a portion of the first upper board top signal line 116D. Similarly, the second signal line 154B is electrically connected to the first upper board through-board via 124A, the first upper board through-board via 124A is electrically connected to the first upper board bottom signal line 122B, the first upper board bottom signal line 122B is electrically connected to the second upper board through-board via 124B, and the second upper board through-board via 124B is electrically connected to the first upper board top signal line 116D.

[0136] The second subcircuit 220 includes a vertical feedthrough circuit 220 that supplies signals from the first subcircuit 210 to the third subcircuit 230. Similarly, the vertical feedthrough circuit 220 includes a portion of the first upper board signal line 116D extending over the upper surface of the upper board (item 114 in Figure 2A, not shown in Figure 2B). Similarly, the vertical feedthrough circuit 220 further includes a third upper board through-board via 124C, a circular upper board bottom metallization via pad 122C, a first bottom board through-board via 140A, and a portion of the bottom board bottom signal line 137. Similarly, the first upper board signal line 116D is electrically connected to the third upper board through-board via 124C, the third upper board through-board via 124C is electrically connected to the circular upper board bottom metallization via pad 122C, the circular upper board bottom metallization via pad 122C is electrically connected to the first bottom board through-board via 140A, and the first bottom board through-board via 140A is electrically connected to the bottom board bottom signal line 137.

[0137] The third subcircuit 230 includes a second escape transition 230. The third subcircuit 230 includes a second escape transition 230 configured to bring a signal between the outside of one or more of the top cover 102 and bottom cover 106 and the inside of one or more of the top cover 102 and bottom cover 106. In this example, the third subcircuit 230 brings a signal from inside the bottom cover 106 to the outside of the top cover 102. Thus, the third subcircuit 230 includes a second microstrip 230. Similarly, the second microstrip 230 includes a portion of the bottom board bottom signal line 137, a second bottom board through-board via 140B, a second top board bottom signal line 122D, a fourth top board through-board via 124D, and a second port signal metal pad 156B. Similarly, the bottom board bottom signal line 137 is electrically connected to the second bottom board bottom through board via 140B, and the second bottom board bottom through board via 140B is electrically connected to the second top board bottom signal line 122D, and the second top board bottom signal line 122D is electrically connected to the fourth top board through board via 124D, and the fourth top board through board via 124D is electrically connected to the second port signal metal pad 156B.

[0138] Therefore, considering the circuit as a whole, the circuit 205 includes, from left to right, a second signal line 154B, a first upper board through-board line 124A, a first upper board bottom signal line 122B, a second upper board through-board via 124B, a first upper board top signal line 116D, a third upper board through-board via 124C, a circular upper board bottom metallization via pad 122C, a first bottom board through-board via 140A, a bottom board bottom signal line 137, a second bottom board bottom through-board via 140B, a second upper board bottom signal line 122D, a fourth upper board through-board via 124D, and finally, a second port signal metal pad 156B.

[0139] To optimize circuit 205, the first sub-circuit 210 may have a different design from the third sub-circuit 230. The typical impedance Z0 of the first sub-circuit 210 is approximately 50 ohms. The typical impedance Z0 of the second sub-circuit 220 is approximately 50 ohms. The typical impedance Z0 of the third sub-circuit 230 is approximately 50 ohms.

[0140] Figure 2C shows details of the first subcircuit 210, which shows a vertical feedthrough circuit 210 for signals entering the H-frame device 100. The H-frame device 100 also includes an upper cover 102, a first upper cover cavity 104A, a second upper cover cavity 104B, a bottom cover 106, and a substrate 110. The substrate 110 also includes an upper substrate 112 and a bottom substrate 126. The upper substrate 112 also includes an upper substrate top surface 114 and an upper substrate bottom surface 120. The upper substrate 112 further includes a first upper substrate through-substrate via 124A and a second upper substrate through-substrate via 124B. The first upper substrate through-substrate via 124A is operably connected to a first upper substrate via pad 232 on its upper surface. Preferably, as shown in the figure, the first upper board through-board via 124A is electrically connected to the first upper board via pad 232. The first upper board through-board via 124A is operably connected to the second upper board via pad 234 at its bottom.

[0141] Similar to the via pads 122C-135C described with respect to Figures 1D and 2E, the second upper substrate via pad 234, with reference to the via pads 122C-135C, includes a portion of the upper substrate bottom metallization (not shown in Figure 2C) and further includes a portion of the bottom substrate top metallization (not shown in Figure 2C), which are joined together using a number of bonding bumps (not shown in Figure 2C). The upper substrate via pad 234 helps to provide one or more of electrical connections and electrical fencing.

[0142] Preferably, as shown in the figure, the first upper substrate through-substrate via 124A is electrically connected to the second upper substrate via pad 234. Similarly, the upper substrate top surface 114 includes the first port signal metal pad 154B and the first upper substrate top signal line 116D. Similarly, the bottom substrate 126 includes the bottom substrate top surface 132, which is coupled to the upper substrate bottom surface 120 at a third bonding interface 134 after assembly. Similarly, the upper substrate bottom surface 120 includes the first upper substrate bottom signal line 122B. Similarly, the bottom substrate 126 further includes the bottom substrate bottom surface 128.

[0143] Preferably, an electronic signal enters the H-frame device 100 from the outside via a first port signal metal pad 154B. The electronic signal proceeds from the first port signal metal pad 154B to the first upper substrate via pad 232. The first upper substrate through-substrate via 124A electrically connects the first port signal metal pad 154B to the first upper substrate bottom signal line 122B, which includes the upper substrate bottom surface 120, the bottom substrate top surface 132, and bumps. The first upper substrate through-substrate via 124A includes a single-layer vertical feedthrough 124B. The electronic signal then proceeds from the first upper substrate through-substrate via 124A to the upper substrate bottom signal line 122B, which includes the upper substrate bottom surface 120, the bottom substrate top surface 126, and bumps. The first upper substrate bottom signal line 122B includes a first strip line 122B, which is configured to travel under the upper cover 102 and further configured to travel over the bottom cover 106 in order to enter the second upper cover cavity 104B.

[0144] To minimize reflections in the vertical feedthrough circuit 210 over a desired frequency band, the dimensions of features within the vertical feedthrough circuit 210 can be carefully designed. Dimensions that can be carefully designed to minimize reflections include one or more of the diameters of the first upper cavity 104A, the second upper cavity 104B, the first upper substrate via pad 232, the second upper substrate via pad 234, and the diameters of the openings. (Although openings are not shown in this figure, an example of an opening can be seen as the upper and bottom metallization openings 262 in Figure 2E.) Depending on the requirements of a particular application, features such as a narrower microstrip section (or "neck") adjacent to one or more of the first upper substrate via pads 232 and the second upper substrate via pads 234 may be included in the design of the microelectronic H-frame device, for example, as shown in Figure 2C. Alternatively or additionally, a narrower section of microstrip may be adjacent to a wider microstrip section (or "shoulder"). For example, such a design can easily achieve good return loss over a wide frequency band.

[0145] For example, the frequency band is selected based on design requirements. For instance, in a system intended to operate under DC up to approximately 20 GHz, a SiC substrate with a thickness of approximately 100 to 300 microns may be selected. For example, in a system intended to operate under DC up to approximately 20 GHz, a SiC substrate with a via diameter of approximately 50 to 150 microns may be selected. For example, in a system intended to operate in a Q band of approximately 33 GHz to 50 GHz, a SiC substrate with a thickness of approximately 75 to 125 microns may be selected.

[0146] Next, the electronic signal proceeds from the first strip line 122B to the second upper board through-board via 124B. The second upper board through-board via 124B includes a single-layer vertical feedthrough 124C. The second upper board through-board via 124B electrically connects the first strip line 122B to the first upper board upper signal line 116D located on the upper surface 114 of the upper board. The signal reaches the first upper board upper signal line 116D, exits the first sub-circuit 210, and thus also exits from the right side of Figure 2C.

[0147] Figure 2D is a graph 250 of simulation data showing typical values ​​of insertion loss 252 and return loss 254 in a plot of insertion loss decibels (dB) 255 and return loss (dB) 256 for the first subcircuit 210 against a frequency 258 in gigahertz (GHz).

[0148] As shown in Graph 250, the insertion loss 254 is less than approximately 0.2 dB across the entire frequency band 258. Also as shown in Graph 250, the return loss 256 is greater than approximately 20 dB across the entire frequency band 258. In general, typical insertion losses range from approximately 0.01 dB to approximately 0.5 dB, depending on one or more of the material, transition type, transition size, frequency, and design. In general, typical return losses range from approximately 15 dB to approximately 30 dB, depending on the application.

[0149] Figure 2E shows details of the second sub-circuit 220, which represents the vertical feedthrough circuit 220 of the signal entering the second sub-circuit 220 of the H-frame device 100. Similarly, the H-frame device 100 includes an upper cover 102, a bottom cover 106, and a substrate 110. Similarly, the upper cover 102 includes a second upper cavity 104B. Similarly, the second upper cavity 104B includes a second upper cavity wall 143B. Similarly, the bottom cover 106 includes a bottom cavity 108. Similarly, the bottom cavity 108 includes a bottom cavity wall 152. The bottom cavity 108 has a typical bottom cavity diameter 260, which is equal to approximately 800 microns.

[0150] Similarly, substrate 110 includes an upper substrate 112 and a bottom substrate 126. Similarly, upper substrate 112 includes an upper substrate top surface 114 and an upper substrate bottom surface 120. Similarly, upper substrate top surface 114 includes a first upper substrate top signal line 116D. Similarly, bottom substrate 126 includes a bottom substrate top surface 132, which is coupled to upper substrate bottom surface 120 at a third bonding interface 134 after assembly. Similarly, upper substrate bottom surface 120 includes a first signal bottom substrate through substrate via 140A and bottom substrate bottom signal line 137. Bottom substrate top surface 132 and upper substrate bottom surface 120 include upper and bottom metallization openings 262 from which substrate material has been removed, which allow signals to pass through bottom substrate top surface 132 and upper substrate bottom surface 120. The upper and lower metallization openings 262 have a typical notch diameter 265 equal to approximately 600 microns.

[0151] Similarly, the bottom surface further includes the bottom substrate bottom surface 128.

[0152] The electronic signal preferably enters the second subcircuit 220 on the upper surface 114 of the upper substrate from the first subcircuit 210 via the first upper substrate upper signal line 116D. The electronic signal proceeds from the first upper substrate upper signal line 116D to the third upper substrate through-board via 124C before reaching the second upper cavity wall 143B. The third upper substrate through-board via 124C electrically connects the first upper substrate upper signal line 116D to the via pads 122C-135C described above with respect to Figure 1D.

[0153] As described above with respect to Figure 1D, when designing the H-frame device 100, the circular upper substrate bottom metallization via pad 122C substantially matches the shape of the circular bottom substrate top metallization via pad (item 135C shown in Figure 1A, not shown in Figure 2E). The circular upper substrate bottom metallization via pad 122C is bonded to the circular bottom substrate top metallization via pad (item 135C shown in Figure 1A, not shown in Figure 2E) at a third bonding interface 134 using a number of bonding bumps (not shown in Figure 2E). Together, the circular upper substrate bottom metallization via pad 122C and the circular bottom substrate top metallization via pad (item 135C shown in Figure 1A, not shown in Figure 2E) form via pads 122C-135C, which helps to provide one or more of electrical connections and electrical fencing. Beer pads 122C to 135C have a typical beer pad diameter of 270, which is approximately 200 microns.

[0154] A third upper substrate through-substrate via 124C is coupled to the upper surface 132 of the bottom substrate at a third bonding interface 134. The third upper substrate through-substrate via 124C includes a single-layer vertical feedthrough 124E. The electronic signal then travels from the circular upper substrate bottom metallization via pad 122C through the upper and bottom metallization openings 240 to the first bottom substrate through-substrate via 140A. The first bottom substrate through-substrate via 140A electrically connects the signal to the bottom substrate bottom signal line 137. Once the signal reaches the bottom substrate bottom signal line 137, the signal continues as an inverted microstrip that travels away from the bottom cavity wall 152 toward the third subcircuit 230, as shown in detail in Figure 2G.

[0155] The second upper cavity wall 143B and the bottom cavity wall 152 include an integral component of the vertical feedthrough transition circuit 220. The second upper cavity wall 143B and the bottom cavity wall 152 help to gradually change the direction of the electric field within the vertical feedthrough transition circuit 220. The second upper cavity wall 143B and the bottom cavity wall 152 essentially form a vertical channel connecting the first upper substrate upper signal line 116D and the first bottom substrate through-substrate via 140A. The first upper substrate upper signal line 116D and the first bottom substrate through-substrate via 140A become horizontal channels 116D and 137, respectively, connected to each other via a single-layer vertical feedthrough 124E, a circular upper substrate bottom metallization via pad 122C, and the first bottom substrate through-substrate via 140A. These elements together form a Z-shaped three-dimensional channelization 272, which prevents signals from leaking into areas outside the channelization 272. The Z-shape of the channelization 272 is an example, and other configurations are possible within the scope of embodiments of the present invention. The channelization 272 allows electronic signals to undergo one or more of the following: a change of direction and a change of height. As shown in the figure, the signal is initially horizontal while passing through the first upper substrate upper signal line 116D, and becomes vertical while passing through the first layer vertical feedthrough 124E, the circular upper substrate bottom metallization via pad 122C, and the first bottom substrate through substrate via 140A. The signal then becomes horizontal again while passing through the bottom substrate bottom signal line 137.

[0156] Therefore, the signal exits the second subcircuit 220 on the right side of Figure 2E via the bottom board bottom signal line 137 located on the bottom board bottom surface 128. Thus, the second subcircuit 220 functions as a vertical feedthrough transition 220, receiving the signal on the top board top surface 114 via the first top board top signal line 116D and generating the output signal on the bottom board bottom surface 128.

[0157] Figure 2F shows details of the third subcircuit 230, which shows a vertical feedthrough circuit 230 for signals entering and exiting the H-frame device 100. Similarly, the H-frame device 100 includes an upper cover 102, a third upper cover cavity 104C, a bottom cover 106, and a substrate 110. Similarly, the substrate 110 includes an upper substrate 112 and a bottom substrate 126. Similarly, the upper substrate 112 includes an upper substrate top surface 114 and an upper substrate bottom surface 120. Similarly, the upper substrate 112 further includes a fourth upper substrate through-substrate via 124D and a fourth upper substrate ground via 125K. Similarly, the bottom substrate 126 further includes a second bottom substrate through-substrate via 140B. Similarly, the upper substrate top surface 114 includes a second port signal metal pad 156B. Similarly, the bottom substrate 126 includes a bottom substrate upper surface 132, which is bonded to the top substrate bottom surface 120 at a third bonding interface 134 after assembly. Similarly, the top substrate bottom surface 120 includes a second top substrate bottom signal line 122D and a bottom substrate bottom signal line 137. Similarly, the bottom substrate 126 further includes a bottom substrate bottom surface 128.

[0158] Preferably, an electronic signal enters the H-frame device 100 from the second subcircuit 220 via the bottom substrate bottom signal line 137. The electronic signal proceeds from the bottom substrate bottom signal line 137 to the second bottom substrate through substrate via 140B. The second bottom substrate through substrate via 140B electrically connects the bottom substrate bottom signal line 137 to the second upper substrate bottom signal line 122D located on the upper substrate bottom surface 120. The electronic signal then proceeds from the second bottom substrate through substrate via 140B to the second upper substrate bottom signal line 122D. The second upper substrate bottom signal line 122D includes a second strip line 122D, which is configured to travel under the upper cover 102 and further configured to travel over the bottom cover 106 in order to exit the bottom cavity 108 and reach the third upper cavity 104C.

[0159] Next, the electronic signal proceeds from the second upper substrate bottom signal line 122D to the fourth upper substrate through-substrate via 124D. The third upper substrate through-substrate via 124D includes a single-layer vertical feedthrough 124D.

[0160] The fourth upper board through-board via 124D electrically connects the second upper board bottom signal line 122D to the second port signal metal pad 156B located on the upper surface 114 of the upper board. The signal reaches the second port signal metal pad 156B, exits to the right side of Figure 2F, thereby exits the third sub-circuit 230, and thereby exits the H-frame device 100 as well.

[0161] The second bottom substrate through-board via 140B and the fourth top substrate through-board via 124D together form an offset vertical feedthrough transition. Although not vertically aligned, the second bottom substrate through-board via 140B and the fourth top substrate through-board via 124D together bring a signal line from the bottom substrate bottom signal line 137 located on the bottom substrate bottom surface 128 to the second port signal metal pad 156B located on the top substrate top surface 114, and then exit through the third subcircuit 230, thereby exiting the H-frame device 100.

[0162] Figure 2G shows a detailed diagram of a grounding structure 280 for a microelectronics H-frame device. The grounding structure 280 includes an upper cover grounding structure 285, a substrate grounding structure 290, and a bottom cover grounding structure 295. The upper cover grounding structure 285 connects to the substrate grounding structure 290 at the upper surface 114 of the upper substrate. The bottom cover grounding structure 295 connects to the substrate grounding structure 290 at the bottom surface 128 of the bottom substrate.

[0163] The upper cover grounding structure 285 includes an upper cover metallization 145. The upper cover metallization 145 grounds the upper cover 102. Thus, the upper cover metallization 145 provides an integral part of the overall grounding structure of the microelectronic H-frame device 100. For example, the upper cover metallization 145 includes an upper cover metallization 145 connected independently. For example, as will be described in more detail below, the upper cover metallization 145 is produced by performing gold plating on a microfabricated silicon wafer. The upper cover metallization 145 includes a metallized upper cover top surface 147. As will be described in more detail below, during the fabrication of the device (item 100 in Figure 1A), the metallized upper cover top surface 147 is bonded to a bump on the upper substrate top surface 114 to complete the bonding. The upper ground plane 116A of the upper cover is connected to the upper board ground vias 125A to 125K, and the upper board ground vias 125A to 125K are connected to the lower ground plane 122A of the upper board.

[0164] The substrate grounding structure 290 includes an upper cover upper metallization 116 including an upper cover upper grounding plane 116A, an upper substrate bottom metallization 122 including an upper substrate bottom grounding plane 122A, upper substrate grounding vias 125A to 125K, bottom substrate bottom metallization 130, bottom substrate upper metallization 135 including a bottom substrate upper grounding plane 135A, and bottom substrate grounding vias 141A to 141N. The bottom substrate upper surface 132 is bonded to the upper substrate bottom surface 120 at a third bonding interface 134. As will be described in more detail below, the bottom substrate upper surface 132 is bonded to the upper substrate bottom surface 120 using a number of bonding bumps included in both the bottom substrate upper surface 132 and the upper substrate bottom surface 120, forming a thicker metal layer.

[0165] Therefore, the upper substrate bottom metallization 122 is electrically connected and, in fact, physically connected to the bottom substrate upper metallization 135. The bottom substrate upper ground plane 135A is electrically connected to the bottom substrate ground vias 141A to 141N.

[0166] The bottom cover 106 includes a bottom cover metallization 149. Bottom substrate ground vias 141A-141N are electrically connected to the bottom cover metallization 149, completing the grounding structure. The bottom cover metallization 149 grounds the bottom cover 106. The bottom cover metallization 149 includes a metallized bottom cover top surface 151. Thus, the bottom cover metallization 149 provides an integral part of the overall grounding structure of the microelectronic H-frame device (item 100 in Figure 1A). For example, the bottom cover metallization 149 includes a bottom cover metallization 149 connected independently. For example, as will be described in more detail below, the bottom cover metallization 149 is produced by performing gold plating on a microfabricated silicon wafer. As will be described in more detail below, during the fabrication of the device (item 100 in Figure 1A), the metallized bottom cover upper surface 151 is bonded to a bump on the bottom substrate upper surface 132 to complete the bonding. The bottom cover metallization 149 is connected to the bottom substrate ground vias 141A-141N, and the upper substrate ground vias 125A-125K are connected to the upper substrate bottom ground plane 122A.

[0167] The bottom cover metallization 149 includes a metallized bottom cavity floor 150. The bottom cover cavity 108 includes a metallized bottom cavity floor 150. When the bottom cover 106 is bonded to the bottom substrate 126, the metallized bottom cavity floor 150 becomes the floor 150 of the bottom cover 106.

[0168] The bottom cover metallization 149 further includes a metallized bottom cavity wall 152. The bottom cover cavity 108 also includes a metallized bottom cavity wall 152.

[0169] The grounding structure 280 performs a role equivalent to that of a metal housing in a conventional electronics module within the microelectronic H-frame device 100. The grounding structure 280 provides reference metallization for microwaves traveling through the microelectronic H-frame device 100. The grounding structure 280 forms a highly insulating channel for circuit elements and transmission lines. The grounding structure 280 suppresses resonance within the channel and grounding region to a desired frequency. The grounding structure 280 prevents radiated leakage. The grounding structure 280 provides an electromagnetic seal similar to a Faraday cage. The grounding structure 280 provides one or more environmental seals. Preferably, the grounding structure 280 provides an environmental seal.

[0170] Figures 3A to 3F are a set of six diagrams illustrating the fabrication method for microelectronic H-frame devices.

[0171] Figures 3A and 3B show the bonding of the upper cover 102 to the upper substrate 112.

[0172] While not mandatory, it is preferable that the fabrication of a microelectronic H-frame device begins with the fabrication of the upper substrate 112 and the bottom substrate (item 126 in Figures 3C to 3D, not shown in Figures 3A to 3B). Alternatively, the fabrication of the device begins with the fabrication of the upper cover 102 and the bottom cover (item 106 in Figures 3C to 3D, not shown in Figures 3A to 3B).

[0173] For example, the upper substrate 112 is manufactured to a thickness of about 200 microns or about 8 mils. Preferably, the upper substrate 112 contains silicon carbide (SiC). Preferably, the upper substrate 112 further includes high-precision metallization features, preferably gold. For example, the metallization on the upper substrate 112 includes one or more of high-precision plated gold and vapor-deposited gold.

[0174] Figure 3A shows the upper cover 102 and upper substrate 112 just before they are joined together.

[0175] In the microelectronics H-frame device fabrication process, the upper cover 102 and the bottom cover (item 106 in Figures 3C-3D, not shown in Figures 3A-3B) are fabricated. For example, one or more of the upper cover 102 and the bottom cover (item 106 in Figures 3C-3D, not shown in Figures 3A-3B) are fabricated using deep reactive ion etching (DRIE). For example, one or more of the upper cavities (items 104A-104C in Figure 1A, not shown in this figure) are fabricated to a depth of approximately 0.635 millimeters (mm) or approximately 25 mils. For example, the bottom cavity (item 108 in Figure 1A, not shown in this figure) is fabricated to a depth of approximately 0.635 millimeters (mm) or approximately 25 mils.

[0176] Similarly, the upper substrate 112 includes the upper substrate top surface 114. Similarly, the upper substrate 112 further includes the upper substrate bottom surface 120.

[0177] The upper substrate 112 further includes a plurality of upper substrate-to-cover bonding bumps 302A and 302B on the upper substrate upper ground plane 116A. Each of the upper substrate-to-cover bonding bumps 302A and 302B includes one or more of the upper substrate upper metallization continuous bumps 158A to 158B and upper substrate upper metallization individual bumps 160A to 160P. Preferably, as shown in the figure, the upper surface 114 of the upper substrate includes a plurality of upper substrate-to-cover bonding bumps 302A and 302B. Preferably, the upper substrate-to-cover bonding bumps 302A and 302B are formed by plating the upper surface 114 of the upper substrate to a thickness of about 5 microns. The upper substrate-to-cover bonding bumps 302A and 302B can be used when bonding the upper substrate 112 to the upper cover 102. The upper substrate-cover bonding bumps 302A and 302B are compressed during bonding, thereby compensating for slight non-planarity of the upper substrate surface 114, and thereby facilitating strong gold-gold thermal compression. For example, the non-planarity may be in the range of about 1 to 3 microns for a wafer with a diameter of about 100 mm. Plating of the bonding bumps may be performed simultaneously with the metallization plating of the signal channels if both have the same thickness. Otherwise, plating of the bonding bumps is performed in a separate photolithography and plating process.

[0178] For example, the bonding bump has a diameter of about 15 microns. For example, the bonding bump has a bump height of about 5 microns. For example, the bumps are spaced about 200 microns apart. The maximum bump spacing is about 1 / 4 wavelength. Preferably, the bump spacing is about 1 / 10 wavelength.

[0179] The upper substrate 112 further includes a plurality of upper substrate-to-substrate junction bumps 310A and 310B on the bottom ground plane 122A of the upper substrate 112, the upper substrate-to-substrate junction bumps 310A and 310B being configured to facilitate bonding of the upper substrate 112 to the bottom substrate (item 126 in Figures 3C to 3D, not shown in Figure 3A). Bonding of the upper substrate 112 to the bottom substrate (item 126 in Figures 3C to 3D, not shown in Figure 3A) creates a third vertical electrical connection between the upper substrate 112 and the bottom substrate 126.

[0180] The shape of the bottom substrate upper metallization 135 connects a second vertical electrical connection inside the bottom cover 106 to a third vertical electrical connection outside the top cover 102. Using the third vertical electrical connection, the bottom substrate upper metallization 135 is electrically connected to the top substrate bottom metallization 122 outside the top cover 102. Using the first vertical electrical connection, the top substrate upper metallization 116 is electrically connected to the top substrate bottom metallization 122. For example, using the first vertical electrical connection, the top substrate upper metallization 116 is electrically connected to the top substrate bottom metallization 122 outside the top cover 102. As described above, using the third vertical connection, the top substrate bottom metallization 122 is electrically connected to the bottom substrate upper metallization 135, and using the second vertical connection, the bottom substrate upper metallization 135 is electrically connected to the bottom substrate bottom metallization 130.

[0181] For example, the bonding of the upper substrate 112 to the bottom substrate 126 forms one or more signal metallizations, each of which includes interconnections of two or more of the following: signal upper substrate upper metallization, signal through substrate vias included in the upper substrate, signal upper substrate bottom metallization, signal bottom substrate upper metallization, signal through substrate vias included in the bottom substrate, and signal bottom substrate bottom metallization.

[0182] Preferably, as shown in the figure, the upper substrate bottom surface 120 further includes a first upper substrate-to-substrate junction bump 310A and a second upper substrate-to-substrate junction bump 310B. Preferably, the upper substrate-to-substrate junction bumps 310A and 310B are formed by plating the upper substrate bottom surface 120 to a thickness of about 5 microns.

[0183] As shown in more detail below in Figures 3C to 3D, the bottom substrate (item 126 in Figures 3C to 3D, not shown in Figure 3A) further includes a number of bottom substrate-substrate bonding bumps (items 310C and 310D in Figures 3C to 3D, not shown in Figure 3A).

[0184] As shown in more detail below in Figures 3E and 3F, the bottom substrate-to-substrate joint bumps (items 310C and 310D in Figures 3C-3D, not shown in Figure 3A) are configured to mate with the upper substrate-to-substrate joint bumps 310A and 310B during bonding.

[0185] The upper substrate bottom surface 120 further includes a plurality of upper standoff bumps 320A and 320B formed on the upper substrate bottom ground plane 122A, which reduces the effective pressure on all bumps 320A, 310A, 310B, and 320B on the upper substrate bottom surface, thereby preventing these bumps from deforming during the joining of 112 and 102. Preferably, as shown, the upper substrate bottom surface 120 further includes a first upper standoff bump 320A and a second upper standoff bump 320B. Preferably, though not required, as shown, the first upper standoff bump 320A is wider than both the upper substrate-to-substrate joint bumps 310A and 310B. Preferably, though not required, as shown, the second upper standoff bump 320B is wider than both the upper substrate-to-substrate joint bumps 310A and 310B.

[0186] Preferably, though not required, the first upper standoff bump 320A is larger than both the upper substrate-to-substrate junction bumps 310A and 310B, as shown in the illustration. Preferably, though not required, the second upper standoff bump 320B is larger than the upper substrate-to-substrate junction bumps 310A and 310B, as shown in the illustration. Therefore, the upper standoff bumps 320A and 320B do not bond to each other.

[0187] Preferably, the upper standoff bumps 320A and 320B are formed by plating the bottom surface 120 of the upper substrate to a thickness of approximately 5 microns. As shown in detail in Figures 3E and 3F, the upper standoff bumps 320A and 320B are configured to prevent crushing of one or more of the upper substrate-substrate bonding bumps 310A and 310B during the bonding of the upper cover to the upper substrate. The first upper standoff bump 320A is offset from both the bottom standoff bumps 320C to 320D. Similarly, the second upper standoff bump 320B is also offset from both the bottom standoff bumps 320C to 320D.

[0188] In summary, the upper standoff bumps 320A and 320B are spaced apart from all other bumps 302A, 302B, 304A, 304B, 310A-310D, 320C, and 320D to enable bonding between the upper substrate-to-substrate junction bumps 310A-310B and the bottom substrate-to-substrate junction bumps 310C-310D, while the bottom standoff bumps 320C and 320D are spaced apart from all other bumps 302A, 302B, 304A, 304B, 310A-310D, 320A, and 320B to avoid affecting the bonding between the upper substrate-to-substrate junction bumps 310A-310B and the bottom substrate-to-substrate junction bumps 310C-310D.

[0189] Therefore, the upper standoff bumps 320A and 320B do not connect to the upper substrate-to-substrate joint bumps 310A and 310B.

[0190] Figure 3B shows the upper cover 102 after it has been bonded to the upper substrate 112 using upper substrate-cover bonding bumps 302A and 302B on the upper substrate upper ground plane 116A to create the upper assembly 330. Similarly, the upper substrate 112 includes the upper substrate top surface 114. Similarly, the upper substrate 112 further includes the upper substrate bottom surface 120. Similarly, the upper substrate 112 further includes a plurality of upper substrate-substrate bonding bumps 310A and 310B on the upper substrate bottom ground plane 122A, the upper substrate-substrate bonding bumps 310A and 310B are configured to facilitate the bonding of the upper substrate 112 to the bottom substrate (item 126 in Figures 3C to 3D, not shown in Figure 3B). The bonding of the upper substrate 112 to the bottom substrate (item 126 in Figures 3C to 3D, not shown in Figure 3A) creates a vertical electrical connection between the upper substrate 112 and the bottom substrate 126. Similarly, the upper substrate 112 further includes a plurality of upper standoff bumps 320A and 320B on the lower ground plane 122A of the upper substrate.

[0191] The reduction in size of the upper substrate-cover bumps 302A and 302B after crushing is shown. At this stage, the exemplary pressure is approximately 600 megapascals (MPa).

[0192] The upper cover 102 is bonded to the upper substrate 112. For example, the upper cover 102 and the upper substrate 112 are bonded together using a high-precision chip bonder. For example, the upper cover 102 and the upper substrate 112 are bonded together to form a strong gold-gold thermal compression bond.

[0193] Figures 3C to 3D show the bonding of the bottom cover 106 to the bottom substrate 126. For example, the bottom substrate 126 is manufactured to a thickness of about 200 microns or about 8 mils. Preferably, the bottom substrate 126 contains silicon carbide (SiC). Preferably, the bottom substrate 126 further includes high-precision metallization features. Preferably, the bottom substrate 126 further contains gold. For example, the bottom substrate 126 contains one or more of high-precision plated gold and vapor-deposited gold.

[0194] Figure 3C shows the bottom cover 106 and bottom substrate 126 before they are joined together.

[0195] Similarly, the bottom substrate 126 includes the bottom substrate bottom surface 128 and the bottom substrate top surface 132.

[0196] The bottom substrate 126 further includes a plurality of bottom substrate-to-cover bonding bumps 304A and 304B on the bottom substrate bottom contact plane 180. The upper substrate-to-cover bonding bumps 302A and 302B each include one or more of the bottom substrate bottom metallization continuous bumps 183A to 183B and bottom substrate bottom metallization individual bumps 185A to 185P. Preferably, as shown in the figure, the bottom substrate bottom surface 128 includes a plurality of bottom substrate-to-cover bonding bumps 304A and 304B. Preferably, the bottom substrate-to-cover bonding bumps 304A and 304B are formed by plating the bottom substrate bottom surface 128 to a thickness of about 5 microns. The bottom substrate-to-cover bonding bumps 304A and 304B can be used when bonding the bottom substrate 110 to the bottom cover 106. The bottom substrate-cover bonding bumps 304A and 304B are crushed during bonding, thereby compensating for slight non-planarity of the bottom substrate bottom surface 128, and thereby facilitating strong gold-gold thermal compression. For example, the non-planarity may be in the range of approximately 1 micron to approximately 3 microns.

[0197] The bottom substrate 126 further includes a plurality of bottom substrate-to-substrate bonding bumps 310C and 310D on the bottom substrate upper ground plane 135A, the bottom substrate-to-substrate bonding bumps 310C and 310D being configured to facilitate bonding of the bottom substrate 126 to the upper substrate (item 112 in Figures 3A to 3B, not shown in Figure 3C). Preferably, as shown, the top surface 132 of the bottom substrate further includes a first bottom substrate-to-substrate bonding bump 310C and a second bottom substrate-to-substrate bonding bump 310D. Preferably, the bottom substrate-to-substrate bonding bumps 310C and 310D are formed by plating the top surface 132 of the bottom substrate to a thickness of about 5 microns.

[0198] As shown in more detail below in Figures 3E and 3F, the bottom substrate-to-substrate joint bumps 310C and 310D are configured to mate with the upper substrate-to-substrate joint bumps (items 310A and 310B in Figures 3A and 3B, not shown in Figure 3C) during bonding.

[0199] The bottom substrate 126 further includes a plurality of bottom standoff bumps 320C and 320D on the bottom substrate upper ground plane 135A. Preferably, though not required, the bottom standoff bumps 320C and 320D are wider than the substrate-to-substrate joint bumps 310C and 310D, as shown in the illustration. Preferably, though not required, the bottom standoff bumps 320C and 320D are larger than the substrate-to-substrate joint bumps 310C and 310D, as shown in the illustration. Preferably, though not required, the bottom standoff bumps 320C and 320D are wider than the substrate-to-substrate joint bumps 310C and 310D, as shown in the illustration. Preferably, though not required, the bottom standoff bumps 320C and 320D are larger than the substrate-to-substrate joint bumps 310C and 310D, as shown in the illustration. Therefore, the bottom standoff bumps 320C and 320D do not join to each other.

[0200] The bottom standoff bumps 320C and 320D are configured to prevent crushing of one or more of the bottom substrate-to-substrate joint bumps 310C and 310D during the bonding of the bottom cover 106 to the bottom substrate 126. Preferably, though not required, the bottom standoff bumps 320C and 320D are larger than the bottom substrate-to-substrate joint bumps 310C and 310D, as shown in the illustration. Preferably, though not required, the bottom standoff bumps 320C and 320D are wider than the bottom substrate-to-substrate joint bumps 310C and 310D, as shown in the illustration. Therefore, the bottom standoff bumps 320C and 320D do not bond to the bottom substrate-to-substrate joint bumps 310C and 310D.

[0201] Figure 3D shows the bottom cover 106 after it has been bonded to the bottom substrate 126 using bottom substrate-cover bumps 304A and 304B on the bottom substrate bottom ground plane 180 to create the bottom assembly 340. Similarly, the bottom substrate 126 includes a bottom substrate bottom surface 128 and a bottom substrate top surface 132. Similarly, the bottom substrate 126 further includes a plurality of bottom substrate-board bonding bumps 310C and 310D on the bottom substrate upper ground plane 135A, which are configured to facilitate the bonding of the bottom substrate 126 to the upper substrate (item 112 in Figures 3A-3B, not shown in Figure 3D). Similarly, the bottom substrate 126 further includes a plurality of bottom standoff bumps 320C and 320D on the bottom substrate upper ground plane 135A.

[0202] The reduction in size of the bottom substrate-cover bumps 304A and 304B after crushing is shown. At this stage, the exemplary pressure is approximately 600 megapascals (MPa).

[0203] Preferably, the bottom standoff bumps 320C and 320D are formed by plating the top surface 132 of the bottom substrate to a thickness of about 5 microns. As shown in detail in Figures 3E and 3F, the bottom standoff bumps 320C and 320D are configured to prevent crushing of one or more of the bottom substrate-to-substrate joint bumps 310C and 310D during the bonding of the bottom cover 106 to the bottom substrate 126. The first bottom standoff bump 320C is offset from both of the upper substrate-to-substrate joint bumps (items 310A to 310B in Figures 3A to 3B, not shown in Figure 3C). Similarly, the second bottom standoff bump 320D is also offset from both of the upper substrate-to-substrate joint bumps (items 310A to 310B in Figures 3A to 3B, not shown in Figure 3C).

[0204] The first bottom standoff bump 320C is also offset from both the upper standoff bumps (items 320A to 320B in Figures 3A to 3B, not shown in Figure 3C). Similarly, the second bottom standoff bump 320D is also offset from both the upper standoff bumps (items 320A to 320B in Figures 3A to 3B, not shown in Figure 3C). Thus, during the bonding of the bottom cover 106 to the bottom substrate 126, all pressure from the bonding is distributed between the bottom standoff bumps 320C and 320D and the bottom bonding bumps 310C and 310D, preventing deformation of the bottom substrate-substrate bonding bumps 310C and 310D.

[0205] Figures 3E to 3F show the bonding of the upper substrate 112 to the bottom substrate 126. The bonding of the upper substrate 112 to the bottom substrate (item 126 in Figures 3C to 3D, not shown in Figure 3A) creates a vertical electrical connection between the upper substrate 112 and the bottom substrate 126. Similarly, the upper substrate 112 includes the upper substrate top surface 114 and the upper substrate bottom surface 120. Similarly, the bottom substrate 126 includes the bottom substrate bottom surface 128 and the bottom substrate top surface 132.

[0206] In Figures 3C to 3D, the bottom substrate-to-substrate joint bumps 310C and 310D on the upper grounding plane 135A of the bottom substrate are configured to align and engage with the upper substrate-to-substrate joint bumps 310A and 310B on the bottom grounding plane 122A of the upper substrate during joining. For example, as shown, the upper substrate-to-substrate joint bump 310C is configured to engage with the upper substrate-to-substrate joint bump 310A during joining. For example, as shown, the upper substrate-to-substrate joint bump 310D is configured to engage with the upper substrate-to-substrate joint bump 310B during joining.

[0207] The upper standoff bumps 320A and 320B on the lower grounding plane 122A of the upper substrate are configured to prevent crushing of one or more of the upper substrate-substrate bonding bumps 310A and 310B during the bonding of the upper cover 102 to the upper substrate 112.

[0208] The bonding of the upper cover 102 to the upper substrate 112 creates a vertical electrical connection between the upper substrate upper metallization 116 and the upper cover metallization 145. Similarly, the bonding of the bottom cover 106 to the bottom substrate 126 creates a vertical electrical connection between the bottom substrate upper metallization 135 and the bottom cover metallization 149.

[0209] The joints of the upper cover 102, upper substrate 112, bottom substrate 126, and bottom cover 106 form a reference metallization, which includes one or more of the following: a) upper cover metallization 145, b) upper reference upper substrate metallization, c) reference upper substrate through substrate vias included in the upper substrate, d) reference upper substrate metallization, e) upper reference bottom substrate metallization, f) reference bottom substrate through substrate vias included in the bottom substrate, g) reference bottom substrate bottom metallization, and h) bottom cover metallization 149.

[0210] The bottom standoff bumps 320C and 320D on the upper ground plane 135A of the bottom substrate are configured to prevent crushing of one or more of the bottom substrate-substrate bonding bumps 310C and 310D during the bonding of the bottom cover 106 to the bottom substrate 126. The first upper standoff bump 320A is offset from both the bottom substrate-substrate bonding bumps 310C to 310D. Similarly, the second upper standoff bump 320B is also offset from both the bottom substrate-substrate bonding bumps 310C to 310D.

[0211] The bottom standoff bump 320C is offset from both the upper board-to-board junction bumps 310A and 310B. Similarly, the bottom standoff bump 320D is also offset from both the upper board-to-board junction bumps 310A and 310B.

[0212] Therefore, during the joining of the upper assembly to the lower assembly, all pressure from the joint is on the upper substrate-to-substrate joint bumps 310A, 310B and the lower substrate-to-substrate joint bumps 310C and 310D.

[0213] Figure 3E shows the upper assembly 330 and the bottom assembly 340 just before they are joined together. Similarly, the upper assembly 330 includes the upper cover 102 and the upper substrate 112. Similarly, the bottom assembly 340 includes the bottom cover 106 and the bottom substrate 126.

[0214] Similarly, the upper assembly 330 includes an upper cover 102 and an upper substrate 112. Similarly, the upper substrate 112 includes an upper substrate top surface 114 and an upper substrate bottom surface 120. Similarly, the bottom substrate 126 includes a bottom substrate bottom surface 128 and a bottom substrate top surface 132.

[0215] Similarly, the bottom surface 120 of the upper substrate includes upper standoff bumps 320A and 320B. Similarly, the top surface 132 of the bottom substrate includes bottom substrate-to-substrate bonding bumps 310C and 310D on the bottom substrate upper ground plane 135A. Similarly, the bottom substrate 132 further includes bottom standoff bumps 320A and 320B on the top substrate bottom ground plane 122A. The upper substrate-to-substrate bonding bump (item 310A in Figure 3E, not shown in Figure 3F) is coupled with the bottom substrate-to-substrate bonding bump (item 310C in Figure 3E, not shown in Figure 3F) to form a first bonding bump 350A, the first bonding bump 350A is configured to help bond the upper substrate 112 to the bottom substrate 126. Similarly, the upper substrate-to-substrate joint bump (item 310B in Figure 3E, not shown in Figure 3F) combines with the lower substrate-to-substrate joint bump (item 310D in Figure 3E, not shown in Figure 3F) to form a second joint bump 350B, which is configured to help bond the upper substrate 112 to the lower substrate 126.

[0216] The upper ground plane of the upper substrate (item 116A in Figures 3A-3B) and the lower ground plane of the upper substrate (item 122A in Figures 3A-3B) are no longer visible after the manufacturing process shown in Figures 3A-3D is completed, and therefore the upper ground plane of the upper substrate (item 116A in Figures 3A-3B) and the lower ground plane of the upper substrate (item 122A in Figures 3A-3B) are not shown in Figures 3E-3F. Similarly, the lower ground plane of the lower substrate (item 180 in Figures 3C-3D) and the upper ground plane of the lower substrate (item 135A in Figures 3C-3D) are no longer visible after the manufacturing process shown in Figures 3A-3D is completed, and therefore the lower ground plane of the lower substrate (item 180 in Figures 3C-3D) and the upper ground plane of the lower substrate (item 135A in Figures 3C-3D) are not shown in Figures 3E-3F.

[0217] Figure 3F shows the moment immediately after the upper assembly 330 and the bottom assembly 340 are joined together, thereby creating the complete H-frame device 100.

[0218] In Figure 3F, after the bonding and crushing of the upper substrate-to-substrate joint bumps (items 310A and 310B in Figures 3A-3B and 3E) and the lower substrate-to-substrate joint bumps (items 310C and 310D in Figures 3C-3E), the upper substrate-to-substrate joint bumps (items 310A and 310B in Figures 3A-3B and 3E) and the lower substrate-to-substrate joint bumps (items 310C and 310D in Figures 3C-3E) merge to form a single bonded bump.

[0219] Figure 4 is a flowchart of Method 400 for fabricating a microelectronic H-frame device.

[0220] The order of steps in Method 400 is not restricted to the order shown in Figure 4 or described below. Some of the steps may be performed in a different order without affecting the final result.

[0221] In step 410, an upper cover usable in a microelectronic H-frame device is microfabricated. Block 410 then transfers control to block 420.

[0222] In step 420, a bottom cover usable in a microelectronic H-frame device is microfabricated. Block 420 then transfers control to block 430.

[0223] In step 430, the top surface of an upper substrate usable in a microelectronic H-frame device and the bottom surface of a bottom substrate usable in a microelectronic H-frame device are fabricated together on the front surface of the wafer, the top surface of the upper substrate includes upper substrate metallization, and the bottom surface of the bottom substrate includes bottom surface metallization. For example, the upper substrate is pattern plated and via etched. For example, the bottom substrate is pattern plated and via etched. Block 430 then transfers control to block 435.

[0224] In step 435, an intermediate substrate metallization is performed. Then, block 435 transfers control to block 440.

[0225] In step 440, the upper substrate is bonded to the upper cover. Next, block 440 transfers control to block 450.

[0226] In step 450, the bottom substrate is bonded to the bottom cover. Next, block 450 transfers control to block 460.

[0227] In step 460, the upper substrate is bonded to the upper surface of the intermediate substrate metallization, and the bottom substrate is bonded to the bottom surface of the intermediate substrate metallization, thereby creating a vertical electrical connection between the upper and bottom substrates. Block 460 then completes the process.

[0228] The fabrication process used for H-frame SiC core chips and silicon sub-cover chips is key to achieving important additional functionality.

[0229] The manufacturing process and the concept of the present invention enable a wide range of functions through the use of geometric shapes within the silicon subcover, such as alcoves, walls, islands, peninsulas, and enclosed chambers.

[0230] The advantages of the present invention include the superior dimensional accuracy achieved by microfabrication, as well as the surface smoothness of the recesses and internal surfaces within the enclosure. Additional advantages include the ability to manufacture devices with highly repeatable characteristics and performance and low electrical loss. Conventional enclosures made by conventional mechanical manufacturing techniques such as machining, electrical discharge machining (EDM), and electroforming have tolerances in the range of 0.2 mil to 1 mil, which is one to two orders of magnitude greater than the precision provided by the semiconductor technology described herein.

[0231] For example, the micro-machined inner surface within the exemplary enclosure has a peak-to-trough roughness of less than 2 μm, or 1.3 μm, compared to a conventional machined copper housing with a peak-to-trough roughness of approximately 9.4 μm. Thus, embodiments of the present invention provide a smoothness improvement of more than seven times.

[0232] While conductive epoxy paste can be used to achieve silicon and SiC assembly, conductive paste offers a technique that is more difficult to control in terms of leachate, thickness variations, voids, poor electrical contact, and placement accuracy.

[0233] Regarding vias, 100-micron diameter metallized through-substrate vias are used to form a highly insulating electromagnetic via fence, connecting ground metallizations on opposing surfaces of the substrate. Simulations show that these vias can provide high insulation of up to 40 decibels (dB) at 20 GHz when spaced at a minimum pitch of 400 microns (μm). The via fence and gold-plated silicon enclosure walls allow individual elements of the two isolated circuits to be effectively placed in their own electromagnetically shielded cavities, minimizing cross-coupling. Through-wafer vias facilitate substantially continuous ground continuity for RF return current between the top and bottom covers, enabling post-fabrication probe testing of the filters.

[0234] A further advantage of embodiments of the present invention is that not only can channels be insulated using “walls” formed by gold-plated silicon enclosure walls and via fences, but individual elements can also be insulated using them. According to embodiments of the present invention, electrical isolation between individual elements eliminates undesirable cross-coupling found in prior art open faceprint designs, thus enabling rapid development and compact layouts.

[0235] Further advantages of embodiments of the present invention are that they are stable across temperature, provide excellent manufacturing reproducibility, are reliable under mechanical stress, offer low costs in mass production, and are completely sealed to prevent foreign object debris (FOD).

[0236] Another advantage of embodiments of the present invention is that they provide twice the "deep" compaction compared to the single-sided prior art, effectively halving the circuit area.

[0237] An additional advantage of embodiments of the present invention is that, compared to prior art techniques that use additional substrates, passive components can now be printed directly onto the substrate. Another further advantage of embodiments of the present invention is the elimination of the need for subcovers required in prior art planar filters, thereby facilitating compaction in the direction perpendicular to the central web, i.e., the "Z" direction.

[0238] A further additional advantage of embodiments of the present invention is the reduction of compaction in the housing floor area, i.e., in the "XY" plane. Embodiments of the present invention eliminate one or more of the need to ensure headroom for the installation of component substrates and the need to ensure headroom for the reworking of component substrates. Furthermore, embodiments of the present invention enable the easy creation of compact channelizations. Embodiments of the present invention provide a device that is 100 times more compact than a prior art device having a central web, which includes many separate components including glass beads, vertical pins, ribbon bonds, a central web, plugs, and one or more different layers. In striking contrast, embodiments of the present invention employ a simple single four-layer design including a top cover, top substrate, bottom substrate, and bottom cover, thereby achieving an equivalent topology by a novel and completely different methodology.

[0239] A further advantage of the embodiments of the present invention is that one or more of the device size and / or device weight are reduced by the use of semiconductors in one or more of the top cover and bottom cover.

[0240] A further additional advantage of embodiments of the present invention is that one or more of the microfabrication and plating of the top and bottom covers enable one or more of the following: precise cavity compaction, RF isolation, and easy mass production. For example, walls having a thickness of about 130 microns are possible in the design of the microstrip.

[0241] Another advantage of embodiments of the present invention is that the thermocompression used to create a homogeneous gold-gold bond allows for one or more of an extremely strong bond and high-precision alignment. A further advantage of embodiments of the present invention is that the high-precision alignment allows for one or more of automated H-frame construction and environmental protection without requiring manual assembly.

[0242] Another advantage of embodiments of the present invention is that one or more of the machined bumps on the cover and the bumps created on the substrate generate strong gold-gold thermal compression.

[0243] The use of rigid substrates and high-precision microelectronic plating for signal paths enables more precise plating techniques and consistent mass production of vias for interconnects. Furthermore, the use of transparent substrates can be selectively employed. This can provide increased interlayer alignment during bonding for consistent via alignment for reliable signal transmission. Additionally, the use of through-wafer vias can be selectively employed, enabling mass production of highly consistent interconnects for both signal and ground between layers of H-frames, thereby reducing the need for manual assembly.

[0244] Embodiments of the present invention provide the ability to create walls with any contour with high precision and reproducibility.

[0245] Another advantage provided by embodiments of the present invention is that additional compaction is provided by replacing the metal central web in a conventional H-frame with a conceptual three-layer printed circuit board (PCB). Due to condensed routing and one or more of the higher component counts, embodiments of the present invention provide greater compaction.

[0246] A further advantage of embodiments of the present invention is the elimination of the feedthrough transitions of the prior art, which require many intricate components and complex assembly procedures, while incurring the risk of one or more of large manufacturing variations and field leakage. In stark contrast, embodiments of the present invention enable the manufacture of both chips in a single manufacturing process.

[0247] Further advantages of embodiments of the present invention include that they enable the design of RF transitions with intricate features without additional cost for optimal performance against return loss and insertion loss, and in particular, that they provide nearly complete isolation from other areas under the same cover.

[0248] Further advantages of embodiments of the present invention include low insertion loss and high return loss. As shown by graph 250 in Figure 2D, the insertion loss 254 is less than approximately 0.2 dB across the entire frequency band 258. Also as shown by graph 250 in Figure 2D, the return loss 256 is greater than approximately 20 dB across the entire frequency band 258.

[0249] A further advantage provided by embodiments of the present invention is that transitions at multiple locations can be formed simultaneously within the substrate.

[0250] The disclosed microelectronics H-frame device offers several clear advantages. This device provides a rigid substrate with a much better defined geometry than the more flexible, shrink-prone, conventional printed circuit board layers and conventional low-temperature co-fired ceramic (LTCC) layers. The better defined geometric shape implies better controlled RF characteristics, such as line impedance and losses, and therefore more predictable RF performance.

[0251] A further advantage of embodiments of the present invention is that the size of the feedthrough transition, including the end walls and notches in the ground plane, is about 30 mils in a stack of two 8 mil thick substrates, compared to about 102 mils, which is a typical dimension of a conventional machined H-frame housing of the prior art. A further advantage of embodiments of the present invention is that it provides more than a tenfold saving in the transition area. Another advantage provided by embodiments of the present invention is that it provides a feedthrough transition without the need to create additional parts or add the additional manufacturing steps required to create them. The main difference between embodiments of the present invention and conventional machined H-frame devices of the prior art is that embodiments of the present invention provide a compact and cost-effective vertical feedthrough.

[0252] An additional advantage of embodiments of the present invention is to provide three-dimensional field channelization and isolation. Embodiments of the present invention allow circuit elements to be placed in close proximity, but with a wall in between, which eliminates potential coupling and thus results in a more compact layout. Thus, another advantage of embodiments of the present invention is the compaction of the circuit layout.

[0253] Microelectronics H-frame devices provide environmentally and electromagnetically sealed circuit packages that offer one or more of the following: accuracy, precision, and high repeatability.

[0254] A further advantage of the embodiments of the present invention is that the etched vias provide one or more of a smaller via diameter and a smaller via pitch. Furthermore, according to the embodiments of the present invention, all vias in a given substrate, which may number in the tens of thousands, are fabricated simultaneously, promoting one or more of uniformity, consistency, and quality.

[0255] Embodiments of the present invention provide high precision when patterning metallization. Typical line width error of embodiments of the present invention is about 1 micron compared to prior art techniques, which typically have a typical line width error at least 10 times higher.

[0256] Embodiments of the present invention include standalone packages. Embodiments of the present invention include higher-level assemblies that can directly produce other components or to join other components.

[0257] The disclosed new methods and devices for constructing electronic modules facilitate an order of magnitude reduction in size, weight, and power (SWAP). The disclosed new methods and devices also provide the RF integrity inherent in high-quality RF products.

[0258] This paper describes dramatically different electronic device systems that feature deep compaction, microelectronic precision, and unprecedented RF routing flexibility and manufacturing repeatability.

[0259] Another advantage of the embodiments of the present invention is the versatility of the available transmission line styles. The disclosed microelectronics H-frame devices allow RF transmission lines to be constructed using one or more of microstrips, coplanar waveguides (CPWs), and strip lines. This flexibility allows designers to select the appropriate line type in different domains for optimal RF performance.

[0260] Etched vias offer additional advantages compared to punched or perforated vias in other technologies. Etching reduces both the via diameter and via pitch, allowing all vias in a substrate—sometimes tens of thousands—to be manufactured simultaneously, resulting in more uniform or consistent quality.

[0261] A further advantage of the embodiments of the present invention is that joining two wafers in a stack essentially crushes the central web, which typically has a thickness in the range of 40 to 160 mils in conventional machined H-frames, into a thin metal layer that may be as thin as a few microns. The change from a finite thickness to a central web of "0" thickness eliminates the need for conventional feedthrough. More importantly, the crushing of the central web changes the design paradigm to the use of planar technology, in which intricate features realized in metallization patterned for optimal RF performance are now possible without additional cost.

[0262] A further advantage of the embodiments of the present invention is the ease of assembly compared to the prior art. According to the embodiments of the present invention, joining two covers and two wafers in a stack completes the microelectronic H-frame assembly. This results in significant cost savings compared to conventional machined H-frames, where the metal housing must first be machined and plated, then multiple substrates and components must be mounted, and then sub-covers must be installed.

[0263] Another advantage provided by embodiments of the present invention is a versatile vertical wall. The cover not only completely seals the package to prevent foreign object debris (FOD), but also provides a vertical wall as needed. For example, the vertical wall provides channelization of the RF path, demodulation of the cavity for stability, and good insulation in vertical transition design.

[0264] Vertical feedthroughs within a microelectronic H-frame (Figure 2E) include one or more vertical metal walls provided by patterned metallization on the substrate, through-substrate vias, and a microfabricated cover. The transitions are designed with intricate features at no additional cost for optimal performance against return and insertion losses, particularly with near-complete isolation from other areas under the same cover.

[0265] A further advantage of the embodiments of the present invention is that the distance between the escape line and the spiral turn is increased from about 3 microns in a typical prior art air bridge to about 200 microns in wafer thickness. The increased spacing reduces capacitive coupling, thereby helping to reduce performance sensitivity to manufacturing variations.

[0266] While the representative embodiments described above have been explained using some components in exemplary configurations, it will be understood by those skilled in the art that other representative embodiments may be implemented using different configurations and / or different components. For example, it will be understood by those skilled in the art that the order of some steps and some components can be changed without substantially impairing the function of the present invention. It will further be understood by those skilled in the art that the number of variations of embodiments of the present invention is virtually infinite. For example, a stack including three or more wafers may be used. For example, if three wafers are used, there will be four metal layers, four different vertical RF transitions, and five-sided sealing covers and two metal layers for escaping from inputs and outputs. For example, the designations of “top” and “bottom” are optional. Such designations can be reversed or otherwise modified without substantially altering the present invention. For example, instead of being plated on the substrate, the bonding bumps may be plated on one or more of the top and bottom covers.

[0267] For example, the number of upper board signal vias is arbitrary and not limited to the specific example provided. For example, the number of upper board ground vias is arbitrary and not limited to the specific example provided. For example, the number of bottom board signal vias is arbitrary and not limited to the specific example provided. For example, the number of bottom board ground vias is arbitrary and not limited to the specific example provided.

[0268] The representative embodiments and subject matter described in detail herein are presented as examples and illustrations, not as limitations. Those skilled in the art will understand that various modifications to the forms and details of the described embodiments may be made to result in equivalent embodiments that remain within the scope of the invention. Therefore, the subject matter in the above description is intended to be illustrative and not as limiting.

Claims

1. A stack of two or more substrates, wherein the stack of substrates includes an upper substrate and a bottom substrate, the bonding of the upper substrate to the bottom substrate creates a vertical electrical connection between the upper substrate and the bottom substrate, the upper surface of the upper substrate includes upper substrate metallization, and the bottom surface of the bottom substrate includes bottom substrate metallization. Metallization of an intermediate substrate located between the upper substrate and the lower substrate, A top cover is bonded to the upper side of the stack of the substrate and is micro-machined to include one or more top cover cavities, The substrate includes a bottom cover bonded to the bottom side of the stack and micro-machined to include one or more bottom cover cavities, A microelectronic H-frame device in which the one or more upper cover cavities and the one or more bottom cover cavities each have metallized walls and include a configuration that converts the direction of the electric field from vertical to horizontal, and is configured to gradually convert the direction of the electric field from vertical to horizontal to suppress reflection.

2. The device according to claim 1, wherein the stack of substrates includes both an upper substrate and a bottom substrate.

3. The device according to claim 2, wherein the upper surface of the upper substrate and the bottom surface of the bottom substrate are fabricated together on the front surface of the wafer.

4. The device according to claim 2, further comprising metallization located between the upper substrate and the bottom substrate.

5. The upper surface of the upper substrate includes an upper substrate metallization, the bottom surface of the upper substrate includes an upper substrate metallization, the upper substrate further includes a metallized upper substrate through-substrate via connecting the upper substrate metallization and the upper substrate metallization, and the metallized upper substrate through-substrate via provides a first vertical electrical connection between the upper substrate metallization and the upper substrate metallization. The device according to claim 2, which forms a connection.

6. The device according to claim 5, wherein the bottom surface of the bottom substrate includes a bottom substrate bottom metallization, the top surface of the bottom substrate includes a bottom substrate upper metallization, the bottom substrate further includes a metallized bottom substrate through substrate via connecting the bottom substrate upper metallization and the bottom substrate bottom metallization, the metallized bottom substrate through substrate via forming a second vertical electrical connection between the bottom substrate upper metallization and the bottom substrate bottom metallization.

7. The device according to claim 6, wherein the bonding of the upper substrate to the lower substrate creates a third vertical electrical connection between the lower metallization of the upper substrate and the upper metallization of the lower substrate.

8. The device according to claim 7, wherein the upper metallization of the upper substrate is electrically connected to the lower metallization of the upper substrate on the outside of the upper cover using the first vertical electrical connection, the shape of the lower metallization of the upper substrate connects the first vertical electrical connection on the outside of the upper cover to the first vertical electrical connection on the inside of the upper cover, and the lower metallization of the upper substrate is electrically connected to the upper metallization of the upper substrate on the inside of the upper cover using the first vertical electrical connection.

9. The device according to claim 7, wherein the bottom bottom metallization of the bottom substrate is electrically connected to the top bottom metallization of the bottom substrate inside the bottom cover using the second vertical electrical connection, the shape of the top bottom metallization of the bottom substrate connects the second vertical electrical connection inside the bottom cover to the third vertical electrical connection outside the top cover, the top bottom metallization of the bottom substrate is electrically connected to the bottom top metallization of the top substrate outside the top cover using the third vertical electrical connection, and the bottom top metallization of the top substrate is electrically connected to the top top metallization of the top substrate outside the top cover using the first vertical electrical connection.

10. The device according to claim 7, wherein the upper metallization of the upper substrate is electrically connected to the lower metallization of the upper substrate using the first vertical electrical connection, the lower metallization of the upper substrate is electrically connected to the upper metallization of the lower substrate using the third vertical electrical connection, and the upper metallization of the lower substrate is electrically connected to the lower metallization of the lower substrate using the second vertical electrical connection.

11. The bonding of the upper substrate to the lower substrate forms one or more signal metallizations, and each of the signal metallizations is a. Metallization of the upper part of the signal substrate, b. Signal-through substrate vias included in the upper substrate, c. Metallization of the bottom of the upper circuit board, d. Metallization of the upper part of the signal base substrate, e. Signal-through substrate vias included in the bottom substrate, and f. Metallization of the bottom of the signal substrate The device according to claim 7, comprising two or more interconnections among them.

12. The device according to claim 7, wherein the upper cover includes upper cover metallization.

13. The device according to claim 12, wherein the bottom cover includes bottom cover metallization.

14. The device according to claim 13, wherein the bonding of the upper cover to the upper substrate creates a first vertical electrical connection between the upper metallization of the upper substrate and the metallization of the upper cover, and the bonding of the bottom cover to the bottom substrate creates a second vertical electrical connection between the upper metallization of the bottom substrate and the metallization of the bottom cover.

15. The bonding of the upper cover, the upper substrate, the bottom substrate, and the bottom cover forms a reference metallization, and the reference metallization is a. The above-mentioned upper cover metallization, b. Metallization of the upper part of the reference upper substrate, c. Reference upper substrate through substrate via included in the upper substrate, d. Metallization of the bottom of the reference upper substrate, e. Metallization of the upper part of the reference bottom substrate, f. Reference bottom substrate through substrate vias included in the bottom substrate, g. Metallization of the base of the reference substrate, and h. Metallization of the bottom cover The device according to claim 14, comprising one or more of the above.

16. A method for fabricating microelectronic H-frame devices, The upper cover usable in the above device is micro-machined to include one or more upper cover cavities, The bottom cover usable in the device is micro-machined to include one or more bottom cover cavities, Forming a metallized wall in each of the one or more upper cover cavities and the one or more bottom cover cavities, The process involves fabricating, together on the front surface of a wafer, the upper surface of an upper substrate usable in the device and the bottom surface of a bottom substrate usable in the device, wherein the upper surface of the upper substrate includes upper substrate metallization and the bottom surface of the bottom substrate includes bottom surface metallization. To fabricate an intermediate substrate metallization, The upper substrate is joined to the upper cover, The bottom substrate is joined to the bottom cover, This includes bonding the upper substrate to the upper surface of the intermediate substrate metallization, bonding the bottom substrate to the bottom surface of the intermediate substrate metallization, thereby creating a vertical electrical connection between the upper substrate and the bottom substrate. A method wherein the one or more upper cover cavities and the one or more bottom cover cavities include a configuration that converts the direction of the electric field from vertical to horizontal, and is configured to gradually convert the direction of the electric field from vertical to horizontal to suppress reflection.

17. The method according to claim 16, wherein the manufacturing step includes manufacturing an upper substrate-cover bonding bump that can be used when bonding the upper substrate to the upper cover.

18. The method according to claim 17, wherein the upper substrate-cover bonding bump is configured to be crushed during bonding, thereby compensating for the slight non-planarity of the upper substrate, and thereby facilitating strong gold-gold thermal compression.

19. The method according to claim 16, wherein the manufacturing step includes manufacturing a bottom substrate-cover bonding bump that can be used when bonding the bottom substrate to the bottom cover.

20. The method according to claim 19, wherein the bottom substrate-cover bonding bump is configured to be crushed during bonding, thereby compensating for the slight non-planarity of the bottom substrate, and thereby facilitating strong gold-gold thermal compression.

21. The aforementioned manufacturing process is: The invention relates to the manufacture of an upper substrate including an upper substrate-substrate bonding bump and an upper standoff bump, and a lower substrate including a lower substrate-substrate bonding bump and a lower standoff bump, wherein the upper standoff bump is configured to prevent crushing of the upper substrate-substrate bonding bump during bonding of the upper cover to the upper substrate, the lower standoff bump is configured to prevent crushing of the lower substrate-substrate bonding bump during bonding of the lower cover to the lower substrate, the upper standoff bump is offset from the lower standoff bump, and the upper standoff bump is offset from the lower substrate - To manufacture such that the bottom standoff bump is offset from the substrate bonding bump, the bottom standoff bump is offset from the upper standoff bump, the bottom standoff bump is offset from the upper substrate-to-substrate bonding bump, the upper standoff bump is spaced apart from all other bumps so as not to affect the bonding between the upper substrate-to-substrate bonding bump and the bottom substrate-to-substrate bonding bump, and the bottom standoff bump is spaced apart from all other bumps so as not to affect the bonding between the upper substrate-to-substrate bonding bump and the bottom substrate-to-substrate bonding bump. The method according to claim 16, further comprising:

22. The method according to claim 16, wherein the step of microfabricating the upper cover includes creating an upper substrate-cover bonding bump, and the step of microfabricating the bottom cover includes creating a bottom substrate-cover bonding bump.

23. A stack of two or more substrates, wherein the stack of substrates includes an upper substrate and a bottom substrate, the upper surface of the upper substrate and the bottom surface of the bottom substrate are fabricated together on the front surface of a wafer, at least one of the upper substrate and the bottom substrate includes at least one of a transmission line, a filter, a power splitter, a coupler, and another electronic component, the bonding of the upper substrate to the bottom substrate creates a vertical electrical connection between the upper substrate and the bottom substrate, the upper surface of the upper substrate includes upper substrate metallization, and the bottom surface of the bottom substrate includes bottom substrate metallization. Metallization of an intermediate substrate located between the upper substrate and the lower substrate, A microfabricated upper cover bonded to the upper side of the stack of the substrate, comprising one or more upper cover cavities, wherein the upper cover includes upper cover metallization, A bottom cover bonded to the bottom side of the stack of the substrate, which is microfabricated to include one or more bottom cover cavities, wherein the bottom cover includes bottom cover metallization, and the microfabricated bottom cover includes A microelectronic H-frame device in which the one or more upper cover cavities and the one or more bottom cover cavities each have metallized walls and include a configuration that converts the direction of the electric field from vertical to horizontal, and is configured to gradually convert the direction of the electric field from vertical to horizontal to suppress reflection.

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