Drive circuit

Abstract

To provide a driving circuit in which power consumption is suppressed with a small-scale configuration, and surge voltage is suppressed when a short-circuit occurs in a power semiconductor element.SOLUTION: A gate driver IC 101 includes: a plurality of switching elements that drive an IGBT 201; a comparator 31 that, when a potential of a shunt register 202 connected between an emitter terminal of the IGBT 201 and the ground is equal to or higher than Vth1, outputs an alarm signal; a delay circuit 33 that outputs a trigger signal after output of the alarm signal is started; and a control unit 34 that controls the on / off of the plurality of switching elements. An upper-arm switching element includes PMOSs 11 and 12 connected to the same voltage source 51. A lower-arm switching element includes NMOSs 21 and 22. The control unit 34 turns on the PMOS 12 when the alarm signal is output, and turns on the NMOS 22 when the trigger signal is output.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a drive circuit for a power semiconductor device.

Background Art

[0002] Patent Document 1 discloses a drive circuit that suppresses the surge voltage during soft shutdown of an IGBT (Insulated Gate Bipolar Transistor) by conducting a switching element in the lower arm connected to the gate of the IGBT and suppressing the current flowing to the gate of the IGBT when a short circuit occurs in the IGBT.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the drive circuit of Patent Document 1, a switching element in the lower arm is required to reduce the current flowing to the gate of the IGBT. In addition, there is a problem that power consumption increases by short - circuiting the switching element in the upper arm and the switching element in the lower arm.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to provide a drive circuit that suppresses power consumption with a small - scale configuration and suppresses the surge voltage when a short circuit occurs in a power semiconductor device.

Means for Solving the Problems

[0006] The drive circuit of the present disclosure is Output terminal connected to the control terminal of the power semiconductor element,Multiple switching elements that drive power semiconductor elements, an overcurrent detector that outputs an alarm signal when the potential of a shunt resistor connected between the main terminal of the power semiconductor element and ground is greater than or equal to a predetermined first threshold, a trigger signal generation circuit that outputs a trigger signal after the overcurrent detector starts outputting an alarm signal, and multiple switching elements Continuity and Non-conductive It comprises a control unit that controls the switching elements, and a plurality of switching elements, including switching elements in the upper arm and switching elements in the lower arm, and the switching elements in the upper arm are powered by the same power supply. And in parallel between the output terminal It includes a first upper switching element and a second upper switching element connected to the lower arm, and the switching element of the lower arm is , connected in parallel between the output terminal and ground The control unit includes a first lower switching element and a second lower switching element, and when an alarm signal is output, 、 The second upper switching element Non-conductive When the trigger signal is output... While keeping the first upper switching element and the second upper switching element in a non-conductive state The second lower switching element Continuity to This lowers the potential of the output terminal towards ground. ru. [Effects of the Invention]

[0007] According to the drive circuit of this disclosure, the lower arm can be configured with a first lower-stage switching element for main interruption and a second lower-stage switching element for soft interruption, thereby reducing the circuit size. Furthermore, since the switching elements of the upper arm and the lower arm do not short-circuit, power consumption can be suppressed, surge voltage can be suppressed, and the reliability of the protection function in the event of a short circuit can be improved. In addition, since multiple drive power supplies are not required for the switching elements of the upper arm, the circuit size can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] This is a circuit diagram of the drive circuit according to Embodiment 1. [Figure 2] This diagram shows the operation of the drive circuit according to Embodiment 1. [Figure 3]Circuit diagram of the drive circuit according to Embodiment 2. [Figure 4] Diagram showing the operation of the drive circuit according to Embodiment 2. [Figure 5] Circuit diagram of the drive circuit according to Embodiment 3. [Figure 6] Diagram showing the operation of the drive circuit according to Embodiment 3. [Figure 7] Circuit diagram of the drive circuit according to Embodiment 4. [Figure 8] Diagram showing the operation of the drive circuit according to Embodiment 4. [Figure 9] Circuit diagram of the drive circuit according to Embodiment 5. [Figure 10] Diagram showing the operation of the drive circuit according to Embodiment 5. [Figure 11] Circuit diagram of the drive circuit according to Embodiment 6. [Figure 12] Diagram showing the operation of the drive circuit according to Embodiment 6. [Figure 13] Circuit diagram of the drive circuit according to Embodiment 7. [Figure 14] Diagram showing the normal operation of the drive circuit according to Embodiment 7. [Figure 15] Diagram showing the operation of the drive circuit when a short circuit occurs according to Embodiment 7. [Figure 16] Circuit diagram of the drive circuit according to Embodiment 8. [Figure 17] Diagram showing the operation of the drive circuit according to Embodiment 8.

Modes for Carrying Out the Invention

[0009] <A. Embodiment 1> <A-1. Configuration> FIG. 1 is a circuit diagram of a gate driver IC (Integrated Circuit) 101 which is a driving circuit according to Embodiment 1. The gate driver IC 101 drives an IGBT 201 which is a power semiconductor device. The gate driver IC 101 includes an input terminal IN, an output terminal OUT, and a short-circuit detection terminal SC. The output terminal OUT is connected to a gate terminal which is a control terminal of the IGBT 201. An emitter terminal which is a main terminal of the IGBT 201 is connected to the ground via a shunt resistor 202. A short-circuit detection terminal SC is connected between the emitter terminal of the IGBT 201 and the shunt resistor 202.

[0010] The gate driver IC 101 includes PMOS (P-channel Metal Oxide Semiconductor) 11 and PMOS 12 as switching elements in the upper stage, that is, the upper arm, and NMOS (N-channel Metal Oxide Semiconductor) 21 and NMOS 22 as switching elements in the lower stage, that is, the lower arm. PMOS 11 and PMOS 12 are also referred to as the first upper-stage switching element and the second upper-stage switching element, and NMOS 21 and NMOS 22 are also referred to as the first lower-stage switching element and the second lower-stage switching element.

[0011] Source terminals of PMOS 11 and PMOS 12 are connected to the same voltage source 51, and drain terminals are connected to the gate terminal of the IGBT 201 via the output terminal OUT. Gate terminals of PMOS 11 and PMOS 12 are connected to a control unit 34. The voltage source 51 supplies a voltage VCC1. Source terminals of NMOS 21 and NMOS 22 are connected to the ground, and drain terminals are connected to the gate terminal of the IGBT 201 via the output terminal OUT. Gate terminals of NMOS 21 and NMOS 22 are connected to the control unit 34.

[0012] Furthermore, the gate driver IC 101 includes a comparator 31, a variable DC power supply 32, a delay circuit 33, and a control unit 34. The + input terminal of the comparator 31 is connected to the short-circuit detection terminal SC, and the - input terminal is connected to ground via the variable DC power supply 32. The variable DC power supply 32 applies a threshold voltage Vth1 to the - input terminal of the comparator 31. When an overcurrent occurs in the IGBT 201, the voltage drop across the shunt resistor 202 increases, and the emitter voltage applied to the + input terminal of the comparator 31 becomes greater than or equal to the threshold voltage Vth1. At this time, the output of the comparator 31 changes from Low to High. The High-level signal of the comparator 31 is called the alarm signal. In this way, the comparator 31 functions as an overcurrent detector that determines that an overcurrent has occurred in the IGBT 201 when the potential of the shunt resistor is greater than or equal to the threshold voltage Vth1 and outputs an alarm signal.

[0013] The output terminal of comparator 31 is connected to delay circuit 33 and control unit 34. Point A is the point between comparator 31 and delay circuit 33 and control unit 34. When an alarm signal is input, control unit 34 turns off PMOS 12, slowing down the rise in the gate voltage of IGBT 201.

[0014] The delay circuit 33 switches its output from Low to High when the alarm signal input from the comparator 31 continues for a predetermined duration T1. The High-level signal from the delay circuit 33 is called the trigger signal. In this way, the delay circuit 33 functions as a trigger signal generation circuit that outputs the trigger signal after the alarm signal output from the comparator 31 begins.

[0015] The output of the delay circuit 33 is input to the control unit 34. Let point B be the point between the delay circuit 33 and the control unit 34. The control unit 34 is connected to the input terminal IN. When the control unit 34 receives a trigger signal from the delay circuit 33, it turns off the PMOS 11, i.e., makes it non-conductive, and turns on the NMOS 22, i.e., makes it conductive, thereby soft-shutting off the IGBT 201. In this way, the trigger signal functions as a trigger for soft-shutting off.

[0016] <A-2. Operation> FIG. 2 is a diagram showing the operation of the gate driver IC 101. First, when the applied voltage to the input terminal IN is at the Low level, the control unit 34 turns off the PMOSs 11 and 12 and turns on the NMOSs 21 and 22. As a result, a Low-level voltage is applied to the output terminal OUT via the NMOSs 21 and 22, and the IGBT 201 turns off.

[0017] When a High-level voltage is applied to the input terminal IN, the control unit 34 turns on the PMOSs 11 and 12 and turns off the NMOSs 21 and 22. As a result, a current flows from the PMOSs 11 and 12 to the output terminal OUT, and the voltage of the output terminal OUT rises. Along with this, the emitter current of the IGBT 201 also increases, and the voltage drop across both ends of the shunt resistor 202 increases, so that the voltage of the short-circuit detection terminal SC also rises.

[0018] When the voltage of the short-circuit detection terminal SC becomes equal to or higher than the threshold voltage Vth1, the comparator 31 outputs an alarm signal to the delay circuit 33 and the control unit 34. The control unit 34 that has received the alarm signal turns off the PMOS 12. As a result, the rise of the gate voltage of the IGBT 201 becomes gentle.

[0019] After that, when the output of the alarm signal by the comparator 31 continues for a predetermined time T1, the delay circuit 33 outputs an alarm continuation signal to the control unit 34. The control unit 34 that has received the alarm continuation signal turns off the PMOS 11 and turns on the NMOS 22. As a result, the gate voltage of the IGBT 201 drops, and along with this, the voltage of the short-circuit detection terminal SC also drops. This is referred to as the soft shutdown of the IGBT 201.

[0020] <A-3. Modified Example> In the above description, the power semiconductor device driven by the gate driver IC101 is an IGBT. However, the power semiconductor device may be a FET composed of a wide bandgap device capable of high-speed driving, such as a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a GaN-FET. Since these devices can be driven at a higher speed compared to an IGBT, there is a risk that the surge voltage during a short circuit may become even larger. Therefore, the effect of surge suppression by the gate driver IC101 is more effectively exerted. This also applies to other embodiments described below.

[0021] <A-4. Effect> The gate driver IC101 includes a plurality of switching elements that drive an IGBT 201, which is a power semiconductor device, a comparator 31 as an overcurrent detector, a delay circuit 33 as a trigger signal generation circuit that outputs a trigger signal after the output start of an alarm signal by the comparator 31, and a control unit 34 that controls the on and off of the plurality of switching elements. The comparator 31 outputs an alarm signal when the potential of a shunt resistor 202 connected between the main terminals of the IGBT 201 and the ground is equal to or higher than a predetermined threshold voltage Vth1. The plurality of switching elements include an upper-arm switching element and a lower-arm switching element. The upper-arm switching element includes a PMOS 11, which is a first upper-stage switching element, and a PMOS 12, which is a second upper-stage switching element, both connected to the same voltage source 51. The lower-arm switching element includes an NMOS 21, which is a first lower-stage switching element, and an NMOS 22, which is a second lower-stage switching element. When an alarm signal is output, the control unit 34 turns off the PMOS 12, and when a trigger signal is output, the control unit 34 turns on the NMOS 22.

[0022] According to the above configuration, since the lower arm of the gate driver IC101 is composed of the NMOS 21 for main interruption and the NMOS 22 for soft interruption, the circuit scale can be reduced. Also, since the upper-stage switching elements PMOS 11 and 12 and the lower-stage switching elements NMOS 21 and 22 do not short-circuit, while suppressing power consumption, surge voltage can be suppressed and the reliability of the protection function at the time of short-circuit occurrence can be enhanced. Further, since a plurality of drive power sources are not required for the switching elements of the upper arm, the circuit scale can be reduced.

[0023] <B. Embodiment 2> <B-1. Configuration> FIG. 3 is a circuit diagram of a gate driver IC102 which is a drive circuit according to Embodiment 2. The gate driver IC102 is different from the gate driver IC101 according to Embodiment 1 only in that the gate terminals of PMOS 11 and PMOS 12 are connected to each other.

[0024] <B-2. Operation> FIG. 4 is a diagram showing the operation of the gate driver ICs is02. In Embodiment 1, when the comparator 31 detects an overcurrent, PMOS 11 remains on and only PMOS 12 turns off. However, in this embodiment, when the comparator 31 detects an overcurrent, both PMOS 11 and 12 turn off. Other operations are the same as those in Embodiment 1.

[0025] <B-3. Effects> According to the gate driver IC102 of this embodiment, since the gate terminals of PMOS 11 and PMOS 12 are connected to each other and PMOS 11 and 12 turn off at the time of overcurrent detection, the current supply to the IGBT 201 is cut off at the time of overcurrent detection. Therefore, the power consumption of the gate driver IC102 is suppressed. Also, since the current supply to the IGBT 201 is cut off at the time of overcurrent detection, the rise of the gate voltage of the IGBT 201 is suppressed, so that the gate voltage can be quickly dropped at the time of soft interruption.

[0026] <C. Embodiment 3> <C-1. Configuration> FIG. 5 is a circuit diagram of a gate driver IC 103 which is a driving circuit according to Embodiment 3. The gate driver IC 103 includes a gate voltage adjustment circuit 35 between the control unit 34 and the PMOS 11, and other configurations are the same as those of the gate driver IC 102 according to Embodiment 2. A point between the control unit 34 and the gate voltage adjustment circuit 35 is designated as point C. The gate voltage adjustment circuit 35 receives a signal from the control unit 34 and increases the voltage drop amount in the PMOS 11.

[0027] <C-2. Operation> FIG. 6 is a diagram showing the operation of the gate driver IC 103. Hereinafter, only the differences from Embodiment 1 will be described.

[0028] When the voltage at the short-circuit detection terminal SC becomes equal to or higher than the threshold voltage Vth1 and the comparator 31 outputs an alarm signal, the control unit 34 turns off the PMOS 12 and outputs a signal to the gate voltage adjustment circuit 35 to increase the voltage drop amount of the PMOS 11. As a result, the gate voltage adjustment circuit 35 increases the voltage drop amount of the PMOS 11, and the amount of current flowing through the gate of the IGBT 201 decreases.

[0029] <C-3. Effect> The gate driver IC 103 of the present embodiment includes a gate voltage adjustment circuit 35 as a voltage adjustment circuit between the gate terminal of the PMOS 11 and the control unit 34. When an overcurrent occurs and the comparator 31 outputs an alarm signal, the gate voltage adjustment circuit 35 receives a signal from the control unit 34 and increases the voltage drop amount between the source and drain of the PMOS 11. As a result, the amount of current flowing through the gate terminal of the IGBT 201 decreases, so that the surge voltage at the time of short circuit of the IGBT 201 can be suppressed. The gate voltage adjustment circuit 35 can precisely control the reduction of the amount of current flowing through the gate of the IGBT 201, and can suppress the maximum value of the gate voltage of the IGBT 201.

[0030] <D. Embodiment 4> <D-1. Configuration> FIG. 7 is a circuit diagram of a gate driver IC 104 which is a driving circuit according to Embodiment 4. The gate driver IC 104 includes a voltage switching circuit 36 and is otherwise the same as the gate driver IC 101 according to Embodiment 1. The voltage switching circuit 36 is provided between a voltage source 51 and the source terminals of PMOSs 11 and 12, and switches the power supply voltage of the PMOSs 11 and 12 from VCC1 to VCC2 which is lower than VCC1 in response to a signal from the control unit 34. Let the point between the voltage switching circuit 36 and the PMOSs 11 and 12 be point D.

[0031] <D-2. Operation> FIG. 8 is a diagram showing the operation of the gate driver IC 104. Hereinafter, only the differences from Embodiment 1 will be described.

[0032] When the voltage at the short-circuit detection terminal SC becomes equal to or higher than the threshold voltage Vth1 and the comparator 31 outputs an alarm signal, the control unit 34 turns off the PMOS 12 and outputs a signal for adjusting the voltage to the voltage switching circuit 36. In response to this signal, the voltage switching circuit 36 switches the voltage applied to the source terminals of the PMOSs 11 and 12 from VCC1 to VCC2.

[0033] <D-3. Effect> The gate driver IC 104 includes a voltage switching circuit 36 provided between the voltage source 51 and the PMOSs 11 and 12. When an overcurrent occurs in the IGBT 201 and an alarm signal is output from the comparator 31, the voltage switching circuit 36 reduces the power supply voltage input to the source terminals of the PMOSs 11 and 12 from VCC1 which is the first voltage to VCC2 which is the second voltage in response to a signal from the control unit 34. Thereby, VCC2 can be adjusted easily and precisely, and the maximum value of the gate voltage of the IGBT 201 at the time of overcurrent occurrence can be suppressed to VCC2. As a result, the surge voltage in the IGBT 201 is suppressed.

[0034] <E. Embodiment 5> <E-1. Configuration> FIG. 9 is a circuit diagram of a gate driver IC 105 which is a drive circuit according to Embodiment 5. The gate driver IC 105 is provided with a comparator 37 instead of the delay circuit 33 as compared with the gate driver IC 101 according to Embodiment 1.

[0035] The + input terminal of the comparator 37 is connected to the output terminal OUT of the gate driver IC 105, and the - input terminal is connected to the ground via a variable DC power supply 38. A threshold voltage Vth2 is applied to the - input terminal of the comparator 37 by the variable DC power supply 38. The comparator 37 compares the gate voltage of the IGBT 201 with the threshold voltage Vth2, and when the gate voltage becomes equal to or higher than the threshold voltage Vth2, it outputs a High-level signal to the control unit 34. The High-level signal output by the comparator 37 is referred to as a trigger signal. Thus, the comparator 37 is a control terminal voltage detector that detects the control terminal voltage of the IGBT 201, and functions as a trigger signal generation circuit that outputs a trigger signal after the output start of the alarm signal by the comparator 31. The point between the comparator 37 and the control unit 34 is designated as point B.

[0036] In Embodiment 1, the continuation of overcurrent detection for a certain period of time is used as a trigger for soft cutoff, but in this embodiment, the potential of the shunt resistor 202 being equal to or higher than the threshold voltage Vth1 and the gate voltage of the IGBT 201 being equal to or higher than the threshold voltage Vth2 are used as triggers for soft cutoff.

[0037] <E-2. Operation> FIG. 10 is a diagram showing the operation of the gate driver IC 105. Hereinafter, only the differences from Embodiment 1 will be described.

[0038] The threshold voltage Vth2 is set to a value greater than the gate voltage when the emitter voltage of the IGBT201 reaches the threshold voltage Vth1. Therefore, when the gate voltage of the IGBT201 rises during turn-on, first the emitter voltage of the IGBT201 exceeds the threshold voltage Vth1, and then the gate voltage of the IGBT201 exceeds the threshold voltage Vth2. Accordingly, the comparator 37 outputs a High-level signal with a delay relative to the comparator 31.

[0039] The control unit 34 that receives the High-level signal from the comparator 37 turns off the PMOS11 and turns on the NMOS22. As a result, the gate voltage of the IGBT201 drops, and accordingly the voltage of the short-circuit detection terminal SC also decreases.

[0040] <E - 3. Effect> The gate driver IC105 includes a comparator 37 which is a control terminal voltage detector that outputs a trigger signal when the gate terminal voltage of the IGBT201 is equal to or higher than the threshold voltage Vth2. The comparator 37 functions as a trigger signal generation circuit. Therefore, according to the gate driver IC105, when a short circuit occurs in the IGBT201, soft shutdown can be flexibly performed according to the state of its gate voltage.

[0041] <F. Embodiment 6> <F - 1. Configuration> FIG. 11 is a circuit diagram of a gate driver IC106 which is a drive circuit according to Embodiment 6. The gate driver IC106 includes a comparator 39 instead of the delay circuit 33 as compared with the gate driver IC101 according to Embodiment 1.

[0042] Comparator 39 has its + input terminal connected to the short - circuit detection terminal SC, and its - input terminal connected to ground via a variable DC power supply 40. A threshold voltage Vth3 greater than the threshold voltage Vth1 is applied to the - input terminal of comparator 39 by the variable DC power supply 40. Comparator 39 compares the emitter voltage of IGBT201 with the threshold voltage Vth3, and when the emitter voltage becomes equal to or higher than the threshold voltage Vth3, it outputs a High - level signal to the control unit 34. Let the point between comparator 39 and control unit 34 be point B. When the control unit 34 receives a High - level signal from comparator 39, it turns off PMOS11 and turns on NMOS22 to perform soft - shutdown of IGBT201. Therefore, the High - level signal output by comparator 39 is referred to as a trigger signal.

[0043] Thus, in this embodiment, when the emitter voltage of IGBT201 becomes equal to or higher than the threshold voltage Vth3, it is used as a trigger for the soft - shutdown of IGBT201.

[0044] <F - 2. Operation> FIG. 12 is a diagram showing the operation of the gate driver IC106. Hereinafter, the description will focus on the differences from Embodiment 1.

[0045] When the gate voltage of IGBT201 rises during turn - on, the emitter voltage of IGBT201 becomes equal to or higher than the threshold voltage Vth1, and comparator 31 outputs an alarm signal. As a result, the control unit 34 turns off PMOS12, and the current flowing through the gate of IGBT201 decreases.

[0046] After that, when the gate voltage of IGBT201 further rises, the emitter voltage of IGBT201 becomes equal to or higher than the threshold voltage Vth3, and comparator 39 outputs a soft - shutdown trigger signal. As a result, the control unit 34 turns off PMOS11 and turns on NMOS22 to perform soft - shutdown of IGBT201.

[0047] <F - 3. Effects> The gate driver IC106 includes a comparator 39. The comparator 39 outputs a trigger signal when the potential of the shunt resistor 202 becomes equal to or higher than a second threshold value Vth3 which is larger than a first threshold value Vth1, and functions as a trigger signal generation circuit. Therefore, according to the gate driver IC106, even when the overcurrent of the IGBT201 rapidly increases, it can quickly shift to soft cutoff. Thus, according to the gate driver IC106, a cutoff operation corresponding to the actually generated overcurrent can be finely performed.

[0048] <G. Embodiment 7> In this embodiment, the gate voltage of the IGBT201 is controlled in two steps during turn-on.

[0049] <G-1. Configuration> FIG. 13 is a circuit diagram of a gate driver IC107 which is a drive circuit according to Embodiment 7. The gate driver IC107 includes a PMOS 13 which is a third upper switching element in addition to PMOSs 11 and 12 which are upper arm switching elements. The source terminal of the PMOS 13 is connected to a voltage source 52 that supplies a voltage VCC3, and the drain terminal is connected to an output terminal OUT. The gate terminal of the PMOS 13 is connected to a control unit 34.

[0050] The voltage VCC3 supplied by the voltage source 52 to the PMOS 13 is higher than the voltage VCC1 supplied by the voltage source 51 to the PMOSs 11 and 12. Note that the voltage VCC1 in this embodiment may be lower than the voltage VCC1 in the previously described embodiment. The other configurations of the gate driver IC107 are the same as those of the gate driver IC101 according to Embodiment 1.

[0051] <G-2. Operation> FIG. 14 is a diagram showing the turn-on operation of the gate driver IC107 during normal times, that is, when no overcurrent occurs.

[0052] When a high-level signal is input to the input terminal IN, that is, when an input signal is input to the control unit 34, the control unit 34 turns on the PMOS 11 and 12 and turns off the NMOS 21 and 22. As a result, the gate voltage of the IGBT 201 rises to VCC1.

[0053] When a predetermined time elapses after an input signal is input to the control unit 34, the control unit 34 turns on the PMOS 13. As a result, the gate voltage of the IGBT 201 rises to VCC3.

[0054] FIG. 15 is a diagram showing the turn-on operation by the gate driver IC 107 when an overcurrent occurs.

[0055] When a high-level signal is input to the input terminal IN, that is, when an input signal is input to the control unit 34, the control unit 34 turns on the PMOS 11 and 12 and turns off the NMOS 21 and 22. As a result, the gate voltage of the IGBT 201 rises.

[0056] When an overcurrent occurs and the voltage of the short-circuit detection terminal SC becomes equal to or higher than the threshold voltage Vth1, an alarm signal is output from the comparator 31, and the control unit 34 turns off the PMOS 12. As a result, the current flowing through the gate terminal of the IGBT 201 decreases, and the rise of the gate voltage of the IGBT 201 becomes gentle. After that, although the gate voltage of the IGBT 201 still rises, it does not rise above VCC1.

[0057] After that, when the output of the alarm signal continues for a predetermined time T1, the delay circuit 33 outputs an alarm continuation signal to the control unit 34. Then, the control unit 34 turns off the PMOS 11 and turns on the NMOS 22. As a result, the IGBT 201 is soft-blocked, and its gate voltage decreases.

[0058] <G-3. Effect> In the gate driver IC107, when the IGBT201 is turned on, the control unit 34 turns on the PMOS11 and 12, and then, if the comparator 31 does not output an alarm signal, turns on the PMOS13 after a predetermined time has elapsed since the PMOS11 and 12 were turned on. As a result, when a short circuit occurs in the IGBT201, the gate voltage of the IGBT201 is suppressed to VCC1, which is lower than VCC3, so that power consumption can be suppressed and the surge voltage at the time of a short circuit in the IGBT201 can be suppressed. Further, by adjusting VCC1 and VCC3, the gate voltage of the IGBT201 that performs two-stage control can be easily changed.

[0059] <H. Embodiment 8> <H-1. Configuration> FIG. 16 is a circuit diagram of a gate driver IC108 which is a drive circuit according to Embodiment 8. The gate driver IC108 includes, as a switching element of the lower arm, an NMOS23 which is a third lower switching element in addition to the NMOS21 and 22. Further, the gate driver IC108 includes a sink adjustment circuit 43 between the gate terminal of the NMOS23 and the control unit 34. The source terminal of the NMOS23 is connected to the ground, and the drain terminal is connected to the output terminal OUT. The configuration of the other gate driver IC108 is the same as that of the gate driver IC101 according to Embodiment 1.

[0060] When an overcurrent occurs in the IGBT201, the sink adjustment circuit 43 turns on the NMOS23 after the PMOS12 is turned off based on a signal acquired from the control unit 34. Thereby, the gate voltage of the IGBT201 is decreased. Let the point between the control unit 34 and the sink adjustment circuit 43 be point E.

[0061] <H-2. Operation> FIG. 17 is a diagram showing the operation of the gate driver IC108. Hereinafter, the description will focus on the differences from Embodiment 1.

[0062] When the voltage at the short-circuit detection terminal SC becomes equal to or higher than the threshold voltage Vth1 at turn-on, the comparator 31 outputs an alarm signal to the delay circuit 33 and the control unit 34. The control unit 34 turns off the PMOS 12 and outputs a signal for turning on the NMOS 23 to the sink adjustment circuit 43.

[0063] Upon receiving the signal from the control unit 34, the sink adjustment circuit 43 turns on the NMOS 23. As a result, the gate voltage of the IGBT 201 decreases.

[0064] Thereafter, when the output of the alarm signal from the comparator 31 continues for a predetermined time T1, the delay circuit 33 outputs an alarm continuation signal to the control unit 34. Upon receiving the alarm continuation signal, the control unit 34 turns off the PMOS 11, turns on the NMOS 22, and performs soft shutdown of the IGBT 201.

[0065] <H-3. Effect> According to the gate driver IC 108, when an overcurrent occurs and the comparator 31 outputs an alarm signal, the control unit 34 turns on the NMOS 23 while keeping the NMOS 21 and 22 off. As a result, the gate voltage of the IGBT 201 rapidly decreases. Consequently, the short-circuit current and the surge voltage are suppressed. Also, when a short circuit occurs, the PMOS 12 turns off, reducing the amount of current flowing through the gate terminal of the IGBT 201. Therefore, the on-resistance of the NMOS 23 can be increased. That is, the size of the NMOS 23 can be reduced.

[0066] Although the preferred embodiments etc. have been described in detail above, the present invention is not limited to the above embodiments etc., and various modifications and substitutions can be made to the above embodiments etc. without departing from the scope described in the claims.

[0067] Hereinafter, aspects of the present disclosure will be summarized and described as appendices.

[0068] (Appendix 1) A plurality of switching elements for driving a power semiconductor device, An overcurrent detector that outputs an alarm signal when the potential of a shunt resistor connected between the main terminal of the power semiconductor element and ground is greater than or equal to a predetermined first threshold, A trigger signal generation circuit that outputs a trigger signal after the overcurrent detector starts outputting the alarm signal, The system comprises a control unit that controls the on and off states of the plurality of switching elements, The plurality of switching elements include switching elements on the upper arm and switching elements on the lower arm. The switching elements of the upper arm include a first upper switching element and a second upper switching element connected to the same power supply. The switching element of the lower arm includes a first lower switching element and a second lower switching element. The control unit turns off the second upper switching element when the alarm signal is output, and turns on the second lower switching element when the trigger signal is output. Drive circuit.

[0069] (Note 2) The control terminal of the first upper switching element and the control terminal of the second upper switching element are connected. When the alarm signal is output, the control unit turns off the first upper switching element and the second upper switching element. The drive circuit described in Appendix 1.

[0070] (Note 3) The circuit includes a voltage adjustment circuit provided between the control terminal of the first upper switching element and the control unit, When the alarm signal is output, the voltage adjustment circuit receives a signal from the control unit and increases the voltage drop of the first upper switching element. The drive circuit described in Appendix 1.

[0071] (Note 4) The system further comprises a voltage switching circuit provided between the same power supply and the first upper switching element and the second upper switching element, When the alarm signal is output, the voltage switching circuit receives a signal from the control unit and reduces the power supply voltage input to the first upper switching element and the second upper switching element from the first voltage to the second voltage. The drive circuit described in any one of the items from Appendix 1 to Appendix 3.

[0072] (Note 5) The trigger signal generation circuit is a delay circuit that outputs the trigger signal when the input of the alarm signal from the overcurrent detector continues for a predetermined duration or longer. The drive circuit described in any one of the items from Appendix 1 to Appendix 4.

[0073] (Note 6) The trigger signal generation circuit is a control terminal voltage detector that outputs the trigger signal when the control terminal voltage of the power semiconductor element is above a predetermined threshold voltage while the alarm signal is in effect. The drive circuit described in any one of the items from Appendix 1 to Appendix 4.

[0074] (Note 7) The trigger signal generation circuit outputs the trigger signal when the potential of the shunt resistor becomes greater than or equal to a second threshold which is greater than the first threshold. The drive circuit described in any one of the items from Appendix 1 to Appendix 4.

[0075] (Note 8) The switching elements of the upper arm include a third upper switching element connected to a power supply that outputs a higher voltage than the power supply to which the first upper switching element and the second upper switching element are connected. The control unit turns on the first upper switching element and the second upper switching element when the power semiconductor element is turned on, and if the overcurrent detector does not output the alarm signal, it turns on the third upper switching element after a predetermined time has elapsed since the first upper switching element and the second upper switching element were turned on. The drive circuit described in any one of the items from Appendix 1 to Appendix 7.

[0076] (Note 9) The switching element of the lower arm includes a third lower switching element. When the alarm signal is output, the control unit turns on the third lower switching element while keeping the first lower switching element and the second lower switching element off. The drive circuit described in any one of the items from Appendix 1 to Appendix 8.

[0077] (Note 10) The aforementioned power semiconductor device is an FET made of a wide-bandgap semiconductor. The drive circuit described in any one of the items from Appendix 1 to Appendix 9. [Explanation of Symbols]

[0078] 11-13 PMOS, 21-23 NMOS, 31,37,39 Comparators, 32 Variable DC power supply, 33 Delay circuit, 34 Control unit, 35 Gate voltage adjustment circuit, 36 Voltage switching circuit, 38,40 Variable DC power supply, 43 Sink adjustment circuit, 51,52 Voltage source, 101-108 Gate driver IC, 201 IGBT, 202 Shunt resistor.

Claims

1. An output terminal connected to the control terminal of a power semiconductor element, Multiple switching elements that drive the aforementioned power semiconductor element, An overcurrent detector that outputs an alarm signal when the potential of a shunt resistor connected between the main terminal of the power semiconductor element and ground is greater than or equal to a predetermined first threshold, A trigger signal generation circuit that outputs a trigger signal after the overcurrent detector starts outputting the alarm signal, The system comprises a control unit that controls the conduction and non-conductivity of the plurality of switching elements, The plurality of switching elements include switching elements on the upper arm and switching elements on the lower arm. The switching elements of the upper arm include a first upper switching element and a second upper switching element connected in parallel between the same power supply and the output terminal. The switching elements of the lower arm include a first lower switching element and a second lower switching element connected in parallel between the output terminal and the ground. When the alarm signal is output, the control unit deactivates the second upper switching element, and when the trigger signal is output, it activates the second lower switching element while keeping the first upper switching element and the second upper switching element in a deactivating state, thereby lowering the potential of the output terminal toward the ground. Drive circuit.

2. The control terminal of the first upper switching element and the control terminal of the second upper switching element are connected. When the alarm signal is output, the control unit deactivates the first upper switching element and the second upper switching element. The drive circuit according to claim 1.

3. The circuit includes a voltage adjustment circuit provided between the control terminal of the first upper switching element and the control unit, When the alarm signal is output, the voltage adjustment circuit receives a signal from the control unit and increases the voltage drop of the first upper switching element. The drive circuit according to claim 1.

4. The system further comprises a voltage switching circuit provided between the same power supply and the first upper switching element and the second upper switching element, When the alarm signal is output, the voltage switching circuit receives a signal from the control unit and reduces the power supply voltage input to the first upper switching element and the second upper switching element from the first voltage to the second voltage. The drive circuit according to claim 1.

5. The trigger signal generation circuit is a delay circuit that outputs the trigger signal when the input of the alarm signal from the overcurrent detector continues for a predetermined duration or longer. The drive circuit according to claim 1.

6. The trigger signal generation circuit is a control terminal voltage detector that outputs the trigger signal when the control terminal voltage of the power semiconductor element is above a predetermined threshold voltage while the alarm signal is in effect. The drive circuit according to claim 1.

7. The trigger signal generation circuit outputs the trigger signal when the potential of the shunt resistor becomes greater than or equal to a second threshold which is greater than the first threshold. The drive circuit according to claim 1.

8. The switching element of the upper arm includes a third upper switching element connected to a power supply that outputs a higher voltage than the power supply to which the first upper switching element and the second upper switching element are connected. The control unit, after making the first upper switching element and the second upper switching element conductive when the power semiconductor element is turned on, and if the overcurrent detector does not output the alarm signal, then makes the third upper switching element conductive after a predetermined time has elapsed since the first upper switching element and the second upper switching element were made conductive. The drive circuit according to claim 1.

9. The switching element of the lower arm includes a third lower switching element. When the alarm signal is output, the control unit keeps the first lower switching element and the second lower switching element in a non-conductive state while making the third lower switching element conductive. The drive circuit according to claim 1.

10. The aforementioned power semiconductor device is an FET made of a wide-bandgap semiconductor. The drive circuit according to claim 1.

Images