Capacitor

Abstract

To accumulate charges in areas where no electrostatic breakdown occurs even when electrostatic breakdown occurs in a dielectric layer.SOLUTION: In a capacitor including two or more dielectric layers and two or more conductive layers alternately laminated on at least an inner surface of a groove formed on a main surface of a substrate, a contact layer is arranged between an electrode formed on the main surface of the substrate and a conductive layer electrically connected to the electrode. The contact layer is made of a metal that contacts the conductive layer and reacts with the material of the conductive layer to form a compound.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention relates to a capacitor.

Background Art

[0002] A capacitor is known in which a layer arrangement in which a conductive layer and a dielectric layer are alternately deposited is embedded inside an opening extending through a substrate (see Patent Document 1). In Patent Document 1, the layer arrangement embedded inside the opening is electrically connected to the electrode on the upper surface of the substrate and the electrode on the back surface of the substrate, respectively.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to increase the capacitance density of a capacitor, there is a method of forming a thin dielectric layer sandwiched between two conductive layers. However, when electrostatic breakdown occurs in the thin dielectric layer, a short - circuit current is generated between the conductive layer and the external electrode, and the short - circuit current causes problems such as malfunction of the capacitor.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a capacitor and a method for manufacturing the same that can accumulate charges at non - breakdown locations even when electrostatic breakdown occurs in the dielectric layer.

Means for Solving the Problems

[0006] To solve the above-mentioned problems, one aspect of the present invention provides a capacitor comprising two or more dielectric layers and two or more conductive layers alternately stacked on the inner surface of grooves formed on the main surface of a substrate, wherein a contact layer is disposed between an electrode formed on the main surface of the substrate and a conductive layer electrically connected to the electrode. The contact layer is made of a metal that contacts the conductive layer and reacts with the material of the conductive layer to form a compound. [Effects of the Invention]

[0007] According to one aspect of the present invention, even if electrostatic discharge occurs in the dielectric layer, charge can be accumulated in areas where it does not occur. [Brief explanation of the drawing]

[0008] [Figure 1A] Figure 1A is a schematic cross-sectional view (a cross-sectional view along the line 1A-1A in Figure 1B) showing the configuration of the capacitor according to the first embodiment. [Figure 1B] Figure 1B is a plan view of the capacitor shown in Figure 1A, when the first main surface of substrate 1 is viewed from the direction of its normal vector. [Figure 2A] Figure 2A is a schematic cross-sectional view illustrating the capacitor according to the first embodiment before operation. [Figure 2B] Figure 2B is a schematic cross-sectional view illustrating the operation of the capacitor according to the first embodiment. [Figure 3A] Figure 3A is a cross-sectional view showing the manufacturing process of the capacitor shown in Figure 1A (Part 1). [Figure 3B] Figure 3B is a cross-sectional view showing the manufacturing process of the capacitor shown in Figure 1A (part 2). [Figure 3C] Figure 3C is a cross-sectional view showing the manufacturing process of the capacitor shown in Figure 1A (part 3). [Figure 3D] Figure 3D is a cross-sectional view showing the steps of the manufacturing method for the capacitor shown in Figure 1A (part 4). [Figure 3E] Figure 3E is a cross-sectional view showing the steps of the manufacturing method for the capacitor shown in Figure 1A (part 5). [Figure 3F]FIG. 3F is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 1A (Part 6). [Figure 3G] FIG. 3G is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 1A (Part 7). [Figure 4] FIG. 4 is a schematic cross-sectional view showing the configuration of the capacitor according to the second embodiment. [Figure 5A] FIG. 5A is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 4 (Part 1). [Figure 5B] FIG. 5B is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 4 (Part 2). [Figure 5C] FIG. 5C is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 4 (Part 3). [Figure 5D] FIG. 5D is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 4 (Part 4). [Figure 5E] FIG. 5E is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 4 (Part 5). [Figure 5F] FIG. 5F is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 4 (Part 6). [Figure 5G] FIG. 5G is a cross-sectional view showing the steps of the method for manufacturing the capacitor shown in FIG. 4 (Part 7). [Figure 6] FIG. 6 is a schematic cross-sectional view showing the configuration of the capacitor according to the third embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0009] Embodiments will be described below with reference to the drawings. In the description of the drawings, the same reference numerals are given to the same parts and the description thereof is omitted. However, the drawings are schematic, and include parts where the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Also, parts where the dimensional relationships and ratios are different are included among the drawings.

[0010] (First Embodiment) Referring to FIGS. 1A and 1B, the configuration of the capacitor according to the first embodiment will be described. FIG. 1A is a schematic cross-sectional view of the capacitor 100. FIG. 1B is a plan view of FIG. 1A when viewed from the first main surface 1F described later. The capacitor 100 includes a substrate 1. The substrate 1 has a first main surface 1F, a second main surface 1R opposite to the first main surface 1F, and a groove 2 formed in the first main surface 1F. The groove 2 has an inner surface 2I. The substrate 1 is a single crystal substrate made of silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). The substrate 1 is doped with a high concentration of N-type or P-type impurities, and the substrate 1 is used as a conductor in the same manner as the conductive layer described later.

[0011] The capacitor 100 includes two or more dielectric layers 3 and two or more conductive layers (4a to 4c, 7a, 7b) alternately laminated on the inner surface 2I of the groove 2, the first main surface 1F, and the second main surface 1R. In this embodiment, five dielectric layers 3 and five conductive layers (4a to 4c, 7a, 7b) are alternately laminated on the inner surface 2I of the groove 2, the first main surface 1F, and the second main surface 1R. The five conductive layers (4a to 4c, 7a, 7b) are electrically insulated from each other by the dielectric layer 3. Each of the five conductive layers (4a to 4c, 7a, 7b) and the five dielectric layers 3 is continuously formed on the first main surface 1F, the inner surface 2I of the groove 2, and the second main surface 1R. The number of dielectric layers and conductive layers laminated on the inner surface 2I of the groove 2 is determined by the width of the groove and the thickness of the dielectric layers and conductive layers, and may be 3 to 4 layers, or 5 layers or more, respectively.

[0012] Hereinafter, the five conductive layers shown in FIG. 1A may be individually referred to as the conductive layer 4a, the conductive layer 7a, the conductive layer 4b, the conductive layer 7b, and the conductive layer 4c in order from the side closer to the substrate 1.

[0013] The groove 2 may penetrate between the first main surface 1F and the second main surface 1R. By extending the groove 2 formed in the substrate 1 from the first main surface 1F to the second main surface 1R, the dielectric layer 3 and conductive layers (4a to 4c, 7a, 7b) formed on the first main surface 1F and the second main surface 1R can be made symmetrical with respect to the center in the film thickness direction of the substrate 1, thereby mitigating warping of the substrate 1 caused by stress in the dielectric layer 3.

[0014] The capacitor 100 further comprises a high-potential surface electrode 23 (first electrode) embedded in a high-potential opening 15 formed on the first main surface 1F, and a low-potential surface electrode 24 (second electrode) embedded in a low-potential opening 13 formed on the first main surface 1F. The high-potential surface electrode 23 is electrically connected to the conductive layers (4a to 4c). The low-potential surface electrode 24 is electrically connected to the conductive layers (7a, 7b) and the substrate 1, which are not electrically connected to the high-potential surface electrode 23. In this embodiment, the case where the high-potential surface electrode corresponds to the first electrode and the high-potential surface electrode corresponds to the second electrode is shown, but the reverse may also be true.

[0015] In this embodiment, two high-potential openings 15 are formed on the first main surface 1F, and high-potential surface electrodes 23 are formed on the side surfaces (including a part of the surface of the contact layer 20 described later) and bottom surfaces of the high-potential openings 15. The high-potential surface electrodes 23 are in contact with the contact layer 20 on the side surfaces of the high-potential openings 15 and are electrically connected to the conductive layers (4a to 4c) via the contact layer 20.

[0016] A high-potential side contact hole is provided in a portion of the inner surface of the high-potential side opening 15. A contact layer 20 is embedded inside the high-potential side contact hole. The contact layer 20 is positioned between the high-potential surface electrode 23 and the conductive layer (4a-4c). The contact layer 20 is made of a metal that contacts the conductive layer (4a-4c) and reacts with the material of the conductive layer (4a-4c) to form a compound.

[0017] The contact layer 20 functions as a microfuse. The contact layer 20 is sandwiched between two dielectric layers 3. The contact layer 20 is generally made of metal. Specifically, titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), and silver (Ag) can be used. Alternatively, the contact layer 20 may be a multilayer film such as titanium (Ti) / nickel (Ni) / silver (Ag). It is preferable that the film thickness of the contact layer 20 is smaller than the film thickness of the high-potential surface electrode 23. This narrows the path of the short-circuit current flowing through the contact layer 20 when a high-density short-circuit current flows through it, thereby increasing its resistance. As a result, the contact layer 20 tends to become hot, and as a result, a fused section can be easily formed inside the contact layer 20. The fused section blocks the current path of the short-circuit current.

[0018] When viewed from the direction normal to the first main surface 1F, each of the multiple contact layers 20 overlaps with the others. Furthermore, the multiple contact layers 20 are in contact with the conductive layers (4a-4c) and the high-potential surface electrodes 23. When the multiple contact layers 20 overlap with each other when viewed from the direction normal to the first main surface 1F, the area occupied by the contact layers 20 on the first main surface 1F can be reduced, thereby improving the capacitance density of the capacitor 100.

[0019] Similarly, two low-potential openings 13 are formed on the first main surface 1F, and low-potential surface electrodes 24 are formed on the side surfaces (including a portion of the surface of the contact layer 21 described later) and bottom surfaces of the low-potential openings 13. The low-potential surface electrodes 24 are in contact with the substrate 1 at the bottom surface of the low-potential openings 13 and electrically connected, and are in contact with the contact layer 21 at the side surfaces of the low-potential openings 13, and are electrically connected to the conductive layers (7a, 7b) via the contact layer 21.

[0020] A low-potential side contact hole is provided in a portion of the inner surface of the low-potential side opening 13. A contact layer 21 is embedded inside the low-potential side contact hole. The contact layer 21 is positioned between the low-potential surface electrode 24 and the conductive layers (7a, 7b). The contact layer 21 is made of a metal that contacts the conductive layers (7a, 7b) and reacts with the material of the conductive layers (7a, 7b) to form a compound.

[0021] The contact layer 21 functions as a microfuse. The contact layer 21 is sandwiched between two dielectric layers 3. The contact layer 21 is generally made of metal. Specifically, titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), and silver (Ag) can be used. Alternatively, the contact layer 21 may be a multilayer film such as titanium (Ti) / nickel (Ni) / silver (Ag). It is preferable that the film thickness of the contact layer 21 is smaller than the film thickness of the low-potential surface electrode 24. This narrows the path of the short-circuit current flowing through the contact layer 21 when a high-density short-circuit current flows through it, thereby increasing its resistance. As a result, the contact layer 21 tends to become hotter, which is preferable because it allows for the easy formation of a fused section inside the contact layer 21. The fused section blocks the current path of the short-circuit current.

[0022] When viewed from the direction normal to the first main surface 1F, each of the multiple contact layers 21 overlaps with the others. Furthermore, the multiple contact layers 21 are in contact with the conductive layers (7a, 7b) and the low-potential surface electrode 24. When the multiple contact layers 21 overlap each other when viewed from the direction normal to the first main surface 1F in this manner, the area occupied by the contact layers 21 on the first main surface 1F can be reduced, thereby improving the capacitance density of the capacitor 100.

[0023] Furthermore, as shown in Figure 1B, when viewed from the direction normal to the first main surface 1F, if the contact layer 20 and the contact layer 21 each surround the groove 2, the stress of the laminated conductive layer and dielectric layer is interrupted around the groove 2 by the contact layer 20 and the contact layer 21, thereby relieving the stress of the entire capacitor 100.

[0024] A silicon oxide film can be used as the dielectric layer 3. This enables operation at high voltages. Alternatively, a silicon nitride film with a high dielectric constant may be used as the dielectric layer 3. This can improve the capacitance density. Alternatively, a laminated film of silicon oxide and silicon nitride may be used as each dielectric layer 3. The dielectric layer 3 electrically insulates the conductive layers (4a to 4c) electrically connected to the high-potential surface electrode 23 from the conductive layers (7a, 7b) electrically connected to the low-potential surface electrode 24.

[0025] For example, a polysilicon film can be used as the conductive layer (4a-4c, 7a, 7b). Alternatively, a metal may be used for the conductive layer (4a-4c, 7a, 7b). In this case, the equivalent series resistance (ESR) of the conductive layer (4a-4c, 7a, 7b) can be reduced. When the conductive layer (4a-4c, 7a, 7b) is made of polysilicon, the conductive layer (4a-4c, 7a, 7b) can be uniformly grown along the first main surface 1F and the second main surface 1R of the substrate 1, as well as the inner surface 2I of the groove 2, using a low-pressure CVD method.

[0026] Next, the basic operation of capacitor 100 will be explained. A positive voltage is applied to the high-potential surface electrode 23, and a negative voltage is applied to the low-potential surface electrode 24. As a result, positive charges are charged to the conductive layers (4a to 4c) electrically connected to the high-potential surface electrode 23, and negative charges are charged to the substrate 1 and conductive layers (7a, 7b) electrically connected to the low-potential surface electrode 24. At this time, polarization occurs inside the dielectric layer 3, and capacitance is generated. In this state, if electrostatic discharge occurs in the dielectric layer 3 between the conductive layer (e.g., conductive layer 4b) electrically connected to the high-potential surface electrode 23 and the conductive layer (e.g., conductive layer 7b) electrically connected to the low-potential surface electrode 24 inside the groove 2, a short-circuit current C flows between conductive layer 4b and conductive layer 7b via a short-circuit point SP, as shown in Figure 2A.

[0027] At this time, a high-density short-circuit current C flows through the contact layer 20 in contact with the conductive layer 4b. Due to the high-density short-circuit current C, the contact layer 20 becomes extremely hot, and the materials of the contact layer 20 and the conductive layer 4b react to form a compound R. Compound R is preferably a silicide. For example, if the conductive layer 4b is made of polysilicon and the contact layer 20 is made of titanium (Ti), molybdenum (Mo), nickel (Ni), or tungsten (W), these react to form a silicide. Simultaneously with this reaction, the metal atoms constituting the contact layer 20, which have melted due to the high temperature, are attracted to the conductive layer 4b side, and as shown in Figure 2B, a fused section F is formed inside the contact layer 20. The fused section F blocks the current path of the short-circuit current C (the path through which current flows from the conductive layer 4b to the conductive layer 7b via the short-circuit point SP). Compound R being a silicide is preferable because it allows for easy formation of the fused section F. In this way, the contact layer 20 operates as a microfuse. Similarly, the contact layer 21 also operates as a microfuse. Furthermore, in areas of the dielectric layer 3 where electrostatic discharge has not occurred, charge can be accumulated, allowing it to function as a capacitor.

[0028] The substrate 1 may be conductive. Since the substrate 1 can be used as a conductive layer, the capacitance density of the capacitor 100 is improved. Of course, this is not the only option; the substrate 1 may have semiconductor properties or insulating properties. If the substrate 1 is insulating, element isolation becomes easier.

[0029] The manufacturing method for the capacitor according to this embodiment will be described below with reference to the drawings. Note that the manufacturing method for the capacitor described below is just one example, and it can be realized by various other manufacturing methods.

[0030] First, a semiconductor substrate (substrate 1) doped with a high concentration of N-type or P-type impurities is prepared. When using a Si substrate, an N-type semiconductor substrate can be manufactured by adding pentavalent elemental impurities such as phosphorus (P) and arsenic (As), and a P-type semiconductor substrate can be manufactured by adding trivalent elemental impurities such as boron (B) and gallium (Ga).

[0031] Next, grooves 2 are formed by etching a portion of substrate 1 from the first main surface 1F to the second main surface 1R. Specifically, first, a mask material is formed on the first main surface 1F of substrate 1. A silicon oxide film can be used as the mask material, and thermal CVD or plasma CVD can be used as the deposition method. Next, a resist is patterned on the mask material. A general photolithography method can be used as the patterning method. The mask material is etched using the patterned resist as a mask. The mask material has openings in the areas where grooves 2 are formed. As for the etching method, wet etching using potassium hydroxide aqueous solution, hydrofluoric acid, or hot phosphoric acid, or dry etching such as reactive ion etching can be used. Next, the resist is removed with oxygen plasma or sulfuric acid, etc. Using the mask material formed in this way, the substrate 1 exposed through the openings in the mask material is etched by dry etching to form grooves 2.

[0032] Next, a dielectric layer 3 is deposited on the surface of the substrate 1, including the inner surface 2I of the groove 2, and the first main surface 1F and the second main surface 1R, so as to cover the substrate 1. A silicon oxide film can be used as the dielectric layer 3, and thermal oxidation or thermal CVD can be used as the deposition method. Furthermore, when using the thermal CVD method, by using reduced pressure conditions, a silicon oxide film can be deposited with good coverage even when the groove 2 is deep.

[0033] Next, a conductive layer 4a is deposited on the surface of the substrate 1, including the inner surface 2I of the groove 2, and the first main surface 1F and the second main surface 1R, so as to cover the dielectric layer 3. Here, a polysilicon film is used as an example of the conductive layer 4a. After the deposition of the polysilicon film, an annealing treatment is performed in POCl3 at 950°C to form an N-type polysilicon film, thereby giving conductivity to the conductive layer 4a. Here, an N-type polysilicon film is used as an example of the conductive layer 4a, but a P-type polysilicon film, a semiconductor film such as silicon germanium, a conductive polysilicon carbide film, or a metal film such as titanium (Ti) or aluminum (Al) can also be used. Vacuum CVD can be used as the method for depositing the polysilicon film.

[0034] Next, as shown in Figure 3A, a mask material 5 made of a silicon oxide film is formed on the first main surface 1F of the substrate 1, and the mask material 5 is patterned using lithography and etching techniques. The patterned mask material 5 has an opening in the region 6 where the low-potential opening 13 will later be formed. Etching is performed using the mask material 5 to selectively etch the conductive layer 4a that is exposed from the opening in the mask material 5. An anisotropic etching method may be used for the etching method. The conductive layer 4a in region 6 is removed, and the dielectric layer 3 is exposed. By giving directionality to the etching direction, region 6 can be formed without etching the dielectric layer 3 and conductive layer 4a deposited on the inner surface 2I of the groove 2.

[0035] Next, a dielectric layer 3 is deposited on the inner surface 2I of the groove 2, as well as on the surface of the substrate 1 including the first main surface 1F and the second main surface 1R, so as to cover the conductive layer 4a. At this time, the dielectric layer 3 is also formed in the region 6 where the low-potential opening 13 will later be formed.

[0036] Next, a conductive layer 7a is deposited on the surface of the substrate 1, including the inner surface 2I of the groove 2, and the first main surface 1F and the second main surface 1R, so as to cover the dielectric layer 3. The material and deposition method of the conductive layer 7a are the same as those for the conductive layer 4a.

[0037] Next, as shown in Figure 3B, a mask material 8 made of a silicon oxide film is formed on the first main surface 1F of the substrate 1, and the mask material 8 is patterned using lithography and etching techniques. The patterned mask material 8 has an opening in the region 9 where the high-potential opening 15 will later be formed. Etching is performed using the mask material 8 to selectively etch the conductive layer 7a that is exposed from the opening in the mask material 8. An anisotropic etching method may be used for the etching method. The conductive layer 7a in region 9 is removed, and the dielectric layer 3 is exposed. By giving directionality to the etching direction, region 9 can be formed without etching the dielectric layer 3 and conductive layer 7a deposited on the inner surface 2I of the groove 2.

[0038] Next, the deposition of the dielectric layer 3 and the deposition and etching of the conductive layers (4a, 7a) are repeatedly performed, as shown in Figures 3A and 3B. As a result, as shown in Figure 3C, conductive layers 4a, 7a, 4b, 7b, and 4c are laminated on the surface of the substrate 1 via the dielectric layer 3, in order from closest to the substrate 1, and the grooves 2 are filled in. Conductive layers 4a and 4b are formed in the region of the first main surface 1F of the substrate 1, excluding region 6 where the low-potential opening 13 will later be formed. Conductive layers 7a and 7b are formed in the region of the first main surface 1F of the substrate 1, excluding region 9 where the high-potential opening 15 will be formed.

[0039] Next, as shown in Figure 3C, a mask material 10 made of a silicon oxide film is formed on the first main surface 1F of the substrate 1, and the mask material 10 is patterned using lithography and etching techniques. The patterned mask material 10 has an opening in the region 6 where the low-potential opening 13 will later be formed. Etching is performed using the mask material 10 to selectively etch the conductive layer 4c exposed from the opening in the mask material 10. An anisotropic etching method may be used for the etching method. The conductive layer 4c in region 6 is removed, and the dielectric layer 3 is exposed.

[0040] Next, as shown in Figure 3D, an interlayer film 11 is deposited on the first main surface 1F and the second main surface 1R of the substrate 1. The interlayer film 11 can be a silicon oxide film. Furthermore, a mask material 12 is formed on the first main surface 1F of the substrate 1, and the mask material 12 is patterned using lithography and etching techniques. The patterned mask material 12 has openings for forming a low-potential side opening 13. Using the mask material 12, the interlayer film 11, dielectric layer 3, conductive layer 7b, dielectric layer 3, conductive layer 7a, and dielectric layer 3 exposed from the openings in the mask material 12 are etched in order. This forms a low-potential side opening 13 through which the substrate 1 is exposed.

[0041] Next, as shown in Figure 3E, a mask material 14 is formed on the first main surface 1F of the substrate 1, and the mask material 14 is patterned using lithography and etching techniques. The patterned mask material 14 has an opening for forming a high-potential opening 15. Using the mask material 14, the interlayer film 11, conductive layer 4c, dielectric layer 3, conductive layer 4b, dielectric layer 3, and conductive layer 4a that are exposed from the opening in the mask material 14 are etched in order. This forms a high-potential opening 15 where the dielectric layer 3 is exposed.

[0042] Next, as shown in Figure 3F, a mask material 16 is formed on the first main surface 1F of the substrate 1, and the mask material 16 is patterned using lithography and etching techniques. The patterned mask material 16 has an opening in a part of the inner surface of the high-potential opening 15 for forming a high-potential contact hole 17, and an opening in a part of the inner surface of the low-potential opening 13 for forming a low-potential contact hole 18. The conductive layers (4a-4c, 7a, 7b) are etched using the mask material 16. An isotropic etching method may be used for etching; for example, the conductive layers (4a-4c, 7a, 7b) are etched to a thickness of 5 μm using a wet etching method. This forms the high-potential contact hole 17 and the low-potential contact hole 18.

[0043] Next, surface electrodes are deposited so as to cover the first main surface 1F of the substrate 1. At this time, surface electrodes are also deposited on the bottom and sides of the high-potential opening 15 and the low-potential opening 13, as well as inside the high-potential contact hole 17 and the low-potential contact hole 18. The surface electrodes deposited inside the high-potential contact hole 17 become a contact layer 20, and the contact layer 20 functions as a microfuse. The surface electrodes deposited inside the low-potential contact hole 18 become a contact layer 21, and the contact layer 21 functions as a microfuse. The surface electrodes are electrically connected to the conductive layer (4a-4c, 7a, 7b) via the substrate 1 exposed on the bottom surface of the low-potential opening 13, and via the contact layers 20 and 21 embedded in the high-potential contact hole 17 and the low-potential contact hole 18, respectively. The contact layers 20 and 21 are made of metals that react with the conductive layers (4a-4c, 7a, 7b) to form compounds. Specifically, they are made of metals such as titanium (Ti), molybdenum (Mo), nickel (Ni), and tungsten (W) that bond with the conductive layers (4a-4c, 7a, 7b) to form silicides. The surface electrodes can be formed using sputtering, electron beam (EB) deposition, or atomic layer deposition (ALD). The surface electrodes correspond to the high-potential surface electrode 23 and low-potential surface electrode 24 before they are separated.

[0044] Next, as shown in Figure 3G, the mask material 22 is patterned using a general photolithography method, and a portion of the surface electrode is etched using dry etching with the patterned mask material 22. As a result, the surface electrode is divided into a high-potential surface electrode 23 and a low-potential surface electrode 24.

[0045] Next, the capacitor 100 is completed by removing the mask material 22.

[0046] Furthermore, by forming groove 2 by dry etching, groove 2 with a high aspect ratio can be formed.

[0047] Alternatively, groove 2 may be formed by wet etching. This allows groove 2 to be formed at a low cost.

[0048] According to this embodiment, even if electrostatic discharge (ESD) occurs in the dielectric layer 3, the contact layer through which the short-circuit current flows acts as a microfuse, and in areas where no ESD has occurred in the dielectric layer 3, charge can be accumulated and it can function as a capacitor.

[0049] Furthermore, by making the film thickness of the contact layer 20 and the contact layer 21 smaller than the film thickness of the high-potential surface electrode 23 and the low-potential surface electrode 24, respectively, the contact layer 20 and the contact layer 21 can easily reach high temperatures, and as a result, melted portions can be easily formed inside the contact layer 20 and the contact layer 21.

[0050] Furthermore, by overlapping the multiple contact layers 20 and the multiple contact layers 21 when viewed from the normal direction of the first main surface 1F, the area occupied by the contact layers 20 and 21 on the first main surface 1F can be reduced, and the capacitance density of the capacitor 100 can be improved.

[0051] Furthermore, when viewed from the direction normal to the first main surface 1F, if the contact layer 20 and the contact layer 21 each surround the groove 2, the stress of the laminated conductive layer and dielectric layer is interrupted around the groove 2 by the contact layer 20 and the contact layer 21, thereby relieving the stress of the entire capacitor 100.

[0052] Furthermore, by extending the groove 2 formed in the substrate 1 from the first main surface 1F to the second main surface 1R, the dielectric layer 3 and conductive layers (4a-4c, 7a, 7b) formed on the first main surface 1F and the second main surface 1R can be made symmetrical with respect to the center of the substrate 1, thereby mitigating warping of the substrate 1 caused by stress in the dielectric layer 3.

[0053] (Second Embodiment) Referring to Figure 4, the configuration of the capacitor according to the second embodiment will be described. Compared to the capacitor 100 shown in Figure 1A, capacitor 100A differs in that a high-potential surface electrode 32 is provided on the first main surface 1F side, a low-potential surface electrode 33 is provided on the second main surface 1R side, and a dielectric layer 3, conductive layers (4a~4c, 7a, 7b), contact layer 30, and contact layer 31 are embedded inside the groove 2.

[0054] The capacitor 100A comprises a high-potential surface electrode 32 (first electrode) formed on the first main surface 1F side and a low-potential surface electrode 33 (second electrode) formed on the second main surface 1R side. The high-potential surface electrode 32 is electrically connected to the conductive layers (4a to 4c). The low-potential surface electrode 33 is electrically connected to the conductive layers (7a, 7b) and the substrate 1, which are not electrically connected to the high-potential surface electrode 23. In this embodiment, the case where the high-potential surface electrode corresponds to the first electrode and the high-potential surface electrode corresponds to the second electrode is shown, but the reverse may also be true.

[0055] Because electrodes (high-potential surface electrode 32 and low-potential surface electrode 33) are arranged on both sides of the substrate 1 (the first main surface 1F side and the second main surface 1R side), the capacitor 100A can be easily mounted on a module or the like.

[0056] Furthermore, the contact layer 30 is in contact with the high-potential surface electrode 32 and the conductive layers (4a to 4c), and superimposed on each other when viewed from the normal direction of the first main surface 1F. Similarly, the contact layer 31 is in contact with the low-potential surface electrode 33 and the conductive layers (7a, 7b), and superimposed on each other when viewed from the normal direction of the first main surface 1F. The materials for the contact layers 30 and 31 can be the same as those for the contact layers 20 and 21 described in the first embodiment. Because the contact layers 30 and 31 are located close to the high-potential surface electrode 32 and the low-potential surface electrode 33, respectively, the lengths of the high-potential surface electrode 32 and the low-potential surface electrode 33 can be minimized, thereby reducing the equivalent series resistance (ESR).

[0057] Furthermore, the substrate 1, conductive layer 4a, conductive layer 7a, conductive layer 4b, conductive layer 7b, conductive layer 4c, and dielectric layer 3 are the same as in the first embodiment, so a further explanation is omitted.

[0058] In this embodiment, the high-potential side contact hole is formed on the first main surface 1F side, and the low-potential side contact hole is formed on the second main surface 1R side. A contact layer 30 is embedded inside the high-potential side contact hole. The contact layer 30 is positioned between the high-potential surface electrode 32 and the conductive layer (4a-4c). The contact layer 30 is made of a metal that contacts the conductive layer (4a-4c) and reacts with the material of the conductive layer (4a-4c) to form a compound. A contact layer 31 is embedded inside the low-potential side contact hole. The contact layer 31 is positioned between the low-potential surface electrode 33 and the conductive layer (7a, 7b). The contact layer 31 is made of a metal that contacts the conductive layer (7a, 7b) and reacts with the material of the conductive layer (7a, 7b) to form a compound.

[0059] Similar to the first embodiment, contact layers 30 and 31 function as microfuses. The basic operation of capacitor 100A is also the same as in the first embodiment, so a further explanation is omitted.

[0060] The manufacturing method for the capacitor according to this embodiment will be described below with reference to the drawings. Note that the manufacturing method for the capacitor described below is just one example, and it can be realized by various other manufacturing methods.

[0061] Similar to the first embodiment, first, a semiconductor substrate (substrate 1) doped with a high concentration of N-type or P-type impurities is prepared. Next, grooves 2 are formed by etching a portion of the substrate 1 from the first main surface 1F to the second main surface 1R. Then, a dielectric layer 3 is deposited on the inner surface 2I of the grooves 2, as well as on the surface of the substrate 1 including the first main surface 1F and the second main surface 1R, so as to cover the substrate 1.

[0062] Next, an interlayer film 25 is deposited on the dielectric layer 3 on the first main surface 1F. The interlayer film 25 can be a silicon oxide film, and atmospheric pressure CVD can be used as the deposition method.

[0063] Next, as shown in Figure 5A, a conductive layer 4a is deposited on the surface of the substrate 1, including the inner surface 2I of the groove 2, the first main surface 1F, and the second main surface 1R, so as to cover the dielectric layer 3 and the interlayer film 25.

[0064] Next, as shown in Figure 5B, the conductive layer 4a on the second main surface 1R of the substrate 1 is etched. An anisotropic etching method can be used for etching. The conductive layer 4a in region 26 is removed, and the dielectric layer 3 is exposed. By giving directionality to the etching direction, region 26 can be formed without etching the dielectric layer 3 and conductive layer 4a deposited on the inner surface 2I of the groove 2.

[0065] Next, a dielectric layer 3 is deposited on the surface of the substrate 1, including the inner surface 2I of the groove 2, the first main surface 1F, and the second main surface 1R, so as to cover the conductive layer 4a.

[0066] Next, a conductive layer 7a is deposited on the surface of the substrate 1, including the inner surface 2I of the groove 2, the first main surface 1F, and the second main surface 1R, so as to cover the dielectric layer 3. The material and deposition method of the conductive layer 7a are the same as those for the conductive layer 4a.

[0067] Next, as shown in Figure 5C, the conductive layer 7a on the first main surface 1F of the substrate 1 is etched. An anisotropic etching method can be used for etching. The conductive layer 7a in region 27 is removed, and the dielectric layer 3 is exposed. By giving directionality to the etching direction, region 27 can be formed without etching the dielectric layer 3 and conductive layer 7a deposited on the inner surface 2I of the groove 2.

[0068] Next, the deposition of the dielectric layer 3 and the deposition and etching of the conductive layers (4a, 7a) are repeatedly performed, as shown in Figures 5A and 5B. As a result, as shown in Figure 5D, conductive layers 4a, 7a, 4b, 7b, and 4c are laminated on the surface of the substrate 1 via the dielectric layer 3, in order from closest to the substrate 1, and the grooves 2 are filled in. Conductive layers 4a and 4b are formed in the region of the second main surface 1R of the substrate 1, excluding region 26. Conductive layers 7a and 7b are formed in the region of the first main surface 1F of the substrate 1, excluding region 27.

[0069] Next, as shown in Figure 5D, a dielectric layer 3 is deposited on the surface of the substrate 1, including the inner surface 2I of the groove 2, the first main surface 1F, and the second main surface 1R, so as to cover the conductive layer 4c and the conductive layer 7b.

[0070] Next, as shown in Figure 5E, the first main surface 1F and the second main surface 1R are subjected to chemical mechanical polishing (CMP) to expose the interlayer film 25 and the second main surface 1R. As a result, conductive layers 4a, 4b, and 4c are exposed on the first main surface 1F side, and conductive layers 7a and 7b are exposed on the second main surface 1R side.

[0071] Next, as shown in Figure 5F, the conductive layers (4a-4c, 7a, 7b) are etched. Either dry etching or wet etching can be used; for example, the conductive layers (4a-4c, 7a, 7b) are etched to a thickness of 5 μm. This forms the high-potential contact hole 28 and the low-potential contact hole 29.

[0072] Next, as shown in Figure 5G, high-potential surface electrodes 32 and low-potential surface electrodes 33 are deposited to cover the first main surface 1F and the second main surface 1R of the substrate 1, respectively. At this time, the high-potential surface electrode 32 deposited inside the high-potential side contact hole 28 becomes a contact layer 30, and the contact layer 30 functions as a microfuse. The low-potential surface electrode 33 deposited inside the low-potential side contact hole 29 becomes a contact layer 31, and the contact layer 31 functions as a microfuse. The high-potential surface electrode 32 is electrically connected to the conductive layers (4a~4c) via the contact layer 30 embedded in the high-potential side contact hole 28. The low-potential surface electrode 33 is electrically connected to the conductive layers (7a, 7b) via the contact layer 31 embedded in the low-potential side contact hole 29. The materials for the high-potential surface electrode 32 and the low-potential surface electrode 33 are metals that react with the materials of the conductive layers (4a-4c, 7a, 7b) to form compounds. Specifically, these are metals such as titanium (Ti), molybdenum (Mo), nickel (Ni), and tungsten (W), which bond with the conductive layers (4a-4c, 7a, 7b) to form silicides. The surface electrodes can be formed using sputtering, electron beam (EB) deposition, or atomic layer deposition (ALD).

[0073] Through the above steps, the 100A capacitor is completed.

[0074] According to the manufacturing method of capacitor 100A according to the second embodiment, the same effects and advantages as in the first embodiment can be obtained, as well as the following effects and advantages.

[0075] Because electrodes (high-potential surface electrode 32 and low-potential surface electrode 33) are arranged on both sides of the substrate 1 (the first main surface 1F side and the second main surface 1R side), the capacitor 100A can be easily mounted on a module or the like.

[0076] Furthermore, the contact layer 30 is in contact with the high-potential surface electrode 32 and the conductive layers (4a to 4c), and when viewed from the direction normal to the first main surface 1F, they overlap each other. The contact layer 31 is in contact with the low-potential surface electrode 33 and the conductive layers (7a, 7b), and when viewed from the direction normal to the first main surface 1F, they overlap each other. Because the contact layers 30 and 31 are located close to the high-potential surface electrode 32 and the low-potential surface electrode 33, respectively, the lengths of the high-potential surface electrode 32 and the low-potential surface electrode 33 can be minimized, and the equivalent series resistance (ESR) can be reduced.

[0077] (Third embodiment) In the first and second embodiments, examples were shown where the contact layer material and the materials of the high-potential surface electrode and low-potential surface electrode were the same. However, as shown in the capacitor 100B in Figure 6, these may be made of different materials.

[0078] The capacitor 100B comprises a high-potential surface electrode 35A (first electrode) embedded in a high-potential opening 15 formed on the first main surface 1F, and a low-potential surface electrode 35B (second electrode) embedded in a low-potential opening 13 formed on the first main surface 1F. The high-potential surface electrode 35A is electrically connected to the conductive layers (4a to 4c). The low-potential surface electrode 35B is electrically connected to the conductive layers (7a, 7b) and the substrate 1, which are not electrically connected to the high-potential surface electrode 35A. In this embodiment, the case where the high-potential surface electrode corresponds to the first electrode and the high-potential surface electrode corresponds to the second electrode is shown, but the reverse may also be true.

[0079] The high-potential surface electrode 35A is in contact with the contact layer 34A on the side of the high-potential opening 15 and is electrically connected to the conductive layers (4a to 4c) via the contact layer 34A. The low-potential surface electrode 35B is in contact with the contact layer 34B on the side of the low-potential opening 13 and is electrically connected to the conductive layers (7a, 7b) via the contact layer 34B.

[0080] The contact layer 34A is made of a metal that contacts the conductive layers (4a-4c) and reacts with the materials of the conductive layers (4a-4c) to form a compound. The contact layer 34B is made of a metal that contacts the conductive layers (7a, 7b) and reacts with the materials of the conductive layers (7a, 7b) to form a compound; for example, aluminum (Al) can be used.

[0081] Contact layers 34A and 34B can be formed by depositing the contact layer material on the bottom and sides of the high-potential opening 15 and the low-potential opening 13, respectively, and inside the high-potential contact hole 17 and the low-potential contact hole 18, and then removing the contact layer material deposited on the bottom and sides of the high-potential opening 15 and the low-potential opening 13, respectively.

[0082] The high-potential surface electrode 35A and the low-potential surface electrode 35B are made of a material with a higher melting point than the contact layer 34A and the contact layer 34B, and for example, nickel (Ni), gold (Au), or platinum (Pt) can be used. By using a material with a higher melting point than the contact layer 34A and the contact layer 34B for the high-potential surface electrode 35A and the low-potential surface electrode 35B, when a short-circuit current flows, the high-potential surface electrode 35A and the low-potential surface electrode 35B are less likely to melt, and only the metal atoms constituting the contact layer 34A and the contact layer 34B are attracted to the conductive layer side, so that when a short circuit occurs, a melted section can be easily formed inside the contact layer 34A and the contact layer 34B.

[0083] Similar to the first embodiment, contact layers 34A and 34B function as microfuses. Furthermore, the substrate 1, conductive layer 4a, conductive layer 7a, conductive layer 4b, conductive layer 7b, conductive layer 4c, and dielectric layer 3 are the same as in the first embodiment, and the basic operation and manufacturing method of capacitor 100B are also the same as in the first embodiment, so further explanation is omitted.

[0084] According to the capacitor 100B of the third embodiment, the same effects and advantages as in the first embodiment can be obtained, as well as the following effects and advantages.

[0085] By forming the high-potential surface electrode 35A and the low-potential surface electrode 35B using materials with a higher melting point than the contact layer 34A and the contact layer 34B, a fused section can be easily formed inside the contact layer 34A and the contact layer 34B when a short circuit occurs.

[0086] (Other embodiments)

[0087] The embodiments described above are examples of ways in which the present invention can be implemented. Therefore, the present invention is not limited to the embodiments described above, and it goes without saying that various modifications can be made to other embodiments, as long as they do not depart from the technical spirit of the present invention, depending on the design and other factors. [Explanation of Symbols]

[0088] 1 circuit board 1st Floor, Main Panel Round 1, Main Field 2 2 grooves 2I Inner Self 3 Dielectric layer 4a, 4b, 4c, 7a, 7b conductive layer 17, 28 High-potential side contact holes 18, 29 Low-voltage side contact holes Contact layers 20, 21, 30, 31, 34A, 34B 23, 32, 35A high potential surface electrode 24, 33, 35B Low potential surface electrode 100, 100A, 100B capacitors

Claims

1. A substrate having a first main surface, a second main surface opposite to the first main surface, and a groove formed on the first main surface, At least two or more dielectric layers and two or more conductive layers are alternately stacked on the inner surface of the groove, A first electrode formed on the first main surface, the first electrode being electrically connected to at least one of the conductive layers, A second electrode formed on the first main surface or the second main surface, the second electrode being electrically connected to at least one of the conductive layers that is not electrically connected to the first electrode, The invention comprises a first electrode and a plurality of first contact layers disposed between each of the plurality of conductive layers electrically connected to the first electrode, The plurality of first contact layers are made of a metal that contacts the conductive layer and reacts with the material of the conductive layer to form a compound. Viewed from the direction normal to the first main surface, each of the plurality of first contact layers is superimposed on one another. Capacitor.

2. A substrate having a first main surface, a second main surface opposite to the first main surface, and a groove formed on the first main surface, At least two or more dielectric layers and two or more conductive layers are alternately stacked on the inner surface of the groove, A first electrode formed on the first main surface, the first electrode being electrically connected to at least one of the conductive layers, A second electrode formed on the first main surface or the second main surface, the second electrode being electrically connected to at least one of the conductive layers that is not electrically connected to the first electrode, A first contact layer disposed between the first electrode and a first conductive layer which is at least one of the conductive layers electrically connected to the first electrode, The device comprises a second contact layer disposed between the second electrode and a second conductive layer which is at least one of the conductive layers electrically connected to the second electrode, The first contact layer is in contact with the first conductive layer and is made of a metal that reacts with the material of the first conductive layer to form a compound. The second contact layer is in contact with the second conductive layer and is made of a metal that reacts with the material of the second conductive layer to form a compound. Capacitor.

3. A substrate having a first main surface, a second main surface opposite to the first main surface, and a groove formed on the first main surface, At least two or more dielectric layers and two or more conductive layers are alternately stacked on the inner surface of the groove, A first electrode formed on the first main surface, the first electrode being electrically connected to at least one of the conductive layers, A second electrode formed on the first main surface or the second main surface, the second electrode being electrically connected to at least one of the conductive layers that is not electrically connected to the first electrode, The device comprises a first electrode and a first contact layer disposed between the first electrode and at least one of the conductive layers electrically connected to the first electrode, The first contact layer is in contact with the first conductive layer and is made of a metal that reacts with the material of the first conductive layer to form a compound. Viewed from the direction normal to the first main surface, the first contact layer surrounds the groove. Capacitor.

4. A substrate having a first main surface, a second main surface opposite to the first main surface, and a groove formed on the first main surface, At least two or more dielectric layers and two or more conductive layers are alternately stacked on the inner surface of the groove, A first electrode formed on the first main surface, the first electrode being electrically connected to at least one of the conductive layers, A second electrode formed on the first main surface or the second main surface, the second electrode being electrically connected to at least one of the conductive layers that is not electrically connected to the first electrode, The device comprises a first electrode and a first contact layer disposed between the first electrode and at least one of the conductive layers electrically connected to the first electrode, The first contact layer is in contact with the first conductive layer and is made of a metal that reacts with the material of the first conductive layer to form a compound. The substrate is insulating, Capacitor.

5. The capacitor according to any one of claims 1 to 4, wherein the thickness of the first contact layer is smaller than the thickness of the first electrode.

6. The capacitor according to any one of claims 1 to 5, wherein the first electrode is made of a material with a higher melting point than the first contact layer.

7. The capacitor according to any one of claims 1 to 6, wherein the groove penetrates between the first main surface and the second main surface.

8. The capacitor according to any one of claims 1 to 7, wherein the conductive layer is made of polysilicon.

9. The capacitor according to any one of claims 1 to 8, wherein the compound is a silicide.

10. The capacitor according to any one of claims 1 to 3, 5 to 9, wherein the substrate is conductive.

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