Semiconductor device, power converter, and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device with an SBD incorporated, in which the decrease in I2t tolerance is suppressed.SOLUTION: A semiconductor device includes a drift layer of a first conductivity type, a well layer of a second conductivity type, a source layer of the first conductivity type, a gate electrode, an interlayer insulating film, and a source electrode. A plurality of body diodes including the well layer and the drift layer at a position not overlapping with the gate electrode in a plan view includes a first operation unit that operates at a first body diode operation voltage, and a plurality of second operation units that operate at a second body diode operation voltage, which is lower than the first body diode operation voltage.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to semiconductor technology. [Background technology]

[0002] In power electronics equipment, insulated-gate semiconductor devices such as insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used as switching elements to control the power supply to loads such as motors.

[0003] On the other hand, MOSFETs or IGBTs using wide-bandgap semiconductors such as silicon carbide (SiC) are attracting attention as next-generation switching elements, and their application to technological fields handling high voltages of around 1kV or higher is considered promising.

[0004] Examples of wide-bandgap semiconductors include SiC, as well as gallium nitride (GaN)-based materials and diamond.

[0005] SiC-MOSFETs have a parasitic body diode (BD) that acts in the opposite direction to the MOSFET, and there is a known technology for MOSFETs with a built-in Schottky barrier diode (SBD) that allows reverse current to flow without operating the BD (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] International Publication No. 2018 / 139556 [Overview of the Initiative]

Problems to be Solved by the Invention

[0007] In a MOSFET with an integrated SBD, when a large current called surge current flows, it is required not to be destroyed for a certain period of time. The tolerance for not being destroyed for this certain period of time is called the I2t tolerance. However, when an SBD is integrated to make it difficult to energize the body diode, the unipolar conduction ability is improved but it affects the I2t tolerance, and the I2t tolerance may decrease.

[0008] The technology disclosed in the present specification is made in view of the problems described above, and is a technology for suppressing a decrease in the I2t tolerance in a semiconductor device with an integrated SBD.

Means for Solving the Problems

[0009] A semiconductor device, which is a first aspect of the technology disclosed in the present specification, includes a drift layer of a first conductivity type, a plurality of well layers of a second conductivity type partially formed on the surface layer of the drift layer, a source layer of the first conductivity type partially formed on the surface layer of each of the well layers, a gate electrode that contacts the well layer sandwiched between the drift layer and the source layer through a gate insulating film, an interlayer insulating film provided to cover the gate electrode, and a source electrode provided to cover the interlayer insulating film, the well layer, and the source layer. Direct contact A plurality of body diodes composed of the well layer and the drift layer at a position where the gate electrode does not overlap in a plan view include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. Furthermore, the width between the well layers in the first operating section is wider than the width between the well layers in the second operating section. .

Advantages of the Invention

[0010] According to at least the first aspect of the technology disclosed in the present specification, a decrease in the I2t tolerance can be suppressed.

[0011] In addition, the objectives, features, aspects, and advantages related to the technology disclosed in the specification of the present application will become even clearer with the detailed description and the accompanying drawings shown below.

Brief Description of the Drawings

[0012] [Figure 1] It is a plan view of a semiconductor device, which is a MOSFET with an embedded SBD using SiC, seen from above. [Figure 2] It is a plan view describing an example of the configuration of mainly the silicon carbide semiconductor portion in the plan view of FIG. 1. [Figure 3] It is a plan view describing an example of the configuration of mainly the silicon carbide semiconductor portion in the plan view of FIG. 1. [Figure 4] It is a cross-sectional view showing an example of the structure of a MOSFET with an embedded SBD in the active region of FIG. 2 or FIG. 3. [Figure 5] It is a cross-sectional view showing an example of the structure of a silicon carbide semiconductor device related to an embodiment. [Figure 6] It is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device related to an embodiment. [Figure 7] It is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device related to an embodiment. [Figure 8] It is a plan view describing an example of the configuration of mainly the silicon carbide semiconductor portion in the top view of FIG. 1. [Figure 9] It is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device related to an embodiment. [Figure 10] It is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device related to an embodiment. [Figure 11] It is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device related to an embodiment. <L [Figure 12] It is a diagram showing an example of the gate voltage-drain current characteristics of a MOSFET with an embedded SBD. [Figure 13] It is a diagram showing an example of the drain voltage-drain current characteristics of a MOSFET with an embedded SBD. [Figure 14] It is a diagram showing an example of the manufacturing method of a silicon carbide semiconductor device related to an embodiment. [Figure 15] This figure shows an example of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 16] This figure shows an example of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 17] This figure shows an example of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 18] This figure shows an example of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 19] This figure shows an example of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 20] This figure shows an example of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 21] This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the embodiment is applied. [Modes for carrying out the invention]

[0013] The embodiments will be described below with reference to the attached drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are illustrative, and not all of them are necessarily essential features for the embodiments to be implementable.

[0014] Please note that the drawings are for illustrative purposes only, and for the sake of clarity, some components may be omitted or simplified as appropriate. Furthermore, the relative sizes and positions of components shown in different drawings are not necessarily accurately represented and may be modified as appropriate. In addition, hatching may be used in drawings other than cross-sectional views, such as plan views, to facilitate understanding of the embodiment.

[0015] Furthermore, in the following explanations, similar components will be denoted by the same symbols, and their names and functions will also be the same. Therefore, detailed explanations of them may be omitted to avoid redundancy.

[0016] Furthermore, in the descriptions contained in this specification, when a certain component is described as "equipped with," "includes," or "has," unless otherwise specified, it is not an exclusive expression that excludes the existence of other components.

[0017] Furthermore, even if ordinal numbers such as "first" or "second" are used in the descriptions contained herein, these terms are used for convenience to facilitate understanding of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0018] Furthermore, even if terms such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back" are used in the descriptions of this specification to indicate a specific position or direction, these terms are used for convenience to facilitate understanding of the embodiments and are not related to the actual position or direction in which the embodiments are carried out.

[0019] Furthermore, in the descriptions contained herein, when a "top surface of..." or "bottom surface of..." is used, it includes not only the top surface or bottom surface of the component in question itself, but also the state in which other components are formed on the top surface or bottom surface of the component in question. That is, for example, when it is stated that "B is provided on the top surface of A", this does not preclude the presence of another component "C" between A and B.

[0020] <First Embodiment> In the following explanation, n and p represent the conductivity types of semiconductors, with the first conductivity type being described as n-type and the second conductivity type as p-type. However, the first conductivity type may be described as p-type and the second conductivity type as n-type.

[0021] Also, n - This indicates that the impurity concentration is lower than n, and n + This indicates that the impurity concentration is higher than n. Similarly, p - This indicates that the impurity concentration is lower than p, and p + This indicates that the impurity concentration is higher than p.

[0022] The embodiments will be described below with reference to the attached drawings. Note that the drawings are schematic representations, and the relative sizes and positions of images shown in different drawings are not necessarily precisely represented and may be modified as appropriate. Furthermore, in the following description, similar components will be denoted by the same reference numerals, and their names and functions will also be the same. Therefore, detailed explanations of these components may be omitted.

[0023] The semiconductor device according to this embodiment will be described below. For the sake of explanation, the inventor will first describe the technology related to the configuration of an SBD-embedded MOSFET that he is familiar with.

[0024] <About the configuration of semiconductor devices> SiC has many crystalline polymorphs. Crystalline polymorphism is based on differences in the arrangement of atoms that make up the crystal, and SiC crystals with different crystalline polymorphs exhibit different physical properties.

[0025] Generally, semiconductor devices used for power control utilize a 4H-SiC crystal polymorph. However, it is difficult to construct a SiC crystal using only one crystal type, and other crystal types may be mixed in during crystal growth. This is called a stacking fault.

[0026] A pn diode called a body diode is parasitic between the drain and source of a MOSFET used for power control. This allows for reverse operation, where a positive voltage is applied to the source electrode, in addition to forward operation, where a positive voltage is applied to the drain electrode.

[0027] By using such body diodes, it is possible to reduce the number of freewheeling diodes placed in parallel with the MOSFET, thereby reducing the number of elements in the circuit.

[0028] While a MOSFET is a unipolar element in which only electrons or holes flow, a pn diode is a bipolar element in which both flow simultaneously. It is known that when SiC operates bipolar, the stacking faults described above are expanded by the recombination energy of electron-hole pairs.

[0029] Since stacking faults in 4H-SiC crystals behave as high resistivity, the expansion of crystal faults leads to an increase in device resistance. Therefore, when connecting a MOSFET and an SBD in parallel, it is necessary to design the SBD so that the MOSFET's body diode does not operate within the range of the current used; in other words, the generated voltage does not fall below the turn-on voltage of the body diode.

[0030] Therefore, SBD-integrated MOSFET technology has been developed, which incorporates an SBD within the SiC-MOSFET and directs the reverse current through the SBD instead of the body diode.

[0031] Figure 1 is a top view of a semiconductor device, which is a SiC-based SBD-integrated MOSFET. In Figure 1, a gate pad 81 is formed on a portion of the top surface of the SBD-integrated MOSFET, and a source electrode 8 is formed adjacent to the gate pad 81. In addition, a gate wiring 82 is formed extending from the gate pad 81.

[0032] Figure 2 is a plan view illustrating an example of the configuration of the silicon carbide semiconductor portion of the plan view in Figure 1. The semiconductor device shown as an example in Figure 2 has unit cell regions arranged in a stripe pattern, with MOSFET regions formed on both sides of an SBD region, and is also called a "stripe type".

[0033] In Figure 2, unit cell regions consisting of n-type separated regions 10 roughly corresponding to SBDs and p-type well layers 3 roughly corresponding to MOSFETs are repeatedly arranged in one direction in a plan view on the drift layer 2. The region in which the SBD-integrated MOSFET is formed is called the active region, and the region formed on the outer periphery of the active region, including the region where the gate pad 81 (see Figure 1) with p-type well layers 31 etc. is formed, is called the termination region.

[0034] Figure 3 is a plan view illustrating an example of the configuration of the silicon carbide semiconductor portion, primarily, of the plan view in Figure 1. The semiconductor device shown as an example in Figure 3 is a "lattice type" in which unit cell regions, each with a MOSFET region surrounding an SBD region, are repeatedly arranged vertically and horizontally in a plan view.

[0035] In Figure 3, unit cell regions consisting of n-type separated regions 10 roughly corresponding to SBDs and p-type well layers 3 roughly corresponding to MOSFETs are repeatedly arranged in the vertical and horizontal directions in a plan view on the drift layer 2. The region in which the SBD-integrated MOSFET is formed is called the active region, and the region formed on the outer periphery of the active region, including the region in which the gate pad 81, which has p-type well layers 31, etc., is formed, is called the termination region.

[0036] Figure 4 is a cross-sectional view showing an example of the structure of an SBD-integrated MOSFET in the active region of Figure 2 or Figure 3.

[0037] As shown in Figure 4, an example of an SBD-integrated MOSFET comprises an n-type semiconductor substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type semiconductor substrate 1, a plurality of p-type well layers 3 partially formed on the surface of the n-type drift layer 2, an n-type source layer 4 formed on the surface of the p-type well layer 3, a p-type contact region 42 partially formed on the surface of the p-type well layer 3 with a higher impurity concentration than the p-type well layer 3, a gate electrode 7 facing the upper surface of the p-type well layer 3 sandwiched between the n-type drift layer 2 and the n-type source layer 4 via a gate insulating film 5, an interlayer insulating film 6 formed covering the upper and side surfaces of the gate electrode 7, a source electrode 8 formed covering the interlayer insulating film 6, the n-type drift layer 2, the p-type well layer 3, the n-type source layer 4, and the p-type contact region 42, and a drain electrode 9 formed on the lower surface of the n-type semiconductor substrate 1. The region between the p-type well layers 3 at a position that does not overlap with the gate electrode 7 in a plan view is defined as an n-type separated region 10. Furthermore, in the case of Figure 4, it is shown that the stacking fault 11 is formed across multiple p-type well layers 3.

[0038] Here, the SBD is formed by an n-type separated region 10 and a source electrode 8. The body diode is formed by a p-type well layer 3 and an n-type drift layer 2.

[0039] Because SBDs are unipolar devices, they do not cause stacking fault expansion like body diodes do. Unlike SBDs located outside the MOSFET, integrated SBDs share an n-type drift layer 2 with the body diode.

[0040] As a result, the voltage across the SBD and the voltage across the body diode become equal, so the rise voltage of the body diode in an SBD-integrated MOSFET is higher than that of a body diode parasitic on a normal MOSFET. In other words, an SBD-integrated MOSFET can handle more SBD current than a normal MOSFET and SBD connected in parallel.

[0041] If a current surge flows through an SBD, it can overheat and potentially be destroyed. To increase its I2t withstand voltage, which is its resistance to this current surge, a structure called a junction barrier controlled Schottky diode (JBS) is used, in which a pn diode is connected in parallel with the SBD.

[0042] The SBD in a JBS has a low rise voltage, while the pn diode in a JBS has a high rise voltage. This allows the SBD to operate during normal operation, while the pn diode operates when a current surge flows, reducing the generated voltage and preventing damage. In particular, the operating voltage of this pn diode decreases at high temperatures, so the JBS has a higher I2t withstand voltage than a normal SBD.

[0043] Even in MOSFETs with built-in SBDs, the body diode functions similarly to the pn diode in JBS. That is, when a certain current surge occurs, the body diode activates, the generated voltage decreases, and the current path switches from the built-in SBD to the body diode.

[0044] However, the inventors discovered that the histogram of the body diode operating voltage (the voltage at which the body diode operates) of a MOSFET with an integrated SBD has multiple peaks, and that this is caused by the stacking faults mentioned above.

[0045] As illustrated in Figure 4, some stacking faults 11 have already reached the surface of the n-type drift layer 2 after epitaxial growth. These high-resistance stacking faults 11 then block the interleaved region 10, which is the built-in SBD, causing the parallel relationship between the body diode and the built-in SBD to be locally dissolved, and the operating voltage of the body diode in that region to decrease.

[0046] Consequently, the electron-hole pairs generated by the operation of the body diode diffuse into the surrounding area, triggering a chain reaction of body diode operation. Therefore, the region where the body diode operates occupies a certain area. Surge current concentrates in this region, resulting in thermal breakdown even at small current values. In particular, in modules where many semiconductor chips are connected in parallel, most of the current concentrates on the chip where the body diode operating voltage has dropped, further reducing the overall I2t withstand voltage.

[0047] On the other hand, it was found that when comparing cases with and without stacking faults, the former sometimes exhibits a higher I2t withstand voltage. When a semiconductor chip does not contain stacking faults, the operating voltage of the body diode increases, leading to increased heat generation at the same current value and a lower I2t withstand voltage. When there are few stacking faults in the semiconductor chip, although the operating voltage of the body diode decreases, the current density at the stacking fault area becomes excessively high, further lowering the I2t withstand voltage. When there are many stacking faults, body diode operation occurs at multiple locations, dispersing the current and making it less likely to reach a current density that causes thermal breakdown, thus increasing the I2t withstand voltage. The location or number of stacking faults manifests as variations in the I2t withstand voltage of power modules.

[0048] Figure 5 is a cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to this embodiment. In the following description, an SBD-integrated MOSFET is used as the silicon carbide semiconductor device, but any device in which a Schottky junction and a pn junction are connected in parallel may be used, such as a JBS.

[0049] As shown in Figure 5 as an example, an SBD-integrated MOSFET comprises an n-type semiconductor substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type semiconductor substrate 1, a plurality of p-type well layers 3 partially formed on the surface of the n-type drift layer 2, a p-type well layer 3A partially formed on the surface of the n-type drift layer 2, an n-type source layer 4 formed on the surface of the p-type well layer 3 and the surface of the p-type well layer 3A, and a p-type contact region with a higher impurity concentration than the p-type well layer 3, partially formed on the surface of the p-type well layer 3 and the surface of the p-type well layer 3A. The semiconductor substrate 1 comprises a region 42, a gate electrode 7 facing the upper surface of a p-type well layer 3 sandwiched between an n-type drift layer 2 and an n-type source layer 4, and the upper surface of a p-type well layer 3A sandwiched between an n-type drift layer 2 and an n-type source layer 4 via a gate insulating film 5, an interlayer insulating film 6 formed covering the upper and side surfaces of the gate electrode 7, a source electrode 8 formed covering the interlayer insulating film 6, the n-type drift layer 2, the p-type well layer 3, the p-type well layer 3A, the n-type source layer 4, and the p-type contact region 42, and a drain electrode 9 formed on the lower surface of the n-type semiconductor substrate 1. The region between the p-type well layer 3 at a position that does not overlap with the gate electrode 7 in a plan view is defined as a separated region 10. The contact resistance of the contact region 42 on the surface of the p-type well layer 3 is higher than the contact resistance of the contact region 42 on the surface of the p-type well layer 3A.

[0050] The width of the p-type well layer 3A is formed to be wider than the width of the p-type well layer 3. In addition, n-type source layers 4 are formed on the surface of the p-type well layer 3A, facing each of the multiple gate electrodes 7. That is, the p-type well layer 3A is formed to fill the spaced region 10 between the p-type well layers 3 and functions as a body diode operating structure.

[0051] As described above, in power modules where SBD-integrated MOSFETs are connected in parallel, the I2t withstand capability varies depending on the number of stacking faults inherent in the semiconductor chip. In particular, when the number of stacking faults is small, the I2t withstand capability drops drastically, raising concerns about failure during use.

[0052] To solve this, there should be multiple locations within the semiconductor chip where body diode operation occurs. In other words, in the silicon carbide semiconductor device according to this embodiment, a body diode operation structure is provided, which is a structure that causes body diode operation, in order to lower the body diode operating voltage.

[0053] The body diode operating structure only needs to satisfy one of the following conditions: the rise voltage of the body diode is lower than that of the stacking fault region, or the linear resistance of the body diode is lower, or both.

[0054] First, to lower the rise voltage of the body diode, you need to reduce the voltage drop across the SBD (Screen Diode).

[0055] For example, the p-type well layer 3A shown in Figure 5 has the separated region 10 blocked by a p-type impurity layer. This breaks the parallel state between the Schottky junction and the pn junction, causing the body diode operating voltage in this region to decrease. In other words, the second operating section, which has a body diode operating structure, has a lower body diode operating voltage compared to the first operating section, which is a normal section without a body diode operating structure.

[0056] Figure 6 is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to this embodiment.

[0057] As shown in Figure 6 as an example, an SBD-integrated MOSFET comprises an n-type semiconductor substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type semiconductor substrate 1, a plurality of p-type well layers 3 partially formed on the surface of the n-type drift layer 2, a p-type well layer 3B partially formed on the surface of the n-type drift layer 2, an n-type source layer 4 formed on the surface of the p-type well layer 3 and the surface of the p-type well layer 3B, and a p-type contact region with a higher impurity concentration than the p-type well layer 3, partially formed on the surface of the p-type well layer 3 and the surface of the p-type well layer 3B. The device comprises a gate electrode 7 facing the upper surface of a p-type well layer 3 sandwiched between an n-type drift layer 2 and an n-type source layer 4, and the upper surface of a p-type well layer 3B sandwiched between an n-type drift layer 2 and an n-type source layer 4, via a gate insulating film 5; an interlayer insulating film 6 formed to cover the upper and side surfaces of the gate electrode 7; a source electrode 8 formed to cover the interlayer insulating film 6, the n-type drift layer 2, the p-type well layer 3, the p-type well layer 3B, the n-type source layer 4, and the p-type contact region 42; and a drain electrode 9 formed on the lower surface of the n-type semiconductor substrate 1. The region between the p-type well layers 3 at positions that do not overlap with the gate electrode 7 in a plan view is defined as a separated region 10. The region between the p-type well layers 3B is defined as a separated region 100.

[0058] The width of the p-type well layer 3B is formed to be wider than the width of the p-type well layer 3. However, the width of the p-type well layer 3B may be the same as the width of the p-type well layer 3. Also, the spacing between p-type well layers 3B is narrower than the spacing between p-type well layers 3. That is, the separated region 100 at a position that does not overlap with the gate electrode 7 formed by multiple p-type well layers 3B in a plan view is narrower than the separated region 10, and functions as a body diode operating structure with a lower body diode operating voltage than the body diode operation formed by the well layer 3 and the drift layer 2 in the separated region 10. Here, the difference in work function between the drift layer 2 and the source electrode 8 that are in Schottky contact in the separated region 10 is higher than the difference in work function between the drift layer 2 and the source electrode 8 that are in Schottky contact at the location where the p-type well layer 3B is formed. Also, the lifetime of electrons flowing from the source electrode 8 to the drain electrode 9 in the separated region 10 is lower than the lifetime of electrons flowing from the source electrode 8 to the drain electrode 9 at the location where the p-type well layer 3B is formed.

[0059] Even without closing the n-type separated region 10 as shown in the example body diode operating structure in Figure 5, it is sufficient to arrange multiple p-type well layers 3B at narrower intervals than the normal first operating section, as shown in the example in Figure 6.

[0060] Figure 7 is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to this embodiment.

[0061] As shown in Figure 7 as an example, an SBD-integrated MOSFET comprises an n-type semiconductor substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type semiconductor substrate 1, multiple p-type well layers 3 partially formed on the surface of the n-type drift layer 2, multiple n-type doped layers 14 partially formed on other surfaces of the n-type drift layer 2, in which the n-type drift layer 2 is doped with n-type impurities, an n-type source layer 4 formed on the surface of the p-type well layer 3, and a p-type well layer 3 partially formed on the surface of the p-type well layer 3. The semiconductor device comprises a gate electrode 7 facing a p-type well layer 3 sandwiched between a p-type doped layer 14 and an n-type source layer 4, via a gate insulating film 5; an interlayer insulating film 6 formed to cover the top and sides of the gate electrode 7; a source electrode 8 formed to cover the interlayer insulating film 6, an n-type drift layer 2, a p-type well layer 3, an n-type source layer 4, an n-type doped layer 14 and a p-type contact layer 42; and a drain electrode 9 formed on the bottom surface of the n-type semiconductor substrate 1. In the region between the p-type well layer 3 at a position that does not overlap with the gate electrode 7 in a plan view, the region where the n-type doped layer 14 is formed is defined as the separated region 10, and the region where the n-type doped layer 14 is not formed is defined as the separated region 101.

[0062] The n-type doped layer 14 is formed by doping the n-type drift layer 2 with n-type impurities (such as ions), and the concentration of n-type impurities in the n-type doped layer 14 is higher than the concentration of impurities in the n-type drift layer 2.

[0063] In a structure like the example shown in Figure 7, the n-type drift layer 2 has a lower impurity concentration than the n-type doped layer 14, so the area where the n-type drift layer 2 is formed (separated region 101) functions as a body diode operating structure.

[0064] The change from the structure exemplified in Figure 4 to the structure exemplified in Figures 5, 6, or 7 can be carried out simply by partially changing the mask used when forming the p-type well layer 3 or the mask used when forming the n-type doped layer 14, and does not involve an increase in manufacturing costs.

[0065] Alternatively, the second operating part may be formed by locally using a metal in which the Schottky barrier height is smaller than that of the first operating part, which is the normal portion.

[0066] By using these techniques, it is possible to create a structure in which the turn-on voltage of the body diode is locally low.

[0067] On the other hand, to lower the linear resistance of the body diode, one can either reduce the resistance of the region where the p-type well layer 3 and the source electrode 8 are in contact (the contact region) in Figure 4 (by providing a p-type contact region 42), or increase the lifetime locally.

[0068] Similar to the case where stacking faults are formed as described above, body diode operation propagates from the body diode operating structure to a certain range. Therefore, the size of the body diode operating structure to be formed should be, for example, 10 μm or more and 500 μm or less.

[0069] Figure 8 is a plan view illustrating an example of the configuration of the silicon carbide semiconductor portion, mainly, of the top view of Figure 1. In the semiconductor device shown as an example in Figure 8, in the active region, striped gate trenches GT (grooves 102 described later) and striped Schottky trenches ST (grooves 102 described later), on which transistors are formed, are arranged alternately and parallel to each other. A p-type well layer 3 is formed in the terminal region surrounding the active region.

[0070] Figure 9 is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to this embodiment. Figure 9 shows the structure of the SBD-integrated MOSFET in the active region of Figure 8.

[0071] As shown in Figure 9, an SBD-integrated MOSFET comprises an n-type semiconductor substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type semiconductor substrate 1, a plurality of p-type well layers 3 partially formed on the surface of the n-type drift layer 2, a plurality of grooves 102 formed extending from the upper surface of the p-type well layer 3 into the n-type drift layer 2, a p-type field relaxation layer 16 formed on one bottom surface of the grooves 102 facing the n-type drift layer 2, an n-type source layer 40 partially formed on the surface of the p-type well layer 3, with a p-type contact region 43 having a higher impurity concentration than the p-type well layer 3, and within some of the grooves 102. The semiconductor substrate 1 comprises a gate insulating film 50 formed in contact with the side and bottom surfaces, a gate electrode 70 in a groove 102 facing the side surface of a p-type well layer 3 sandwiched between an n-type drift layer 2 and an n-type source layer 40 via the gate insulating film 50, a p-type field relaxation layer 16A continuously formed across the bottom surface of the multiple grooves 102 on which the gate electrode 70 is formed, facing the n-type drift layer 2, an interlayer insulating film 60 formed covering the upper surface of the gate electrode 70, a source electrode 8 formed covering the interlayer insulating film 60, the p-type well layer 3, the n-type source layer 40, the p-type contact region 43, the field relaxation layer 16, and the p-type field relaxation layer 16A, and a drain electrode 9 formed on the lower surface of the n-type semiconductor substrate 1. Here, the region between the p-type field relaxation layers 16 is defined as the separated region 10A.

[0072] The width of the p-type field relaxation layer 16A is formed to be wider than the width of the p-type field relaxation layer 16. The p-type field relaxation layer 16A is formed to fill the spaced region 10A between the p-type field relaxation layers 16 and functions as a body diode operating structure.

[0073] Furthermore, although this depends on the size of the semiconductor chip, the number of parallel connections, or the current value, multiple body diode operating structures may be provided within the semiconductor chip.

[0074] On the other hand, due to its nature, the body diode operating structure inevitably generates body diode current even under normal conditions (except when surge currents occur). While body diode current causes stacking fault expansion, the body diode operating region created by the body diode operating structure is limited to approximately several hundred micrometers. Therefore, even if stacking faults expand within this region, fluctuations in the overall characteristics of the semiconductor chip are sufficiently suppressed.

[0075] While Figures 4, 5, 6, and 7 illustrate a planar-type SBD-integrated MOSFET, the structure of this embodiment is also applicable to trench-type SBD-integrated MOSFETs, as shown in Figure 9 as an example.

[0076] In trench-type SBD-integrated MOSFETs, a p-type field relaxation layer 16 is often provided to mitigate the electric field applied to the bottom of the groove 102. In addition to the body diode formed by the p-type well layer and n-type drift layer 2 in planar-type SBD-integrated MOSFETs, it is also necessary to address the body diode formed by the p-type field relaxation layer 16 and n-type drift layer 2.

[0077] Depending on the impurity concentration of the field relaxation layer 16, or how the field relaxation layer 16 is connected to the source electrode 8, in most cases the body diode current flows around the body diode formed by the p-type well layer 3 and the n-type drift layer 2.

[0078] In a trench-type SBD-integrated MOSFET, there are three possible locations for the integrated MOSFET. The first is to create a separation region in the p-type well layer 3 between the grooves 102; the second is to create a separation region in the field relaxation layer 16; and the third is to use the space between the p-type well layer 3 on the side of the groove 102 and the field relaxation layer 16 as the separation region. However, the third method is undesirable because it requires a wider trench width.

[0079] In the first and second methods, stacking faults are formed to block the separation regions, and in the third method, stacking faults are formed to block the spaces between the field relaxation layers 16, which can lead to a decrease in the body diode operating voltage similar to that of a planar diode.

[0080] The body diode operating structure for this can also be the same as that used in planar type SBD-integrated MOSFETs. In the first method, the same measures as for the planar type (see body diode operating structure in Figure 9) are sufficient. In the second and third methods, the p-type well layer can be replaced with the field relaxation layer 16.

[0081] Figure 10 is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to this embodiment.

[0082] As shown in Figure 10, an SBD-integrated MOSFET comprises an n-type semiconductor substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type semiconductor substrate 1, a plurality of p-type well layers 3 partially formed on the surface of the n-type drift layer 2, a plurality of grooves 102 formed extending from the upper surface of the p-type well layer 3 into the n-type drift layer 2, a p-type field relaxation layer 16 formed on one bottom surface of the grooves 102 facing the n-type drift layer 2, an n-type source layer 40 partially formed on the surface of the p-type well layer 3, with a p-type contact region 43 having a higher impurity concentration than the p-type well layer 3, and the interior of some of the grooves 102 The semiconductor substrate 1 comprises a gate insulating film 50 formed in contact with the side and bottom surfaces, a gate electrode 70 in a groove 102 facing the side surface of a p-type well layer 3 sandwiched between an n-type drift layer 2 and an n-type source layer 40 via the gate insulating film 50, a p-type field relaxation layer 16B discontinuously formed across the bottom surface of a plurality of grooves 102 on which the gate electrode 70 is formed, facing the n-type drift layer 2, an interlayer insulating film 60 formed to cover the upper surface of the gate electrode 70, a source electrode 8 formed to cover the interlayer insulating film 60, the p-type well layer 3, the n-type source layer 40, the p-type contact region 43, the field relaxation layer 16, and the p-type field relaxation layer 16B, and a drain electrode 9 formed on the lower surface of the n-type semiconductor substrate 1.

[0083] The p-type field relaxation layers 16B that span the bottom surfaces of multiple grooves 102 are arranged such that the spacing between the field relaxation layers 16B (spacing regions 100A) is narrower than the spacing between the multiple field relaxation layers 16 (spacing regions 10A). In other words, the p-type field relaxation layers 16B function as a body diode operating structure.

[0084] Figure 11 is a cross-sectional view showing another example of the structure of a silicon carbide semiconductor device according to this embodiment.

[0085] As shown in Figure 11 as an example, the SBD-integrated MOSFET comprises an n-type semiconductor substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type semiconductor substrate 1, a plurality of p-type well layers 3 partially formed on the surface of the n-type drift layer 2, a plurality of n-type doped layers 14A partially formed on other surface layers of the n-type drift layer 2, in which the n-type drift layer 2 is doped with n-type impurities, a plurality of grooves 102 formed extending from the upper surface of the p-type well layer 3 into the n-type drift layer 2 and the n-type doped layers 14A, a p-type field relaxation layer 16 formed on one bottom surface of the groove 102 facing the n-type drift layer 2 side, and a plurality of n-type impurities partially formed on the surface of the p-type well layer 3, sandwiching the grooves 102. The semiconductor comprises a source layer 40, a p-type contact region 43 partially formed on the surface of the p-type well layer 3 with a higher impurity concentration than the p-type well layer 3, a gate insulating film 50 formed in contact with the side and bottom surfaces inside a portion of the groove 102, a gate electrode 70 in the groove 102 facing the side of the p-type well layer 3 sandwiched between the n-type doped layer 14A and the n-type source layer 40 via the gate insulating film 50, an interlayer insulating film 60 formed covering the upper surface of the gate electrode 70, a source electrode 8 formed covering the interlayer insulating film 60, the p-type well layer 3, the n-type source layer 40, the p-type contact region 43, and the field relaxation layer 16, and a drain electrode 9 formed on the lower surface of the n-type semiconductor substrate 1. Here, the region where the n-type doped layer 14A is formed between the p-type field relaxation layers 16 is defined as the separated region 10A, and the region where the n-type doped layer 14A is not partially formed between the p-type field relaxation layers 16 is defined as the separated region 101A.

[0086] The n-type doped layer 14A is a layer formed by doping the n-type drift layer 2 with n-type impurities (such as ions), and the concentration of n-type impurities is higher than the concentration of impurities in the n-type drift layer 2.

[0087] In a structure like the example shown in Figure 11, the n-type drift layer 2 has a lower impurity concentration than the n-type doped layer 14A, so the area where the n-type drift layer 2 is formed (separated region 101A) functions as a body diode operating structure.

[0088] <Second Embodiment> A semiconductor device according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0089] <About the configuration of semiconductor devices> In the first embodiment, a first operating section and a second operating section with different body diode operating voltages are formed in the SBD-integrated MOSFET to lower the body diode operating voltage of the semiconductor chip. Alternatively, stacking faults may be used as the body diode operating structure.

[0090] Specifically, by selecting only those body diodes with low operating voltages and modularizing them, the variation in the I2t withstand voltage of the modules can be improved.

[0091] The reason for variations in the I2t withstand voltage of modules is that semiconductor chips with different body diode operating voltages are connected in parallel. In other words, by pre-inspecting the semiconductor chips used in the module and selecting those with lower body diode operating voltages, the variations in the I2t withstand voltage of modules can be improved.

[0092] In this case, the stacking faults must be contained within the MOSFET region. Specifically, the stacking faults exist planarly from one p-type well layer 3 to an adjacent p-type well layer 3, blocking the separated region, thereby reducing the body diode operating voltage at the stacking fault portion. Furthermore, the body diode operating structure described in the first embodiment may or may not be used.

[0093] The body diode operating voltage can be determined by measurement at the chip level. However, due to the nature of MOSFETs with integrated SBDs, the body diode is less likely to move, and measurement at high temperature and high current density is required to confirm the body diode operating voltage.

[0094] Alternatively, a method may be used to select the body diode operating voltage based on other electrical characteristics.

[0095] For example, in a MOSFET with an integrated SBD, stacking faults that reduce the body diode operating voltage can also affect the gate-source electrical characteristics. Depending on the structure of the p-type well layer of the MOSFET with an integrated SBD, the gate voltage-drain current characteristics may be sluggish, as exemplified in Figure 12. This is due to the same type of stacking faults that reduce the body diode operating voltage. Here, Figure 12 shows an example of the gate voltage-drain current characteristics of a MOSFET with an integrated SBD. In Figure 12, the vertical axis represents the drain current and the horizontal axis represents the gate voltage. In the example in Figure 12, the gate voltage Vg1a at drain current Id1 (see dotted line) is lower than the gate voltage Vg1 at drain current Id1 (see solid line) of a MOSFET with an integrated SBD that does not have stacking faults that reduce the body diode operating voltage.

[0096] Therefore, the gate voltage Vg1 when a certain drain current Id1 flows decreases to Vg1a if the SBD-integrated MOSFET contains stacking faults. In this way, by comparing the gate voltages of SBD-integrated MOSFETs, it is possible to select semiconductor chips with low body diode operating voltages.

[0097] Furthermore, as illustrated in Figure 13, stacking faults also affect the breakdown voltage characteristics of SBD-integrated MOSFETs. The drain current value Id2 (see solid line) of an SBD-integrated MOSFET at a certain drain voltage Vd2 increases to Id2a (see dotted line) if stacking faults are present. Therefore, semiconductor chips with low body diode operating voltages can also be selected by measuring the drain current. Here, Figure 13 shows an example of the drain voltage-drain current characteristics of an SBD-integrated MOSFET. In Figure 13, the vertical axis represents the drain current and the horizontal axis represents the drain voltage.

[0098] These methods may be determined by the result of a single measurement, or by the difference or ratio of multiple different current and voltage measurements.

[0099] Alternatively, it is possible to inspect stacking faults at a stage after epitaxial growth using different methods. Since stacking faults have a different band gap than 4H-SiC, their in-plane position can be confirmed using methods such as photoluminescence. This can then be compared with the position of the semiconductor chip to select semiconductor chips containing stacking faults.

[0100] The stacking faults in the drift layer 2 are inspected using one of the methods described above, and several specific regions are identified where the number of stacking faults per unit area is below a predetermined threshold. Then, p-type impurities are ion-implanted into the surface of the drift layer 2, and the implanted impurities are diffused by heat treatment to lower the body diode operating voltage in the specified regions to a lower level than the body diode operating voltage in other regions.

[0101] Three methods have been described above, but one of them may be used alone, or a combination of several may be used for discrimination.

[0102] Based on the above, by selecting and using semiconductor chips with low body diode operating voltages, it is possible to improve the I2t withstand voltage variation of power modules.

[0103] <Third Embodiment> A method for manufacturing a semiconductor device according to this embodiment will now be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0104] <Regarding the manufacturing method of silicon carbide semiconductor devices (planar type)> Next, a method for manufacturing a MOSFET (planar type) with an embedded SBD, which is a silicon carbide semiconductor device of the present embodiment, will be described while referring to FIGS. 14 to 16. FIGS. 14 to 16 are diagrams showing an example of a method for manufacturing a silicon carbide semiconductor device according to the present embodiment.

[0105] First, on the upper surface of a semiconductor substrate 1 made of n-type, low-resistance silicon carbide having a (0001) plane with an off-angle on the surface orientation of the first main surface and having a 4H polytype, by chemical vapor deposition (that is, CVD) method, 1×10 15 cm -3 or more, and 17 cm -3 or less of an n-type impurity concentration, an epitaxial drift layer 2 made of silicon carbide with a thickness of 5 μm or more and 50 μm or less is grown.

[0106] Next, an implantation mask is formed in a predetermined region on the surface layer of the drift layer 2 using a photoresist or the like, and Al (aluminum), which is a p-type impurity, is ion-implanted. At this time, the depth of the Al ion implantation is set to be 0.5 μm or more and about 3 μm or less that does not exceed the thickness of the drift layer 2. Also, the impurity concentration of the ion-implanted Al is 1×10 17 cm -3 or more, and 19 cm -3 or less, and is made higher than the impurity concentration of the drift layer 2.

[0107] Thereafter, the implantation mask is removed. By this step, the region ion-implanted with Al ions becomes the well layer 3 and the well layer 3A in the active region, and becomes the well layer 31 in the termination region.

[0108] Next, an implantation mask is formed in the surface layer of the drift layer 2 in the termination region using a photoresist or the like, and Al with a p-type impurity concentration is ion-implanted. At this time, the depth of the Al ion implantation is set to be 0.5 μm or more and about 3 μm or less that does not exceed the thickness of the drift layer 2. Also, the impurity concentration of the ion-implanted Al is 1×10 16 cm-3 The above, and 1 × 10 18 cm -3 The following range applies, where the impurity concentration is higher than that of the drift layer 2 and lower than that of the well layer 3.

[0109] Subsequently, the injection mask is removed. This process results in a JTE region (not shown here) where Al has been ion-implanted.

[0110] Similarly, in a given region, a concentration higher than the impurity concentration of well layer 3 is 1 × 10⁻¹⁶. 16 cm -3 The above, and 1 × 10 18 cm -3 The contact region 42 is formed by ion implanting Al at the following impurity concentrations.

[0111] Next, an implantation mask is formed using photoresist or the like so that a predetermined location on the inside of the well layer 3 on the surface of the drift layer 2 is opened, and n-type impurity, nitrogen (N), is ion-implanted. The ion implantation depth of N is set to be shallower than the thickness of the well layer 3. The impurity concentration of the ion-implanted N is 1 × 10⁻⁶. 18 cm -3 The above, and 1 × 10 21 cm -3 The following range applies, and the concentration of p-type impurities exceeds that of well layer 3. Of the regions into which N is injected in this process, the n-type region becomes source layer 4.

[0112] Next, the material is annealed in an inert gas atmosphere, such as argon (Ar) gas, at a temperature of 1300°C or higher and 1900°C or lower, for 30 seconds or more and 1 hour or less, using a heat treatment apparatus. This annealing electrically activates the ion-implanted N and Al. Figure 14 shows the configuration of the active region after this ion implantation is complete.

[0113] Next, using CVD, photolithography, or other techniques, a field insulating film (not shown here) made of silicon oxide is formed on the semiconductor layer in the region excluding the active region which is roughly corresponding to the region where the well layer 3 is formed. The film thickness is 0.5 μm or more and 2 μm or less, and is thicker than the gate insulating film thickness.

[0114] Next, the upper surface of the silicon carbide not covered by the field insulating film is thermally oxidized to form a silicon oxide film, which is the gate insulating film 5, of the desired thickness. Then, a conductive polycrystalline silicon film is formed on the upper surfaces of the gate insulating film 5 and the field insulating film by vacuum CVD, and this is patterned to form the gate electrode 7. Next, an interlayer insulating film 6, which is thicker than the gate insulating film and made of silicon oxide, is formed by vacuum CVD. Figure 15 shows the configuration of the active region after the steps up to this stage.

[0115] Next, an active region contact hole is formed that penetrates the interlayer insulating film 6 and the gate insulating film 5 and reaches the source layer 4 within the active region.

[0116] Figure 16 shows the structure of the active region after the process up to this stage.

[0117] Next, a wiring metal such as Al is formed on the upper surface of the semiconductor substrate 1 by sputtering or vapor deposition, and the source electrode 8 is formed by processing it into a predetermined shape using photolithography technology. A drain electrode 9 is also formed on the lower surface of the semiconductor substrate 1. In this way, the silicon carbide semiconductor device shown in Figure 5 can be manufactured.

[0118] Next, we will explain the operation of the SBD-integrated MOSFET shown in Figure 5. Here, we will explain using a semiconductor device with 4H-type silicon carbide as the semiconductor material as an example. In this case, the diffusion potential of the pn junction is approximately 2V.

[0119] The operation of the SBD-integrated MOSFET in this embodiment will be briefly explained by dividing it into three states.

[0120] The first state is when a high voltage is applied to the drain electrode 9 relative to the source electrode 8, and a positive voltage above a threshold is applied to the gate electrode 7; this is hereafter referred to as the "on state". In this on state, an inversion channel is formed in the channel region, and a path is formed for electron carriers to flow from the n-type source layer 4 to the drift layer 2 directly below the gate electrode 7. On the other hand, no current flows between the separated region 10 and the source electrode 8. Electrons flowing from the source electrode 8 to the drain electrode 9 reach the drain electrode 9 via the electric field formed by the positive voltage applied to the drain electrode 9, passing through the source layer 4, the channel region, the drift layer 2, and the semiconductor substrate 1. Therefore, by applying a positive voltage to the gate electrode 7, an on current flows from the drain electrode 9 to the source electrode 8.

[0121] The voltage applied between the source electrode 8 and the drain electrode 9 at this time is called the on-voltage, and the value obtained by dividing the on-voltage by the density of the on-current is called the on-resistance, which is equal to the sum of the resistances of the paths through which the electrons flow. Since the product of the on-resistance and the square of the on-current is equal to the current loss consumed by the MOSFET when it is energized, a lower on-resistance is preferable.

[0122] The second state is when a high voltage is applied to the drain electrode 9 relative to the source electrode 8, and a voltage below the threshold is applied to the gate electrode 7; this is hereinafter referred to as the "off state". In this state, since there are no inversion carriers in the channel region, no on-current flows, and the high voltage that was applied to the load in the on state is applied between the source electrode 8 and the drain electrode 9 of the MOSFET. Ideally, no current flows between the separated region 10 and the source electrode 8, but since a much higher electric field is applied than in the "on state", leakage current can occur. If the leakage current is large, it can increase the heat generated by the MOSFET and cause thermal damage to the MOSFET and the module using the MOSFET, so it is preferable to keep the electric field applied to the Schottky junction low in order to reduce the leakage current.

[0123] The third state is when a low voltage is applied to the drain electrode 9 relative to the source electrode 8, i.e., a back electromotive force is applied to the MOSFET, and a freewheeling current flows from the source electrode 8 to the drain electrode 9. Hereafter, this state will be referred to as the "freewheeling state". In the freewheeling state, a forward electric field (forward bias) is applied between the separated region 10 and the source electrode 8, and a unipolar current consisting of electron current flows from the source electrode 8 to the n-type separated region 10. At this time, the freewheeling current component of the freewheeling diode is mainly this unipolar component.

[0124] Furthermore, the source electrode 8 and the well layer 3 are at the same potential. As a result, a forward bias is applied to the pn junction between the p-type well layer 3 and the drift layer 2. However, the pn junction is formed in parallel with the Schottky junction formed by the n-type separated region 10 and the source electrode 8. When transitioning from the off state to the freewheeling state, the Schottky junction, which has a lower threshold voltage, turns on before the pn junction. Therefore, the freewheeling current flows almost entirely through the Schottky junction and not through the pn junction.

[0125] In this way, by incorporating an SBD, it is possible to suppress the flow of forward current, which is a bipolar current, through the pn junction even in a freewheeling state.

[0126] When bipolar current flows through a pn junction, and a starting point such as a basal plane dislocation exists in such a location, stacking faults can expand, potentially reducing the transistor's breakdown voltage. Specifically, leakage current can occur when the transistor is off, and the heat generated by this leakage current can destroy the element or circuit.

[0127] However, by incorporating an SBD, it is possible to suppress the flow of bipolar current through the pn junction during reflux, thereby improving the reliability of the semiconductor device.

[0128] <Regarding the manufacturing method of silicon carbide semiconductor devices (trench type)> Next, the manufacturing method for the SBD-embedded MOSFET (trench type), which is a silicon carbide semiconductor device of this embodiment, will be described with reference to Figures 17 to 20. Figures 17 to 20 are diagrams showing examples of manufacturing methods for silicon carbide semiconductor devices according to this embodiment.

[0129] First, the surface orientation of the first main surface is an off-angle (0001) plane, and the upper surface of the semiconductor substrate 1, which is made of n-type, low-resistance silicon carbide with a 4H polytype, is subjected to chemical vapor deposition (CVD) by a method that produces 1 × 10 15 cm -3 The above, and 1 × 10 17 cm -3 A drift layer 2 made of silicon carbide with a thickness of 5 μm or more and 50 μm or less is epitaxially grown at the following n-type impurity concentrations.

[0130] Next, an implantation mask is formed in a predetermined area of ​​the surface layer of drift layer 2 using a photoresist or the like, and p-type impurity Al (aluminum) is ion-implanted. At this time, the depth of Al ion implantation is set to be between 0.5 μm and 3 μm, not exceeding the thickness of drift layer 2. The impurity concentration of the ion-implanted Al is 1 × 10⁻¹⁶. 17 cm -3 The above, and 1 × 10 19 cm -3 The following range applies, and the impurity concentration should be higher than that of drift layer 2.

[0131] Subsequently, the injection mask is removed. In this process, the Al ion-implanted region becomes well layer 3 in the active region and well layer 31 in the terminal region. Well layer 3 may be formed on the drift layer 2 by an epitaxial method.

[0132] Next, a solution with a concentration higher than the impurity concentration of well layer 3, 1 × 10⁻¹⁰, is added to a predetermined area of ​​the surface layer of well layer 3. 16 cm -3 The above, and 1 × 10 18 cm -3The contact region 43 is formed by ion implanting Al at the following impurity concentrations.

[0133] Furthermore, n-type impurities, such as nitrogen (N), are ion-implanted into a predetermined region inside the well layer 3 on the surface of the drift layer 2. The ion implantation depth of N is set to be shallower than the thickness of the well layer 3. The impurity concentration of the ion-implanted N is set to 1 × 10⁻⁶. 18 cm -3 The above, and 1 × 10 21 cm -3 The following range applies, and the concentration of p-type impurities exceeds that of well layer 3. Of the regions into which N is injected in this process, the n-type region becomes the source layer 40. Figure 17 shows the configuration of the active region at this stage.

[0134] Next, a groove 102 is formed in the area where the source layer 40 is formed, and then an electric field relaxation layer 16 is formed at the bottom of the groove 102 by ion implanting Al, which is a p-type impurity, into the bottom of the groove 102. The impurity concentration of the electric field relaxation layer 16 is 1 × 10⁻⁶. 17 cm -3 The above, and 1 × 10 19 cm -3 The following range is acceptable. In addition, for a portion of the groove 102 in which the gate electrode 70 will not be formed in a later step, the ion implantation amount and implantation direction (for example, oblique ion implantation) are adjusted so as to connect with the adjacent field relaxation layer, thereby forming a p-type field relaxation layer 16A that spans the bottom of multiple grooves 102.

[0135] Here, if the surface orientation of the first main surface of the semiconductor substrate 1 is a (0001) surface with an off-angle in the <11-20> direction, the grooves 102 in the active region should both be formed parallel to the <11-20> direction. In this way, the sides of the grooves 102 are no longer affected by the off-direction of the semiconductor substrate 1, thus reducing variations in the barrier height of the Schottky interface of the grooves 102. In addition, the threshold voltage of the MOSFET in the grooves 102 is no longer affected by the off-direction of the semiconductor substrate 1, thus reducing variations in the threshold voltage of the MOSFET.

[0136] Next, the material is annealed in an inert gas atmosphere, such as Ar gas, at a temperature of 1300°C or higher and 1900°C or lower, for 30 seconds or more and 1 hour or less, using a heat treatment apparatus. This annealing electrically activates the ion-implanted N and Al. Figure 18 shows the configuration of the active region at this stage.

[0137] Next, as shown in Figure 19, a protective insulating film 52, such as silicon dioxide, is filled into some of the grooves 102.

[0138] Next, the upper surface of the drift layer 2, which is not covered by the protective insulating film 52, is thermally oxidized to form a silicon oxide film, which is a gate insulating film 50 of a desired thickness. Then, a conductive polycrystalline silicon film is formed on the upper surface of the gate insulating film 50 by a reduced-pressure CVD method, and the gate electrode 70 is formed by patterning this film.

[0139] Next, an interlayer insulating film 60 made of silicon oxide, which is thicker than the gate insulating film 50, is formed by a reduced-pressure CVD method. Then, the interlayer insulating film 60 and the gate insulating film 50 are removed by wet etching so that the source layer 40 in the active region is exposed. Figure 20 shows the configuration of the active region after this ion implantation is completed.

[0140] Next, the protective insulating film 52 in the groove 102 is removed using hydrofluoric acid or the like. Then, a source electrode 8, mainly made of Al, is formed to cover the upper surface of the drift layer 2. The gate pad 81 and gate wiring 82 can also be formed at the same time as the source electrode 8.

[0141] Furthermore, a metal film drain electrode 9 is formed on the underside of the semiconductor substrate 1. In this way, the silicon carbide semiconductor device shown in Figure 9 can be manufactured.

[0142] Next, the operation of the SBD-integrated MOSFET shown in Figure 9 will be explained. The operation of the trench-type SBD-integrated MOSFET is the same as that of the planar-type SBD-integrated MOSFET in the "on state" and "off state".

[0143] Furthermore, in the freewheeling state, a low voltage is applied to the drain electrode 9 relative to the source electrode 8, i.e., a back electromotive force is applied to the MOSFET, and a freewheeling current flows from the source electrode 8 to the drain electrode 9. In the freewheeling state, a forward electric field (forward bias) is applied to the Schottky junction formed at the contact point between the drift layer 2 and the source electrode 8, and a unipolar current consisting of electron current flows from the source electrode 8 to the n-type drift layer 2. At this time, the freewheeling current component of the freewheeling diode is mainly this unipolar component.

[0144] The source electrode 8 and the well layer 3 are at the same potential. As a result, a forward bias is applied to the pn junction between the p-type well layer 3 and the drift layer 2. However, the pn junction is formed in parallel with the Schottky junction formed by the n-type separated region 10A and the source electrode 8. When transitioning from the off state to the freewheeling state, the Schottky junction, which has a lower threshold voltage, turns on before the pn junction. Therefore, the freewheeling current flows almost entirely through the Schottky junction and not through the pn junction.

[0145] In this way, by incorporating an SBD, it is possible to suppress the flow of forward current, which is a bipolar current, through the pn junction even in a freewheeling state.

[0146] When bipolar current flows through a pn junction, and a starting point such as a basal plane dislocation exists in such a location, stacking faults can expand, potentially reducing the transistor's breakdown voltage. Specifically, leakage current can occur when the transistor is off, and the heat generated by this leakage current can destroy the element or circuit.

[0147] However, by incorporating an SBD, it is possible to suppress the flow of bipolar current through the pn junction during reflux, thereby improving the reliability of the semiconductor device.

[0148] <Regarding the effects resulting from the multiple embodiments described above> Next, examples of the effects produced by the multiple embodiments described above will be shown. In the following description, the effects will be described based on the specific configurations illustrated in the multiple embodiments described above, but they may be replaced with other specific configurations illustrated in this specification to the extent that similar effects are produced. That is, for convenience, in the following, only one of the corresponding specific configurations may be described as representative, but the specific configuration described as representative may be replaced with other corresponding specific configurations.

[0149] Furthermore, such substitutions may be made across multiple embodiments. That is, the respective configurations exemplified in different embodiments may be combined to produce similar effects.

[0150] According to the embodiment described above, the semiconductor device comprises a drift layer 2 of a first conductivity type (n-type), a well layer 3 (or well layer 3A, well layer 3B) of a second conductivity type (p-type), an n-type source layer 4 (or source layer 40), a gate electrode 7 (or gate electrode 70), an interlayer insulating film 6 (or interlayer insulating film 60), and a source electrode 8. Multiple p-type well layers 3 are partially formed on the surface layer of the drift layer 2. The n-type source layer 4 is partially formed on the surface layer of each well layer 3. The gate electrode 7 contacts the well layer 3 sandwiched between the drift layer 2 and the source layer 4 via a gate insulating film 5 (or gate insulating film 50). The interlayer insulating film 6 is provided covering the gate electrode 7. The source electrode 8 is provided covering the interlayer insulating film 6, the well layer 3, and the source layer 4. Furthermore, a plurality of body diodes, each composed of a well layer 3 and a drift layer 2, located in positions that do not overlap with the gate electrode 7 in a plan view, include a first operating section (for example, the body diodes in the separated region 10 in Figure 6) that operates at a first body diode operating voltage, and a plurality of second operating sections (for example, the body diodes in the separated region 100 in Figure 6) that operate at a second body diode operating voltage lower than the first body diode operating voltage.

[0151] With this configuration, by providing multiple locations where the body diode operating voltage is lower than the area where stacking faults are formed, the body diode operating voltage across the entire semiconductor chip can be effectively reduced, thereby suppressing a decrease in I2t withstand voltage. Furthermore, even if a stacking fault occurs in the first operating section, the impact on the characteristics of the semiconductor device can be minimized. In addition, by including stacking faults with low body diode operating voltages, the body diode operating voltage across the entire semiconductor chip can be reduced, increasing the tolerable surge current. Therefore, the I2t withstand voltage of the semiconductor device can be increased, suppressing premature failure. If a MOSFET with an integrated SBD contains stacking faults, the SBD current path is blocked by the stacking fault in the area where the stacking fault exists, allowing the body diode operating voltage in this area to be reduced. Note that when bipolar current flows through a pn junction, there is a possibility that crystal defects such as stacking faults may expand. However, since the sequence time during which surge current flows is expected to be short, ranging from several hundred nanoseconds to several microseconds, expansion of crystal defects such as stacking faults is unlikely.

[0152] Furthermore, the same effect can be achieved even if other configurations exemplified in this specification are added to the above configuration as appropriate, that is, if other configurations in this specification that were not mentioned as the above configuration are added as appropriate.

[0153] Furthermore, according to the embodiments described above, the width between the well layers 3 in the first operating section is wider than the width between the well layers 3B in the second operating section. With this configuration, the separated region 100 formed by the multiple p-type well layers 3B becomes narrower than the separated region 10, and functions as a body diode operating structure, thereby effectively lowering the body diode operating voltage across the entire semiconductor chip and suppressing a decrease in I2t withstand voltage.

[0154] Furthermore, according to the embodiments described above, the width of the well layer 3 in the first operating section is narrower than the width of the well layer 3A in the second operating section. With this configuration, the p-type well layer 3A is formed to fill the spaced region 10 between the p-type well layers 3 and functions as a body diode operating structure, thereby effectively lowering the body diode operating voltage across the entire semiconductor chip and suppressing a decrease in I2t withstand voltage.

[0155] Furthermore, according to the embodiment described above, the semiconductor device includes a groove 102 formed extending from the upper surface of the source layer 40 to a position deeper than the well layer 3, and an electric field relaxation layer 16 (or electric field relaxation layer 16A, electric field relaxation layer 16B) formed at the bottom of the groove 102. The gate insulating film 50 is formed within the groove 102, covering the side surface of the well layer 3 sandwiched between the source layer 40 and the drift layer 2. The gate electrode 70 is also formed within the groove 102, surrounded by the gate insulating film 50. With this configuration, the body diode operating voltage across the entire trench-type semiconductor chip can be effectively reduced, thereby suppressing a decrease in I2t withstand voltage.

[0156] Furthermore, according to the embodiments described above, the width between the field relaxation layers 16 in the first operating section is wider than the width between the field relaxation layers 16B in the second operating section. With this configuration, the p-type field relaxation layer 16B functions as a body diode operating structure, thereby effectively lowering the body diode operating voltage across the entire semiconductor chip and suppressing a decrease in I2t withstand voltage.

[0157] Furthermore, according to the embodiments described above, the width of the electric field relaxation layer 16 in the first operating section is narrower than the width of the electric field relaxation layer 16A in the second operating section. With this configuration, the p-type electric field relaxation layer 16A is formed to fill the separation region 10A between the p-type electric field relaxation layers 16 and functions as a body diode operating structure, thereby effectively lowering the body diode operating voltage across the entire semiconductor chip and suppressing a decrease in I2t withstand voltage.

[0158] Furthermore, according to the embodiments described above, the impurity concentration of the drift layer 2 in the first operating section is higher than the impurity concentration of the drift layer 2 in the second operating section. With this configuration, since the impurity concentration of the n-type drift layer 2 is lower than that of the n-type doped layer 14, the location where the n-type drift layer 2 is formed functions as a body diode operating structure, thereby effectively lowering the body diode operating voltage across the entire semiconductor chip and suppressing a decrease in I2t withstand voltage.

[0159] Furthermore, according to the embodiments described above, the stacking faults are linear in a plan view in at least one of the first and second operating parts. The stacking fault density in the second operating part is lower than that in the first operating part (the second operating part does not necessarily have to contain stacking faults). With this configuration, the stacking faults exist in a planar manner and function as a body diode operating structure by blocking the separated regions, thereby effectively lowering the body diode operating voltage across the entire semiconductor chip and suppressing a decrease in I2t withstand voltage.

[0160] Furthermore, according to the embodiments described above, the semiconductor device includes a p-type contact region 42 (or contact region 43) partially formed on the surface layer of the well layer 3. The impurity concentration of the contact region 42 is higher than that of the well layer 3, and the contact resistance of the contact region 42 of the first operating part is higher than that of the contact region 42 of the second operating part. With such a configuration, the body diode operating voltage across the entire semiconductor chip can be effectively reduced, thereby suppressing a decrease in I2t withstand voltage.

[0161] Furthermore, according to the embodiments described above, the difference in work function between the drift layer 2 and the source electrode 8 that make Schottky contact in the first operating section is higher than the difference in work function between the drift layer 2 and the source electrode 8 that make Schottky contact in the second operating section. With such a configuration, the body diode operating voltage across the entire semiconductor chip can be effectively reduced, thereby suppressing a decrease in I2t withstand voltage.

[0162] Furthermore, according to the embodiments described above, the lifetime of electrons flowing from the source electrode 8 to the drain electrode 9 located on the lower surface side of the drift layer 2 opposite to the source electrode 8 in the first operating section is lower than the lifetime of electrons flowing from the source electrode 8 to the drain electrode 9 in the second operating section. With such a configuration, the body diode operating voltage across the entire semiconductor chip can be effectively reduced, thereby suppressing a decrease in I2t withstand voltage.

[0163] According to the embodiments described above, in the method for manufacturing a semiconductor device, an n-type drift layer 2 is formed by epitaxial growth. The stacking faults of the drift layer 2 are then inspected to identify a plurality of specific regions in which the number of stacking faults per unit area is below a predetermined threshold. Then, p-type impurities are ion-implanted into the surface layer of the drift layer 2. The implanted impurities are then diffused by heat treatment to make the body diode operating voltage in the plurality of specific regions lower than the body diode operating voltage in the regions other than the specific regions.

[0164] With this configuration, by providing multiple locations where the body diode operating voltage is lower than the area where stacking faults are formed, the body diode operating voltage across the entire semiconductor chip can be effectively reduced, thereby suppressing a decrease in I2t withstand capability.

[0165] Unless otherwise specified, the order in which each process is performed can be changed.

[0166] Furthermore, the same effect can be achieved even if other configurations exemplified in this specification are appropriately added to the above configuration, that is, if other configurations in this specification that are not mentioned as above configurations are appropriately added.

[0167] Furthermore, according to the embodiments described above, stacking faults are inspected by electrical property testing or photoluminescence testing. With such a configuration, it is possible to effectively identify specific regions where the number of stacking faults is below a predetermined threshold.

[0168] <Fourth Embodiment> This embodiment applies the semiconductor devices described in the first to third embodiments above to a power converter. Although this embodiment is not limited to a specific power converter, a fourth embodiment will be described below in which the above-mentioned semiconductor devices are applied to a three-phase inverter.

[0169] Figure 21 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0170] The power conversion system shown in Figure 21 consists of a power source 400, a power converter 200, and a load 300. The power source 400 is a DC power source and supplies DC power to the power converter 200. The power source 400 can be composed of various components, for example, a DC grid, a solar cell, or a battery, or it may be composed of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power source 400 may be composed of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0171] The power converter 200 is a three-phase inverter connected between the power supply 400 and the load 300. It converts the DC power supplied from the power supply 400 into AC power and supplies AC power to the load 300. As shown in Figure 21, the power converter 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202 to control the drive circuit 202.

[0172] Load 300 is a three-phase electric motor driven by AC power supplied from power converter 200. Note that Load 300 is not limited to a specific application; it is an electric motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0173] The details of the power converter 200 are described below. The main conversion circuit 201 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 400 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. A semiconductor device according to one of the embodiments described above is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0174] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203, which will be described later, it outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element. When the switching elements are kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching elements, and when the switching elements are kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching elements.

[0175] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state based on the power to be supplied to the load 300. For example, the main converter circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0176] In the power conversion device according to this embodiment, since the semiconductor devices described in Embodiments 1 to 3 are used as switching elements in the main conversion circuit 201, improved reliability can be achieved.

[0177] In this embodiment, an example of applying this technology to a two-level three-phase inverter has been described, but this technology is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used, and when supplying power to a single-phase load, this technology may be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, this technology can also be applied to a DC / DC converter or an AC / DC converter.

[0178] Furthermore, power conversion devices to which this technology is applied are not limited to cases where the load is an electric motor, but can also be used, for example, as power supply devices for electrical discharge machining equipment, laser processing machines, induction heating cookers, and non-contact power supply systems, and can even be used as power conditioners for solar power generation systems and energy storage systems.

[0179] <Modifications of the multiple embodiments described above> In the various embodiments described above, the material, dimensions, shape, relative arrangement, or implementation conditions of each component may also be described, but these are all examples and not limiting.

[0180] Accordingly, countless variations and equivalents not shown are envisioned within the scope of the art disclosed herein. These include, for example, modifications, additions, or omissions of at least one component, as well as the extraction of at least one component from at least one embodiment and its combination with a component from another embodiment.

[0181] Furthermore, in at least one embodiment described above, if a material name or the like is mentioned without further specification, it is assumed that the material includes other additives, such as an alloy, unless otherwise specified, to avoid any inconsistencies.

[0182] Furthermore, unless contradictory, when it is stated that "one" component is provided in the embodiments described above, "one or more" such components may be provided.

[0183] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component consists of multiple structures, where one component corresponds to a part of a structure, and where multiple components are provided in a single structure.

[0184] Furthermore, each component in the embodiments described above shall include structures having other structures or shapes, as long as they perform the same function.

[0185] Furthermore, the descriptions in this specification are referenced for all purposes related to the present technology and are not considered to be prior art.

[0186] The various aspects of this disclosure are summarized below as an appendix.

[0187] (Note 1) A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and a source electrode provided covering the source layer, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. Semiconductor equipment.

[0188] (Note 2) The semiconductor device described in Appendix 1, The width of the well layer in the first operating part is narrower than the width of the well layer in the second operating part. Semiconductor equipment.

[0189] (Note 3) A semiconductor device as described in Appendix 1 or 2, The width between the well layers in the first operating part is wider than the width between the well layers in the second operating part. Semiconductor equipment.

[0190] (Note 4) The semiconductor device described in Appendix 1, A groove formed extending from the upper surface of the source layer to a position deeper than the well layer, The groove further comprises an electric field relaxation layer formed at the bottom of the groove, The gate insulating film is formed within the groove, covering the side surface of the well layer sandwiched between the source layer and the drift layer. The gate electrode is formed within the groove, surrounded by the gate insulating film. Semiconductor equipment.

[0191] (Note 5) The semiconductor device is as described in Appendix 4. The width between the electric field relaxation layers in the first operating unit is wider than the width between the electric field relaxation layers in the second operating unit. Semiconductor equipment.

[0192] (Note 6) A semiconductor device as described in Appendix 4 or 5, The width of the electric field relaxation layer in the first operating unit is narrower than the width of the electric field relaxation layer in the second operating unit. Semiconductor equipment.

[0193] (Note 7) A semiconductor device described in any one of the appendices 1 to 6, The impurity concentration of the drift layer in the first operating unit is higher than the impurity concentration of the drift layer in the second operating unit. Semiconductor equipment.

[0194] (Note 8) A semiconductor device described in any one of the appendices 1 to 7, At least one of the first operating part and the second operating part includes a linear stacking fault in a plan view, The stacking fault density in the second operating part is lower than the stacking fault density in the first operating part. Semiconductor equipment.

[0195] (Note 9) A semiconductor device described in any one of the appendices 1 to 8, The well layer further comprises a second conductive contact region partially formed on its surface, The impurity concentration in the contact region is higher than the impurity concentration in the well layer. The contact resistance of the contact area of ​​the operating part Semiconductor equipment.

[0196] (Note 10) A semiconductor device described in any one of the appendices 1 to 9, In the first operating part, the difference in work function between the drift layer and the source electrode that are in Schottky contact is higher than the difference in work function between the drift layer and the source electrode that are in Schottky contact in the second operating part. Semiconductor equipment.

[0197] (Note 11) A semiconductor device described in any one of the appendices 1 to 10, In the first operating unit, the lifetime of electrons flowing from the source electrode toward the drain electrode located on the lower surface side of the drift layer opposite to the source electrode is lower than the lifetime of electrons flowing from the source electrode toward the drain electrode in the second operating unit. Semiconductor equipment.

[0198] (Note 12) A first conductive drift layer is formed by epitaxial growth. The stacking faults in the drift layer are inspected to identify a number of specific regions where the number of stacking faults per unit region is below a predetermined threshold. A second type of conductive impurity is ion-implanted into the surface layer of the drift layer. The injected impurities are diffused by heat treatment to make the body diode operating voltage in multiple specific regions lower than the body diode operating voltage in regions other than the specific regions. A method for manufacturing a semiconductor device.

[0199] (Note 13) The method for manufacturing a semiconductor device as described in Appendix 12, The stacking faults are inspected by electrical property testing or photoluminescence testing. A method for manufacturing a semiconductor device.

[0200] (Note 14) A semiconductor device described in any one of the appendices 1, 2, 4, and 5, comprising a main conversion circuit that converts and outputs the input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, The system includes a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit, Power converter. [Explanation of Symbols]

[0201] 1 Semiconductor substrate, 2 Drift layer, 3 Well layer, 3A Well layer, 3B Well layer, 4 Source layer, 5 Gate insulating film, 6 Interlayer insulating film, 7 Gate electrode, 8 Source electrode, 9 Drain electrode, 10 Separation region, 10A Separation region, 11 Stack fault, 14 Dope layer, 14A Dope layer, 16 Field relaxation layer, 16A Field relaxation layer, 16B Field relaxation layer, 31 Well layer, 40 Source layer, 52 Protective insulating film, 60 Interlayer insulating film, 70 Gate electrode, 71 Schottky electrode, 81 Gate pad, 82 Gate wiring, 90 Active region contact hole, 91 Termination region contact hole, 95 Gate contact hole, 102 Groove, GT Gate trench, Id1 Drain current, Id2 Drain current value, ST Schottky trench, Vd2 Drain voltage, Vg1 Gate voltage, Vg1a Gate voltage, 200 Power converter, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load, 400 power supply.

Claims

1. A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and the source layer, and a source electrode provided in direct contact with and covering them, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. The width between the well layers in the first operating part is wider than the width between the well layers in the second operating part. Semiconductor equipment.

2. A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and a source electrode provided covering the source layer, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. A groove formed extending from the upper surface of the source layer to a position deeper than the well layer, The groove further comprises an electric field relaxation layer formed at the bottom of the groove, The gate insulating film is formed within the groove, covering the side surface of the well layer sandwiched between the source layer and the drift layer. The gate electrode is formed within the groove, surrounded by the gate insulating film. The width between the electric field relaxation layers in the first operating unit is wider than the width between the electric field relaxation layers in the second operating unit. Semiconductor equipment.

3. A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and a source electrode provided covering the source layer, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. The impurity concentration of the drift layer in the first operating unit is higher than the impurity concentration of the drift layer in the second operating unit. Semiconductor equipment.

4. A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and a source electrode provided covering the source layer, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. At least one of the first operating part and the second operating part includes a linear stacking fault in a plan view, The stacking fault density in the second operating part is lower than the stacking fault density in the first operating part. Semiconductor equipment.

5. A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and a source electrode provided covering the source layer, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. The well layer further comprises a second conductive contact region partially formed on its surface, The impurity concentration in the contact region is higher than the impurity concentration in the well layer. The contact resistance of the contact region of the first operating unit is higher than the contact resistance of the contact region of the second operating unit. Semiconductor equipment.

6. A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and a source electrode provided covering the source layer, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. In the first operating section, the difference in work function between the drift layer and the source electrode that are in Schottky contact is higher than the difference in work function between the drift layer and the source electrode that are in Schottky contact in the second operating section. Semiconductor equipment.

7. A first conductive drift layer, A second conductive well layer partially formed on the surface of the drift layer, A first conductive source layer partially formed on the surface of each of the aforementioned well layers, A gate electrode is in contact with the well layer sandwiched between the drift layer and the source layer via a gate insulating film, An interlayer insulating film provided covering the gate electrode, The system comprises the interlayer insulating film, the well layer, and a source electrode provided covering the source layer, A plurality of body diodes, each composed of the well layer and the drift layer, located at positions that do not overlap with the gate electrode in a plan view, include a first operating portion that operates at a first body diode operating voltage and a plurality of second operating portions that operate at a second body diode operating voltage lower than the first body diode operating voltage. In the first operating unit, the lifetime of electrons flowing from the source electrode toward the drain electrode located on the lower surface side of the drift layer opposite to the source electrode is lower than the lifetime of electrons flowing from the source electrode toward the drain electrode in the second operating unit. Semiconductor equipment.

8. A semiconductor device according to any one of claims 1, 3 to 7, The width of the well layer in the first operating part is narrower than the width of the well layer in the second operating part. Semiconductor equipment.

9. A semiconductor device according to any one of claims 3 to 7, A groove formed extending from the upper surface of the source layer to a position deeper than the well layer, The groove further comprises an electric field relaxation layer formed at the bottom of the groove, The gate insulating film is formed within the groove, covering the side surface of the well layer sandwiched between the source layer and the drift layer. The gate electrode is formed within the groove, surrounded by the gate insulating film. Semiconductor equipment.

10. The semiconductor device according to claim 2, The width of the electric field relaxation layer in the first operating unit is narrower than the width of the electric field relaxation layer in the second operating unit. Semiconductor equipment.

11. A first conductive drift layer is formed by epitaxial growth. The stacking faults in the drift layer are inspected to identify a number of specific regions where the number of stacking faults per unit region is below a predetermined threshold. A second conductive impurity is ion-implanted into the surface layer of the drift layer. The injected impurities are diffused by heat treatment to make the body diode operating voltage in multiple specific regions lower than the body diode operating voltage in regions other than the specific regions. A method for manufacturing a semiconductor device.

12. A method for manufacturing a semiconductor device according to claim 11, The stacking faults are inspected by electrical property testing or photoluminescence testing. A method for manufacturing a semiconductor device.

13. A semiconductor device according to any one of claims 1 to 7, comprising a main conversion circuit that converts and outputs input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, The system includes a control circuit that outputs a control signal to the drive circuit to control the drive circuit, Power converter.

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