Method for manufacturing a semiconductor structure having a working layer made from silicon carbide with improved electrical properties.

Abstract

The present invention relates to a method for manufacturing a semiconductor structure, the method comprising the steps of: a) providing a donor substrate made of single crystal silicon carbide and a carrier substrate made of silicon carbide; b) preparing an active layer to be transferred, - implanting light species in a donor substrate on its front side in order to form a damage profile that can be measured in particular by Rutherford backscattering spectrometry, said profile having a main peak of depth defects that define the embedded brittle plane and secondary peaks of defects that define the damaged surface layer; - removing the damaged surface layer by chemical etching and / or by chemical-mechanical polishing of the front surface of the donor substrate in order to form a new front surface of the donor substrate, the buried brittle surface together with the front surface of the donor substrate defining a transferred active layer having a thickness of 50 nm to 1400 nm, c) bonding the front side donor substrate and the carrier substrate by molecular adhesion to form a bonded assembly along a bonding interface; d) Separating along the buried brittle plane resulting in transfer of the working layer onto a carrier substrate to form a semiconductor structure.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor materials for microelectronics components. In particular, this invention relates to a method for manufacturing a semiconductor structure comprising a working layer made from single-crystal silicon carbide and transferred onto a carrier substrate made from silicon carbide via a bonding interface. This method makes it possible to improve the electrical properties of the working layer as well as the electrical properties of the semiconductor structure when vertical electrical conductivity is desired. [Background technology]

[0002] It is common to form semiconductor structures by transferring a thin, high-crystal-quality semiconductor working layer onto a semiconductor carrier substrate, advantageously, one with lower crystal-quality. One well-known thin-layer transfer solution is the Smart Cut® process, which is based on the injection of light species and bonding by molecular adhesion at the bonding interface. The light species are conventionally selected from hydrogen ions, helium ions, or a combination of these two species. Direct bonding by molecular adhesion can be achieved by various approaches, such as applying pressure to the substrate after bringing the surfaces to be bonded into close contact at ambient temperature, or at ambient or controlled temperatures, particularly in a vacuum, or simply by locally initiating a bonding wave when the surfaces to be bonded are positioned facing each other. The various direct bonding approaches can also be distinguished by the preliminary treatment of the surfaces to be bonded, which is performed immediately before bonding. Dry or wet chemical cleaning, plasma or atomic impact surface activation (e.g., SAB (Surface Activated Bonding), ADB (Atomic Diffusion Bonding), etc.), mechanical or chemical smoothing of the surface, or deposition of an additional layer that actually promotes bonding may be applied to one or both of the substrates to be bonded.

[0003] After transferring the working layer onto the carrier substrate, it is also common practice to apply high-temperature or very high-temperature annealing to the semiconductor structure to restore the structural and electrical quality of the working layer and bonding interface. It is also well known to perform thermal smoothing or chemical-mechanical polishing on the free surface of the transferred working layer, which is intended to house micro-electronic components, in order to obtain a low surface roughness.

[0004] In particular, in the field of power electronics, excellent conductivity of the working layer is expected. Furthermore, it may be advantageous to form a semiconductor structure that ensures good electrical conductivity between the working layer and the carrier substrate, enabling the fabrication of vertical components.

[0005] For example, in the case of a semiconductor structure comprising a working layer made from single-crystal silicon carbide and a carrier substrate made from low-quality (single-crystal or polycrystalline) silicon carbide, the electrical properties of the working layer are expected to follow Ohm's law, and the resistivity of the layer is defined by its doping level. To accommodate vertical components, vertical electrical conduction, i.e., that involving conduction across the bonding interface, is expected to be operable, meaning the resistivity of the bonding interface should be as low as possible, preferably 1 mohm.cm. 2 Less than, or 0.1 mohm.cm 2 It is less than ohms I(V) (current as a function of voltage) and exhibits characteristics of ohms.

[0006] The Smart Cut® process, which involves final restoration annealing applied to semiconductor structures, transfers a working layer made from single-crystal silicon carbide onto a carrier substrate also made from single-crystal silicon carbide via an intermediate metal layer, performed in the temperature range of 1300°C to 1700°C. However, as is evident in Figure 4(a), this is insufficient to obtain the aforementioned electrical properties: the electrical properties of the working layer and the I(V) curve representing the electrical properties of perpendicular electrical conduction (across the bonding interface) of the semiconductor structure do not satisfy the objective of ohmic behavior.

[0007] Naturally, annealing at higher temperatures, typically above 1800°C, can partially improve the electrical properties of the working layer and the semiconductor structure. However, such processing is particularly cumbersome to perform and can also introduce other types of undesirable crystalline defects, particularly step bunching, requiring additional steps to protect the surface to avoid these defects appearing, or additional steps to treat the surface later to remove them. [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] The present invention aims to overcome all or some of the aforementioned drawbacks. In particular, the present invention relates to a method for manufacturing a semiconductor structure, wherein the working layer is made from single-crystal silicon carbide and transferred via a bonding interface onto a carrier substrate made from silicon carbide, and the semiconductor structure has excellent electrical properties. The method according to the present invention further enables improvement of the vertical conductivity of the semiconductor structure, while simultaneously proposing a simple packaging process. [Means for solving the problem]

[0009] The present invention relates to a method for manufacturing a semiconductor structure, and the method includes the following steps. a) A step of providing a donor substrate made from single-crystal silicon carbide and a carrier substrate made from silicon carbide, b) A step of preparing the working layer to be transferred, - A step of injecting a light species into a donor substrate on a front surface in order to form a damage profile that can be specifically measured by Rutherford backscattering spectrometry, wherein the profile has a primary peak of depth defects defining an embedded brittle surface and a secondary peak of defects defining a damaged surface layer. - A step of removing a damaged surface layer from the front surface of a donor substrate by chemical etching and / or chemical mechanical polishing in order to form a new front surface of the donor substrate, wherein the embedded brittle surface, together with the front surface of the donor substrate, defines a range of a transferable working layer having a thickness of 50 nm to 1400 nm. c) A step of bonding a front side donor substrate and a carrier substrate by molecular adhesion in order to form an assembly bonded along the bonding interface. d) A process of separating along embedded brittle surfaces to form a semiconductor structure, resulting in the transfer of the working layer onto a carrier substrate.

[0010] Other advantageous and non-limiting features of the present invention allow for the following, individually or in any technically feasible combination: • Removal in step b) removes a layer of 5 nm to 200 nm, preferably 30 nm to 50 nm. The carrier substrate material is either single-crystal or polycrystalline. • Light species are hydrogen ions, with energies of 30 keV to 210 keV, and 1 × 10⁻¹⁶ 16 / cm 2 ~5×10 17 / cm 2 It is injected in the amount provided. The manufacturing method involves a finishing step e) applied to the semiconductor structure obtained from step d), but step e) involves heat treatment at a temperature of 1300°C to 1700°C. Step e) includes a chemical and mechanical smoothing treatment of the free surface of the working layer. Step c) comprises forming at least one additional layer on the front surface of the donor substrate and / or the front surface of the carrier substrate prior to bonding by molecular adhesion, wherein the bonded assembly obtained after bonding by molecular adhesion includes an additional layer between the donor substrate and the carrier substrate, the layer being adjacent to or including the bonding interface. -At least one-additional layer contains a material selected from silicon, tungsten, carbon, and titanium. · The method further includes a step of fabricating at least one high-voltage ultra-small electronic technology component on a semiconductor structure.

[0011] The present invention also relates to a high-voltage ultra-small electronic technology component fabricated on a semiconductor structure obtained by the above manufacturing method.

Brief Description of the Drawings

[0012] Other features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. [Figure 1] Shows a semiconductor structure fabricated according to the manufacturing method of the present invention. [Figure 2a] Shows the steps of the manufacturing method according to the present invention. [Figure 2b] Shows the steps of the manufacturing method according to the present invention. [Figure 2b-1] Shows the steps of the manufacturing method according to the present invention. [Figure 2c] Shows the steps of the manufacturing method according to the present invention. [Figure 2d] Shows the steps of the manufacturing method according to the present invention. [Figure 2e] Shows the steps of the manufacturing method according to the present invention. [Figure 3] Shows the Rutherford backscattering spectrometry (RBS) measurement values of an unused donor substrate and a donor substrate that has received a light species implantation in step d) of the manufacturing method according to the present invention, respectively. [Figure 4] Shows the I(V) curve of the current as a function of the applied voltage measured from two electrodes fabricated on a semiconductor structure. The current path crosses the bonding interface of the structure. (a) relates to a semiconductor structure of the prior art, and (b) relates to a semiconductor structure according to the present invention. [Figure 5](a) Transmission Electron Microscopy (TEM) image of a final semiconductor structure not according to the present invention, and (b) an image obtained by SSRM (Scanning Spread Resistance Microscope) resistance measurement of the final semiconductor structure not according to the present invention are shown.

[0013] The same reference numerals in the figures may be used for the same kind of elements. The figures are schematic diagrams and, for ease of reading, the scales are not accurate. In particular, the thickness of the layers along the z-axis line is not to the same scale as the horizontal dimensions along the x-axis and y-axis lines, and the relative thicknesses of the layers with respect to each other are not considered in the schematic diagrams.

[0014] Various possibilities (variations and embodiments illustrated and / or described in detail in the following description) are not mutually exclusive and should be understood to be combinable with each other.

Mode for Carrying Out the Invention

[0015] The present invention relates to a method for manufacturing a semiconductor structure 100 comprising an operating layer 10 made of single-crystalline silicon carbide (SiC) transferred onto a carrier substrate 2 (FIG. 1). The carrier substrate 2 can be formed from single-crystalline silicon carbide or polycrystalline silicon carbide.

[0016] The manufacturing method includes step a) providing a donor substrate 1 made from single-crystal silicon carbide and a carrier substrate 2 made from single-crystal silicon carbide or polycrystalline silicon carbide (Figure 2a). These two initial substrates 1, 2 are preferably wafers (in a plane (x, y)) with a diameter of 100 mm, 150 mm, or 200 mm and a thickness (along the z axis) of typically 300 to 800 microns. They have front surfaces 1a, 2a and back surfaces 1b, 2b, respectively. The surface roughness of the front surfaces 1a, 2a is advantageously selected to be less than 1 nm RMS, measured by atomic force microscopy (AFM) with a 20 micron × 20 micron scan.

[0017] The donor substrate 1 may be, for example, a 4H polytype (a crystalline multilayer repeating structure) or a 6H polytype and may have n-type or p-type doping. After the process, the working layer 10 of the semiconductor structure 100 is separated from the donor substrate 1, and therefore the donor substrate 1 should have the mechanical, electrical, and crystallographic properties required for the target application.

[0018] According to one particular embodiment, the donor substrate 1 includes an initial substrate on which a donor layer has been formed by epitaxy. The epitaxial growth process is performed such that the donor layer has a lower crystal defect density than the initial substrate. In this case, the working layer 10 is separated from the donor layer, so the initial substrate does not require a higher quality level than the donor layer.

[0019] The carrier substrate 2 must meet specifications regarding mechanical strength and, in some cases, specifications regarding electrical properties that enable good vertical electrical conductivity for the operation of vertical power components fabricated on and within the final semiconductor structure 100.

[0020] Next, the manufacturing method includes a consistent step b) for preparing the working layer 10 to be transferred. This step first includes injecting light species into the donor substrate 1 (or the donor layer, if one exists) on the front surface 1a to form an injection profile and a damage profile 11 (Figure 2b) of light species. These two profiles largely overlap, with the first profile corresponding to the concentration of the injected species due to the depth, and the other profile corresponding to defects generated within the crystal lattice of the SiC material of the donor substrate 1 as the species penetrates.

[0021] The damage profile 11 can be measured, in particular, by Rutherford backscatter spectroscopy (i.e., RBS). As is well known, RBS is used to determine the structure and composition of a material by analyzing the backscatter of a high-energy ion beam impacting the material. In this case, it becomes possible to reveal regions of defects present within the implanted SiC crystal lattice of the donor substrate 1.

[0022] Curve A in Figure 3 corresponds to the RBS measurement of donor substrate 1 before injection of light species, but the RBS profile is flat (except for a very narrow peak detected on front surface 1a, which appears on all measured samples and is therefore not specific).

[0023] Curve B in Figure 3 corresponds to the RBS measurement of the donor substrate 1 after injection of the light species. The damage profile 11 has a primary peak 12a of depth defects (substantially overlapping with the peak of the concentration of the injected light species) that defines the embedded brittle surface 12. The damage profile 11 also has a secondary peak 13a of defects that defines the damaged surface layer 13.

[0024] The light species to be implanted are preferably hydrogen, helium, or a co-implantation of these two species. Referring to the Smart Cut (registered trademark) process described in the introduction section, these light species form microvoids distributed in a thin layer parallel to the front surface 1a of the donor substrate 1, i.e., parallel to the plane (x, y) in the figure, at the main peak 12a and / or in the vicinity of the main peak 12a. For the sake of simplicity, this thin layer is called the embedded brittle plane 12.

[0025] The implantation energy of the light species is selected to reach a predetermined depth within the donor substrate 1. Typically, hydrogen ions are implanted at an energy of 30 keV to 210 keV to form an embedded brittle plane 12 at a depth of 100 nm to 1500 nm, with a dose of 1×10 16 / cm 2 ~5×10 17 / cm 2 .

[0026] As can be seen in Figure 3, the donor substrate 1 is expanded to a variable nm, which essentially means that the secondary peak 13a from the front surface 1a at a depth of 10 nm to 100 nm depends on the implantation conditions (energy, dose, temperature, etc.). This damaged surface layer 13 can particularly include local crystal defects, extended defects (dislocations, etc.), or species that are not intentionally introduced other than the implanted light species. The surface roughness of the donor substrate 1 on the implanted front surface 1a is not affected and remains substantially the same as the initial roughness, typically less than 1 nm RMS.

[0027] After ion-implanting the light species, step b) of preparing the active layer 10 includes removing the damaged surface layer 13 by chemical etching of the front surface 1a of the donor substrate 1 and / or by chemical mechanical polishing (Figure 2b-1).

[0028] Chemical etching is advantageously dry etching, such as reactive ion etching based on O2 / SF6 / Ar / F gas. Chemical mechanical polishing can be performed using a polishing solution (slurry) containing alumina-based or diamond-based nanoabrasives and conventional cloths of polyurethane or thermoplastic foam type.

[0029] Regardless of the technique used, the removal performed in step b) results in the exfoliation of SiC in the range of 5 nm to 200 nm, preferably 20 nm to 100 nm, and more preferably 30 nm to 50 nm. After this material is exfoliated, a new front surface 1a' of the donor substrate 1 is formed.

[0030] The objective is to remove the entire damaged surface layer 13 while maintaining good uniformity of the working layer 10 to be transferred. Specifically, the working layer 10 is defined after delamination by the embedded brittle surface 12 and the front surface 1a' of the donor substrate 1. A non-uniformity of less than + / - 20% in the thickness of the working layer 10 is targeted. The working layer 10 to be transferred typically has a thickness of 50 nm to 1400 nm.

[0031] Next, the manufacturing method includes step c), which involves bonding a donor substrate 1 on the side of its front surface 1a' to a carrier substrate 2 on the side of its front surface 2a by molecular adhesion in order to form an assembly 50 bonded along a bonding interface 51 (Figure 2c).

[0032] As is well known, direct bonding by molecular adhesion does not require adhesive materials because the bond between the bonding surfaces is established at the atomic scale. Several types of bonding by molecular adhesion exist, and they differ particularly in temperature, pressure, atmospheric conditions, or treatment prior to surface contact. Examples include bonding at room temperature with or without prior plasma activation of the surfaces to be bonded, atomic diffusion bonding (ADB), and surface activated bonding (SAB).

[0033] The bonding step c) may include a conventional sequence of chemical cleaning (e.g., RCA cleaning) and surface activation (e.g., by oxygen or nitrogen plasma) or other surface treatment (such as scrubbing cleaning) prior to bringing the surfaces to be bonded into contact, which may enhance the quality of the bonding interface 51 (low defect density, high bonding energy).

[0034] According to the first embodiment, as shown in Figure 2c, the front surface 1a' of the donor substrate 1 and the front surface 2a of the carrier substrate 2 are directly joined.

[0035] According to the second embodiment, step c) includes forming at least one additional layer (not shown) on the front surface 1a' of the donor substrate 1 and / or on the front surface 2a of the carrier substrate 2 prior to bonding by molecular adhesion. The at least one additional layer may include a material such as silicon, tungsten, carbon, or titanium, and is advantageously selected to promote perpendicular electrical conduction in the final semiconductor structure 100. Furthermore, the intermediate layer is likely to promote bonding by molecular adhesion, particularly by eliminating residual roughness or surface defects present on the surfaces to be bonded. Conventional planarization or smoothing treatments may be performed to achieve a roughness of less than 1 nm RMS or less than 0.5 nm RMS to promote bonding, and preliminary treatments such as those described above (cleaning, activation, etc.) may also be performed. The thickness of the additional layer is preferably selected to be between 0.5 nm and 50 nm.

[0036] The manufacturing method according to the present invention finally includes step d) separating along the embedded brittle surface 12 to form a semiconductor structure 100, resulting in the transfer of the working layer 10 onto the carrier substrate 2 (Figure 2d).

[0037] Separation along the embedded brittle surface 12 is typically performed by applying heat treatment at a temperature of 800°C to 1200°C. Such heat treatment induces voids and microcracks within the embedded brittle surface 12, which are pressurized by a gaseous light species until fracture propagates along the brittle surface 12. Alternatively or in conjunction, mechanical stress can be applied to the bonded assembly 50, particularly to the embedded brittle surface 12, to propagate or assist in the mechanical propagation of fracture leading to separation. As a result of this separation, a semiconductor structure 100 is obtained, comprising, on the one hand, a transferred working layer 3 fabricated from the carrier substrate 2 and single-crystal SiC, and on the other hand, the remaining portion 1'' of the donor substrate. The level and type of doping of the working layer 10 are defined by the selection of properties of the donor substrate 1 or can be adjusted later through well-known techniques for doping semiconductor layers.

[0038] The free surface 10a of the working layer 10 is typically rough after separation, for example, having a roughness of 5 nm to 100 nm RMS (AFM, 20 micron × 20 micron scan). To restore a good surface finish (typically a roughness of less than a few angstroms RMS with a 20 micron × 20 micron AFM scan), cleaning and / or smoothing steps may be applied.

[0039] This is particularly, preferably, the objective of finishing step e) included in the manufacturing method according to the present invention. This step, applied to the semiconductor structure 100 obtained from step d), may include chemical-mechanical smoothing (CMP) of the free surface 10a of the working layer 10. By peeling at 50 nm to 300 nm, it becomes possible to effectively restore the surface finish of the layer 10.

[0040] Step e) may also include a heat treatment at a temperature of 1300°C to 1700°C. Such a heat treatment is applied to remove residual light species from the working layer 10 and to promote the rearrangement of the crystal lattice of the working layer 10.

[0041] As mentioned in the introduction, if the finishing heat treatment is performed at a temperature below 1800°C, it is difficult to obtain good electrical properties of the working layer 10, which was conventionally transferred by injecting light species. In the embodiment shown in Figure 4(a), a semiconductor structure not according to the present invention is formed from a working layer made of single-crystal SiC (typical resistivity of about 20 mohm.cm), transferred onto a carrier substrate (typical resistivity of about 50 mohm.cm) via an additional metal layer, and the conditions under which injection into the donor substrate is performed are 130 keV, 6 × 10⁻¹⁰ 16 H / cm 2 The final heat treatment was performed at 1700°C for 1 hour. It can be seen that the I(V) behavior of this structure is not ohmic.

[0042] In the method according to the present invention, this heat treatment can be performed at a temperature of 1700°C or less, or 1400°C to 1500°C. In fact, on the I(V) curve in Figure 4(b), the perfect ohmic behavior of the working layer 10 and bonding interface 51 of the semiconductor structure 100 fabricated according to the present invention can be observed. The semiconductor structure is formed from a working layer 10 fabricated from single-crystal SiC (typical resistivity of about 20 mohm.cm), transferred onto a carrier substrate 2 (typical resistivity of about 20 mohm.cm) via an additional metal layer (a stack corresponding to the prior art structure described above with reference to Figure 4(a)), and injected into a donor substrate 1 (step b)) under conditions of 130 keV, 6 × 10⁻¹⁰ 16 H / cm 2 The removal of the damaged surface layer 13 (step b)) consisted of peeling it off by 50 nm using CMP, and the heat treatment in step e) was performed at 1700°C for 1 hour.

[0043] While annealing up to 1900°C can obviously be performed, it should be noted that these extremely high temperatures are not necessary to restore the electrical quality of the thin layer 10 in the method according to the present invention.

[0044] The applicant has confirmed that removing the damaged surface layer 13 generated during ion implantation in step b) preparing the working layer 10 to be transferred from the donor substrate 1 is important in order to maintain a reasonable finish heat treatment temperature while generally obtaining excellent electrical properties of the thin layer 10 and the semiconductor structure 100 after transfer.

[0045] If this damaged surface layer 13 is not removed during step b) of the method according to the present invention, it causes residual defects 13' in the thin layer of the final semiconductor structure, as shown in Figure 5(a): these residual defects 13' remain despite heat treatment at high temperatures up to 1700°C or 1900°C, as observed in this transmission electron microscope (TEM) image. SSRM (scanning spreading resistance microscopy, a technique for measuring resistance by scanning with the tip of an atomic force microscope) measurements, showing a region of higher resistivity near the bonding interface 51 of the semiconductor structure correlated with the region of residual defects 13', can also be seen in Figure 5(b). If the damaged surface layer 13 is not removed before bonding, the residual defects 13' present in the working layer 10 near the bonding interface 51 cause the non-ohmic electrical behavior of the semiconductor structure observed in Figure 4(a).

[0046] The manufacturing method according to the present invention provides for removing a damaged surface layer 13 generated by injecting light species into a donor substrate 1, thereby ensuring the high quality of the working layer 10 in the final semiconductor structure 100 and its ohmic electrical behavior.

[0047] The present invention also relates to one (or more) high-voltage miniature electronic components, such as Schottky diodes and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), which are fabricated on and / or within the semiconductor structure 100 obtained by the aforementioned manufacturing method. Although conventional processes for fabricating the components may be carried out, the semiconductor structure 100 is fully compatible with miniature electronic technology and miniature electron beams.

[0048] Naturally, the present invention is not limited to the embodiments and examples described, and modified embodiments may be added thereto without departing from the scope of the invention as defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure (100), a) A step of providing a donor substrate (1) made from single-crystal silicon carbide and a carrier substrate (2) made from silicon carbide, b) A step of preparing the working layer to be transferred, - A step of injecting a light species into the donor substrate (1) on a front surface (1a) to form a damage profile (11) which can be specifically measured by Rutherford backscattering spectrometry, wherein the profile has a primary peak (12a) of depth defects defining an embedded brittle surface (12) and a secondary peak (13a) of defects defining a damaged surface layer (13), - A step of removing the damaged surface layer (13) by chemical etching and / or chemical mechanical polishing of the front surface (1a) of the donor substrate (1) in order to form a new front surface (1a') of the donor substrate (1), wherein the embedded brittle surface (12), together with the front surface (1a') of the donor substrate (1), defines the range of the working layer (10) to be transferred, having a thickness of 50 nm to 1400 nm. c) A step of bonding the donor substrate (1) on the side of the front surface (1a') and the carrier substrate (2) by molecular adhesion in order to form an assembly (50) bonded along the bonding interface (51), d) A step of separating along the embedded brittle surface (12) to form the semiconductor structure (100) and bringing the working layer (10) onto the carrier substrate (2), A manufacturing method that includes this.

2. The manufacturing method according to claim 1, wherein the removal in step b) removes a layer of 5 nm to 200 nm, preferably 30 nm to 50 nm.

3. The manufacturing method according to claim 1 or 2, wherein the material of the carrier substrate (2) is a single crystal or a polycrystalline material.

4. The aforementioned light species is a hydrogen ion, and at an energy of 30 keV to 210 keV, 1 × 10⁻¹⁶ 16 / cm 2 ~5 x 10 17 / cm 2 The manufacturing method according to claim 1 or 2, wherein the injection is carried out in the amount supplied.

5. The manufacturing method according to claim 1 or 2, comprising a finishing step e) applied to the semiconductor structure (100) obtained from step d), wherein step e) involves heat treatment at a temperature of 1300°C to 1700°C.

6. The manufacturing method according to claim 5, wherein step e) includes a chemical and mechanical smoothing treatment of the free surface (10a) of the working layer (10).

7. - Step c) includes forming at least one additional layer on the front surface (1a') of the donor substrate (1) and / or on the front surface (2a) of the carrier substrate (2) prior to the bonding by molecular adhesion, - The manufacturing method according to claim 1 or 2, wherein the bonded assembly (50) obtained after bonding by molecular adhesion includes the additional layer between the donor substrate (1) and the carrier substrate (2), the layer being adjacent to or including the bonding interface (51).

8. The manufacturing method according to claim 7, wherein the at least one additional layer comprises a material selected from silicon, tungsten, carbon, and titanium.

9. The manufacturing method according to claim 1 or 2, further comprising the step of fabricating at least one high-voltage ultra-miniature electronic component on the semiconductor structure (100).

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