DC-DC converter output adjustment system and method

Abstract

To provide a system and method for adaptively controlling peak current in a DC-DC converter.SOLUTION: A DC-DC converter comprises: a controller 120 that receives an output voltage of a power stage 110 and adjusts a switching frequency of a converter in response to a state of an output load; and an output load sensing circuit 130 that determines the state of the output load and supplies a peak current to the controller. The output load sensing circuit contains a first timer that supplies a delayed first signal to a peak current controller in response to the output load being a heavy load. A second timer supplies a delayed second signal to the peak current controller in response to the output load being a light load. The peak current controller is configured to adjust the peak current on the basis of the received first and second signals, and supplies the peak current to the controller.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application generally relates to DC-DC converters, and more particularly, for example, to systems and methods for adaptive peak current control in DC-DC converters.

Background Art

[0002] Power converters such as DC-DC converters are used to supply power to many electronic devices. The amount of load drawn by these electronic devices can vary from device to device. An electronic device can be a light load that does not draw much current, while another electronic device can be a heavy load that draws substantially more current from the DC-DC converter. Further, the load can vary within the same device or between interconnected devices depending on usage and mode. When the load varies, the output of the DC-DC converter may cause voltage ripple or interference, which may adversely affect the performance of the device. From the above perspectives, there is a continuing need for improvement in DC-DC converters to reduce these and other negative effects.

Summary of the Invention

[0003] This disclosure describes an improved DC-DC converter, including an improved system and method for adjusting the output of the DC-DC converter. A circuit is described according to one embodiment of this disclosure. This circuit may include a control circuit configured to receive the output voltage of the converter and adjust the switching frequency of the converter in response to the state of the output load. The output load sensing circuit is configured to determine the state of the output load and supply a peak current to the control circuit. The output load sensing circuit includes a first timer configured to supply a delayed first signal to the peak current control in response to the output load being a heavy load; a second timer configured to supply a delayed second signal to the peak current control in response to the output load being a light load; and a peak current control configured to adjust the peak current based on the received first and second signals and supply a peak current to the control circuit.

[0004] A method is described in accordance with other embodiments of the present disclosure. This method may include measuring the timing between a first switching cycle of a converter and a second switching cycle of a converter; determining whether the second switching cycle begins before the end of a predetermined first time; and incrementing a peak current control in response to the determination that the second switching cycle begins before the end of a predetermined first time.

[0005] The scope of this disclosure is defined by the claims incorporated into this chapter by reference. A more complete understanding of the embodiments of this disclosure, as well as the realization of their additional advantages, can be obtained by considering the following detailed descriptions of one or more embodiments. An appendix of drawings, briefly described first, will be referenced. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram of an exemplary DC-DC converter according to one embodiment of the present disclosure.

[0007] [Figure 2] Figure 2 is a block diagram of an exemplary DC-DC converter illustrating the interconnections between various modules according to one embodiment of the present disclosure.

[0008] [Figure 3] Figure 3 is an exemplary circuit diagram of a load sensing circuit and a DC-DC converter control circuit according to one embodiment of the present disclosure.

[0009] [Figure 4] Figure 4 is an exemplary timing diagram showing various waveforms representing the transition of a DC-DC converter from a light load state to a heavy load state, according to one embodiment of the present disclosure.

[0010] [Figure 5] Figure 5 is an exemplary timing diagram showing various waveforms representing the transition of a DC-DC converter from a well-loaded state to a light-loaded state, according to one embodiment of the present disclosure.

[0011] [Figure 6] Figure 6 is an exemplary timing diagram showing various waveforms representing the transition of a DC-DC converter from a heavy load state to a light load state, according to one embodiment of the present disclosure.

[0012] [Figure 7] Figure 7 is an exemplary timing diagram showing various waveforms representing the transition of a DC-DC converter from a good-load state to a good-load state, according to one embodiment of the present disclosure.

[0013] [Figure 8] Figure 8 shows an example of a waveform for adaptive peak current control for adjusting the switching frequency according to one embodiment of the present disclosure.

[0014] Embodiments of this disclosure and their advantages are best understood by referring to the detailed description below. Unless otherwise stated, similar reference numbers throughout the accompanying drawings and written descriptions refer to similar elements; therefore, they are not described repeatedly. For clarity, the relative sizes of elements, layers, and areas may be emphasized in the drawings. [Modes for carrying out the invention]

[0015] Illustrative embodiments are described below with reference to the accompanying drawings. These examples, however, can be carried out in various different forms and should not be construed as being limited only to the embodiments shown herein. Rather, these embodiments are provided as examples so that the disclosure may be complete and perfect and to fully present to those skilled in the art aspects of the disclosure. For this reason, processes, elements, and techniques that are unnecessary for those skilled in the art to fully understand the aspects and features of the invention may not be described.

[0016] A DC-DC power converter ("converter") generally receives a first voltage and converts this voltage into a second voltage which is provided as an output voltage. For example, a converter may receive a 5V input voltage and provide a 1.5V output voltage. The output of the converter may be connected to a load which may include, for example, electronic devices such as music players, tablet devices, and mobile phones. Embodiments of this disclosure are intended to be techniques for monitoring the state of the output load (e.g., heavy load, light load, etc.) and adjusting the output voltage and switching frequency of the converter.

[0017] Figure 1 is a block diagram of an exemplary DC-DC converter 100 according to one embodiment of the present disclosure. In this example, the DC-DC converter 100 includes a power stage module 110, a controller module 120, and an output load sensing module 130. The power stage module 110 receives an input voltage (e.g., 5V DC) and converts it to another voltage (e.g., 1.5V DC) supplied as the output voltage from the converter 100. In various embodiments, the power stage module 110 may be, for example, a boost converter, a buck converter, or a buck-boost converter. However, those skilled in the art will be able to consider other types of power converters that may be implemented as the power stage module 110.

[0018] According to various embodiments, the output load sensing module 130 is configured to determine the load state of the converter 100 and supply this state information to the controller module 120. The controller module 120 then supplies feedback to the power stage module 110 to adjust the power conversion. In some embodiments, the controller module 120 may be a DC-DC converter controller for an asynchronous DCM or other controller.

[0019] The operation of the DC-DC converter 100 in Figure 1 will be described in further detail here in relation to the block diagram in Figure 2. The block diagram in Figure 2 further illustrates the interconnections between various modules according to one embodiment of this disclosure. As will be described in more detail later, the output load sensing module 130 determines the state of the output load and controls Ipeak_control <a:0>The controller module 120 is configured to receive a corresponding value via a signal such as the one shown. Based on this, the controller module 120 provides feedback to the power stage module 110 by supplying one or more feedback signals (for example, logic signals hs_on or ls_on) to the power stage module 110. In response, the power stage 110 is configured to adjust the peak current of the power stage module 110, thereby adjusting the power conversion.

[0020] Figure 3 shows an exemplary circuit diagram of a power stage, load sensing circuit, and DC-DC converter control circuit according to one embodiment of the present disclosure. Circuit 300 is configured to monitor the output load state of the DC-DC converter (DC-DC step-down converter) using a continuous-time timer of the DC-DC converter output load sensing circuit 310. Control circuit 350 (e.g., DC-DC converter control circuit of an asynchronous DCM) is configured to use this output load state information to perform adaptive peak current control so as to support higher output load capacity when the converter is heavily loaded and smaller output voltage ripple when the output load is light, and is also configured to adjust the switching frequency between audible and radio frequencies across the output load to reduce interference. In addition, control circuit 350 is configured to adaptively change the power mode to power-save mode in light load conditions to reduce quiescent current and to change the power mode to power-burst mode in heavy load conditions to support even higher output load capacity.

[0021] Controlling the adaptive peak current supports a higher output load capacity by incrementing the peak current, and by decrementing the peak current and controlling the switching frequency by varying the peak current, supports making the ripple in the output voltage lower. For example, in applications to audio and wireless, the switching frequency of a DC-DC converter, which is a frequency between the audible frequency and the radio frequency, is desired to reduce interference. Pulse density modulation techniques can be used for peak current control, but pulse density modulation uses an oscillator (e.g., the frequency of the oscillator ≥ the maximum DC-DC switching frequency). This is difficult for a low-power asynchronous DC-DC converter. Therefore, embodiments of the present disclosure present a technique for performing adaptive peak current control using two continuous-time timers and asynchronous DC-DC converter control for application to a DC-DC converter with a small quiescent current. In some embodiments, more than two timers, for example, three or more timers may be implemented for further control of the adaptive peak current.

[0022] In some embodiments for an asynchronous DCM DC-DC converter, a peak current detector and a zero-crossing detector may consume the maximum quiescent current. Such a peak current detector and zero-crossing detector are disabled during a light output load state (e.g., power save mode) because the quiescent current can be comparable to the current of the light output load. However, when the peak current detector and the zero-crossing detector are disabled, the DC-DC control is configured to wait until such detectors are activated for the next switching cycle, and for this reason, this enable settling delay may reduce the maximum output load capacity. In a heavy output load state, the quiescent current may be negligible with respect to the output load current, and therefore, all of the peak current detector and the zero-crossing detector are kept enabled to support a heavier output load capacity (e.g., power boost mode). In response, the described embodiments show adaptive power mode control in an asynchronous DCM DC-DC converter by a continuous-time timer used in adaptive peak current control.

[0023] FIG. 3 is a circuit diagram of a load sensing circuit 310 and a control circuit 350 of a DC-DC converter 300 according to an embodiment of the present disclosure. As shown, the asynchronous DCM DC-DC converter control 350 starts a switching cycle when an output comparator (comp1) senses that the output voltage (vout) is lower than a threshold voltage (VREF). The output comparator (comp1) transitions the vout_islow signal to logic high. The vout_islow signal is supplied to a reset-priority SR latch (sr1) that latches the vout_islow_latch signal. When the vout_islow_latch signal is set to logic high, an enable signal for a detection block (e.g., zero-cross detection and peak current detection) also transitions to high when the output load is in a light state because heavy_load_status = low.

[0024] When the enable signal transitions to high, the DC-DC control 350 waits for an enable tuning delay (en_delay) to confirm whether the detection block is activated before turning on the high-side FET (hs_on = high). When turning on the high-side FET, the inductor current increases. The peak current detector detects that the inductor current is Ipeak_control <a:0>If it detects that the value is greater than the value set by , the Ipeak signal is switched to high. The Ipeak signal then turns off the high-side FET and on the low-side FET (hs_on=low, ls_on=high), thereby reducing the inductor current. As the inductor current approaches zero, the zero-cross detection is switched to high, turning off the low-side FET (ls_on=low), and entering idle mode (both the high-side and low-side FETs are off). After a minimum idle delay (idle_delay), the asynchronous DC-DC converter is ready for the next switching cycle when vout is again lower than VREF.

[0025] The DC-DC converter output load sensing circuit 310 illustrates two continuous-time timers (heavy_delay_cell and light_delay_cell) and a peak current digital control (Ipeak_control). In some embodiments, the peak current digital control (Ipeak_control) may be a 4-bit controller that outputs various levels of current in 16 different increments. In other embodiments, Ipeak_control may be, for example, a 3-bit or 5-bit controller. At the end of the switching cycle, the DC-DC converter enters idle mode, the vout_islow_latch signal transitions to logic low by reset-priority SR latch (sr1) reset=high, and the heavy_load_cell begins an X-fall delay. During the X-fall delay, the heavy_load signal remains high (indicating a "heavy load" state), and after the X-delay, heavy_load transitions to logic low.

[0026] When the heavy_load signal goes low, the light_load_cell starts a Y rising edge delay. During the Y rising edge delay, both the heavy_load and light_load signals are low (indicating a "good load" state between a heavy load and a light load). After the Y rising edge delay, light_load goes logically high (indicating a "light load" state). The light_load and heavy_load signals are sampled using the rising edge of the vout_islow_latch signal by a D-flip-flop (dff1) and peak current digital control (Ipeak_control). If heavy_load=high and light_load=low are sampled, it indicates a "heavy load" state and that the time between switching cycles is shorter than the X delay. If heavy_load=low and light_load=low are sampled, it indicates a "good load" state and that that the time between switching cycles is between X and X+Y. If heavy_load=low and light_load=high are sampled, it indicates a "light load condition" and also indicates that the time between switching cycles is longer than the Y delay.

[0027] According to one embodiment, using these sampled heavy_load and light_load signals, peak current digital control (Ipeak_control) is performed. <a:0>Incrementing the code increases the peak current under "heavy load conditions", and Ipeak_control <a:0>Decrementing the code reduces the peak current in the "light load" state and maintains the same peak current in the "good load" state. dff1 samples the heavy_load signal to enable power boost mode (heavy_load_status=high). If heavy_load_status=high, the enable and en_settle signals are held logic high by the OR gate (or1) for the next switching cycle. Power boost mode (heavy_load_status=high) bypasses the enable settling delay (en_delay) and turns on the high-side FET as soon as the shortest idle time (idle_delay) ends. In heavy_delay_cell, a rise time of 10ns is added to reduce or prevent incorrect sampling of heavy_load=high.

[0028] When the vout_islow_latch signal transitions to logic high, the heavy_load signal transitions to logic high 10 nanoseconds later. Therefore, if the heavy_load signal is logic low at the rising edge of the vout_islow_latch signal, heavy_load = low is sampled. Furthermore, this 10 nanosecond rising delay keeps the light_load signal high in order to sample light_load = high. Therefore, if the light_load signal is high at the rising edge of the vout_islow_latch signal, light_load = high is sampled. The 10 ns delay is an arbitrary delay to prevent heavy_load = high from being accidentally selected and to accurately sample light_load = high. Therefore, in some embodiments, this 10 nanosecond delay may be longer or shorter. In further different embodiments, the heavy_load_cell and light_delay_cell may be implemented using a resistor-capacitor delay or a bias current-capacitor delay to achieve zero quiescent current.

[0029] Figure 4 is a timing diagram showing various waveforms when a DC-DC converter transitions from a good load state to a heavy load state according to one embodiment of the present disclosure. As shown, the heavy_load signal and light_load signal are initially low when the vout_islow_latch signal goes high. This indicates that the previous switching cycle was a good load state. Since heavy_load=low and light_load=low are sampled by the vout_islow_latch signal, Ipeak_control <x:0>The code for the same peak current is maintained. Also, the heavy_load_status signal is low (e.g., power save mode). At the end of the first switching cycle, when the zero-cross detection goes high, the reset signal remains high for the shortest idle time, and the reset signal also goes low to the vout_islow_latch signal. When the vout_islow_latch signal goes low, the heavy_delay_cell starts an X falling delay. Before the X falling delay has passed, the second switching cycle begins with the vout_islow going high. And when the vout_islow_latch signal goes high, it samples heavy_load=high and light_load=low, indicating a heavy load condition. Accordingly, the peak current control block sets the peak current code to Ipeak_control. <a:0>This is incremented, for example, from 4 to 5, to support heavy load capacity. Then, ddf1 samples and sets heavy_load_status=high to enable power boost mode.

[0030] Therefore, since the first switching cycle was a "good load condition," all detection blocks were disabled to reduce quiescent current. When the vout_islow_latch signal goes high for the second switching cycle, it enables the detection blocks and waits only for the enable set delay (en_delay) before turning on the high-side FET. At the end of the second switching cycle, the X falling delay is initiated, and before the X falling delay ends, the vout_islow_latch signal goes high, initiating the third switching cycle. Heavy_load=high and light_load=low are sampled ("heavy load condition"), and therefore, to support an even larger load capacitance, the peak current control block Ipeak_control is activated. <a:0>For example, increment from 5 to 6. Because the previous switching cycle (second cycle) was under heavy load (heavy_load_status=high), the detection block remained active. Therefore, the DC-DC asynchronous control bypasses the enable settling delay (en_delay) and immediately starts turning on the high-side FET (e.g., power boost mode). By incrementing the peak current and bypassing the enable settling time, the DC-DC converter can increase its maximum output load capacity.

[0031] Figure 5 is a timing diagram showing various waveforms when a DC-DC converter transitions from a heavy load state to a light load state according to one embodiment of the present disclosure. As shown, the DC-DC converter starts in a "heavy load state" (sampled heavy_load=low and light_load=low). At the end of the first switching cycle, zero-cross detection (ZCD) goes high and the vout_islow_latch signal goes low due to the reset signal.

[0032] Under light load conditions, vout remains higher than VREF for a longer period, and therefore the vout_islow and vout_islow_latch signals remain low for a longer time than the X+Y delay. After the X delay, the heavy_load signal goes low as the X falling-edge delay of heavy_delay_cell and the Y rising-edge delay of light_delay_cell begin. After the Y delay, the light_load signal goes high (light load condition), and when the vout_islow_latch signal also goes high, light_load=high is sampled. Finally, to reduce output power ripple and increase the switching frequency, Ipeak_control is used. <a:0>This value is decremented. Due to power-saving mode, heavy_load_status also goes to low.

[0033] Figure 6 is a timing diagram showing various waveforms when a DC-DC converter transitions from a heavy load state to a light load state according to one embodiment of the present disclosure. As shown, the heavy_load signal is initially high, so when the vout_islow signal transitions, heavy_load=high is sampled, and heavy_load=high sets heavy_load_status to high. The high heavy_load_status keeps the enable signal for the detection block high. However, after an X+Y delay from the end of the first switching cycle, the light_load signal transitions to high. The inverted light_load signal gates heavy_load_status to low by an AND gate (and1). Therefore, when the light_load signal transitions to high, the enable signal transitions to low, disabling the detection block and entering power-saving mode.

[0034] Figure 7 is a timing diagram showing various waveforms when a DC-DC converter is in a steady state according to one embodiment of the present disclosure. In the steady state, the switching frequency is already at the good load state and remains at the good load state. For example, Figure 4-6 shows a procedure in which the load changes suddenly, for example, from heavy load to light load, or vice versa. In these procedures, the peak current is adaptively adjusted to the good load state for the new output load value. Thus, after the sudden load change, the output load becomes steady, the adaptive peak current loop is completed, and the DC-DC converter converges to the good load state regardless of the updated output load value. Therefore, as shown in Figure 7, when the load does not change, the DC-DC converter remains at the good load state (e.g., sampled heavy_load=low and light_load=low). Since all switching cycles start during the Y delay, when the output load is in a steady state, the converted good load state causes the switching period to be between X and X+Y.

[0035] Figure 8 shows various waveforms of adaptive peak current control for adjusting the switching frequency according to one embodiment of the present disclosure. For example, adaptive peak current control adjusts the switching frequency between the audible frequency and the radio frequency. If the switching frequency is too high and interferes with the radio frequency (block 810), the peak current may be incremented to lower the switching frequency in the next switching cycle, thereby bringing the peak current into a good switching frequency range. If the switching frequency is too low (block 820) and interferes with the audible frequency, the peak current may be decremented to raise the switching frequency in the next pulse, thereby bringing the peak current into a good switching frequency range. When the output load is in a steady state, the switching frequency may be adjusted between 1 / X and 1 / (X+Y), as shown. By setting the X delay to be longer than the period of the radio frequency (e.g., longer than 415 ns, corresponding to applications for 2.4 MHz Bluetooth®) and the X+Y delay to be shorter than the period of the audible frequency (e.g., longer than 25 microseconds, corresponding to the maximum audible frequency of 40 kHz), the DC-DC converter of the asynchronous DCM can reduce interference to audible and radio frequencies by pushing and holding the peak current within a good switching frequency range. In some embodiments, a Z delay (or additional delay) may be added for further adjustment and peak current control.

[0036] In some embodiments, the described technique may be implemented for a synchronous DC-DC converter. However, a synchronous DC-DC converter may consume more quiescent current for the oscillator.

[0037] In further embodiments, more than two timers may be implemented to check more than three output load states. For example, four continuous-time timers may check the following five output load states: for example, 1) a "heavy load state" where the peak current is incremented by 2 LSB, 2) a "heavy load state" where the peak current is incremented by 1 LSB, 3) a "good load state" where the same peak current is maintained, 4) a "light load state" where the peak current is decremented by 1 LSB, and 5) a "heavy light load state" where the peak current is decremented by 2 LSB. The switching frequency may then converge to the good load state even faster.

[0038] The electronic or electrical devices and / or other related devices or components according to embodiments of the present invention described herein may be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and / or hardware. For example, the various components of these devices may be formed separately on one integrated circuit (IC) chip or on multiple IC chips. Furthermore, the various components of these devices may be formed on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or a single substrate. Furthermore, the various components of these devices may be processes or threads that execute instructions of a computer program to perform the various functions described herein, running on one or more processors in one or more computing devices, and interacting with other system components. The computer program instructions are stored in memory which may be implemented in the computing device using standard memory devices such as random-access memory (RAM). Instructions for computer programs may also be stored on other non-temporary computer-readable media, such as CD-ROMs or flash drives. Furthermore, those skilled in the art should recognize, without departing from the spirit and scope of the exemplary embodiments of the present invention, that the functions of various computing devices may be combined or integrated into a single computing device, or that the functions of a particular computing device may be distributed across one or more other computing devices.

[0039] The embodiments described herein are for illustrative purposes only. Those skilled in the art will be able to identify various alternative embodiments from the specifically disclosed embodiments. These alternative embodiments are also intended to fall within the scope of this disclosure. Accordingly, the embodiments are limited only by the following claims and their equivalents.

Claims

1. An output load sensing circuit configured to determine the state of the output load of a converter and to supply a signal to control the peak current of the converter, A control circuit is configured to adjust the peak current of the converter in accordance with the signal that controls the peak current, and to control the switching frequency of the converter by adjusting the peak current. Equipped with, The output load sensing circuit is, A first timer configured to supply a first signal indicating whether the output load is a heavy load, A second timer configured to supply a second signal indicating whether the output load is a light load, A peak current control system configured to supply a signal to the control circuit that controls the peak current of the converter based on the first signal and the second signal, Equipped with, circuit.

2. The peak current control is configured to increment the peak current in response to the output load being a heavy load. The circuit according to claim 1.

3. The peak current control is configured to decrement the peak current in response to the output load being a light load. The circuit according to claim 1.

4. The system further comprises a power stage configured to receive an input voltage and convert the input voltage into an output voltage different from the input voltage. The circuit according to claim 1.

5. The control circuit further comprises a first latch circuit configured to receive the converted output voltage and, in response to the output voltage of the converter being lower than a threshold voltage, to supply a latch signal to the first timer of the output load sensing circuit. The circuit according to claim 4.

6. The peak current control is configured to increment the peak current in response to the first signal indicating that the output load is a heavy load and the second signal indicating that the output load is not a light load. The circuit according to claim 1.

7. The peak current control is configured to decrement the peak current in response to the second signal indicating that the output load is a light load and the first signal indicating that the output load is not a heavy load. The circuit according to claim 1.

8. Determining the state of the output load of the converter, The first timer generates a first signal indicating whether the output load is a heavy load, The second timer generates a second signal indicating whether the output load is a low load, Adjusting the peak current of the converter based on the first signal and the second signal, The switching frequency of the converter is adjusted by adjusting the peak current. including, method.

9. Controlling the peak current includes incrementing the peak current in response to the output load being a heavy load, The method of claim 8.

10. Controlling the peak current includes decrementing the peak current in response to the output load being a light load, The method of claim 8.

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