Image sensor using a transfer gate signal with three voltage levels and its operating method

Abstract

To provide an image sensor configured to suppress degradation of image quality due to unintended charging or discharging of charges in a floating diffusion node.SOLUTION: An image sensor includes a photodiode PD and a pixel PIX including a transfer transistor MT and a reset transistor MR. An operation method includes the steps of: accumulating first charges through a photo diode; applying a first transfer gate signal TG having a first voltage level to the transfer transistor; performing, through the reset transistor, a first reset operation on a floating diffusion node FD; changing the first voltage level of the first transfer gate signal to a second voltage level higher than the first voltage level, during the first reset operation; changing the changed second voltage level to a third voltage level higher than the second voltage level; and changing the third voltage level to the second voltage level after diffusing the first charges to the floating diffusion node through the transfer transistor.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly to an image sensor using a transfer gate signal having three voltage levels and an operation method thereof.

Background Art

[0002] An image sensor detects light reflected from an external object and generates an electrical signal including image data. Generally, an image sensor includes a plurality of pixels. Each pixel includes a photodiode and a floating diffusion node. A transfer gate signal controls the movement of the charge accumulated in the photodiode to the floating diffusion node.

[0003] In recent years, in order to increase the resolution of image data, the pixels of image sensors have been miniaturized. As pixels are miniaturized, their capacitance decreases, and they may be sensitive to unintentional charge changes. Charge changes degrade the image quality of image data. For example, due to external noise, temperature changes, leakage current, white spots based on process defects, dark current, etc., unintentional charging or discharging of charge occurs at the floating diffusion node of the pixel. Unlike the control of the transfer gate signal, when charge is charged or discharged at the floating diffusion node, the image quality of image data may be degraded.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0005] The present invention has been made in view of the above-mentioned conventional problems, and the object of the present invention is to provide an image sensor using a transfer gate signal having three voltage levels and a method for operating the same. [Means for solving the problem]

[0006] An image sensor according to one aspect of the present invention made to achieve the above objective comprises a pixel including a photodiode, a transfer transistor, and a reset transistor, and a row driver for controlling the pixel, wherein the operation method of the image sensor includes the steps of: accumulating a first charge in the photodiode; applying a first transfer gate signal having a first voltage level to the transfer transistor; performing a first reset of a floating diffusion node connected to the reset transistor and the transfer transistor by the reset transistor; changing the first voltage level of the first transfer gate signal to a second voltage level higher than the first voltage level during the first reset; changing the changed second voltage level of the first transfer gate signal to a third voltage level higher than the second voltage level to diffuse the accumulated first charge of the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the first transfer gate signal to the second voltage level.

[0007] To achieve the above objective, another aspect of the present invention provides an image sensor comprising a pixel including a photodiode, a transfer transistor, and a reset transistor, and a row driver for controlling the pixel, wherein the operation method of the image sensor includes the steps of: accumulating a first charge in the photodiode; applying a first transfer gate signal having a first voltage level to the transfer transistor; performing a first reset of a floating diffusion node connected to the reset transistor and the transfer transistor by the reset transistor; after performing the first reset, changing the first voltage level of the first transfer gate signal to a second voltage level higher than the first voltage level; changing the changed second voltage level of the first transfer gate signal to a third voltage level higher than the second voltage level to diffuse the accumulated first charge of the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the first transfer gate signal to the second voltage level.

[0008] An image sensor according to one aspect of the present invention made to achieve the above objectives comprises a pixel array including a plurality of pixels, and a row driver configured to generate a first transfer gate signal having one of a first voltage level, a second voltage level higher than the first voltage level, or a third voltage level higher than the second voltage level, and a reset gate signal, wherein the first pixel of the plurality of pixels includes a first photodiode configured to sense light and store charge, a first transfer transistor connected between the first photodiode and a floating diffusion node and operating on the first transfer gate signal, and a reset transistor connected between a power node and a floating diffusion node and operating on the reset gate signal, wherein the row driver is configured to apply the first transfer gate signal having the first voltage level to the first transfer transistor while the first photodiode is storing the charge, change the first voltage level of the first transfer gate signal to the second voltage level after the first photodiode has stored the charge, and change the second voltage level of the first transfer gate signal to the third voltage level to diffuse the stored charge of the first photodiode to the floating diffusion node. [Effects of the Invention]

[0009] According to the present invention, an image sensor using a transfer gate signal having three voltage levels and a method for operating the same can be provided.

[0010] Furthermore, by suppressing adverse effects caused by defects while the photodiode is accumulating charge, and by suppressing adverse effects caused by leakage during the readout section, it is possible to provide an image sensor and its operating method that generate high-quality image data. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram of an electronic device according to one embodiment of the present invention. [Figure 2] It is a block diagram embodying the image sensor of FIG. 1. [Figure 3] It is a diagram of an example embodying the pixel array of FIG. 2. [Figure 4] It is a circuit diagram of an example embodying the pixel of FIG. 2. [Figure 5] It is a cross-sectional view explaining the transfer transistor according to an embodiment of the present invention. [Figure 6] It is a timing diagram explaining the signals of a general image sensor. [Figure 7] It is a timing diagram explaining the signals of an image sensor according to an embodiment of the present invention. [Figure 8] It is a timing diagram embodying the signals of an image sensor according to various embodiments of the present invention. [Figure 9] It is a timing diagram embodying the signals of an image sensor according to various embodiments of the present invention. [Figure 10A] It is a timing diagram embodying the signals of an image sensor according to various embodiments of the present invention. [Figure 10B] It is a timing diagram embodying the signals of an image sensor according to various embodiments of the present invention. [Figure 11] It is a circuit diagram of another example embodying the pixel of FIG. 2. [Figure 12] It is a diagram embodying the pixel of FIG. 11. [Figure 13] It is a flowchart explaining the operation method of an image sensor according to an embodiment of the present invention. [Figure 14] It is a flowchart explaining the operation method of an image sensor according to an embodiment of the present invention. [Figure 15] It is a block diagram of an electronic device including a multi-camera module according to an embodiment of the present invention. [Figure 16] It is a block diagram embodying the camera module of FIG. 15.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0013] The components and functional blocks shown in the drawings, described with reference to terms such as unit, module, and layer used in the detailed description, are implemented in the form of software, hardware, or a combination thereof. For example, software includes machine code, firmware, embedded code, and application software. For example, hardware includes electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, MEMS (microelectromechanical systems), passive elements, or a combination thereof.

[0014] Figure 1 is a block diagram of an electronic device according to one embodiment of the present invention. Figure 1 shows the electronic device 10. The electronic device 10 is a device that detects light reflected from an external object and processes image data based on the detected light. For example, the electronic device 10 is implemented in one of various types of electronic devices such as a smartphone, tablet PC (personal computer), laptop PC, or wearable device.

[0015] The image sensor 100 includes an image sensor 100 and an image processor 11. The image sensor 100 operates according to the control of the image processor 11. For example, the image sensor 100 detects light reflected from an external object, converts the detected light into an electrical signal, and provides the electrical signal to the image processor 11 as image data. The image processor 11 receives the image data from the image sensor 100 and processes the image data.

[0016] The image sensor 100 includes a row driver 110 and a pixel array 120. The row driver 110 generates a selection signal SEL, a reset gate signal RG, and a transfer gate signal TG. The selection signal SEL is a signal that selects a portion of the pixels in the pixel array 120. The reset gate signal RG is a signal that controls the reset transistor of a pixel in the pixel array 120. The transfer gate signal TG is a signal that controls the transfer transistor of a pixel in the pixel array 120. A more detailed description of the pixels in the pixel array 120 controlled by the row driver 110 will be described later with reference to Figure 4.

[0017] According to one embodiment of the present invention, the row driver 110 generates a transfer gate signal TG having three voltage levels. For example, the transfer gate signal TG has a first voltage level, a second voltage level, or a third voltage level. In other words, the transfer gate signal TG has a first voltage level, a second voltage level, and a third voltage level at different points in time. The second voltage level is higher than the first voltage level. The third voltage level is higher than the second voltage level.

[0018] The first voltage level transfer gate signal TG suppresses adverse effects from defects (e.g., defects in the insulating film) while the pixel detects light and accumulates charge. The second voltage level transfer gate signal TG suppresses adverse effects from leakage (e.g., unintended leakage current) during the readout section. The third voltage level transfer gate signal TG forms a channel between the photodiode and the floating diffusion node. A further detailed explanation of the transfer gate signals TG will be provided later with reference to Figures 7, 8, 9, 10A, and 10B.

[0019] The pixel array 120 contains multiple pixels. For example, the pixel array 120 contains multiple pixels arranged in the row and column directions. The pixel array 120 operates based on the selection signal SEL, reset gate signal RG, and transfer gate signal TG from the row driver 110. The pixel array 120 outputs image data to the image processor 11.

[0020] The image processor 11 communicates with the image sensor 100. The image processor 11 controls the operation of the image sensor 100. For example, the image processor 11 controls the row driver 110 to generate a selection signal SEL, a reset gate signal RG, and a transfer gate signal TG. In one embodiment, the image processor 11 controls the row driver 110 to generate the selection signal SEL, the reset gate signal RG, and the transfer gate signal TG. The image processor 11 receives image data generated by the pixel array 120. The image processor 11 corrects the image data (for example, corrects the image data of a defective pixel based on the image data of an adjacent pixel) and stores the image data in a storage device or outputs the image data to a display device.

[0021] In one embodiment, the image processor 11 controls the row driver 110 to adjust the waveform of the transfer gate signal TG. For example, the image processor 11 controls the point in time when the transfer gate signal TG changes from a first voltage level to a second voltage level, or when the transfer gate signal TG changes from a second voltage level to a first voltage level. For example, the image processor 11 adjusts the second voltage level of the transfer gate signal TG (i.e., increases or decreases the second voltage level). For example, the image processor 11 adjusts the length of the time interval in which the transfer gate signal TG is maintained at a third voltage level.

[0022] Figure 2 is a block diagram illustrating the image sensor in Figure 1. Referring to Figures 1 and 2, the image sensor 100 includes a row driver 110, a pixel array 120, a timing controller 130, an analog-to-digital converter 140, and an output buffer 150.

[0023] The row driver 110 outputs a selection signal SEL, a reset gate signal RG, and a transfer gate signal TG to the pixel array 120. The selection signal SEL selects the pixel PIX of the corresponding row from among the pixels PIX of the pixel array 120. The reset gate signal RG and the transfer gate signal TG control the reset transistor and transfer transistor of the corresponding pixel PIX.

[0024] The pixel array 120 includes multiple pixels PIX. The pixels PIX are arranged in the row and column directions. For ease of understanding of the present invention, Figure 2 shows the pixel array 120 to include 4 pixels PIX in the row direction and 4 pixels PIX in the column direction, but the scope of the present invention is not limited thereto. For example, in one embodiment, the number of pixels in the row and column directions is greater than 4. And in one embodiment, the number of pixels PIX included in the pixel array 120 increases or decreases in the row and column directions.

[0025] Each of the multiple pixels PIX in the pixel array 120 operates based on a selection signal SEL, a reset gate signal RG, and a transfer gate signal TG received from the row driver 110. Each of the multiple pixels PIX detects light reflected from an external object and outputs an output signal OT, which is an electrical signal containing image data, to the analog-to-digital converter 140.

[0026] The timing controller 130 communicates with the image processor 11. The timing controller 130 controls the row driver 110, the analog-to-digital converter 140, and the output buffer 150 according to the control of the image processor 11. The timing controller 130 generates a clock signal and controls the input and output timing of the row driver 110, the analog-to-digital converter 140, and the output buffer 150. In one embodiment, the timing controller 130 controls the operation of the row driver 110 to generate a selection signal SEL, a reset gate signal RG, and a transfer gate signal TG according to the control of the image processor 11.

[0027] The analog-to-digital converter 140 receives an output signal OT from the pixel array 120. The analog-to-digital converter 140 performs an analog-to-digital conversion operation based on the output signal OT. The analog-to-digital converter 140 outputs the converted output signal to the output buffer 150. For example, the output signal OT generated from the pixel array 120 is an analog signal, and the analog-to-digital converter 140 converts the output signal OT into a digital signal and outputs the converted output signal to the output buffer 150.

[0028] The output buffer 150 receives the output signal converted from the analog-to-digital converter 140. The output buffer 150 stores the converted output signal. Based on the control of the timing controller 130, the output buffer 150 outputs the stored output signal to the image processor 11.

[0029] Figure 3 is a diagram illustrating an example of the pixel array shown in Figure 2. Referring to Figures 2 and 3, the pixel array 120 includes multiple pixel groups PIXGR.

[0030] For the sake of explanation, the following will refer to the first direction D1, the second direction D2, and the third direction D3. The first direction D1 is the direction in which the pixels are arranged. The second direction D2 is the direction perpendicular to the first direction D1. The third direction D3 is the direction perpendicular to the plane defined by the first direction D1 and the second direction D2. For example, the first direction D1 and the second direction D2 are the row and column directions of the pixel array 120, respectively. The third direction D3 is the direction perpendicular to the semiconductor substrate on which the pixels PIX of the pixel array 120 are formed.

[0031] Multiple pixel groups PIXGR of the pixel array 120 are arranged in the first direction D1 and the second direction D2. Each of the multiple pixel groups PIXGR contains four pixels (PIX11, PIX12, PIX21, PIX22). The pixels (PIX11, PIX12, PIX21, PIX22) are arranged in the first direction D1 and the second direction D2.

[0032] For example, in pixel group PIXGR, pixel PIX12 is adjacent to pixel PIX11 in the first direction D1. Pixel PIX21 is adjacent to pixel PIX11 in the opposite direction of the second direction D2. Pixel PIX22 is adjacent to pixel PIX21 in the first direction D1.

[0033] According to one embodiment of the present invention, color filters are placed on the pixels (PIX11, PIX12, PIX21, PIX22) of the pixel group PIXGR. For example, as shown in Figure 3, a blue filter is placed on pixel PIX11, a green filter on pixel PIX12, a green filter on pixel PIX21, and a red filter on pixel PIX22. Thus, pixel PIX11 generates an electrical signal corresponding to the amount of blue light, pixels (PIX12, PIX21) generate an electrical signal corresponding to the amount of green light, and pixel PIX22 generates an electrical signal corresponding to the amount of red light.

[0034] According to one embodiment of the present invention, each of the pixels (PIX11, PIX12, PIX21, PIX22) in the pixel group PIXGR contains multiple subpixels of the same color type. For example, pixel PIX11 contains four subpixels (B11, B12, B21, B22) arranged in a first direction D1 and a second direction D2. The color type of the subpixels (B11, B12, B21, B22) is blue. Similarly, each of the pixels (PIX12, PIX21) contains subpixels (G11, G12, G21, G22) with a color type of green, and pixel PIX22 contains subpixels (R11, R12, R21, R22) with a color type of red.

[0035] In one embodiment, the subpixels contained within a single pixel are implemented in a four-shared structure, sharing other circuits besides the photodiode and transfer transistor. A more detailed explanation of this will be provided later with reference to Figures 11 and 12.

[0036] Figure 4 is a circuit diagram of an example that embodies the pixel in Figure 2. Referring to Figures 2 and 4, the pixel PIX is coupled to a row driver 110 and an analog-to-digital converter 140. The pixel PIX receives a selection signal SEL, a reset gate signal RG, and a transfer gate signal TG from the row driver 110. The pixel PIX operates based on the power supply voltage Vdd and the ground voltage GND. The pixel PIX detects light and generates an output signal OT containing image data.

[0037] For example, the pixel PIX receives a selection signal SEL from the row driver 110 via the selection line SL. Similarly, the pixel PIX receives a transfer gate signal TG from the row driver 110 via a transfer line (not shown) and a reset gate signal RG from the row driver 110 via a reset line (not shown). The pixel PIX also outputs an output signal OT to the analog-to-digital converter 140 via the output line OL.

[0038] The pixel PIX includes a photodiode PD, a transfer transistor MT, a capacitor Cfd, a reset transistor MR, a source follower transistor MSF, and a selection transistor MSL.

[0039] A photodiode PD detects light reflected from an external object and accumulates charge. The photodiode PD provides the accumulated charge to a floating diffusion node FD via a transfer transistor MT. For example, the photodiode PD detects light during the integration phase and accumulates charge. The photodiode PD provides the accumulated charge to the floating diffusion node FD via a transfer transistor MT during the readout phase.

[0040] The transfer transistor MT is connected between the output terminal of the photodiode PD and the floating diffusion node FD. The transfer transistor MT operates based on the transfer gate signal TG.

[0041] According to one embodiment of the present invention, the transfer gate signal TG has a first voltage level, a second voltage level, or a third voltage level. The first voltage level is lower than the ground voltage GND. The second voltage level is higher than the first voltage level. The third voltage level is higher than the second voltage level. The third voltage level is higher than the threshold voltage of the transfer transistor MT.

[0042] The transfer transistor MT detects light during the integration section and accumulates charge based on the transfer gate signal TG at the first voltage level. At this time, the transfer transistor MT can be biased to a voltage level lower than the ground voltage GND to suppress adverse effects from defects in the insulating film.

[0043] The transfer transistor MT disconnects the photodiode PD and the floating diffusion node FD for a portion of the readout section based on the transfer gate signal TG at the second voltage level. By biasing the transfer transistor MT to a second voltage level higher than the first voltage level, adverse effects from unintended leakage can be suppressed.

[0044] The transfer transistor MT forms a channel between the photodiode PD and the floating diffusion node FD for a portion of the readout interval based on a third voltage level transfer gate signal TG. For example, charge accumulated in the photodiode PD during the integration interval is diffused to the floating diffusion node FD while the third voltage level transfer gate signal TG is applied to the transfer transistor MT.

[0045] A more detailed explanation of the adverse effects of the transfer transistor MT will be provided later, along with Figure 5.

[0046] Capacitor Cfd is connected between the floating diffusion node FD and the ground node having a ground voltage GND. Capacitor Cfd stores the charge received from the photodiode PD to determine the voltage level of the floating diffusion node FD.

[0047] The reset transistor MR is connected between the power supply node, which has a power supply voltage Vdd, and the floating diffusion node FD. The reset transistor MR performs the reset of the floating diffusion node FD based on the reset gate signal RG.

[0048] For example, when a low-voltage reset gate signal RG is applied, the reset transistor MR is shut off. When the reset transistor MR is shut off, the floating diffusion node FD becomes floating. When a high-voltage reset gate signal RG is applied, the reset transistor MR resets the voltage level of the floating diffusion node FD by activating the connection between the power node and the floating diffusion node FD.

[0049] The source follower transistor MSF is coupled between a power supply node having a supply voltage Vdd and a selection transistor MSL. The source follower transistor MSF operates in response to the voltage level of the floating diffusion node FD. For example, when the voltage level of the floating diffusion node FD exceeds the threshold voltage level of the source follower transistor MSF, the source follower transistor MSF activates the coupling between the power supply node and the selection transistor MSL.

[0050] The selection transistor MSL is coupled between the source follower transistor MSF and the output line OL. The gate of the selection transistor MSL is coupled to the selection line SL. Based on the selection signal SEL received via the selection line SL, the selection transistor MSL provides the electrical signal received from the source follower transistor MSF as the output signal OT to the output line OL.

[0051] For example, when a low-voltage selection signal SEL is applied, the selection transistor MSL disconnects the source follower transistor MSF from the output line OL. When a high-voltage selection signal SEL is applied, the selection transistor MSL activates the connection between the source follower transistor MSF and the output line OL, thereby outputting the output signal OT through the output line OL.

[0052] Figure 5 is a cross-sectional view illustrating a transfer transistor according to one embodiment of the present invention. Figure 5 shows a cross-sectional view of the transfer transistor. The transfer transistor corresponds to the transfer transistor MT in Figure 4. The transfer transistor is connected between the photodiode PD and the floating diffusion node FD and is controlled by the transfer gate signal TG.

[0053] The semiconductor substrate 201 is formed parallel to a plane defined by a first direction D1 and a second direction D2. A semiconductor well region 202 is formed on the semiconductor substrate 201. The semiconductor well region 202 is a P-type region. A photodiode PD, a transfer transistor, and a floating diffusion node FD are formed on the semiconductor well region 202.

[0054] The photodiode PD is formed by a P-type semiconductor region 212 on the surface and an N-type semiconductor region 211 below it. Here, the P-type semiconductor region 212 is a P-type high-concentration impurity region. The floating diffusion node FD is an N-type impurity region 221.

[0055] The transfer transistor includes a photodiode PD, a transfer gate electrode that receives a transfer gate signal TG, and a floating diffusion node FD. The transfer gate electrode is formed on the gate insulating film 240. Although not shown in Figure 5, the floating diffusion node FD is electrically connected via wiring to the source electrode of the reset transistor MR and the gate electrode of the source follower transistor MSF in Figure 4.

[0056] An isolation region 231 is formed at one end of the photodiode PD. For example, the isolation region 231 is formed adjacent to the first direction D1 on the photodiode PD and in the opposite direction to the third direction D3. For example, the isolation region 231 includes a P-type high-concentration impurity region. The isolation region 231 electrically isolates the photodiode PD from other circuit elements (e.g., transistors of other pixels). Similarly, an isolation region 232 is formed at one end of the floating diffusion node FD. The isolation region 232 electrically isolates the floating diffusion node FD from other circuit elements.

[0057] In one embodiment of the present invention, a defect may occur at the lower end of the transfer gate electrode. The adverse effects of the defect can be suppressed by lowering the turn-off voltage level of the transfer gate signal TG. The turn-off voltage level refers to the voltage level that blocks channel formation of the transfer transistor.

[0058] More specifically, defects may occur at the upper edges of the gate insulating film 240 and the opposing semiconductor well region 202. These defects are unintended process defects that occur during the actual manufacturing process of the semiconductor device. While the transfer transistor is shut off by a transfer gate signal TG at the turn-off voltage level, the defects help the charge of the photodiode PD to diffuse into the floating diffusion node FD. This charge diffusion due to the defects can cause image data degradation, such as white spots and dark currents.

[0059] To eliminate this degradation in image quality, the turn-off voltage level of the transfer gate signal TG is lowered. For example, setting the turn-off voltage level of the transfer gate signal TG to a negative voltage lower than the ground voltage strongly shuts off the channel of the transfer transistor, thereby suppressing the adverse effects of defects.

[0060] However, the lower the turn-off voltage level of the transfer gate signal TG, the stronger the electric field between the transfer gate electrode and the semiconductor well region 202 becomes. This can lead to adverse effects such as Gate-Induced Drain Leakage (GIDL) in the floating diffusion node FD. When the charge in the floating diffusion node FD is discharged due to such leakage, the image quality of the image data may deteriorate.

[0061] As mentioned above, the turn-off voltage level of the transfer gate signal TG needs to be reduced to suppress the adverse effects of defects during charge accumulation in the photodiode PD. However, the turn-off voltage level of the transfer gate signal TG needs to be increased to suppress the adverse effects of leakage during the readout section that processes the accumulated charge in the photodiode PD.

[0062] Figure 6 is a timing diagram illustrating the signals of a typical image sensor. Figure 6 shows the waveforms of the selection signal SEL, reset gate signal RG, and transfer gate signal TG used in a typical image sensor. The typical transfer gate signal TG has two voltage levels. The horizontal axis represents the time axis. The vertical axis represents the logic state of the signal.

[0063] The image sensor includes pixels. Each pixel includes a photodiode, a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor. The selection signal SEL controls the selection transistor. The reset gate signal RG controls the reset transistor. The transfer gate signal TG controls the transfer transistor.

[0064] The time interval between the first time point T1 and the second time point T2 is called the integration interval. The integration interval refers to the period during which the photodiode accumulates charge.

[0065] During the integration section, the selection signal SEL is maintained at the turn-off voltage level. The reset gate signal RG is changed from the turn-off voltage level to the turn-on voltage level. The transfer gate signal TG is maintained at the turn-off voltage level.

[0066] The time interval between the second time point T2 and the third time point T3 is called the readout interval. The readout interval is the time interval after the integration interval. The readout interval is the interval in which the charge accumulated in the photodiode of the corresponding pixel during the integration interval is processed. For example, during the readout interval, the image sensor diffuses the charge accumulated in the photodiode to a floating diffusion node and generates a corresponding output signal based on the voltage level of the floating diffusion node.

[0067] The readout interval includes each time point (Tr1, Tt1, Tt2, Tr2). During the readout interval, the selection signal SEL is maintained at the turn-on voltage level, but the scope of the present invention is not necessarily limited thereto.

[0068] At time point Tr1, the reset gate signal RG is changed from the turn-on voltage level to the turn-off voltage level. That is, at time point Tr1, the reset transistor finishes resetting the floating diffusion node, and the floating diffusion node becomes floating.

[0069] At time Tt1, the transfer gate signal TG is changed from the turn-off voltage level to the turn-on voltage level. Here, the turn-on voltage level is higher than the turn-off voltage level, as shown in Figure 6. At time Tt2, the transfer gate signal TG is changed from the turn-on voltage level to the turn-off voltage level. That is, the transfer transistor forms a channel during the time interval between time Tt1 and time Tt2.

[0070] At time point Tr2, the reset gate signal RG is changed from the turn-off voltage level to the turn-on voltage level. That is, at time point Tr2, the reset transistor resets the floating diffusion node.

[0071] As described above, the transfer gate signal TG has a turn-on voltage level during the time interval between time points Tt1 and Tt2, and a turn-off voltage level during the other time intervals. As illustrated in Figure 5, if the turn-off voltage level of the transfer gate signal TG is excessively low, adverse effects due to leakage may occur, and if the turn-off voltage level of the transfer gate signal TG is excessively high, adverse effects due to defects may occur.

[0072] To improve the image quality of image data, a technique may be required that uses two types of turn-off voltage levels depending on the time interval. In other words, an image sensor that uses a transfer gate signal TG with three voltage levels is required.

[0073] Figure 7 is a timing diagram illustrating the signals of an image sensor according to one embodiment of the present invention. The image sensor includes the pixel PIX in Figure 4. Figures 4 and 7 show the waveforms of the selection signal SEL, reset gate signal RG, and transfer gate signal TG used in the image sensor according to one embodiment of the present invention. The transfer gate signal TG has three voltage levels. The horizontal axis represents the time axis. The vertical axis represents the logic state of the signal.

[0074] The image sensor includes a pixel PIX. The pixel PIX includes a photodiode PD, a transfer transistor MT, a reset transistor MR, a source follower transistor MSF, and a selection transistor MSL. The selection signal SEL controls the selection transistor MSL. The reset gate signal RG controls the reset transistor MR. The transfer gate signal TG controls the transfer transistor MT.

[0075] According to this embodiment, the image sensor uses a transfer gate signal TG having three voltage levels. More specifically, the transfer gate signal TG has a first voltage level, a second voltage level, or a third voltage level. For example, the first voltage level is a negative voltage lower than the ground voltage. The first voltage level blocks the channel of the transfer transistor MT. The second voltage level is higher than the first voltage level and blocks the channel of the transfer transistor MT. The third voltage level is higher than the second voltage level and forms the channel of the transfer transistor MT. That is, unlike the transfer gate signal TG in Figure 6, the transfer gate signal TG in Figure 7 further includes a second voltage level which is an intermediate voltage level.

[0076] The time interval between the first time point T1 and the second time point T2 is called the integration interval. The integration interval refers to the period during which the photodiode PD accumulates charge.

[0077] During the integration section, the selection signal SEL is maintained at the turn-off voltage level. During the integration section, the reset gate signal RG is changed from the turn-off voltage level to the turn-on voltage level. The transfer gate signal TG is maintained at the first voltage level. While charge is being stored in the photodiode PD, the gate of the transfer transistor MT is biased to a negative voltage, thereby suppressing the adverse effects of defects.

[0078] The time interval between the second time point T2 and the third time point T3 is called the readout interval. The readout interval is the interval in which the pixels generate an output signal based on the charge accumulated in the photodiode. The readout interval includes the first time interval, the second time interval, and the third time interval. The first time interval is the time interval between time point Tr1 and time point Tt1. The second time interval is the time interval between time point Tt1 and time point Tt2. The third time interval is the time interval between time point Tt2 and time point Tr2. During the readout interval, the selection signal SEL is maintained at the turn-on voltage level.

[0079] At time point Tr1, the reset gate signal RG is changed from the turn-on voltage level to the turn-off voltage level. That is, at time point Tr1, the reset transistor finishes resetting the floating diffusion node, and the floating diffusion node becomes floating. The transfer gate signal TG is changed from the first voltage level to the second voltage level. That is, the voltage level applied to the gate of the transfer transistor MT is increased.

[0080] During the first time interval, the selection signal SEL is maintained at the turn-on voltage level. The reset gate signal RG is maintained at the turn-off voltage level. The transfer gate signal TG is maintained at the second voltage level. At this time, the transfer transistor MT is biased to the second voltage level, which is higher than the first voltage level, thus suppressing adverse effects from leakage to the floating diffusion node FD.

[0081] At time Tt1, the transfer gate signal TG is changed from the second voltage level to the third voltage level. Based on the transfer gate signal TG at the third voltage level, the transfer transistor MT forms a channel connecting the photodiode PD and the floating diffusion node FD.

[0082] During the second time interval, the selection signal SEL is maintained at the turn-on voltage level. The reset gate signal RG is maintained at the turn-off voltage level. The transfer gate signal TG is maintained at the third voltage level. As the transfer transistor MT is turned on, the charge accumulated in the photodiode PD is diffused through the transfer transistor MT to the floating diffusion node FD.

[0083] In one embodiment, the longer the second time interval, the smoother the transfer of charge from the photodiode PD to the floating diffusion node FD. The image processor controlling the image sensor increases the length of the second time interval when it determines that the external environment is dark (i.e., less charge is accumulated on the photodiode PD). The image processor controlling the image sensor decreases the length of the second time interval when it determines that the external environment is bright (i.e., a large amount of charge is accumulated on the photodiode PD).

[0084] At time Tt2, the transfer gate signal TG is changed from the third voltage level to the second voltage level. At this time, the transfer transistor MT blocks the channel between the photodiode PD and the floating diffusion node FD.

[0085] During the third time interval, the selection signal SEL is maintained at the turn-on voltage level. The reset gate signal RG is maintained at the turn-off voltage level. The transfer gate signal TG is maintained at the second voltage level. Similar to the first time interval, the transfer transistor MT is biased to the second voltage level, which is higher than the first voltage level, thus suppressing adverse effects from leakage to the floating diffusion node FD.

[0086] At time point Tr2, the reset gate signal RG is changed from the turn-off voltage level to the turn-on voltage level. The transfer gate signal TG is changed from the second voltage level to the first voltage level. That is, at time point Tr2, the reset transistor MR resets the floating diffusion node FD. To process the next image data, the gate of the transfer transistor MT is biased to a negative voltage to suppress the adverse effects of defects.

[0087] As described above, this embodiment provides an image sensor that uses a transfer gate signal TG having three voltage levels (i.e., a first voltage level, a second voltage level, or a third voltage level). By biasing the transfer transistor MT to the first voltage level during the integration section, the image sensor can suppress adverse effects due to defects. During the readout section, by biasing the transfer transistor MT to the second voltage level before and after turning on the transfer transistor MT, the image sensor can suppress adverse effects due to leakage.

[0088] Figure 8 is a timing diagram illustrating the signals of an image sensor according to various embodiments of the present invention. The image sensor includes the pixel PIX in Figure 4. Figures 4 and 8 show the waveforms of the reset gate signal RG and the transfer gate signal TG used in an image sensor according to one embodiment of the present invention. The transfer gate signal TG has a first voltage level VL1, a second voltage level VL2, or a third voltage level VL3. The horizontal axis represents the time axis. The vertical axis represents the logic state or voltage level of the signal.

[0089] According to this embodiment, unlike the graph in Figure 7, the point at which the voltage level of the transfer gate signal TG changes is different from the point at which the voltage level of the reset gate signal RG changes.

[0090] For example, at time Tm1, the transfer gate signal TG is changed from the first voltage level VL1 to the second voltage level VL2. At time Tr1, the reset gate signal RG is changed from the turn-on voltage level to the turn-off voltage level. At time Tr2, the reset gate signal RG is changed from the turn-off voltage level to the turn-on voltage level. At time Tm2, ​​the transfer gate signal TG is changed from the second voltage level VL2 to the first voltage level VL1. In this case, time Tm1 is earlier than time Tr1, and time Tm2 is later than time Tr2.

[0091] During the reset by the reset gate signal RG, the bias voltage of the transfer transistor MT increases, allowing the voltage level of the floating diffusion node FD to be stably maintained. More specifically, regardless of the change in the voltage level of the transfer gate signal TG from the first voltage level VL1 to the second voltage level VL2, the floating diffusion node FD after the reset has a voltage level corresponding to the power supply voltage Vdd.

[0092] In one embodiment, the length of the time interval between time point Tm1 and time point Tr1 is the same as the length of the time interval between time point Tr2 and time point Tm2. For example, the time interval from the point in time when the turn-off voltage level of the transfer transistor MT changes to the point in time when the first reset is completed is the same as the time interval from the point in time when the second reset is started to the point in time when the turn-off voltage level of the transfer transistor MT changes.

[0093] As described above, this embodiment provides an image sensor in which the turn-off voltage level of the transfer gate signal TG increases during the reset of the floating diffusion node FD by the reset transistor MR.

[0094] Figure 9 is a timing diagram illustrating the signals of an image sensor according to various embodiments of the present invention. The image sensor includes the pixel PIX in Figure 4. Figures 4 and 9 show the waveforms of the reset gate signal RG and the transfer gate signal TG used in an image sensor according to one embodiment of the present invention. The transfer gate signal TG has a first voltage level VL1, a second voltage level VL2, or a third voltage level VL3. The horizontal axis represents the time axis. The vertical axis represents the logic state or voltage level of the signal.

[0095] According to this embodiment, unlike the graph in Figure 7, the point at which the voltage level of the transfer gate signal TG changes is different from the point at which the voltage level of the reset gate signal RG changes.

[0096] For example, at time Tr1, the reset gate signal RG is changed from the turn-on voltage level to the turn-off voltage level. At time Tm1, the transfer gate signal TG is changed from the first voltage level VL1 to the second voltage level VL2. At time Tm2, ​​the transfer gate signal TG is changed from the second voltage level VL2 to the first voltage level VL1. At time Tr2, the reset gate signal RG is changed from the turn-off voltage level to the turn-on voltage level. In this case, time Tm1 is later than time Tr1. Time Tm2 is earlier than time Tr2.

[0097] After a reset by the reset gate signal RG, the bias voltage of the transfer transistor MT increases, which increases the voltage difference between the photodiode PD and the floating diffusion node FD, making charge transfer smoother. More specifically, after the reset by the reset gate signal RG is performed, the floating diffusion node FD is floated. When the transfer gate signal TG is changed from a first voltage level VL1 to a second voltage level VL2, the voltage level of the floating diffusion node FD can be lowered. Because the voltage difference between the photodiode PD and the floating diffusion node FD increases, charge transfer from the diode PD to the floating diffusion node FD can be smoothed while the channel of the transfer transistor MT is formed (i.e., during the time interval between time points Tt1 and Tt2).

[0098] In one embodiment, the length of the time interval between time point Tr1 and time point Tm1 is the same as the length of the time interval between time point Tm2 and time point Tr2. For example, the time interval from when the first reset is completed until the time when the turn-off voltage level of the transfer transistor MT is changed is the same as the time interval from when the turn-off voltage level of the transfer transistor MT is changed until the second reset is started.

[0099] As described above, this embodiment provides an image sensor in which the turn-off voltage level of the transfer gate signal TG increases after the reset of the floating diffusion node FD by the reset transistor MR is performed.

[0100] Figures 10A and 10B are timing diagrams illustrating the signals of an image sensor according to various embodiments of the present invention. Figure 10A shows the waveform of the reset gate signal RG and the waveform of the transfer gate signal TG, which adjusts a second voltage level, an intermediate voltage level. The reset gate signal RG and the transfer gate signal TG are used in an image sensor including the pixel PIX in Figure 4.

[0101] Figures 4 and 10A show the waveforms of the reset gate signal RG and the transfer gate signal TG used in an image sensor according to one embodiment of the present invention. The transfer gate signal TG has a first voltage level VL1, a second voltage level VL2, or a third voltage level VL3. The second voltage level VL2 increases or decreases. The horizontal axis represents the time axis. The vertical axis represents the logic state or voltage level of the signal.

[0102] In this embodiment, unlike those shown in Figures 7, 8, and 9, the second voltage level VL2 is modified. For example, the image processor adjusts the second voltage level VL2 generated from the row driver of the image sensor. The second voltage level VL2 is adjusted to be higher than the first voltage level VL1 and lower than the third voltage level VL3.

[0103] When the second voltage level VL2 is low, within the range between the first voltage level VL1 and the third voltage level VL3, adverse effects from defects such as white spots and dark currents can be suppressed. The lower the second voltage level VL2 is, within the range between the first voltage level VL1 and the third voltage level VL3, the more likely adverse effects from leakage, such as GIDL, are to occur. On the other hand, when the second voltage level VL2 is high, within the range between the first voltage level VL1 and the third voltage level VL3, adverse effects from leakage can be suppressed. The higher the second voltage level VL2 is, within the range between the first voltage level VL1 and the third voltage level VL3, the more likely adverse effects from defects are to occur.

[0104] The image processor increases or decreases the second voltage level VL2 of the transfer gate signal TG generated by the image sensor's row driver, taking into account the image data generated in the previous cycle, external brightness, image sensor temperature, application settings, user settings, etc.

[0105] Figure 10B shows the waveforms of the selection signal SEL, the reset gate signal RG, and the transfer gate signal TG, which adjusts a second voltage level that is an intermediate voltage level. The selection signal SEL, the reset gate signal RG, and the transfer gate signal TG are used in an image sensor, including the pixel PIX in Figure 4.

[0106] Figures 4 and 10B show the waveforms of the selection signal SEL, reset gate signal RG, and transfer gate signal TG used in an image sensor according to one embodiment of the present invention. The transfer gate signal TG has a first voltage level VL1, a lower second voltage level VL2a, a higher second voltage level VL2b, or a third voltage level VL3. The horizontal axis represents the time axis. The vertical axis represents the logic state or voltage level of the signal.

[0107] The time interval between the first time point T1 and the second time point T2 is called the first integration interval. The first integration interval refers to the first time interval in which the photodiode PD accumulates charge.

[0108] The time interval between the second time point T2 and the third time point T3 is referred to as the first readout interval. The first readout interval refers to the interval in which the pixel PIX processes the charge accumulated in the photodiode PD during the first integration interval. During the time interval between time point Tr1 and time point Tt1, the transfer gate signal TG is maintained at a low second voltage level VL2a. During the time interval between time point Tt1 and time point Tt2, the transfer gate signal TG is maintained at a third voltage level VL3. During the time interval between time point Tt2 and time point Tr2, the transfer gate signal TG is maintained at a low second voltage level VL2a.

[0109] The time interval between the third time point T3 and the fourth time point T4 is referred to as the setting interval. During the setting interval, the image processor 11 in Figure 1 adjusts the voltage level used for the intermediate voltage level of the transfer gate signal TG of the row driver 110. For example, the image processor 11 changes the intermediate voltage level of the transfer gate signal TG of the row driver 110 from a lower second voltage level VL2a to a higher second voltage level VL2b. Once the setting change of the transfer gate signal TG is completed in the setting interval, the transfer gate signal TG has a first voltage level VL1, a higher second voltage level VL2b, or a third voltage level VL3 until there is another setting change.

[0110] The time interval between the fourth time point T4 and the fifth time point T5 is called the second integration interval. The second integration interval refers to the second time interval in which the photodiode PD accumulates charge.

[0111] The time interval between the fifth time point T5 and the sixth time point T6 is referred to as the second readout interval. The second readout interval refers to the interval in which the pixel PIX processes the charge accumulated in the photodiode PD during the second integration interval. During the time interval between time point Tr3 and time point Tt3, the transfer gate signal TG is maintained at a high second voltage level VL2b. During the time interval between time point Tt3 and time point Tt4, the transfer gate signal TG is maintained at a third voltage level VL3. During the time interval between time point Tt4 and time point Tr4, the transfer gate signal TG is maintained at a high second voltage level VL2b.

[0112] As described above, an example of changing the second voltage level, which is the intermediate voltage level of the transfer gate signal TG, has been explained with reference to Figures 10A and 10B. To facilitate understanding of the present invention, a timing diagram in which the intermediate voltage level is changed from a lower second voltage level VL2a to a higher second voltage level VL2b is shown in Figure 10B, but the scope of the present invention is not limited thereto. Unlike what is shown in Figure 10B, the intermediate voltage level of the transfer gate signal TG may be changed (e.g., decreased) from a higher second voltage level VL2b to a lower second voltage level VL2a, depending on the control of the image processor, and a variety of intermediate voltage levels can be used in addition to the voltage levels (VL2a, VL2b). For example, in one embodiment, the image processor adjusts the intermediate voltage level to increase or decrease in stages over a continuous setting interval. In another embodiment, the image processor adjusts the intermediate voltage level to increase first in a first setting interval and then decrease in a second setting interval.

[0113] Figure 11 is a circuit diagram of another example that embodies the pixels in Figure 2. Pixel PIXf in Figure 11 corresponds to pixel PIX in the pixel array 120 in Figure 2. The first transfer gate signal TG1, the second transfer gate signal TG2, the third transfer gate signal TG3, and the fourth transfer gate signal TG4 in Figure 11 correspond to the transfer gate signal TG in Figure 2.

[0114] Referring to Figures 2 and 11, the pixel PIXf is coupled to the row driver 110 and the analog-to-digital converter 140. The pixel PIXf receives the selection signal SEL, the reset gate signal RG, and the first to fourth transfer gate signals (TG1, TG2, TG3, TG4) from the row driver 110. The pixel PIXf operates based on the power supply voltage Vdd and the ground voltage GND. The pixel PIXf detects light and generates an output signal OT containing image data.

[0115] According to this embodiment, the pixel PIXf is implemented in a four-shared structure in which the first photodiode PD1, the second photodiode PD2, the third photodiode PD3, and the fourth photodiode PD4 share a floating diffusion node FD.

[0116] Pixel PIXf includes first to fourth photodiodes (PD1, PD2, PD3, PD4), first transfer transistor MT1, second transfer transistor MT2, third transfer transistor MT3, and fourth transfer transistor MT4, as well as a floating diffusion node FD, capacitor Cfd, reset transistor MR, source follower transistor MSF, and selection transistor MSL. Pixel PIXf is connected to the selection line SL and output line OL.

[0117] The characteristics, structure, and function of the capacitor Cfd, reset transistor MR, source follower transistor MSF, selection transistor MSL, selection line SL, and output line OL are the same as those shown in Figure 4, so a detailed explanation of them is omitted.

[0118] The first photodiode PD1 detects light reflected from an external object and accumulates charge. The first photodiode PD1 provides the accumulated charge to the floating diffusion node FD via the first transfer transistor MT1. The first transfer transistor MT1 is controlled by the first transfer gate signal TG1.

[0119] In one embodiment, the first transfer gate signal TG1 has a first voltage level, a second voltage level, or a third voltage level. The second voltage level is higher than the first voltage level. The third voltage level is higher than the second voltage level. More specifically, during the integration section in which the first photodiode PD1 accumulates charge, the first transfer gate signal TG1 has a first voltage level. During the readout section in which the accumulated charge of the first photodiode PD1 is processed, the first transfer gate signal TG1 uses the second voltage level as the turn-off voltage level and the third voltage level as the turn-on voltage level.

[0120] Similarly, the second photodiode PD2 detects light and accumulates charge. The charge accumulated in the second photodiode PD2 is supplied to the floating diffusion node FD via the second transfer transistor MT2. The second transfer transistor MT2 is controlled by the second transfer gate signal TG2, which has three voltage levels.

[0121] The third photodiode PD3 detects light and accumulates charge. The charge accumulated in the third photodiode PD3 is supplied to the floating diffusion node FD via the third transfer transistor MT3. The third transfer transistor MT3 is controlled by the third transfer gate signal TG3. The third transfer gate signal TG3 has three voltage levels.

[0122] The fourth photodiode PD4 detects light and accumulates charge. The charge accumulated in the fourth photodiode PD4 is supplied to the floating diffusion node FD via the fourth transfer transistor MT4. The fourth transfer transistor MT4 is controlled by the fourth transfer gate signal TG4. The fourth transfer gate signal TG4 has three voltage levels.

[0123] Figure 12 is a diagram illustrating the pixel in Figure 11. Referring to Figures 11 and 12, the pixel PIXf is implemented in a four-shared structure. The pixel PIXf includes a pixel region PRG and a transistor region TRG.

[0124] The pixel region PRG includes the first to fourth photodiodes (PD1, PD2, PD3, PD4), the first to fourth transfer transistors (MT1, MT2, MT3, MT4), and a floating diffusion node FD. The first to fourth photodiodes (PD1, PD2, PD3, PD4) share the floating diffusion node FD. Each of the first to fourth transfer transistors (MT1, MT2, MT3, MT4) controls the connection between the first to fourth photodiodes (PD1, PD2, PD3, PD4) and the floating diffusion node FD. The first to fourth photodiodes (PD1, PD2, PD3, PD4) are referred to as the first to fourth subpixels of the pixel PIXf (see Figure 3).

[0125] In one embodiment, the second photodiode PD2 is adjacent to the first photodiode PD1 in the first direction D1. The third photodiode PD3 is adjacent to the first photodiode PD1 in the opposite direction to the second direction D2. The fourth photodiode PD4 is adjacent to the third photodiode PD3 in the first direction D1.

[0126] The transistor region TRG includes the reset transistor MR, the source follower transistor MSF, and the selection transistor MSL.

[0127] The reset transistor MR is connected to a power supply node with a supply voltage Vdd and a floating diffusion node FD, and operates in response to a reset gate signal RG. The source follower transistor MSF is connected to a power supply node with a supply voltage Vdd and a selection transistor MSL, and operates in response to the voltage level of the floating diffusion node FD. The selection transistor MSL is connected to the source follower transistor MSF and the output line OL, and operates in response to a selection signal SEL. For example, the floating diffusion node FD is connected via wiring to the source node of the reset transistor MR and the gate node of the source follower transistor MSF.

[0128] Figure 13 is a flowchart illustrating the operation method of an image sensor according to one embodiment of the present invention. Figure 13 illustrates the operation method of an image sensor including a pixel and a row driver. The image sensor corresponds to the image sensor 100 in Figures 1 and 2. The image sensor includes the pixel PIX in Figure 4 or the pixel PIXf in Figure 11. The pixels of the image sensor include a photodiode, a transfer transistor, and a reset transistor. The row driver of the image sensor controls the pixels.

[0129] In step S110, the image sensor accumulates charge in the photodiode. For example, the photodiode of the image sensor detects light reflected from an external object and accumulates charge. The time interval during which the photodiode of the image sensor accumulates charge is called the integration interval.

[0130] In step S120, the image sensor applies a transfer gate signal having a first voltage level to the transfer transistor. In one embodiment, the first voltage level is one of the turn-off voltage levels of the transfer transistor and is lower than the ground voltage level.

[0131] In step S130, the image sensor performs a reset of the floating diffusion node connected to the reset transistor and the transfer transistor using the reset transistor. For example, when a reset gate signal having a turn-on voltage level is applied to the reset transistor, the reset transistor forms a channel between the power node having a power supply voltage and the floating diffusion node.

[0132] In step S140, the image sensor changes the first voltage level of the transfer gate signal to a second voltage level during reset. The second voltage level is higher than the first voltage level. For example, the second voltage level is one of the turn-off voltage levels of the transfer transistor.

[0133] In one embodiment, changing the first voltage level of the transfer gate signal to a second voltage level reduces the leakage current of the floating diffuse node of the image sensor pixels.

[0134] In step S150, the image sensor changes the second voltage level of the transfer gate signal to a third voltage level. The third voltage level is higher than the second voltage level. For example, the third voltage level is the turn-on voltage level of the transfer transistor. When the third voltage level is applied to the transfer transistor, the transfer transistor forms a channel connecting the photodiode and the floating diffusion node. While the transfer gate signal is maintained at the third voltage level, the charge accumulated in the photodiode in step S110 is diffused through the transfer transistor to the floating diffusion node.

[0135] In step S160, the image sensor changes the third voltage level of the transfer gate signal to the second voltage level. When the transfer gate signal is changed to the second voltage level, the channel of the transfer transistor is shut off.

[0136] In one embodiment, the operation method of the image sensor further performs an additional reset after step S160. For convenience of explanation, the reset in step S130 is referred to as the first reset, and the additional resets from step S160 onward are referred to as the second reset. The operation method of the image sensor further includes, after step S160, a step of performing a second reset of the floating diffusion node by a reset transistor, and a step of changing the second voltage level of the transfer gate signal to the first voltage level during the second reset. The first time interval between the time when the first voltage level of the transfer gate signal is changed to the second voltage level and the time when the first reset is completed in step S130 is the same as the second time interval between the time when the second reset is started and the time when the second voltage level of the transfer gate signal is changed to the first voltage level (see, for example, Figure 8).

[0137] In one embodiment, the operation method of the image sensor further includes a step of changing the settings for controlling pixels by a row driver. For example, the image sensor communicates with an image processor. The image processor adjusts the waveform of the transfer gate signal generated from the row driver of the image sensor.

[0138] In one embodiment, the step of changing the settings for controlling a pixel includes the step of changing the intermediate voltage level (i.e., the second voltage level) of the transfer gate signal. For example, the step of changing the settings for controlling a pixel includes, after the settings have been changed, the step of controlling the row driver to generate other transfer gate signals having a first voltage level, a third voltage level, or a fourth voltage level. The fourth voltage level is the intermediate voltage level. More specifically, the fourth voltage level is greater than the first voltage level, less than the third voltage level, and different from the second voltage level.

[0139] In one embodiment, the operation method of the image sensor includes a step of processing image data according to the changed settings after changing the settings. For convenience of explanation, the reset in step S130 is referred to as the first reset, and the additional reset after step S160 and before the setting change is referred to as the second reset. The transfer gate signal in step S120 is referred to as the first transfer gate signal, and the other transfer gate signal after the setting change is referred to as the second transfer gate signal. After the settings have been changed, the row driver generates a second transfer gate signal having a first voltage level, a third voltage level, or a fourth voltage level. The fourth voltage level is an intermediate voltage level and is different from the second voltage level in step S140.

[0140] In this case, the operation method of the image sensor further includes the steps of: setting the settings and accumulating charge in the photodiode; applying a second transfer gate signal having a first voltage level to the transfer transistor after setting the settings; performing a third reset of the floating diffusion node with a reset transistor; changing the first voltage level of the second transfer gate signal to a fourth voltage level during the third reset; changing the modified fourth voltage level of the second transfer gate signal to a third voltage level to diffuse the charge accumulated in the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the second transfer gate signal to a fourth voltage level.

[0141] In another example, the operation method of the image sensor further includes the steps of changing the third voltage level of the second transfer gate signal to a fourth voltage level, then performing a fourth reset of the floating spread node by a reset transistor, and changing the fourth voltage level of the second transfer gate signal to a first voltage level during the fourth reset.

[0142] In one embodiment, the step of changing the settings for controlling a pixel includes changing the interval of the turn-on voltage level of the transfer gate signal. For example, the step of changing the settings for controlling a pixel further includes determining the time interval over which the second transfer gate signal is maintained at a third voltage level after the settings have been changed. The third voltage level is the turn-on voltage level of the transfer transistor. The longer the time interval over which the transfer gate signal is maintained at the third voltage level, the smoother the charge transfer from the photodiode to the floating diffusion node becomes.

[0143] Figure 14 is a flowchart illustrating the operation method of an image sensor according to one embodiment of the present invention. Figure 14 illustrates the operation method of an image sensor including a pixel and a row driver. The image sensor corresponds to the image sensor 100 in Figures 1 and 2. The image sensor includes a pixel PIX in Figure 4 or a pixel PIXf in Figure 11. The pixels of the image sensor include a photodiode, a transfer transistor, and a reset transistor. The row driver of the image sensor controls the pixels.

[0144] Since stages S210, S220, S230, S250, and S260 in Figure 14 are the same as stages S110, S120, S130, S150, and S160 in Figure 13, a detailed explanation of these stages will be omitted.

[0145] In step S240, after the reset performed in step S230, the image sensor changes the first voltage level of the transfer gate signal to the second voltage level. For example, in one embodiment, after the reset operation is completed, the image sensor changes the first voltage level of the transfer gate signal to the second voltage level. The second voltage level is higher than the first voltage level.

[0146] In one embodiment, the operation method of the image sensor further performs an additional reset after step S260. For convenience of explanation, the reset in step S230 is referred to as the first reset, and the additional reset is referred to as the second reset. The operation method of the image sensor further includes, after step S260, a step of changing the second voltage level of the transfer gate signal to the first voltage level, and a step of performing a second reset of the floating diffusion node by a reset transistor after the second voltage level of the transfer gate signal has been changed to the first voltage level. The first time interval between the time when the first reset is completed in step S230 and the time when the first voltage level of the transfer gate signal is changed to the second voltage level is the same as the second time interval between the time when the second voltage level of the transfer gate signal is changed to the first voltage level and the time when the second reset is started (see, for example, Figure 9).

[0147] In one embodiment, the operation method of the image sensor further includes a step of changing the settings for controlling pixels by the row driver. For example, the image sensor communicates with an image processor. The image processor adjusts the waveform of the transfer gate signal generated from the row driver of the image sensor.

[0148] In one embodiment, the step of changing the settings for controlling a pixel includes the step of changing the intermediate voltage level (i.e., the second voltage level) of the transfer gate signal. For example, the step of changing the settings for controlling a pixel includes, after the settings have been changed, the step of controlling the row driver to generate other transfer gate signals having a first voltage level, a third voltage level, or a fourth voltage level. The fourth voltage level is the intermediate voltage level. More specifically, the fourth voltage level is greater than the first voltage level, less than the third voltage level, and different from the second voltage level.

[0149] In one embodiment, the operation method of the image sensor includes a step of processing image data according to the changed setting after changing the setting. For convenience of explanation, the reset in step S230 is referred to as the first reset, and the additional reset after step S260 and before the setting change is referred to as the second reset. The transfer gate signal in step S220 is referred to as the first transfer gate signal, and the other transfer gate signal after the setting change is referred to as the second transfer gate signal. After the setting has been changed, the row driver generates a second transfer gate signal having a first voltage level, a third voltage level, or a fourth voltage level. The fourth voltage level is an intermediate voltage level and is different from the second voltage level in step S240.

[0150] In this case, the operation method of the image sensor further includes the steps of: setting the settings and accumulating charge in the photodiode; setting the settings and applying a second transfer gate signal having a first voltage level to the transfer transistor; performing a third reset of the floating diffusion node with a reset transistor; after the third reset, changing the first voltage level of the second transfer gate signal to a fourth voltage level; changing the modified fourth voltage level of the second transfer gate signal to a third voltage level to diffuse the charge accumulated in the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the second transfer gate signal to a fourth voltage level.

[0151] In another example, the operation method of the image sensor further includes the steps of changing the third voltage level of the second transfer gate signal to the fourth voltage level, then changing the fourth voltage level of the second transfer gate signal to the first voltage level, and after the fourth voltage level of the second transfer gate signal has been changed to the first voltage level, performing a fourth reset of the floating diffusion node by a reset transistor.

[0152] Figure 15 is a block diagram of an electronic device including a multi-camera module according to one embodiment of the present invention. Figure 16 is a block diagram that materializes the camera module of Figure 15.

[0153] Referring to Figure 15, the electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC (power management integrated circuit) 1300, and an external memory 1400.

[0154] The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). The figure shows an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, but the embodiment is not limited to this. In one embodiment, the camera module group 1100 is modified to include only two camera modules. In another embodiment, the camera module group 1100 is modified to include n camera modules (where n is a natural number greater than or equal to 4).

[0155] Each of the multiple camera modules (1100a, 1100b, 1100c) includes an image sensor according to an embodiment of the present invention. For example, each of the multiple camera modules (1100a, 1100b, 1100c) includes the image sensor 100 shown in Figures 1 and 2. The image sensor includes the pixel PIX shown in Figure 4 or the pixel PIXf shown in Figure 11. The pixels of the image sensor include a photodiode, a transfer transistor, and a reset transistor. The row driver of the image sensor controls the pixels. The image sensor performs the operation methods shown in Figures 13 and 14.

[0156] The detailed configuration of camera module 1100b will be described in more detail below with reference to Figure 16, but the following description also applies to other camera modules (1100a, 1100b) depending on the embodiment.

[0157] Referring to Figure 16, the camera module 1100b includes a prism 1105, an optical path folding element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage device 1150.

[0158] The prism 1105 includes a reflective surface 1107 made of light-reflecting material and alters the path of light L incident from the outside.

[0159] In one embodiment, the prism 1105 changes the path of light L incident in the X direction to the Y direction perpendicular to the X direction. The prism 1105 rotates the reflective surface 1107 of the light-reflecting material in the A direction around the central axis 1106, or rotates it in the B direction around the central axis 1106 to change the path of light L incident in the X direction to the perpendicular Y direction. At this time, the OPFE 1110 also moves in the Z direction perpendicular to the X and Y directions.

[0160] In one embodiment, as shown in Figure 16, the maximum rotation angle of the prism 1105 in the A direction is 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, but the embodiment is not limited to this.

[0161] In one embodiment, the prism 1105 moves within approximately 20 degrees in the positive (+) or negative (-)B direction, between 10 and 20 degrees, or between 15 and 20 degrees. Here, the angle of movement is either the same angle in the positive (+) or negative (-)B direction, or to a substantially similar angle within approximately 1 degree.

[0162] In one embodiment, the prism 1105 moves the reflective surface 1107 of the light-reflecting material in the Z direction parallel to the extension of the central axis 1106.

[0163] The OPFE1110 includes, for example, a group of m optical lenses (where m is a natural number). The m lenses move in the Y direction to change the optical zoom magnification of the camera module 1100b. For example, if the basic optical zoom magnification of the camera module 1100b is Z, then by moving the m optical lenses included in the OPFE1110, the optical zoom magnification of the camera module 1100b can be changed to 3Z, 5Z, or 5Z or greater.

[0164] The actuator 1130 moves the OPFE 1110 or optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is positioned at the focal length of the optical lens for accurate sensing.

[0165] The image sensing device 1140 includes an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 senses (perceives) an image to be sensed using light L provided through an optical lens. The control logic 1144 controls the overall operation of the camera module 1100b. For example, the control logic 1144 controls the operation of the camera module 1100b according to control signals provided via the control signal line CSLb.

[0166] Memory 1146 stores information necessary for the operation of the camera module 1100b, such as calibration data 1147. Calibration data 1147 includes information necessary for the camera module 1100b to generate image data using light L supplied from an external source. Calibration data 1147 includes, for example, information on the rotation angle, focal length, and optical axis. If the camera module 1100b is implemented as a multi-state camera in which the focal length changes depending on the position of the optical lens, calibration data 1147 includes focal length values ​​for each position (or state) of the optical lens and information on autofocusing.

[0167] The storage device 1150 stores image data sensed via the image sensor 1142. The storage device 1150 is located outside the image sensing device 1140 and is implemented in a stacked form on the sensor chip that constitutes the image sensing device 1140. In one embodiment, the storage device 1150 is implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiment is not limited to this.

[0168] Referring to both Figures 15 and 16, in one embodiment, each of the multiple camera modules (1100a, 1100b, 1100c) includes an actuator 1130. Thus, each of the multiple camera modules (1100a, 1100b, 1100c) includes identical or different calibration data 1147 depending on the operation of the actuator 1130 contained within it.

[0169] In one embodiment, one of the multiple camera modules (1100a, 1100b, 1100c) (for example, 1100b) is a folded lens type camera module including the prism 1105 and OPFE 1110 described above, while the remaining camera modules (for example, 1100a, 1100b) are vertical type camera modules in which the prism 1105 and OPFE 1110 are omitted; however, the embodiment is not limited thereto.

[0170] In one embodiment, one of the multiple camera modules (1100a, 1100b, 1100c) (for example, 1100c) is a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor 1200 merges the image data provided by this depth camera with the image data provided by the other camera modules (for example, 1100a or 1100b) to generate a 3D depth image.

[0171] In one embodiment, at least two of the multiple camera modules (1100a, 1100b, 1100c) (e.g., 1100a, 1100b) have different fields of view (angles of view). In this case, for example, the optical lenses of at least two of the multiple camera modules (1100a, 1100b, 1100c) (e.g., 1100a, 1100b) are different, but the present invention is not limited thereto.

[0172] In one embodiment, the field of view of each of the multiple camera modules (1100a, 1100b, 1100c) is different. In this case, the optical lenses included in each of the multiple camera modules (1100a, 1100b, 1100c) are also different, but this is not limited to the above.

[0173] In one embodiment, each of the multiple camera modules is physically separated and arranged. That is, instead of the sensing area of ​​one image sensor being divided and used by multiple camera modules (1100a, 1100b, 1100c), an independent image sensor is arranged inside each of the multiple camera modules (1100a, 1100b, 1100c).

[0174] Referring again to Figure 15, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 is implemented separately from the multiple camera modules (1100a, 1100b, 1100c). For example, the application processor 1200 and the multiple camera modules (1100a, 1100b, 1100c) are each implemented on separate semiconductor chips.

[0175] The image processing unit 1210 includes a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216.

[0176] The image processing device 1210 includes multiple sub-image processors (1212a, 1212b, 1212c) in a number corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0177] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding sub-image processors (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such transfer of image data is performed using, for example, a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0178] On the other hand, in one embodiment, one sub-image processor is arranged to correspond to multiple camera modules. For example, instead of sub-image processors 1212a and 1212c being implemented separately as shown in the figure, they are integrated and implemented in a single sub-image processor, and the image data provided from camera modules 1100a and 1100c are selected via a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0179] The image data provided to each sub-image processor (1212a, 1212b, 1212c) is provided to the image generator 1214. The image generator 1214 generates an output image using the image data provided from each sub-image processor (1212a, 1212b, 1212c) according to the generating information or mode signal.

[0180] More specifically, the image generator 1214 generates an output image by merging at least a portion of the image data generated from camera modules (1100a, 1100b, 1100c) having different field of view angles, according to the image generation information or mode signal. Alternatively, the image generator 1214 may select any one of the image data generated from camera modules (1100a, 1100b, 1100c) having different field of view angles, according to the image generation information or mode signal, to generate the output image.

[0181] In one embodiment, the image generation information includes a zoom signal (or zoom factor). Furthermore, in one embodiment, the mode signal is a signal based on a mode selected, for example, by the user.

[0182] If the image generation information is a zoom signal (zoom factor), and each camera module (1100a, 1100b, 1100c) has a different field of view (field of view angle), the image generator 1214 performs different operations depending on the type of zoom signal. For example, if the zoom signal is a first signal, the image data output from camera module 1100a and the image data output from camera module 1100c are merged, and then the merged image signal and the image data output from camera module 1100b that was not used in the merging are used to generate the output image. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such merging of image data, but instead selects one of the image data output from each camera module (1100a, 1100b, 1100c) to generate the output image. However, the embodiment is not limited to this, and the method of processing the image data can be modified in various ways as needed.

[0183] In one embodiment, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors (1212a, 1212b, 1212c), and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with an increased dynamic range.

[0184] The camera module controller 1216 provides control signals to each camera module (1100a, 1100b, 1100c). The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc).

[0185] One of several camera modules (1100a, 1100b, 1100c) is designated as the master camera (e.g., 1100b) based on image generation information including a zoom signal or a mode signal, while the remaining camera modules (e.g., 1100a, 1100c) are designated as slave cameras. This information is included in the control signals and provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc).

[0186] The camera modules operating as master and slave are changed according to the zoom factor or operating mode signal. For example, if the field of view of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a lower zoom magnification, camera module 1100b operates as the master and camera module 1100a operates as the slave. Conversely, if the zoom factor indicates a higher zoom magnification, camera module 1100a operates as the master and camera module 1100b operates as the slave.

[0187] In one embodiment, the control signals provided from the camera module controller 1216 to each camera module (1100a, 1100b, 1100c) include a sink enable signal. For example, if camera module 1100b is the master camera and camera modules (1100a, 1100c) are slave cameras, the camera module controller 1216 sends a sink enable signal to camera module 1100b. Upon receiving such a sink enable signal, camera module 1100b generates a sink signal based on the provided sink enable signal and provides the generated sink signal to camera modules (1100a, 1100c) via the sink signal line SSL. Camera modules 1100b and (1100a, 1100c) transfer image data to the application processor 1200 in synchronization with such sink signals.

[0188] In one embodiment, the control signals provided from the camera module controller 1216 to a plurality of camera modules (1100a, 1100b, 1100c) include mode information corresponding to the mode signal. Based on such mode information, the plurality of camera modules (1100a, 1100b, 1100c) operate in a first operating mode and a second operating mode according to the sensing speed.

[0189] Multiple camera modules (1100a, 1100b, 1100c) generate an image signal at a first speed (for example, an image signal at a first frame rate) in the first operating mode, encode it at a second speed higher than the first speed (for example, encode an image signal at a second frame rate higher than the first frame rate), and transfer the encoded image signal to the application processor 1200. At this time, the second speed is 30 times or less the first speed.

[0190] The application processor 1200 stores the received image signal, i.e., the encoded image signal, in an internal memory 1230 located inside the application processor 1200 or in an external memory 1400 located outside the application processor 1200. Then, it reads the encoded image signal from the internal memory 1230 or external memory 1400, decodes it, and displays the image data generated based on the decoded image signal. For example, one of the multiple sub-image processors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding, and further processes the decoded image signal.

[0191] Multiple camera modules (1100a, 1100b, 1100c) generate image signals at a third speed lower than the first speed in the second operating mode (for example, generating image signals at a third frame rate lower than the first frame rate) and send the image signals to the application processor 1200. The image signals provided to the application processor 1200 are unencoded signals. The application processor 1200 either performs image processing on the received image signals or stores the image signals in the internal memory 1230 or external memory 1400.

[0192] The PMIC1300 supplies power, such as a power supply voltage, to each of the multiple camera modules (1100a, 1100b, and 1100c). For example, under the control of the application processor 1200, the PMIC1300 supplies first power to camera module 1100a via power signal line PSLa, second power to camera module 1100b via power signal line PSLb, and third power to camera module 1100c via power signal line PSLc.

[0193] The PMIC 1300 responds to the power control signal PCON from the application processor 1200 to generate power corresponding to each of the multiple camera modules (1100a, 1100b, 1100c) and further adjusts the power level. The power control signal PCON includes power adjustment signals for each operating mode of the multiple camera modules (1100a, 1100b, 1100c). For example, the operating mode includes a low-power mode. In this case, the power control signal PCON includes information about the camera modules operating in low-power mode and the power level to be set. The power levels provided to each of the multiple camera modules (1100a, 1100b, 1100c) are either the same or different. Note that the power levels are changed dynamically.

[0194] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0195] 10, 1000 electronic devices 11 Image Processors 100 Image Sensors 110-line driver 120-pixel array 130 Timing Controller 140 Analog-to-Digital Converters 150 output buffer 201 Semiconductor substrate 202 Semiconductor well region 211 N-type semiconductor region 212 P-type semiconductor region 221 N-type impurity region 231, 232 Separation area 240 Gate Insulator 1100 Camera Module Group 1100a~1100c Camera Module 1105 Prism 1106 Center axis 1107 Reflective surface 1110 Optical Path Bend Element (OPFE) 1130 Actuator 1140 Image Sensing Device 1142 Image Sensor 1144 Control Logic 1146 memory 1147 Calibration data 1150 Storage Device 1200 application processors 1210 Image Processing Device 1212a~1212c Sub-image processors 1214 Image Generator 1216 Camera Module Controller 1220 Memory Controller 1230 memory 1300 PM (power management) IC 1400 External memory B11, B12, B21, B22 subpixels CFD capacitor CSLa~CSLc control signal line FD Floating Diffusion Node G11, G12, G21, G22 subpixels GND (Ground Voltage) ISLa~ISLc Image Signal Line MR reset transistor MSF Source Follower Transistor MSL Select Transistor MT transfer transistor MT1~MT4 Transfer Transistors OL output line OT output signal PCON Power Control Signal PD photodiode PD1-PD4: 1st to 4th photodiodes PIX, PIX11, PIX12, PIX21, PIX22 pixels PIXf Pixel PIXGR Pixel Group PRG Pixel Area PSLa~PSLc Power Signal Line R11, R12, R21, R22 subpixels RG Reset Gate Signal SEL selection signal SL Selection Line SSL Sync Signal Line TG Transfer Gate Signal TG1~TG4 1st~4th Transfer Gate Signals TRG Transistor Region Vdd Power supply voltage VL1~VL3 1st~3rd Voltage Levels VL2a, VL2b: Low and high second voltage levels.

Claims

1. A method for operating an image sensor comprising a pixel including a photodiode, a transfer transistor, and a reset transistor, and a row driver for controlling the pixel, A step of accumulating a first charge in the photodiode, The steps include applying a first transfer gate signal having a first voltage level to the transfer transistor, The steps include: performing a first reset of the floating diffusion node connected to the reset transistor and the transfer transistor using the reset transistor; The steps include changing the first voltage level of the first transfer gate signal to a second voltage level that is higher than the first voltage level during the first reset, A method characterized by comprising the steps of changing the modified second voltage level of the first transfer gate signal to a third voltage level higher than the second voltage level, thereby diffusing the accumulated first charge of the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the first transfer gate signal to the second voltage level.

2. After the third voltage level of the first transfer gate signal is changed to the second voltage level, the reset transistor performs a second reset of the floating diffusion node. The method according to claim 1, further comprising the step of changing the second voltage level of the first transfer gate signal to the first voltage level during the second reset.

3. The method according to claim 2, characterized in that the first time interval between the time when the first voltage level of the first transfer gate signal is changed to the second voltage level and the time when the first reset is completed is the same as the second time interval between the time when the second reset is started and the time when the second voltage level of the first transfer gate signal is changed to the first voltage level.

4. The method according to claim 1, characterized in that the leakage current of the floating diffusion node is reduced by changing the first voltage level of the first transfer gate signal to a second voltage level.

5. The method according to claim 1, characterized in that the first voltage level is lower than the ground voltage level.

6. The process further includes the step of changing the settings for controlling the pixel using the row driver, The step of changing the settings for controlling the pixel by the row driver includes, after changing the settings, controlling the row driver to generate a second transfer gate signal having the first voltage level, the third voltage level, or the fourth voltage level, The method according to claim 1, characterized in that the fourth voltage level is greater than the first voltage level, less than the third voltage level, and different from the second voltage level.

7. After changing the aforementioned settings, the step of accumulating a second charge in the photodiode, After changing the above setting, the step of applying a second transfer gate signal having the first voltage level to the transfer transistor, The steps include: performing a third reset of the floating diffusion node using the reset transistor; The steps include changing the first voltage level of the second transfer gate signal to the fourth voltage level during the third reset, The method according to 6, further comprising the step of changing the modified fourth voltage level of the second transfer gate signal to the third voltage level to diffuse the accumulated second charge of the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the second transfer gate signal to the fourth voltage level.

8. After the third voltage level of the second transfer gate signal is changed to the fourth voltage level, the reset transistor performs a fourth reset of the floating diffusion node. The method according to 7, further comprising the step of changing the fourth voltage level of the second transfer gate signal to the first voltage level during the fourth reset.

9. The method according to 6, wherein the step of changing the settings for controlling the pixel by the row driver further includes the step of determining a time interval in which the second transfer gate signal is maintained at the third voltage level after the settings have been changed.

10. A method for operating an image sensor comprising a pixel including a photodiode, a transfer transistor, and a reset transistor, and a row driver for controlling the pixel, A step of accumulating a first charge in the photodiode, The steps include applying a first transfer gate signal having a first voltage level to the transfer transistor, The steps include: performing a first reset of the floating diffusion node connected to the reset transistor and the transfer transistor using the reset transistor; After performing the first reset, the first voltage level of the first transfer gate signal is changed to a second voltage level that is higher than the first voltage level. A method characterized by comprising the steps of changing the modified second voltage level of the first transfer gate signal to a third voltage level higher than the second voltage level, thereby diffusing the accumulated first charge of the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the first transfer gate signal to the second voltage level.

11. The steps include changing the third voltage level of the first transfer gate signal to the second voltage level, and then changing the second voltage level of the first transfer gate signal to the first voltage level, The method according to 10, further comprising the step of performing a second reset of the floating diffusion node by the reset transistor after the second voltage level of the first transfer gate signal has been changed to the first voltage level.

12. The method according to 11, characterized in that the first time interval between the time when the first reset is completed and the time when the first voltage level of the first transfer gate signal is changed to the second voltage level is the same as the second time interval between the time when the second voltage level of the first transfer gate signal is changed to the first voltage level and the time when the second reset is started.

13. The process further includes the step of changing the settings for controlling the pixel using the row driver, The step of changing the settings for controlling the pixel by the row driver includes, after changing the settings, controlling the row driver to generate a second transfer gate signal having the first voltage level, the third voltage level, or the fourth voltage level, The method according to 10, characterized in that the fourth voltage level is greater than the first voltage level, less than the third voltage level, and different from the second voltage level.

14. After changing the aforementioned settings, the step of accumulating a second charge in the photodiode, After changing the above setting, the step of applying a second transfer gate signal having the first voltage level to the transfer transistor, The steps include: performing a third reset of the floating diffusion node using the reset transistor; After performing the third reset, the first voltage level of the second transfer gate signal is changed to the fourth voltage level, The method according to 13, further comprising the step of changing the modified fourth voltage level of the second transfer gate signal to the third voltage level to diffuse the accumulated second charge of the photodiode to the floating diffusion node via the transfer transistor, and then changing the third voltage level of the second transfer gate signal to the fourth voltage level.

15. After the third voltage level of the second transfer gate signal is changed to the fourth voltage level, the fourth voltage level of the second transfer gate signal is changed to the first voltage level. The method according to 14, further comprising the step of performing a fourth reset of the floating diffusion node by the reset transistor after the fourth voltage level of the second transfer gate signal has been changed to the first voltage level.

16. A pixel array containing multiple pixels, A row driver configured to generate a first transfer gate signal having one of a first voltage level, a second voltage level higher than the first voltage level, or a third voltage level higher than the second voltage level, and a reset gate signal, The first of the aforementioned plurality of pixels is A first photodiode configured to sense light and accumulate charge, A first transfer transistor is connected between the first photodiode and the floating diffusion node and operates based on the first transfer gate signal, Includes a reset transistor connected between the power node and the floating diffusion node and operating based on the reset gate signal, The aforementioned row driver, While the first photodiode is accumulating the charge, the first transfer gate signal having the first voltage level is applied to the first transfer transistor. After the first photodiode has accumulated the charge, the first voltage level of the first transfer gate signal is changed to the second voltage level. An image sensor characterized by being configured to change the second voltage level of the first transfer gate signal to the third voltage level in order to diffuse the accumulated charge of the first photodiode to the floating diffusion node.

17. The plurality of pixels include a first pixel, a second pixel, a third pixel, and a fourth pixel that form a pixel group. The second pixel is adjacent to the first pixel in the first direction, the third pixel is adjacent to the first pixel in the second direction perpendicular to the first direction, and the fourth pixel is adjacent to the second pixel in the first direction. The row driver is further configured to generate a second transfer gate signal, a third transfer gate signal, and a fourth transfer gate signal, each having one of the first voltage level, the second voltage level, or the third voltage level. The image sensor according to claim 16, further comprising: a first pixel; a second photodiode; a second transfer transistor connected between the second photodiode and the floating diffusion node and operating in response to the second transfer gate signal; a third photodiode; a third transfer transistor connected between the third photodiode and the floating diffusion node and operating in response to the third transfer gate signal; and a fourth photodiode; a fourth transfer transistor connected between the fourth photodiode and the floating diffusion node and operating in response to the fourth transfer gate signal.

18. The image sensor according to claim 16, further characterized in that the row driver is configured to change the first voltage level of the first transfer gate signal to the second voltage level while the reset transistor is performing the reset of the floating diffusion node.

19. The image sensor according to claim 16, wherein the row driver is further configured to change the first voltage level of the first transfer gate signal to the second voltage level after the reset transistor has performed the reset of the floating diffusion node.

Images