Gate trench power semiconductor device having improved fracture performance and method for forming such device

Abstract

The semiconductor device includes a semiconductor layer structure having a gate trench formed in an upper surface, a gate finger within the gate trench, an auxiliary dielectric layer on an upper surface of the gate finger and overlapping the gate trench in a direction perpendicular to the gate trench, and a gate connector on an upper surface of the auxiliary dielectric layer and on an upper surface of the gate finger.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 847,650, filed on 23 June 2023, the entirety of which is incorporated herein by reference.

[0002] The present invention relates to semiconductor devices, and more particularly to gate trench power semiconductor devices. [Background technology]

[0003] A metal-insulating semiconductor field-effect transistor ("MISFET") is a well-known type of semiconductor transistor that can be used as a switching device. A MISFET is a three-terminal device having a gate terminal, a drain terminal, a source terminal, and a semiconductor body. The semiconductor body has source and drain regions separated by a channel region, and the gate electrode (often also called the gate finger) is separated from the channel region by a thin insulating layer called the "gate dielectric layer." A MISFET may be turned on or off by applying an appropriate bias voltage to the gate finger. When a MISFET is turned on (i.e., when the MISFET is in its "on state"), current flows through the channel region of the MISFET between the source and drain regions. When the bias voltage is removed from the gate finger (or reduced below a threshold level, which may be a negative voltage), current no longer flows through the channel region. As an example, an n-type MISFET has a source and drain region made of n-type semiconductor and a channel region made of p-type semiconductor. Therefore, an n-type MISFET has an "npn" design. When a gate bias voltage sufficient to generate a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and drain regions, the n-type MISFET turns on, thereby enabling majority carrier conduction between them.

[0004] In most cases, the gate dielectric layer separating the gate fingers of a power MISFET from the channel region is implemented as a thin oxide layer (e.g., a silicon oxide layer). MISFETs with an oxide gate dielectric layer are called metal oxide semiconductor field-effect transistors (MOSFETs). Oxide-based gate dielectric layers are used almost always due to their superior properties, and although the discussion herein focuses on MOSFETs rather than MISFETs, it will be understood that the techniques by the embodiments of the present invention described herein are equally applicable to devices having gate dielectric layers formed from non-oxide materials.

[0005] Because the gate fingers of a MOSFET are isolated from the channel region by the gate dielectric layer, a minimal gate current is required to maintain the MOSFET in its on state or to switch it between its on and off states. Since the gate forms a capacitor with the channel region, the gate current during switching is kept low. Therefore, because only minimal charge / discharge current is required during switching, the gate drive circuit can be simplified and the switching speed can be increased. MOSFETs may be standalone devices or may be combined with other circuit devices. For example, an insulated-gate bipolar transistor ("IGBT") is a semiconductor device that includes both a MOSFET and a bipolar junction transistor ("BJT"), combining the high-impedance gate of the MOSFET with the low on-state conduction loss that can be achieved by the BJT. An IGBT may be implemented, for example, as a Darlington pair with a high-voltage n-channel MOSFET at the input and a BJT at the output. The basic current of the BJT is supplied through the MOSFET channel, which allows for a simplified external drive circuit (since the drive circuit only charges and discharges the gate of the MOSFET).

[0006] There is a growing demand for high-power semiconductor switching devices that can carry large currents in the ON state and block large voltages (e.g., hundreds or thousands of volts) in the reverse-blocked state. To support high current densities and block such high voltages, power MOSFETs and power IGBTs typically have a vertical structure with sources and drains on both sides (e.g., top and bottom) of a thick semiconductor layer structure to block higher voltage levels. For very high-power applications, semiconductor switching devices are typically formed from wide-bandgap semiconductor material systems, such as silicon carbide ("SiC"). (Hereinafter, the term "wide-bandgap semiconductor" encompasses any semiconductor having a bandgap of at least 1.4 electron volts), and silicon carbide has several advantageous properties, including, for example, high field dielectric strength, high thermal conductivity, high electron mobility, high melting point, and high saturation electron drift rate. For example, compared to devices formed using other semiconductor materials such as silicon, power semiconductor devices formed using silicon carbide may have the ability to operate at higher temperatures, higher power densities, higher speeds, higher power levels, and / or higher radiation densities.

[0007] Vertical power semiconductor devices, including MOSFET transistors, can have a standard gate design in which gate fingers are formed on top of the semiconductor layer structure, or alternatively, gate fingers embedded in each trench within the semiconductor layer structure. MOSFETs with embedded gate fingers are commonly called gate trench MOSFETs. In a standard gate design, the channel region of each unit cell transistor is located horizontally below the gate fingers. In contrast, in a gate trench MOSFET design, the channel is located vertically. Gate trench MOSFETs can achieve performance enhancements but typically require more complex manufacturing processes.

[0008] One failure mechanism in power MOSFETs is the so-called "breakdown" of the gate dielectric layer. When a power MOSFET is in its conduction or ON state, the gate dielectric layer is subjected to a high electric field. The stress on the gate dielectric layer caused by these electric fields leads to defects in the dielectric material that develop over time. When the concentration of defects reaches a critical value, so-called "percolation paths" may form through the gate dielectric layer, which electrically connect the gate fingers to the source region located beneath them, causing a short circuit between the gate fingers and the source region and potentially destroying the device. The "lifetime" of the gate dielectric layer (i.e., how long the device can operate before breakdown occurs) depends, among other things, on the magnitude of the electric field the gate dielectric layer is subjected to and the length of time the electric field is applied. Figure 1 is a schematic semi-logarithmic graph showing the relationship between the operating time before breakdown occurs ("gate dielectric lifetime") and the level of electric field applied to the gate dielectric layer. This graph assumes that the same electric field is always applied (this is not necessarily the case) and assumes a gate dielectric layer of a specific thickness. An important point that can be seen from Figure 1 is that there can be a linear relationship between the logarithm of the gate dielectric lifetime and the electric field, meaning that as the electric field level increases, the lifetime of the gate dielectric layer can be shortened. The lifetime of the gate dielectric layer can be extended by increasing the thickness of the gate dielectric layer, but since the performance of the MOSFET is also determined by the thickness of the gate dielectric layer, increasing the thickness of the gate dielectric layer is not usually an acceptable way to extend the lifetime of the gate dielectric layer.

[0009] Today, silicon carbide-based power MOSFETs are used in applications requiring high voltage blocking. For example, they can block voltages from 300V to over 20kV with a blocking current of 10A / cm². 2Silicon carbide MOSFETs with the above current density ratings are commercially available. To form such a device, typically multiple "unit cells" are formed, each containing a MOSFET transistor. In high-power applications, a large number of these unit cells (e.g., hundreds or thousands) are typically located on / within a semiconductor layer structure and electrically connected in parallel. On the upper side of the semiconductor layer structure, gate pads are formed, connected to individual gate fingers through one or more gate buses, allowing the gate pads to send gate signals to all unit cells. The opposite (bottom) side of the semiconductor layer structure acts as a common drain for all unit cells of the device. A common source contact, exposed between the gate fingers, is formed on the source region of the semiconductor layer structure. The resulting device has three terminals: a common source terminal, a common drain terminal, and a common gate terminal, which act as terminals for hundreds or thousands of individual unit cell transistors electrically connected in parallel. [Overview of the project] [Means for solving the problem]

[0010] According to an embodiment of the present invention, a semiconductor device is provided comprising a semiconductor layer structure having a gate trench formed in its upper surface, a gate finger located within the gate trench, an auxiliary dielectric layer located on the upper surface of the gate finger and overlapping the gate trench perpendicularly, and a gate connector located on the upper surface of both the auxiliary dielectric layer and the gate finger.

[0011] In some embodiments, the semiconductor device further comprises a gate dielectric layer between the semiconductor layer structure within the gate trench and the gate finger. In some embodiments, the auxiliary dielectric layer is thicker than the gate dielectric layer. In some embodiments, the auxiliary dielectric layer is at least twice as thick as the gate dielectric layer. In some embodiments, the auxiliary dielectric layer overlaps the gate finger perpendicularly over less than half the length of the gate finger.

[0012] In some embodiments, the auxiliary dielectric layer directly contacts a portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench. In some embodiments, the auxiliary dielectric layer also directly contacts the upper surface of the gate fin.

[0013] In some embodiments, the gate trench extends longitudinally within the semiconductor layer structure and has a longitudinally extending bottom surface, first and second longitudinally extending sidewalls on opposite sides of each other, and first and second end walls on opposite sides of each other. The gate dielectric layer includes a first portion that extends upward along the first end wall of the gate trench, and the auxiliary dielectric layer directly contacts the first portion of the gate dielectric layer.

[0014] In some embodiments, the gate fin extends longitudinally within the gate trench and has a longitudinally extending upper surface, a longitudinally extending bottom surface, first and second longitudinally extending sidewalls on opposite sides of each other, and first and second end walls on opposite sides of each other. The auxiliary dielectric layer extends over the first end wall of the gate fin.

[0015] In some embodiments, the semiconductor device further includes an inter-metal dielectric layer on the upper surface of the gate connector and a source contact on the upper surface of the inter-metal dielectric layer. In some embodiments, the inter-metal dielectric layer vertically overlaps the auxiliary dielectric layer. In some embodiments, the semiconductor device further includes a gate bus, the gate connector electrically connects the gate bus to the gate fin, and the gate connector is between the auxiliary dielectric layer and the inter-metal dielectric layer.

[0016] In some embodiments, the auxiliary dielectric layer is a field oxide layer, and the semiconductor device further includes a gate bus on the upper surface of the auxiliary dielectric layer.

[0017] In some embodiments, the semiconductor device further includes a gate pad electrically connected to the gate fin through the gate bus and the gate connector.

[0018] In some embodiments, the auxiliary dielectric layer is also on the upper surface of a portion that is in the inactive area of the semiconductor device at the end of the gate trench in the semiconductor layer structure.

[0019] In some embodiments, the semiconductor device includes a metal-oxide-semiconductor field-effect transistor, and the semiconductor layer structure includes a silicon carbide drift layer having a first conductivity type, a silicon carbide well having a second conductivity type on the upper portion of the silicon carbide drift layer, and a silicon carbide source region having the first conductivity type on the upper portion of the silicon carbide well, and the gate fin includes silicon.

[0020] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer that directly contacts the upper surface of the semiconductor layer structure adjacent to the sidewall of the gate trench, and the thickness of the second dielectric layer exceeds the thickness of the gate dielectric layer. In some embodiments, the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench over the entire length of the gate trench. In some embodiments, the thickness of the auxiliary dielectric layer is at least twice the thickness of the gate dielectric layer.

[0021] In some embodiments, the auxiliary dielectric layer overlaps the gate fin in a direction perpendicular to the gate fin along substantially the entire length of the gate fin. In some embodiments, the auxiliary dielectric layer directly contacts the gate fin along substantially the entire length of the gate fin.

[0022] In some embodiments, the semiconductor device further includes a gate bond pad and a gate bus, the gate fin is electrically connected to the gate bond pad at least through a gate connector and the gate bus, and the auxiliary dielectric layer extends under both the gate bond pad and the gate bus.

[0023] In some embodiments, the auxiliary dielectric layer extends laterally across the entire width of the gate finger in at least a portion of the inert region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a portion of the active region of the semiconductor device.

[0024] A further embodiment of the present invention provides a semiconductor device comprising a semiconductor layer structure having a gate trench inside, a gate finger located within the gate trench, a gate dielectric layer located between the semiconductor layer structure and the gate finger within the gate trench, another gate finger located within the gate trench, an auxiliary dielectric layer located on the upper surface of the gate dielectric layer and the gate finger, and an intermetallic dielectric layer overlapping the auxiliary dielectric layer perpendicularly.

[0025] In some embodiments, the auxiliary dielectric layer overlaps perpendicular to the gate trench.

[0026] In some embodiments, the auxiliary dielectric layer is in direct contact with a portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench.

[0027] In some embodiments, the gate trench extends longitudinally within the semiconductor layer structure and has a longitudinally extending bottom surface, first and second longitudinally extending side walls opposite to each other, and first and second end walls opposite to each other, the gate dielectric layer includes a first portion extending upward along the first end wall of the gate trench, and the auxiliary dielectric layer is in direct contact with the first portion of the gate dielectric layer.

[0028] In some embodiments, the auxiliary dielectric layer is at least four times the thickness of the gate dielectric layer.

[0029] In some embodiments, the semiconductor device further comprises a gate bus and a gate connector for electrically connecting gate fingers to the gate bus, the gate connector being located between an auxiliary dielectric layer and an intermetallic dielectric layer.

[0030] In some embodiments, the semiconductor device further comprises a gate bond pad and a gate bus, the gate finger is electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer includes a field oxide layer extending beneath both the gate bond pad and the gate bus.

[0031] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is adjacent to the sidewall of the gate trench and in direct contact with the upper surface of the semiconductor layer structure, the thickness of the second dielectric layer being at least twice the thickness of the gate dielectric layer. In some embodiments, the auxiliary dielectric layer extends over the semiconductor layer structure adjacent to the sidewall of the gate trench along the entire length of the gate trench. In some embodiments, the auxiliary dielectric layer overlaps the gate finger perpendicularly along substantially the entire length of the gate finger.

[0032] In some embodiments, the auxiliary dielectric layer extends laterally across the entire width of the gate finger in at least a portion of the inert region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a portion of the active region of the semiconductor device.

[0033] A further embodiment of the present invention provides a semiconductor device comprising a semiconductor layer structure having a gate trench inside, a gate finger located within the gate trench, a gate bus, a gate connector electrically connecting the gate finger to the gate bus, and an auxiliary dielectric layer interposed between the end portion of the gate finger and the gate connector.

[0034] In some embodiments, the gate connector makes direct contact with both the gate fingers and the auxiliary dielectric layer.

[0035] In some embodiments, the semiconductor device further comprises a gate dielectric layer between the semiconductor layer structure within the gate trench and the gate finger. In some embodiments, the auxiliary dielectric layer is in direct contact with the portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench. In some embodiments, the auxiliary dielectric layer is also in direct contact with the upper surface of the gate finger. In some embodiments, the auxiliary dielectric layer is at least twice as thick as the gate dielectric layer.

[0036] In some embodiments, the semiconductor device further comprises an intermetallic dielectric layer on the upper surface of the gate connector and a source contact on the upper surface of the intermetallic dielectric layer. In some embodiments, the intermetallic dielectric layer overlaps the auxiliary dielectric layer perpendicularly.

[0037] In some embodiments, the semiconductor device further comprises a gate bond pad and a gate bus, the gate finger is electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer comprises a field oxide layer extending beneath both the gate bond pad and the gate bus.

[0038] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer that is adjacent to the sidewall of the gate trench and in direct contact with the upper surface of the semiconductor layer structure, the thickness of the second dielectric layer being at least four times the thickness of the gate dielectric layer. In some embodiments, the auxiliary dielectric layer extends along the entire length of the gate trench, adjacent to the sidewall of the gate trench, onto the semiconductor layer structure.

[0039] In some embodiments, the auxiliary dielectric layer overlaps the gate finger perpendicularly along substantially the entire length of the gate finger.

[0040] In some embodiments, the auxiliary dielectric layer extends laterally across the entire width of the gate finger in at least a portion of the inert region of the semiconductor device, and the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a portion of the active region of the semiconductor device.

[0041] According to an additional embodiment of the present invention, a semiconductor device is provided comprising: a semiconductor layer structure; a gate trench extending longitudinally within the upper surface of the semiconductor layer structure, having a longitudinally extending lower surface, first and second longitudinally extending side walls on opposite sides, and first and second end walls on opposite sides; gate dielectric layers on the lower surface, first and second side walls, and first and second end walls of the gate trench; gate fingers within the gate trench; and an auxiliary dielectric layer overlapping perpendicularly to the gate trench and in direct contact with the portion of the gate dielectric layer located at the first end wall of the gate trench.

[0042] In some embodiments, the auxiliary dielectric layer also directly contacts the upper surface of the gate finger. In some embodiments, the auxiliary dielectric layer is at least twice as thick as the gate dielectric layer.

[0043] In some embodiments, the semiconductor device further comprises a gate bus, a gate connector, and an intermetallic dielectric layer, the gate connector electrically connecting the gate fingers to the gate bus, and the intermetallic dielectric layer located on the upper surface of the gate connector. In some embodiments, the intermetallic dielectric layer overlaps the auxiliary dielectric layer perpendicularly.

[0044] In some embodiments, the semiconductor device further comprises a gate bond pad and a gate bus, the gate finger is electrically connected to the gate bond pad at least through the gate bus, and the auxiliary dielectric layer comprises a field oxide layer extending beneath both the gate bond pad and the gate bus.

[0045] In some embodiments, the auxiliary dielectric layer includes at least a portion of a second dielectric layer adjacent to the sidewall of the gate trench and in direct contact with the upper surface of the semiconductor layer structure, wherein the thickness of the second dielectric layer is at least twice the thickness of the gate dielectric layer.

[0046] In some embodiments, the auxiliary dielectric layer extends along the entire length of the gate trench, adjacent to the sidewalls of the gate trench, on the semiconductor layer structure.

[0047] In some embodiments, the auxiliary dielectric layer is in direct contact with the gate finger along substantially the entire length of the gate finger.

[0048] Further embodiments of the present invention provide a semiconductor device comprising a semiconductor layer structure having a gate trench inside, a first dielectric layer on the sidewalls and bottom surface of the gate trench, a gate finger on the first dielectric layer within the gate trench, and a second dielectric layer on the upper surface of the semiconductor layer structure that is in direct contact with the upper surface of the first dielectric layer. The second dielectric layer is at least twice as thick as the first dielectric layer.

[0049] In some embodiments, the first dielectric layer includes a first portion of the gate dielectric layer that is located within the gate trench.

[0050] In some embodiments, the second dielectric layer includes a combination of a second portion of the gate dielectric layer extending to the upper surface of the semiconductor layer structure and an auxiliary dielectric layer extending to the upper surface of the second portion of the gate dielectric layer.

[0051] In some embodiments, the second dielectric layer includes an auxiliary dielectric layer extending over the semiconductor layer structure.

[0052] In some embodiments, the second dielectric layer extends along the entire length of the gate trench, adjacent to the sidewalls of the gate trench, on a semiconductor layer structure.

[0053] In some embodiments, the gate finger comprises first and second sidewalls extending longitudinally in the gate trench, and the second dielectric layer overlaps perpendicularly to both the first and second sidewalls of the gate finger.

[0054] In some embodiments, the gate finger comprises first and second sidewalls extending longitudinally in the gate trench, and the second dielectric layer includes a first portion overlapping perpendicularly to the first sidewall of the gate finger and a second portion overlapping perpendicularly to the second sidewall of the gate finger. In some embodiments, the semiconductor device further comprises a gate connector for electrically connecting the gate finger to a gate bus. In some embodiments, a portion of the gate connector is positioned between the first and second portions of the second dielectric layer.

[0055] According to yet another embodiment of the present invention, a semiconductor device is provided comprising a semiconductor layer structure having a gate trench inside, a first dielectric layer on the side walls and bottom surface of the gate trench, a gate finger on the first dielectric layer within the gate trench, and a second dielectric layer on the upper surface of the semiconductor layer structure that is in direct contact with the gate finger and overlaps it vertically.

[0056] In some embodiments, the second dielectric layer is at least twice as thick as the first dielectric layer.

[0057] In some embodiments, the semiconductor device further comprises a gate connector that directly contacts both the second dielectric layer and the gate finger.

[0058] In some embodiments, the first dielectric layer includes a first portion of the gate dielectric layer that is located within the gate trench.

[0059] In some embodiments, the second dielectric layer includes a combination of a second portion of the gate dielectric layer that extends to the upper surface of the semiconductor layer structure and an auxiliary dielectric layer that extends to the upper surface of the second portion of the gate dielectric layer.

[0060] In some embodiments, the second dielectric layer includes an auxiliary dielectric layer extending over the semiconductor layer structure.

[0061] In some embodiments, the second dielectric layer is in direct contact with the gate finger along substantially the entire length of the gate finger.

[0062] In some embodiments, the gate finger comprises first and second sidewalls extending longitudinally in the gate trench, and the second dielectric layer includes a first portion overlapping perpendicularly to the first sidewall of the gate finger and a second portion overlapping perpendicularly to the second sidewall of the gate finger.

[0063] In some embodiments, the semiconductor device further comprises a gate connector that electrically connects the gate fingers to a gate bus, with a portion of the gate connector positioned between a first portion and a second portion of a second dielectric layer.

[0064] In some embodiments, at least a portion of the second dielectric layer extends laterally across the entire width of the gate finger in at least a portion of the inert region of the semiconductor device, and at least a portion of the auxiliary dielectric layer extends laterally across less than the entire width of the gate finger in at least a portion of the active region of the semiconductor device.

[0065] Further embodiments of the present invention provide a method for forming a semiconductor device. According to these methods, a gate trench is formed within a semiconductor layer structure. A gate dielectric layer is formed within the gate trench. A gate finger is formed on the gate dielectric layer within the gate trench. An auxiliary dielectric layer is formed on the gate finger and on the gate dielectric layer. A gate bus is formed on the auxiliary dielectric layer.

[0066] In some embodiments, the auxiliary dielectric layer is formed on the portion of the gate finger that lies within the gate trench.

[0067] In some embodiments, the auxiliary dielectric layer overlaps perpendicular to the gate trench.

[0068] In some embodiments, the method further includes forming a gate connector on an auxiliary dielectric layer. In some embodiments, the auxiliary dielectric layer is interposed between the gate connector and the gate finger. In some embodiments, the gate connector extends between the gate bus and the gate finger, electrically connecting the gate finger to the gate bus.

[0069] In some embodiments, the auxiliary dielectric layer extends over the gate trench for less than half the length of the gate trench.

[0070] In some embodiments, the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps the gate trench perpendicularly along substantially the entire length of the gate trench.

[0071] In some embodiments, the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps the gate fingers perpendicularly along substantially the entire length of the gate trench. [Brief explanation of the drawing]

[0072] [Figure 1] This is a semi-logarithmic graph showing the relationship between the applied electric field strength and the lifetime of the gate dielectric layer. [Figure 2A] This is a schematic top view of a conventional silicon carbide MOSFET. [Figure 2B] Figure 2A is a schematic top view of a conventional silicon carbide MOSFET with various upper metal and dielectric layers removed. [Figure 3A] This is a greatly enlarged view of section C of the top view in Figure 2B. [Figure 3B] This is a schematic cross-sectional view taken along line B-B in Figure 3A. [Figure 3C] This is a schematic cross-sectional view taken along the line C-C in Figure 3A. [Figure 3D]This is a schematic cross-sectional view taken along line D-D in Figure 3A. [Figure 4A] This is a significantly enlarged view of a MOSFET according to an embodiment of the present invention, and the figure corresponds to part C shown in Figure 2B. [Figure 4B] This is a schematic cross-sectional view taken along line B-B in Figure 4A. [Figure 4C] This is a schematic cross-sectional view taken along the line C-C in Figure 4A. [Figure 4D] This is a schematic cross-sectional view taken along line D-D in Figure 4A. [Figure 5A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 5B] Figure 5A is a schematic cross-sectional view taken along the gate trench. [Figure 5C] Figure 5A is a schematic cross-sectional view taken between the two gate trenches. [Figure 5D] Figure 5A is a schematic cross-sectional view taken across the gate trench. [Figure 6A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 6B] Figure 6A is a schematic cross-sectional view taken along the gate trench. [Figure 6C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 6A. [Figure 6D] Figure 6A is a schematic cross-sectional view taken across the gate trench. [Figure 7A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 7B] Figure 7A is a schematic cross-sectional view taken along the gate trench. [Figure 7C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 7A. [Figure 7D] Figure 7A is a schematic cross-sectional view taken across the gate trench. [Figure 8A]Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 8B] Figure 8A is a schematic cross-sectional view taken along the gate trench. [Figure 8C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 8A. [Figure 8D] Figure 8A is a schematic cross-sectional view taken across the gate trench. [Figure 9A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 9B] Figure 9A is a schematic cross-sectional view taken along the gate trench. [Figure 9C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 9A. [Figure 9D] Figure 9A is a schematic cross-sectional view taken across the gate trench. [Figure 10A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 10B] Figure 10A is a schematic cross-sectional view taken along the gate trench. [Figure 10C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 10A. [Figure 10D] Figure 10A is a schematic cross-sectional view taken across the gate trench. [Figure 11A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 11B] Figure 11A is a schematic cross-sectional view taken along the gate trench. [Figure 11C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 11A. [Figure 11D] Figure 11A is a schematic cross-sectional view taken across the gate trench. [Figure 12A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 12B] Figure 12A is a schematic cross-sectional view taken along the gate trench. [Figure 12C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 12A. [Figure 12D] Figure 12A is a schematic cross-sectional view taken across the gate trench. [Figure 13A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 13B] Figure 13A is a schematic cross-sectional view taken along the gate trench. [Figure 13C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 13A. [Figure 13D] Figure 13A is a schematic cross-sectional view taken across the gate trench. [Figure 14A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 14B] Figure 14A is a schematic cross-sectional view taken along the gate trench. [Figure 14C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 14A. [Figure 14D] Figure 14A is a schematic cross-sectional view taken across the gate trench. [Figure 15A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 15B] Figure 15A is a schematic cross-sectional view taken along the gate trench. [Figure 15C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 15A. [Figure 15D] Figure 15A is a schematic cross-sectional view taken across the gate trench. [Figure 16A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 16B] Figure 16A is a schematic cross-sectional view taken along the gate trench. [Figure 16C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 16A. [Figure 16D] Figure 16A is a schematic cross-sectional view taken across the gate trench. [Figure 17A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 17B] Figure 17A is a schematic cross-sectional view taken along the gate trench. [Figure 17C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 17A. [Figure 17D] Figure 17A is a schematic cross-sectional view taken across the gate trench. [Figure 18A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 18B] Figure 18A is a schematic cross-sectional view taken along the gate trench. [Figure 18C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 18A. [Figure 18D] Figure 18A is a schematic cross-sectional view taken across the gate trench. [Figure 19A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 19B] Figure 19A is a schematic cross-sectional view taken along the gate trench. [Figure 19C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 19A. [Figure 19D] Figure 19A is a schematic cross-sectional view taken across the gate trench. [Figure 20A] Figures 4A to 4D show the method for fabricating the MOSFETs, and this is a schematic top view corresponding to Figure 4A. [Figure 20B] Figure 20A is a schematic cross-sectional view taken along the gate trench. [Figure 20C] This is a schematic cross-sectional view taken between the two gate trenches in Figure 20A. [Figure 20D] Figure 20A is a schematic cross-sectional view taken across the gate trench. [Figure 21] Figures 4A to 4D are schematic cross-sectional views of the modified version of the silicon carbide MOSFET. [Figure 22A] Figures 4A to 4D are schematic cross-sectional views of another modified version of the silicon carbide MOSFET. [Figure 22B] Figures 4A to 4D are schematic cross-sectional views of another modified version of the silicon carbide MOSFET. [Figure 23A] This is a schematic cross-sectional view showing an alternative method for fabricating silicon carbide semiconductor devices according to embodiments of the present invention. [Figure 23B] This is a schematic cross-sectional view showing an alternative method for fabricating silicon carbide semiconductor devices according to embodiments of the present invention. [Figure 23C] This is a schematic cross-sectional view showing an alternative method for fabricating silicon carbide semiconductor devices according to embodiments of the present invention. [Figure 23D] This is a schematic cross-sectional view showing an alternative method for fabricating silicon carbide semiconductor devices according to embodiments of the present invention. [Figure 24] This is a flowchart illustrating a method according to an embodiment of the present invention for fabricating gate trench semiconductor devices. [Modes for carrying out the invention]

[0073] Vertical silicon carbide-based power semiconductor devices with gate trenches, such as vertical power MOSFETs and vertical IGBTs, are attractive for many applications due to their inherently low on-resistivity, which allows for more efficient operation in power switching. Gate trench vertical power devices exhibit lower on-state resistivity because the channels are formed in the sidewalls of the gate trench. Furthermore, the carrier mobility in the sidewall channels of gate trench power devices can be approximately 2 to 4 times higher than the corresponding carrier mobility in the horizontal channels of standard (i.e., non-gate trench) vertical power devices. This increased channel mobility leads to increased current density in on-state operation, enabling higher switching speeds. Additionally, the trench design allows for a reduced overall device pitch, improving integration density. Reduced conduction losses (due to reduced on-state resistance) and increased switching speeds make gate trench power devices suitable for high-frequency power applications with low to moderate voltage blocking requirements (e.g., 600-1200 volts). These devices reduce the requirements of associated passive components, resulting in lower costs, lower weight, and potentially requiring relatively simple cooling schemes. Since MOSFETs are the most widely used silicon carbide-based power semiconductor gate devices, the following discussion will primarily focus on MOSFET embodiments. However, it will be understood that, alternatively, each of the embodiments described may be implemented using a non-oxide gate dielectric layer (e.g., nitrides, high-dielectric-constant materials, etc.), and the same techniques may be used to form other gate-trench power semiconductor devices such as IGBTs and gate-controlled thyristors.

[0074] Gate trench power MOSFETs are susceptible to oxide reliability issues due to the presence of high electric fields in the gate oxide layer lining the bottom and side walls of the gate trench. These high electric fields can degrade the gate oxide layer over time, potentially leading to device failure. The high electric fields occur in the lower and upper corner regions of the gate oxide layer, and the electric field congestion effect can dramatically increase the level of the electric field in the gate oxide layer. When a gate trench MOSFET operates in reverse-blocking mode (i.e., when the MOSFET is in its off state), the electric field extends upward from the drain terminal (located at the bottom of the semiconductor layer structure) towards the top of the semiconductor layer structure. Therefore, under reverse-blocking operation, the bottom portion of the gate dielectric layer experiences high electric field levels, with the electric field being highest along the lower corners of the gate oxide layer formed at the bottom edge of the gate trench. The so-called "trench shielding region" (which is a high-density semiconductor layer having the same conductivity type as the channel region) is typically located below and / or beside the gate trench of a gate trench power MOSFET to reduce the electric field level in the gate oxide layer during reverse blocking operation.

[0075] During the ON state or "forward" operation, the electric field is highest in the upper portion of the gate oxide layer. Typically, gate fingers are recessed so that the upper surface of each gate finger lies within the gate trench (i.e., below the upper surface of the semiconductor layer structure), thereby reducing the electric field at the upper corners of the gate oxide layer. However, at the ends of the gate trench where the gate fingers connect to the gate bus, the gate structure needs to extend over the gate oxide layer in the upper corner region to make electrical connections between each gate finger and the gate bus. Therefore, the upper corners of the gate oxide layer at one or both ends of the gate trench can be the most fragile parts of the gate dielectric layer during ON state operation.

[0076] Another potential problem with conventional gate trench power MOSFETs is that the field oxide layer formed beneath the gate bus can be laterally undercut during the fabrication process. Such lateral undercuts can arise because the field oxide layer is a blanket onto which it is deposited on the device and therefore formed within the gate trench. Wet etching is performed to remove the field oxide layer from the gate trench. Unfortunately, this wet etching process can be difficult to control, and as a result, lateral undercuts of the field oxide layer beneath the gate bus may occur. This undercut is undesirable because it can cause detachment of the photoresist used during wet etching and / or lead to problems with uniformity between wafers.

[0077] According to embodiments of the present invention, a gate trench power semiconductor device is provided having a gate dielectric layer with reinforced upper corners at one or both ends of the gate trench. In some embodiments, these reinforced gate dielectric layers may comprise both a conventional gate dielectric layer and an auxiliary dielectric layer placed on top of the conventional gate dielectric layer. The reinforced dielectric layer can be thicker than the conventional dielectric layer (and often several times thicker), thereby providing improved protection against oxide film breakdown at the upper corners of the gate trench ends. Thus, the gate trench power semiconductor device according to embodiments of the present invention can exhibit an extended lifetime. Furthermore, in the fabrication of the gate trench power semiconductor device according to embodiments of the present invention, wet etching, which is performed to remove field oxide from the gate trench, may be omitted. Thus, potential lateral undercuts of the field oxide layer beneath the gate bus that may occur during such wet etching can be avoided. This further improves the reliability of the gate trench power semiconductor device according to embodiments of the present invention.

[0078] According to further embodiments of the present invention, the reinforced gate dielectric layer may extend along the length of the gate trench to the upper surface of the semiconductor layer structure, thereby providing improved protection against fracture of the gate dielectric layer along the entire length of the upper corners of the gate trench. In some embodiments, this may be achieved by "thickening" the upper portion of each gate dielectric layer along the entire length of each gate trench by having an auxiliary dielectric layer that overlaps perpendicularly with the portion of each gate dielectric layer that extends to the sidewall of each gate trench. In other embodiments, the auxiliary dielectric layer may extend laterally and overlap perpendicularly with the gate fingers. Such embodiments may provide even greater protection against dielectric fracture.

[0079] Before discussing gate trench power semiconductor devices according to embodiments of the present invention and methods for forming such devices, it is beneficial to review conventional gate trench power semiconductor devices.

[0080] Figure 2A is a schematic top view of a conventional power MOSFET 100. Figure 2B is a schematic plan view of the power MOSFET 100, with its various upper metal and dielectric layers omitted to show the gate fingers and gate bus. Figure 3A is a greatly enlarged view of portion C of the top view in Figure 2B. Figures 3B to 3D are schematic cross-sectional views taken along lines B-B, CC, and DD in Figure 3A. It should be understood that the thicknesses of the various layers, patterns, and elements in Figures 3A to 3D and other figures herein are not necessarily to scale.

[0081] First, referring to Figures 3B to 3D, it can be seen that the power MOSFET 100 includes a semiconductor layer structure 150 and multiple metal layers and dielectric layers formed on both sides of the semiconductor layer structure 150.

[0082] Referring to Figure 2A, a gate bond pad 102 and one or more source bond pads 104-1, 104-2 are formed on the upper side of the semiconductor layer structure 150, and a drain pad (not shown) may be provided on the bottom side of the MOSFET 100. Each of the gate pad 102 and source pad 104 may be formed of a metal such as aluminum to which bond wires can be easily attached via conventional techniques such as thermal compression or soldering. A protective layer 109, such as a polyimide layer, may cover the entire upper surface of the MOSFET 100 other than the gate pad 102 and source pad 104.

[0083] The MOSFET 100 includes source contacts 170 / 172 (shown as dashed boxes in Figure 2A) that electrically connect the source region 130 (Figures 3B-3D) in the semiconductor layer structure 150 to source bond pads 104-1, 104-2. In some embodiments, the source bond pads 104-1, 104-2 may be portions of the source contacts 170 / 172 exposed through openings in the protective layer 109. The source contacts 170 / 172 may generally be located on or corresponding to the "active region" 106 of the MOSFET where the unit cell transistor is located. The inactive region 108 of the MOSFET 100 surrounds the active region 106. The inactive region 108 may include a gate pad region located beneath the gate pad 102 and a gate bus region (discussed below) that extends to the periphery of the device.

[0084] Bond wires are shown in Figure 2A and may be used to connect the gate bond pad 102 and the source bond pad 104 to an external circuit. The drain pad (not shown) on the bottom side of the MOSFET 100 may be connected to an external circuit, for example, through a submount (not shown) placed underneath.

[0085] Referring to Figure 2B, the MOSFET 100 further includes a plurality of gate fingers 166 connected to a gate pad 102 via one or more gate buses 174. The gate fingers 166 may include, for example, a doped polysilicon pattern. The gate fingers 166 may extend horizontally across the semiconductor layer structure 150 (as shown in Figure 2B) or vertically across the semiconductor layer structure 150. Other configurations may be used (for example, the unit cell may have a hexagonal configuration). The gate fingers 166 are formed in gate trenches within the upper surface of the semiconductor layer structure 150. The gate pad 102 and gate buses 174 may have a metallic structure in the exemplary embodiment and are located within the inert region 108 of the MOSFET 100.

[0086] Figure 3A is a greatly enlarged view of portion "C" of Figure 2B, showing the portion of MOSFET 100 in which some of the gate fingers 166 of MOSFET 100 are connected to one of the gate buses 174. As shown in Figure 3A, the gate bus 174 is connected to a gate pad 176 (the gate pad 176 may be a gate bond pad 102, or a separate structure electrically connected to the gate bond pad 102). The connection between the gate bus 174 and the gate pad 176 may be a direct connection as shown in Figure 3A, or alternatively, through a gate resistor (not shown). Multiple gate trenches 160 are formed within the semiconductor layer structure 150, with their ends near the gate buses 174. Source contacts 170 / 172 extend over the gate trenches 160 in an inert region 108. The intermetallic dielectric layer 168 (for example, a silicon oxide layer) insulates the gate finger 166, gate bus 174, and gate pad 176 from the source contacts 170 / 172.

[0087] Figures 3B to 3D show the layer structure of the MOSFET 100. First, referring to FIGS. 3C and 3D, the MOSFET 100 includes a substrate 110. The substrate 110 may include, for example, a single crystal 4H silicon carbide semiconductor substrate (i.e., an n+ silicon carbide substrate) highly doped with n-type impurities. An n-type silicon carbide drift region 112 is formed on the upper surface of the substrate 110. The n-type silicon carbide drift region 112 may be formed, for example, by epitaxial growth on the silicon carbide substrate 110. The n-type silicon carbide drift region 112 may be a low-concentration n-type (n - ) region, and in this specification, it may be referred to as either a drift "region" or a drift "layer". In an exemplary embodiment, the n-type silicon carbide drift region 112 may have a doping concentration of 1×10 14 to 5×10 16 dopants / cm 3 . The n-type silicon carbide drift region 112 may be, for example, a thick region having a vertical height of 3 to 100 microns above the substrate 110. The upper portion of the n-type silicon carbide drift region 112 is doped at a higher concentration than its lower portion (for example, 1×10 16 to 1×10 17 dopants / cm 3 ), and a current diffusion layer may be provided in the upper portion of the n-type silicon carbide drift region 112.

[0088] A medium-concentration (p)p-type silicon carbide well region 120 ("p-well") is formed on the upper surface of the current diffusion layer 114. The p-well 120 may be formed, for example, by ion implantation. Then, for example, by ion implantation, a high-concentration (n + ) n-type silicon carbide source region 130 is formed in the upper portion of the p-type well 120. As shown in FIGS. 3B and 3D, a deep shielding region 124 is provided in the drift region 112 and the current diffusion layer 114. (Since the deep shielding connection pattern 122 is outside the portion shown in cross-section in FIGS. 3B to 3D), although not visible in the figure, a high-concentration (p +)p-type silicon carbide deep shielding connection pattern 122 is formed. Finally, high concentration p-type (p - ) Region 140 is formed in the upper part of the n-type drift region 112 by ion implantation. High concentration p-type (p - ) Region 140 is formed in the inert region 108 of MOSFET 100. High concentration p-type (p - Region 140 is formed beneath the gate bus 174 and gate pad 176. Substrate 110, drift region 112, current diffusion layer 114, p-well 120, deep shielding connection pattern 122, source region 130, and high-density p-type (p - The regions 140 form a semiconductor layer structure 150. Each of these regions may contain silicon carbide. Therefore, the semiconductor layer structure 150 may be a wide-bandgap semiconductor layer structure 150.

[0089] Multiple gate trenches 160 are formed on the upper surface of the semiconductor layer structure 150 (for example, by etching). It will be understood that only a small portion of each gate trench 160 is visible in Figure 3A. The gate dielectric layer 164 lines the bottom, side walls, and end walls of each gate trench 160. Each gate finger 166 may substantially fill each gate trench 160, separated from the semiconductor layer structure 150 by the gate dielectric layer 164. At the ends of the gate trenches 160, each gate finger 166 includes a gate finger extension 167 that projects laterally from the gate trench 160 across the semiconductor layer structure 150. The gate dielectric layer 164 and the field oxide layer 162 separate each gate finger extension 167 from the semiconductor layer structure 150. The gate bus 174 is formed on the gate finger extension 167 to provide an electrical connection between the gate finger 166 and the gate bus 174.

[0090] During ON-state operation, a high electric field is generated in the portion of the gate dielectric layer 164 that extends along the upper sidewalls and end walls of each gate trench 160. Due to the electric field congestion effect, a high electric field is generated at the upper corners of the gate trench 160 where the sidewalls and end walls of the gate trench 160 merge with the upper surface of the semiconductor layer structure 150. The electric field along the upper surface of the sidewalls of the gate trench 160 can be reduced by recessing the upper surface of the gate finger 166 down to below the upper surface of the gate trench 160. However, at the end of the gate trench 160 where the gate finger extension 167 protrudes from the gate trench 160 and connects to the gate bus 174, the gate finger 166 cannot be recessed. As a result, a very high electric field (as indicated by the arrow) can be generated in the portion of the gate dielectric layer 164 within the region labeled E in Figure 3B. These high electric fields may damage the corner regions of the gate dielectric layer 164, which are circled in region E.

[0091] The upper corner of the gate trench 160 refers to the region where the opposite side walls (or end walls) of the gate trench 160 meet or intersect with the upper surface of the semiconductor layer structure 150, and the lower corner of the gate trench 160 refers to the region where the opposite side walls (or end walls) of the trench 160 meet or intersect with the bottom surface of the gate trench 160. Therefore, it will be understood that "corner" can refer to both a two-dimensional corner (as shown in region E of Figure 3B) and / or a three-dimensional corner existing in a cubic shape, for example.

[0092] As discussed above, one common failure mechanism in power semiconductor devices is device failure due to the breakdown of the gate dielectric layer. The strength of the electric field generated in the gate dielectric layer of conventional power semiconductor devices during on-state operation is not constant. The gate dielectric layer 164 of the MOSFET 100 in Figures 3A to 3D may be considered as the dielectric of a U-shaped parallel plate capacitor, where each gate finger 166 acts as the inner plate of the capacitor, and the portion of the semiconductor layer structure 150 on the other side of the gate dielectric layer 164 opposite the gate fingers 166 acts as the outer plate of the capacitor. The bottom and side walls of the U-shaped capacitor act like a standard parallel plate capacitor, so during on-state operation, the electric field will have a roughly constant value throughout these "parallel plate" regions of the gate dielectric layer. However, in the lower and upper "corner / corner regions" of the gate dielectric layer 164, where the extension transitions from vertical to horizontal, the electric field congestion effect increases the level of the electric field. In the off state (reverse blocking operation), the highest electric field is generated at the lower corner of the dielectric layer 164 where the side wall of the gate trench 160 meets its bottom surface. In the on state (forward conducting operation), the highest electric field is generated at the upper corner of the gate dielectric layer 164 where the gate dielectric layer 164 extends from the upper side wall and end wall of the gate trench 160 to the upper surface of the semiconductor layer structure 150. As described above, the upper surface of the gate finger 166 may be recessed down to below the upper surface of the gate trench 160, thereby reducing the electric field of the gate dielectric layer 164 along the upper side wall of the gate trench 160. However, as shown in Figure 3B, in order to electrically connect the gate fingers 166 to the gate bus 174, the corresponding gate finger connectors 167 must extend beyond the end walls of each gate trench 160 and contact each gate finger 166 located within the gate trench 160. Therefore, such recesses cannot occur adjacent to at least one end wall of each gate trench 160.

[0093] When a gate bias voltage is applied to turn on the MOSFET 100, a very high electric field is formed in the portion of the gate oxide layer 164 that extends vertically along the end wall of the gate trench 160 and then transitions 90° horizontally along the semiconductor layer structure 150. Here, the electric field is particularly high due to the electric field congestion effect that occurs in the corner / edge regions of the dielectric layer. Therefore, this portion of the gate oxide layer 164 is particularly susceptible to failure.

[0094] As discussed above, embodiments of the present invention provide an improved gate trench power semiconductor device having a thicker dielectric layer lining the end walls of the gate trench. By providing a thickened dielectric layer adjacent to the upper portion of the end walls of the gate trench, the electric field is more diffused in these regions during on-state operation, thereby reducing its level, and more dielectric material is provided between the gate structure and the semiconductor layer structure. Therefore, the semiconductor device according to embodiments of the present invention is less prone to failure.

[0095] Figures 4A to 4D are various diagrams of a gate trench MOSFET 200 according to an embodiment of the present invention. Specifically, Figure 4A is a greatly enlarged view of the MOSFET 200 showing the region corresponding to part C shown in Figure 2B (Note that although Figures 2A and 2B show MOSFET 100, the corresponding diagram of MOSFET 200 is the same as that shown in Figures 2A and 2B, and therefore the corresponding diagram of MOSFET 200 is not provided or described herein). Figure 4B is a schematic cross-sectional view taken along line B-B in Figure 4A. Figure 4C is a schematic cross-sectional view taken along line C-C in Figure 4A. Finally, Figure 4D is a schematic cross-sectional view taken along line D-D in Figure 4A.

[0096] As shown in Figures 4B to 4D, a silicon carbide drift region 212 is provided on the upper surface of the substrate 210. The substrate 210 may include, for example, a single-crystal 4H silicon carbide semiconductor substrate (i.e., an n+ silicon carbide substrate) highly doped with n-type impurities. However, other polytype silicon carbide substrates may be used, or the substrate may be made of a material other than silicon carbide. The n-type silicon carbide drift region 212 may be formed, for example, by epitaxial growth on the silicon carbide substrate 210. The n-type silicon carbide drift region 212 may be doped at a low concentration with an n-type dopant (n - For example, the n-type silicon carbide drift region 212 is 1 × 10⁻⁶. 14 From 5x10 16 Dopant / CM 3 It may have a doping concentration of . The n-type silicon carbide drift region 212 may be, for example, a thick region above the substrate 210 with a vertical height of 3 to 100 microns. The upper portion of the n-type silicon carbide drift region 212 may be doped to a higher concentration than its lower portion (for example, 1 × 10⁻⁶). 16 From 1 x 10 17 Dopant / CM 3 (Doping concentration) A current diffusion layer 214 may be provided in the upper part of the n-type silicon carbide drift region 212.

[0097] A medium-concentration (p)p-type silicon carbide well region 220 ("p-well") is formed on the upper surface of the current diffusion layer 214. The p-well 220 may be formed, for example, by ion implantation. Then, a high-concentration (n + The n-type silicon carbide source region 230 is formed, for example, by ion implantation, in the upper part of the p-type well 220. As shown in Figures 4B and 4D, the deep shielding region 224 is provided within the drift region 212 and the current diffusion layer 214. (Although not visible in the figures, as the deep shielding connection pattern 222 is outside the portion shown in the cross-sectional view in Figures 4B to 4D), the deep trench shielding region 224 is electrically connected to the source contacts 270 / 272, resulting in a high concentration (p +)p-type silicon carbide deep shielding connection pattern 222 is formed. Finally, by ion implantation, a high concentration of p-type (p - ) Region 240 is formed. (corresponding to region 108 in Figure 2A) Ion implantation in at least a portion of the inert region 208 of the device results in a high concentration of p-type (p) in the upper portion of the n-type drift region 212. - ) Region 240 is formed. Specifically, high concentration p-type (p - Region 240 is formed in the inert region 208 of the MOSFET 200, in the portion below the gate bus 274 and gate pad 276. Substrate 210, drift region 212, current diffusion layer 214, p-well 220, deep shielding connection pattern 222, source region 230, and high-concentration p-type (p - Region 240 forms a semiconductor layer structure 250. Each of these regions and layers may contain silicon carbide. The semiconductor layer structure 250 shown in Figures 10A to 10D is merely an example, and it will be understood that other configurations of the semiconductor layer structure 250 can be used without departing from the embodiments described herein. For example, the semiconductor layer structure 250 may include additional layers or regions, or regions (e.g., current diffusion layer 214) may be omitted.

[0098] Multiple gate trenches 260 are formed on the upper surface of the semiconductor layer structure 250 (for example, by etching). It will be understood that only a small portion of each gate trench 260 can be seen in Figure 4A. The gate dielectric layer 264 lines the bottom, side walls, and end walls of each gate trench 260. The gate dielectric layer 264 is also a high-concentration p-type (p - ) extends to region 240. Each gate finger 266 may substantially fill each gate trench 260 and is separated from the semiconductor layer structure 250 by the gate dielectric layer 264.

[0099] At the end of the gate trench 160, each gate finger 166 includes a gate finger extension 167 that protrudes laterally from the gate trench 160 across the semiconductor layer structure 150. The gate dielectric layer 164 and the field oxide layer 162 separate each gate finger extension 167 from the semiconductor layer structure 150. A gate bus 174 is formed on the gate finger extension 167 to provide an electrical connection between the gate finger 166 and the gate bus 174. The auxiliary dielectric layer 262 is a high-concentration p-type (p) oxide layer of the gate dielectric layer 264. - The auxiliary dielectric layer 262 extends over the portion that extends into region 240. The auxiliary dielectric layer 262 further extends onto the upper surface of the gate finger 266. The auxiliary dielectric layer 262 may have a thickness of, for example, 2 to 15 times that of the gate dielectric layer 264. In some embodiments, the auxiliary dielectric layer 262 may be a field oxide layer.

[0100] As described above, the auxiliary dielectric layer 262 overlaps perpendicularly with both the gate trench 260 and the gate finger 266. In this specification, two elements of a semiconductor device are "overlapping perpendicularly" if the axis perpendicular to the bottom surface of the semiconductor layer structure of the device intersects with both elements.

[0101] As best illustrated in Figure 4B, the auxiliary dielectric layer 262 increases the amount of dielectric material provided on the upper edge of the gate trench 260. This diffuses the electric field in this region of the gate dielectric layer 264 during on-state operation. Furthermore, by increasing the thickness of the dielectric material layer in this region of the device, more dielectric material must be destroyed before the dielectric layer is damaged enough to allow a short circuit between the gate finger 266 and the semiconductor layer structure 250, thus extending the time to failure. Consequently, the auxiliary dielectric layer 262 can significantly extend the expected lifespan of MOSFET 200 compared to that of MOSFET 100 under the same operating conditions.

[0102] Figures 5A to 5D through 20A to 20D are various diagrams illustrating the manufacturing method of MOSFET 200 shown in Figures 4A to 4D. Specifically, Figures 5A to 20A are schematic top views corresponding to region C shown in Figure 2B. Figures 5B to 20B are schematic cross-sectional views taken along the corresponding BB lines in Figures 5A to 20A, respectively. Figures 5C to 20C are schematic cross-sectional views taken along the corresponding CC lines in Figures 5A to 20A, respectively. Figures 5D to 20D are schematic cross-sectional views taken along the corresponding DD lines in Figures 5A to 20A, respectively. Note that, to avoid obscuring the drawings, only the cross-sectional lines are shown in Figures 5A to 20A, and the labels BB, CC, and DD are not shown. Figure 4A includes the labels BB, CC, and DD, and it should be understood that the corresponding cross-sectional lines in Figures 5A to 20A are the same as those shown in Figure 4A.

[0103] Referring to Figures 5A to 5D, a low-concentration n-type drift layer 212 is formed on a high-concentration n-type semiconductor substrate 210. Optionally, an n-type current diffusion layer 214, doped to a higher concentration than the drift layer 212, may be formed in or on the upper portion of the drift layer 212. For example, after a medium-concentration (p)p-type silicon carbide p-well 220 is formed on the current diffusion layer 214 by ion implantation, a high-concentration (n + A high concentration (p) n-type silicon carbide source region 230 is formed in the upper portion of the p-well 220. Finally, as shown in Figure 5A, the deep trench shielding region formed below the gate trench in a later processing step is electrically connected to the source contacts 270 / 272. + A p-type silicon carbide deep shielding connection pattern 222 is formed. The deep shielding connection pattern 222 is located outside of what is shown in the cross-sectional view in Figures 5B to 5D.

[0104] Referring to Figures 6A to 6D, an ion implantation mask (for example, a photoresist mask) 242 is formed on the active area 206 of the MOSFET 200.

[0105] Referring to Figures 7A to 7D, the inert region 208 of MOSFET 200 contains the above high-concentration p-type (p + To form region 240, a p-type dopant is implanted into the exposed region of the semiconductor layer structure 250 via ion implantation.

[0106] Referring to Figures 8A to 8D, the ion implantation mask 242 may then be removed.

[0107] Referring to Figures 9A to 9D, multiple gate trenches 260 are formed on the upper surface of the semiconductor layer structure 250. The gate trenches 260 primarily extend across the active region 206 of the MOSFET 200, although the end portions of the gate trenches 260 may extend into the inactive region 208. As shown in Figures 9C and 9D, the gate trenches 260 extend vertically through the p-well 220 and may also extend partially or completely through the current diffusion layer 214. In this specification, “vertical” means a direction perpendicular to the main surface of the semiconductor layer structure of the device. The gate trenches 260 may have a depth of, for example, 0.5 to 3.0 microns. The sidewalls of the p-well 220 exposed by the gate trenches 260 act as the channel region of the completed MOSFET 200.

[0108] Referring to Figures 10A to 10D, an annealing step is performed to round the upper edge of the gate trench 260. In addition, high-concentration p-type (p) is implanted by ion implantation. + A deep shielding region 224 is formed beneath the gate trench 260 within the semiconductor layer structure 250, and as part of this ion implantation process, a p-type deep shielding connection pattern 222 may also be formed at a selected location on the sidewall of each gate trench 260, as shown in Figure 10A. The masks used in forming the deep shielding region 224 and the deep shielding connection pattern 222 are not shown.

[0109] As shown in the figure, in this processing step, the device includes a semiconductor layer structure comprising a substrate 210, a drift layer 212, a current diffusion layer 214, a well region 220, a deep shielding connection pattern 222, a deep shielding pattern 224, a source region 230, and a high-density p-type layer 240. A trench 260 is provided on the upper surface of the semiconductor layer structure 250, and a deep shielding region 224 is formed below each gate trench 260.

[0110] Referring to Figures 11A to 11D, the gate dielectric layer 264 is a blanket formed in the active region 206 of the device (and extending into a portion of the inactive region 208). The gate dielectric layer 264 may include a stable dielectric material having a band gap of approximately 2 eV (or more), which is larger than the semiconductor material placed beneath it. The gate dielectric layer 264 is typically implemented as a silicon oxide (SiO2) layer, but other materials may be used. For example, the gate dielectric layer 264 may include silicon nitride, silicon oxynitride, etc. as alternatives. In some cases, the gate dielectric layer 264 may be a multilayer structure comprising at least two layers of different dielectric materials.

[0111] The gate dielectric layer 264 may be a conformal layer lining the bottom, side walls, and end walls of the gate trench 260. As shown in the figure, the gate dielectric layer 264 may also extend to the top surface of the semiconductor layer structure 250. In other embodiments, the gate dielectric layer 264 may not extend to the top surface of the semiconductor layer structure 250, or some or all of any such portion may be removed. Typically, the thickness of the gate dielectric layer is based on a desired equivalent electrooxide thickness that optimizes various performance characteristics of the device. For example, when a silicon oxide dielectric layer is used, a typical thickness of the gate oxide layer in a silicon carbide-based power semiconductor device may be, for example, approximately 300 to 1500 nm. After the gate dielectric layer 264 is formed, an annealing step may be performed in a nitrogen / oxygen atmosphere to increase the density of the gate dielectric layer 264.

[0112] In this specification, when referring to the "thickness" of the gate dielectric layer (for example, the gate dielectric layer 264), it should be noted that this thickness refers to the extent of the gate dielectric layer in the direction perpendicular to the substrate on which the gate dielectric layer is formed. Therefore, the vertical thickness of the gate dielectric layer 264 is measured for the portion of the gate dielectric layer 264 that is on the upper surface of the semiconductor layer structure 250 and the portion that is below the gate trench 260, and the horizontal thickness of the portion of the gate dielectric layer 264 that is on the sidewalls and endwalls of the gate trench 260 is measured.

[0113] Continuing to refer to Figures 11A to 11D, the conductive layer 265 is a deposited blanket that is patterned in a later processing step to form the gate fingers 266 of the MOSFET 200. In the exemplary embodiment, the conductive layer 265 may be a doped polysilicon layer. In other embodiments, the conductive layer 265 may contain a silicide (e.g., NiSi, TiSi, WSi, CoSi), a metal, or another stable conductor. Other suitable materials for the gate electrode include various metals such as Ti, Ta, or W, or metal nitrides such as TiN, TaN, or WN. The conductive layer 265 may fill the gate trench 260, or it may cover the entire semiconductor layer structure 250.

[0114] Referring to Figures 12A to 12D, an etch-back process is performed on the conductive layer 265 to remove the conductive layer 265 from the portion of the conductive layer 265 that is not inside the gate trench 260. The conductive layer 265 is a conformal layer deposited to have a thickness greater than twice the width of the gate trench 260. As a result, the conductive layer 265 fills the gate trench 260 and may have small depressions (areas of reduced thickness, not shown) extending longitudinally above the center of each trench 260. This etch-back process may be reactive ion etching and may remove the conductive pattern 265 from the portion not inside the gate trench 260. This etch-back process converts the conductive layer 265 into a plurality of gate fingers 266 formed within each gate trench 260. The portion of the gate oxide layer 264 that is outside the gate trench 260 may or may not be removed during this etch-back process, depending on the selection of the etch recipe. Although the gate oxide layer 264 is shown in Figures 12A to 12D as not being removed from the top surface of the semiconductor layer structure 250, it should be understood that, if a different etch recipe is used, the portion of the gate oxide layer 264 that is outside the gate trench may be removed.

[0115] Referring to Figures 13A to 13D, the auxiliary dielectric layer 262 is deposited on the semiconductor layer structure 250. The auxiliary dielectric layer 262 may be a single oxide layer or a combination of dielectric layers, such as one or more silicon oxide layers. The auxiliary dielectric layer 262 may be a thick layer (for example, 4,000 to 15,000 angstroms thick). In the exemplary embodiment, the auxiliary dielectric layer 262 may be 2 to 15 times thicker than the gate dielectric layer 264. In other embodiments, the auxiliary dielectric layer 262 may be 4 to 12 times thicker than the gate dielectric layer 264, or 6 to 10 times thicker than the gate dielectric layer 264. In the exemplary embodiment, the auxiliary dielectric layer 262 may be a field oxide layer 262. The auxiliary dielectric layer 262 may be formed, for example, using a high-temperature oxide deposition process. The auxiliary dielectric layer 262 may be formed throughout the entire inert region 208 of the device, or it may be a blanket formed throughout the entire device.

[0116] Referring to Figures 14A to 14D, an etch-back process is performed on the auxiliary dielectric layer 262. The auxiliary dielectric layer 262 is etched so as not to cover the gate trench 260, but as shown in Figures 14A and 14B, the auxiliary dielectric layer 262 covers the edge portions of the gate trench 260. Specifically, the auxiliary dielectric layer 262 extends to the upper surface of the end of each gate finger 266 and to the source region 230 adjacent to the end of the gate trench 260 (Figure 14C). Thus, the auxiliary dielectric layer 262 extends over the gate fingers in the longitudinal direction of the gate fingers 266. In particular, the auxiliary dielectric layer 262 increases the thickness of the dielectric material layer provided above the end walls of the gate trench 260. Therefore, the electric field formed in the portion of the gate dielectric layer 264 extending from the end wall of the trench 260 to the upper surface of the p-type region 240 diffuses from the gate dielectric layer 264 to the auxiliary dielectric layer 262, thereby reducing the value of the electric field.

[0117] Referring to Figures 15A to 15D, the conductive layer 282 is selectively formed on the auxiliary dielectric layer 262 and the gate finger 266. In the exemplary embodiment, the conductive layer 282 may include, for example, a polysilicon layer, but other semiconductor materials or metals may be used as alternatives or additions.

[0118] Referring to Figures 16A to 16D, a photoresist mask 242 is formed to cover a portion of the conductive layer 282. Subsequently, an etch-back process is performed to planarize the portion of the conductive layer 282 exposed to the photoresist mask 242.

[0119] Referring to Figures 17A to 17D, the photoresist mask 242 is removed.

[0120] Referring to Figures 18A to 18D, a photoresist mask 244 is formed to cover a portion of the conductive layer 282. Another etch-back process is then performed to further flatten the portion of the conductive layer 282 exposed to the photoresist mask 244, converting the conductive layer 282 into one or more gate connectors 280. The gate connectors 280 are used to electrically connect each gate finger 266 to a gate bus formed in a later processing step. The gate connectors 280 may include a plurality of individual gate connectors, each connecting a gate finger 266 to the (later formed) gate bus, or they may comprise one or more larger conductive structures, each electrically connecting a number of gate fingers 266 to the gate bus. Note that in some embodiments, the conductive layer 282 can function as a gate connector 280, as shown in Figures 16A to 16D, and therefore the processing steps shown in Figures 18A to 18D may be omitted.

[0121] Referring to Figures 19A to 19D, the intermetallic dielectric layer 268 is a blanket formed in the active region 206. The intermetallic dielectric layer 268 may include, for example, a silicon oxide layer, but the embodiments of the present invention are not limited thereto. For example, in other embodiments, the intermetallic dielectric layer 268 may include, as an alternative or addition, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, etc. Next, as can be seen in Figures 19C and 19D, the intermetallic dielectric layer 268 is selectively etched to expose the semiconductor layer structure 250 between the gate trenches 260 (for example, the source region 220 and the deep shielding connection pattern 222). This etching step can convert a portion of the intermetallic dielectric layer 268 in the active region 206 into a plurality of elongated gate insulating fingers covering the upper surface of each gate finger 266.

[0122] Continuing to refer to Figures 19A to 19D, the ohmic source contact metal 270 is formed in the exposed region of the semiconductor layer structure 250 in the active region 206. The ohmic source contact metal 270 may be selectively deposited (not shown) or may be a blanket deposited extending into the intermetallic dielectric layer 268 and then etched back. In the exemplary embodiment, the ohmic source contact metal 270 may include a metal that forms an ohmic contact using silicon carbide. The ohmic source contact metal 270 may include one or more layers that perform various functions, such as a layer that forms an ohmic contact, a layer that forms a diffusion barrier, etc. As best shown in Figures 19B to 19D, the intermetallic dielectric layer 268 covers the gate finger 266 to prevent the gate finger 266 from short-circuiting with the source contact metallized portion 270. The intermetallic dielectric layer 268 also electrically isolates the gate connector 280 from the ohmic source contact metal 270.

[0123] Referring to Figures 20A to 20D, the intermetallic dielectric layer 268 is etched in the inert region 208 to expose the end portion of the gate connector 280.

[0124] Referring again to Figures 4A to 4D (showing the completed device), metal is deposited to form all three components: the bulk source contact metal layer 272, the gate bus 274, and the gate pad 276 (by selectively etching the metal after depositing it, or by selectively depositing the metal). The bulk source contact metal layer 272 is formed in the active region 206 of the MOSFET 200, and the gate bus 274 and gate pad 276 are formed in the inactive region 208 of the MOSFET 200. A metal drain contact (not shown) is formed on the underside of the substrate 210, opposite the drift layer 212.

[0125] As best illustrated in Figure 4B, the auxiliary dielectric layer 262 extends to the end of the gate finger 266 adjacent to the gate bus 274. Therefore, the auxiliary dielectric layer 262 increases the amount of dielectric material present on the upper edge of each gate trench 260. Consequently, when a gate bias voltage is applied to turn the MOSFET 200 into its ON state, the electric field generated in this region of the gate dielectric layer 264 diffuses into the auxiliary dielectric layer 262, which reduces the magnitude of the electric field experienced in this corner region of the gate dielectric layer 264. Furthermore, by increasing the thickness of the dielectric material layer in this region of the device, more dielectric material must be destroyed before the dielectric layer is damaged enough to allow a short circuit between the gate finger 266 and the semiconductor layer structure 250, thus extending the time to failure. Therefore, the auxiliary dielectric layer 262 can significantly extend the expected lifespan of MOSFET 200 compared to that of MOSFET 100 under identical operating conditions.

[0126] Accordingly, as shown in Figures 4A to 4D, embodiments of the present invention provide a gate trench semiconductor device comprising a semiconductor layer structure 250 having a gate trench 260 formed on its upper surface. A gate finger 266 is formed within the gate trench 260. An auxiliary dielectric layer 262 is formed on the upper surface of the gate finger 266 and, in some embodiments, may be in direct contact with the gate finger 266. The auxiliary dielectric layer 262 also overlaps the gate trench 260 perpendicularly. In some embodiments, the auxiliary dielectric layer 262 may be a field oxide layer. In some embodiments, the auxiliary dielectric layer 262 may extend beneath the gate pad 276 and / or one or more gate buses 274 of the gate trench semiconductor device. The auxiliary dielectric layer 262 may be significantly thicker than the gate dielectric layer 264 (e.g., 2 to 10 times thicker). The semiconductor device may further include a gate connector 280 located on the upper surface of the auxiliary dielectric layer 262 and the upper surface of the gate finger 266.

[0127] The semiconductor device may further include a gate dielectric layer 264 located between the semiconductor layer structure 250 and the gate finger 266 within the gate trench 260. The auxiliary dielectric layer 262 is in direct contact with the portion of the gate dielectric layer 264 that at least partially covers the upper corner of the gate trench 260. The gate trench 260 extends longitudinally within the semiconductor layer structure 250 and has a longitudinally extending bottom surface, first and second longitudinally extending side walls on opposite sides, and first and second end walls on opposite sides. The gate dielectric layer 264 has a first portion that extends upward along the first end wall of the gate trench. The auxiliary dielectric layer 262 may be in direct contact with this first portion of the gate dielectric layer 264.

[0128] The semiconductor device may further include an intermetallic dielectric layer 268 on the upper surface of the gate connector 280, source contacts 270 / 272 on the upper surface of the intermetallic dielectric layer 268, and a gate bus 274 on the upper surface of the auxiliary dielectric layer 262. The intermetallic dielectric layer 268 may overlap the auxiliary dielectric layer 262 perpendicularly. The gate connector 280 may electrically connect the gate bus 274 to the gate finger 266, and the gate connector 280 may be located between the auxiliary dielectric layer 262 and the intermetallic dielectric layer 268.

[0129] In some embodiments, the auxiliary dielectric layer 262 may extend over the portion of the semiconductor layer structure 250 that is located in the inert area 208 of the semiconductor device adjacent to the end of the gate trench 260.

[0130] A gate trench semiconductor device is provided, comprising a semiconductor layer structure 250 having a gate trench 260 internally, with a gate finger 266 and a gate dielectric layer 264 disposed within the gate trench 260. An auxiliary dielectric layer 262 is formed on the upper surface of the gate dielectric layer 264 and the upper surface of the gate finger 266. An intermetallic dielectric layer 268 overlaps the auxiliary dielectric layer 262 perpendicularly and / or overlaps the gate trench 260 perpendicularly.

[0131] According to yet another embodiment of the present invention, a gate trench semiconductor device is provided comprising a semiconductor layer structure 250 having a gate trench 260 inside, with gate fingers 266 located within the gate trench 260. These semiconductor devices further comprise a gate bus 274 and a gate connector 280 for electrically connecting the gate fingers to the gate bus 274. An auxiliary dielectric layer 262 is interposed between the end portions of the gate fingers 266 and the gate connector 280. In some embodiments, the gate connector 280 may be in direct contact with both the gate fingers 266 and the auxiliary dielectric layer 262. Further embodiments of the present invention provide a gate trench semiconductor device comprising a semiconductor layer structure 250. The gate trench 260 extends longitudinally within the upper surface of the semiconductor layer structure 250, and the gate trench 260 has a longitudinally extending lower surface, first and second longitudinally extending side walls opposite to each other, and first and second end walls opposite to each other. A gate dielectric layer 264 is provided on the lower surface, the first and second side walls, and the first and second end walls of the gate trench 260. A gate finger 266 is formed within the gate trench 266, and an auxiliary dielectric layer 262 overlaps the gate trench 260 perpendicularly and is in direct contact with the portion of the gate dielectric layer 264 located at the first end wall of the gate trench 260. The auxiliary dielectric layer 262 may also be in direct contact with the upper surface of the gate finger 266.

[0132] According to a further embodiment of the present invention, the above fabrication process may be modified to allow a portion of the auxiliary dielectric layer 262 to extend through the entire active area between the gate trenches 260. Figure 21 is a cross-sectional view taken across one of the gate trenches of a MOSFET 300, including such a design.

[0133] As shown in Figure 21, the auxiliary dielectric layer 262 is formed in the active area of ​​the device so as to extend over the semiconductor layer structure 250 on both sides of each gate trench 260. The auxiliary dielectric layer 262 may extend slightly into the gate trench 260 so as to overlap perpendicularly with the gate dielectric layer 264 that extends along the sidewall of the gate trench 260. As a result, the auxiliary dielectric layer 262 acts to increase the thickness of the sidewall of the gate dielectric layer 264, thereby allowing the electric field in the portion of the gate dielectric layer 264 that extends along the upper sidewall of the gate trench 260 to diffuse into the auxiliary dielectric layer 262, and reducing the electric field level in the gate dielectric layer 264.

[0134] As shown in Figure 21, the MOSFET 300 may be considered to have a first dielectric layer lining the bottom and side walls of the gate trench 260. Here, this first dielectric layer has a thickness of "x" and corresponds to the gate dielectric layer 264. A second dielectric layer extends onto the upper surface of the semiconductor layer structure 250 adjacent to each side of each gate trench 260. This second dielectric layer has a thickness of "y" and may correspond to a combination of the gate dielectric layer 264 and the auxiliary dielectric layer 262. The thickness "y" may be greater than the thickness x, thereby improving the dielectric breakdown performance of the device. In some embodiments, the thickness y may be at least 2 times, at least 3 times, at least 4 times, at least 6 times, at least 8 times, or at least 10 times the thickness "x". In the embodiments shown, the second dielectric layer corresponds to a combination of the gate dielectric layer 264 and the auxiliary dielectric layer 262, but it will be understood that in other embodiments, the gate dielectric layer 264 may be removed from the top surface of the semiconductor layer structure so that the second dielectric layer corresponds only to the auxiliary dielectric layer 262. In other words, in some embodiments, the gate dielectric layer 264 does not need to extend to the top surface of the semiconductor layer structure 250 beneath the auxiliary dielectric layer 262, and in such embodiments, the auxiliary dielectric layer 262 may be placed directly on top of the semiconductor layer structure 250. Since the auxiliary dielectric layer 262 can be significantly thicker than the gate dielectric layer 264, this still serves to improve the device's failure performance.

[0135] To clarify the above discussion, Figure 21 schematically shows a semiconductor device 300 comprising a semiconductor layer structure 250 having a gate trench 260 inside. A first dielectric layer is formed on the side walls and bottom surface of the gate trench 260. Here, the first dielectric layer corresponds to the portion of the gate dielectric layer 264 located within the gate trench 260. A gate finger 266 is formed on the first dielectric layer 264 within the gate trench 260. A second dielectric layer is provided on the upper surface of the semiconductor layer structure 250, and this second dielectric layer is in direct contact with the upper surface of the first dielectric layer 264. Here, the second dielectric layer corresponds to a combination of an auxiliary dielectric layer 262 and the portion of the gate dielectric layer 264 adjacent to the gate trench 260 and located on the upper surface of the semiconductor layer structure 250. As shown in Figure 21, the second dielectric layer 262 / 264 is thicker than the first dielectric layer 264. In the embodiments shown, the second dielectric layer corresponds to a combination of the auxiliary dielectric layer 262 and the portion of the gate dielectric layer 264 adjacent to the gate trench 260 and on the upper surface of the semiconductor layer structure 250. However, in other embodiments, the gate dielectric layer 264 may not be formed on the upper surface of the semiconductor layer structure 250, or it may be removed from there before the auxiliary dielectric layer 262 is formed. In such embodiments, the second dielectric layer may correspond to the auxiliary dielectric layer 262 alone. As described above, since the auxiliary dielectric layer 262 can be 2 to 15 times thicker than the gate dielectric layer 264, making the auxiliary dielectric layer 262 extending over the portion of the gate dielectric layer 264 that covers the sidewalls of the gate trench much thicker can significantly improve the on-state breakdown performance of the MOSFET 300 compared to conventional gate trench power semiconductor devices.

[0136] Figures 22A and 22B show a MOSFET 400 according to a further embodiment of the present invention. MOSFET 400 is a modified version of MOSFET 300. Figure 22A is a cross-sectional view of MOSFET 400 taken along line B-B in Figure 4A. Figure 22B is a cross-sectional view of MOSFET 400 taken along line E-E in Figure 4A.

[0137] As shown in Figure 22A, the MOSFET 400 differs from the MOSFET 300 in that the auxiliary dielectric layer 262 extends inward onto the gate trench 260 beyond the gate dielectric layer 264, so that the auxiliary dielectric layer 262 overlaps perpendicularly to the gate dielectric layer 264 within the gate trench 260, as well as perpendicularly to the gate fingers 266. In other words, the auxiliary dielectric layer 262 extends longitudinally adjacent to each side of each gate trench 260, and also extends laterally to partially cover each gate trench 260. As a result, the auxiliary dielectric layer 262 acts to further increase the amount of dielectric material present along the upper corners of the gate dielectric layer 264 that extend along the length of the gate trench 260. This allows the electric field in the portion of the gate dielectric layer 264 that extends along the upper sidewall of the gate trench 260 to diffuse into the auxiliary dielectric layer 262, thereby reducing the electric field level in the gate dielectric layer 264.

[0138] As further shown in Figure 22A, the MOSFET 400 may be considered to have a first dielectric layer lining the bottom and side walls of the gate trench 260. Here, this first dielectric layer has a thickness of "x" and corresponds to the gate dielectric layer 264. A second dielectric layer extends onto the upper surface of the semiconductor layer structure 250 adjacent to each side of each gate trench 260. This second dielectric layer has a thickness of "y" and may correspond to a combination of the gate dielectric layer 264 and the auxiliary dielectric layer 262. The thickness "y" may be greater than the thickness x, thereby improving the dielectric breakdown performance of the device. In some embodiments, the thickness y may be at least 2 times, at least 3 times, at least 4 times, at least 6 times, at least 8 times, or at least 10 times the thickness "x". Furthermore, the second dielectric layer may extend inward by a distance t from the plane defined by the sidewalls of the gate trench 260, whereas the first dielectric layer extends inward by a distance x from the plane defined by the sidewalls of the gate trench 260. In some embodiments, the distance t may be at least twice, at least three times, at least four times, at least six times, at least eight times, or at least ten times the thickness "y".

[0139] Figure 22A is a cross-sectional view of the gate trench 260 in the active area of ​​the MOSFET 400. Figure 22B is a cross-sectional view of the gate trench 260 in the inactive area of ​​the MOSFET 400. Comparing Figures 22A and 22B, the main difference is that in the inactive area of ​​the MOSFET 400, the auxiliary dielectric layer 262 extends laterally across the gate finger 266 to cover the entire upper surface of the end portion of the gate finger, whereas in the active area of ​​the MOSFET 400, the auxiliary dielectric layer 262 covers only a portion of each side of the gate finger 266. This allows a conductive layer (which may be the gate connector 280) to contact the upper surface of the gate finger 266 and supply the gate signal to the gate finger 266.

[0140] To clarify the above discussion, Figures 22A and 22B schematically show a semiconductor device 400 comprising a semiconductor layer structure 250 having a gate trench 260 inside. A first dielectric layer is formed on the side walls and bottom surface of the gate trench 260. Here, the first dielectric layer corresponds to the portion of the gate dielectric layer 264 that is located within the gate trench 260. The gate finger 266 is formed on the first dielectric layer 264 within the gate trench 260. A second dielectric layer is provided on the upper surface of the semiconductor layer structure 250, and this second dielectric layer directly contacts and overlaps the gate finger 266 in a vertical direction. In other words, the second dielectric layer extends from the upper surface of the semiconductor layer structure 250 (on each side of the gate trench 260) onto the gate trench 260, extends a sufficient distance on the gate trench 260 to reach above the gate finger 266, and can directly contact the gate finger 266. Here, the second dielectric layer corresponds to a combination of the auxiliary dielectric layer 262 and the portion of the gate dielectric layer 264 adjacent to the gate trench 260 and on the upper surface of the semiconductor layer structure 250. However, in other embodiments, the second dielectric layer may be implemented as only the auxiliary dielectric layer 262 in the same manner as discussed above with reference to the MOSFET 300 in Figure 21. The second dielectric layer may be significantly thicker than the first dielectric layer (for example, 2 to 15 times thicker).

[0141] MOSFETs 300 and 400 include an auxiliary dielectric layer 262 that provides enhanced protection for the portion of the gate dielectric layer 264 located on the upper sidewall of the gate trench 260, and can be formed in various ways. In a first approach, the conductive layer 265 (Figures 11A-11D) can be planarized as shown in Figures 12A-12D to form the gate fingers 266, in which case the auxiliary dielectric layer 262 may be a blanket formed on the device as shown in Figures 13A-13D. The auxiliary dielectric layer 262 may then be etched in a manner similar to that shown in Figures 14A-14D, except that small stripes of the auxiliary dielectric layer 262 are left on each side of each gate trench (the auxiliary dielectric layer 262 may be removed in the remaining region between adjacent gate trenches so that the source contact metallized portions 270 / 272 contact the semiconductor layer structure 250).

[0142] In the second approach, the conductive layer 265 may be partially planarized, as shown in Figures 11A–11D, but not to the extent shown in Figures 12A–12D. Then, an oxidation process may be carried out to oxidize the upper portion of the (polysilicon) conductive layer 265 to form an auxiliary dielectric layer 262 in the active region of the device on the gate finger 266. The auxiliary dielectric layer 262 also extends outward beyond the sidewall of the gate trench 260, as shown in Figures 21 and 22A–22D. Thus, it will be understood that MOSFETs 300 and 400 can be fabricated in a variety of different ways.

[0143] In yet another embodiment of the present invention, the auxiliary dielectric layer 262 may be formed before the gate trenches 260 are formed by etching the upper surface of the semiconductor layer structure 250. In these embodiments, the devices shown in Figures 8A to 8D may be formed first. Figures 23A to 23D show how the gate trenches may be formed. Referring to Figures 23A to 23D, Figure 23A is a copy of Figure 8D, but all the reference numerals in Figure 8D are increased by 100. Referring to Figure 23B, the auxiliary dielectric layer 262 is a blanket formed on the device. The auxiliary dielectric layer 262 is then etched. In the active region of the device, the auxiliary dielectric layer 262 may be etched as shown in Figure 23B, which is a cross-section taken along the same line as Figure 23A (Figure 8D), but the cross-section in Figure 23B is a longer cross-section that extends across the region where several gate trenches 260 are formed.

[0144] Referring to Figure 23C, trench etching may be performed using the auxiliary dielectric layer 262 as a mask to form the gate trench 260.

[0145] Referring to Figure 23D, a conductive layer 265 (for example, a doped polysilicon layer) may be formed, filling the gate trench 260 and extending across the upper surface of the semiconductor layer structure 250. Subsequently, appropriate etching of the conductive layer 265 and the auxiliary dielectric layer 262 may be performed to fabricate the MOSFET 200 (or MOSFET 300, 400).

[0146] The above diagram focuses on the regions of the illustrated MOSFETs 200, 300, and 400, where the gate fingers are supplied via a gate bus; however, it will be understood that some gate fingers may be supplied directly from the gate pad rather than from the gate bus. In such embodiments, the gate connector may extend between the gate pad and the gate finger, and the auxiliary dielectric layer according to embodiments of the present invention may still overlap the gate trench and the corresponding gate finger that connects directly to the gate pad perpendicularly.

[0147] Figure 24 is a flowchart illustrating a method for fabricating a gate trench semiconductor device according to an embodiment of the present invention. As shown in Figure 24, the operation may begin with the formation of a gate trench within a semiconductor layer structure (block 500). The semiconductor layer structure may include, for example, a silicon carbide semiconductor layer structure. Next, a gate dielectric layer is formed within the trench (block 510). In the exemplary embodiment, the gate dielectric layer may include, for example, a thin, high-quality silicon oxide layer. Next, a gate finger is formed on the gate dielectric layer within the gate trench such that the gate dielectric layer is between the semiconductor layer structure and the gate finger (block 520). In the exemplary embodiment, the gate finger may include doped polysilicon.

[0148] Next, an auxiliary dielectric layer is formed on the gate fingers and on the gate dielectric layer (block 530). The auxiliary dielectric layer may be formed on the portion of the gate fingers that is in the gate trench, or it may overlap the gate trench perpendicularly. In some embodiments, the auxiliary dielectric layer may be interposed between the gate connector and the gate fingers. In some cases, the auxiliary dielectric layer is in direct contact with both the gate connector and the gate fingers. Then, a gate bus and / or gate pad may be formed on the auxiliary dielectric layer (block 540). The method may also include forming a gate connector on the auxiliary dielectric layer (block 550). The gate connector may extend between the gate bus and the gate fingers, and the gate fingers may be electrically connected to the gate bus.

[0149] In some embodiments, the auxiliary dielectric layer may extend only over the edge portion of the gate trench, and therefore over less than half the length of the gate trench, or over less than a quarter of the length of the gate trench. In such embodiments, the auxiliary dielectric layer may be designed primarily to protect the portion of the gate dielectric layer that extends over the upper end wall of the gate trench. In other embodiments, the auxiliary dielectric layer extends over substantially the entire length of the gate trench and overlaps perpendicularly to the gate trench along substantially the entire length of the gate trench. In these embodiments, the auxiliary dielectric layer may be designed to protect the portion of the gate dielectric layer that extends over both the upper side wall and the upper end wall of the gate trench. In some cases, the auxiliary dielectric layer may extend over substantially the entire length of the gate trench and may extend inward over the gate trench so as to overlap perpendicularly to the gate fingers along substantially the entire length of the gate trench.

[0150] Although the above description uses MOSFET200 as an example, it will be understood that the techniques described herein can be used in any gate trench semiconductor device using a metal oxide and / or metal insulator interface, such as MISFETs, IGBT devices, and gate-controlled thyristors, to name a few. Therefore, it will be understood that the same fabrication techniques can be used to form other devices having an auxiliary dielectric layer protecting the upper corner of the gate oxide layer extending from the gate trench, without departing from the embodiments described herein. Furthermore, it will be understood that the above description pertains to n-type MOSFETs. In p-type devices, the locations of the source contact and drain contact may be reversed, and the conductivity types of other n-type and p-type regions may be swapped. All embodiments disclosed herein can be implemented as either n-type or p-type devices.

[0151] The present invention has been described above with reference to the accompanying drawings illustrating embodiments of the invention. However, the invention may be embodied in many different forms and should not be construed as limiting the embodiments described herein. Rather, these embodiments are provided so as to give thoroughness and completeness to this disclosure and to fully convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and areas may be exaggerated for clarity. When an element or layer is referred to as "on," "connected to," or "bonded to" another element or layer, it will be understood that there may be elements or layers directly on, directly connected to, or directly bonded to, or intervening elements or layers of the other element or layer. In contrast, when an element is referred to as "on," "directly connected to," or "directly bonded to" another element or layer, there are no intervening elements or layers. As used herein, the terms "and / or" include any combination of one or more of the related enumerated items. Similar reference numerals refer to similar elements throughout.

[0152] In this specification, the terms "first" and "second" are used to describe various regions, layers, and / or elements, but it will be understood that these regions, layers, and / or elements should not be limited by these terms. These terms are merely used to distinguish one region, layer, or element from another. Accordingly, without departing from the scope of the invention, the first region, layer, or element discussed below can be replaced with the second region, layer, or element, and similarly, the second region, layer, or element can be replaced with the first region, layer, or element.

[0153] Relational terms such as “underside” or “bottom” and “upside” or “top” may be used herein to describe the relationship of one element to another, as shown in the drawings. It will be understood that the relational terms are intended to encompass different orientations of the device, in addition to the orientation shown in the drawings. For example, if the device is upside down in the drawing, an element described as being “below” another element will be oriented towards the “above” of the other element. Thus, the exemplary term “underside” may encompass both “underside” and “above,” depending on the particular orientation of the drawing. Similarly, if the device is upside down in one of the drawings, an element described as being “below” or “below” another element will be oriented towards the “above” of the other element. Thus, exemplary terms such as “below” or “down” encompass both upward and downward orientations.

[0154] The technical terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise explicitly indicated. Furthermore, the terms “equipped,” “equipped,” “contain,” and / or “contain,” where used herein, specify the presence of the described feature, element, and / or component, but are not intended to exclude the presence or addition of one or more other features, elements, components, and / or groups thereof.

[0155] In this specification, "almost (effectively)" means within 10%.

[0156] Embodiments of the present invention are described herein with reference to schematic cross-sectional views. Therefore, variations from the illustrated shapes are expected, for example, as a result of manufacturing techniques and / or manufacturing tolerances. Accordingly, embodiments of the present invention should not be construed as being limited to specific shapes of the regions shown herein, but rather include, for example, deviations in shape resulting from manufacturing. For example, an injection region shown as a rectangle typically has rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary transition from the injection region to the uninjected region. Therefore, the regions shown in the figures are essentially schematic, and their shapes are not intended to represent the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.

[0157] It will be understood that the embodiments disclosed herein are combinatorial. Therefore, features described and / or explained in relation to the first embodiment may similarly be included in the second embodiment, and vice versa.

[0158] While the above embodiments are described with reference to specific figures, some embodiments of the present invention may include additional and / or intervening layers, structures, or elements, and / or certain layers, structures, or elements may be omitted. Although several exemplary embodiments of the present invention have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without significantly departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to fall within the scope of the present invention as defined in the claims. Thus, the above is illustrative of the present invention and should not be construed as limiting the specific embodiments disclosed, and it should be understood that the disclosed embodiments, as well as modifications to other embodiments, are intended to fall within the scope of the appended claims. The present invention is defined by the following claims, and the equivalents of the claims are also included within its scope.

Claims

1. A semiconductor layer structure comprising a gate trench formed in the upper surface of the semiconductor layer structure, The gate finger located within the gate trench, An auxiliary dielectric layer located on the upper surface of the gate finger and overlapping the gate trench perpendicularly, A gate connector comprising a semiconductor material, further comprising a first portion on the upper surface of a portion of the auxiliary dielectric layer extending beyond the first end of the gate trench, and a second portion on the upper surface of the gate finger, A metal gate bus, wherein the gate connector is disposed between the semiconductor layer structure and the metal gate bus, The intermetallic dielectric layer on the upper surface of the first portion of the gate connector, The source contact located on the upper surface of the intermetallic dielectric layer and A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, further comprising a gate dielectric layer in the gate trench located between the semiconductor layer structure and the gate finger.

3. The auxiliary dielectric layer is in direct contact with the portion of the gate dielectric layer that at least partially covers the upper corner of the gate trench. The semiconductor device according to claim 2, wherein the auxiliary dielectric layer also directly contacts the upper surface of the gate finger.

4. The semiconductor device according to any one of claims 1 to 3, wherein the auxiliary dielectric layer overlaps the gate finger perpendicularly over a length of less than half the total length of the gate finger.

5. The semiconductor device according to claim 2, wherein the auxiliary dielectric layer is thicker than the gate dielectric layer.

6. The semiconductor device according to claim 1, wherein the intermetallic dielectric layer overlaps the auxiliary dielectric layer perpendicularly.

7. The semiconductor device according to claim 1, wherein the auxiliary dielectric layer overlaps the gate finger perpendicularly along substantially the entire length of the gate finger.

8. The semiconductor device according to claim 1, wherein the auxiliary dielectric layer extends laterally across the entire width of the gate finger in at least a portion of the inert region of the semiconductor device, and the auxiliary dielectric layer extends laterally in less than the entire width of the gate finger in at least a portion of the active region of the semiconductor device.

9. The semiconductor device according to claim 1, wherein the intermetallic dielectric layer extends beyond the first end of the gate trench.

10. The semiconductor device according to claim 1, further comprising a gate bond pad, wherein the gate finger is electrically connected to the gate bond pad at least via the gate bus, and the auxiliary dielectric layer includes a field oxide layer extending below both the gate bond pad and the gate bus.

11. A method for forming a semiconductor device, Forming gate trenches within the upper surface of the semiconductor layer structure, Forming a gate dielectric layer within the gate trench, Forming gate fingers on the gate dielectric layer within the gate trench, To form an auxiliary dielectric layer located on the gate finger and the gate dielectric layer, and overlapping perpendicularly to the gate trench, A gate connector is formed, comprising a semiconductor material and including a first portion on the upper surface of a portion of the auxiliary dielectric layer extending beyond the first end of the gate trench, and a second portion on the upper surface of the gate finger. Forming a metal gate bus, wherein the gate connector is disposed between the semiconductor layer structure and the metal gate bus, Forming an intermetallic dielectric layer on the upper surface of the first portion of the gate connector, Forming a source contact on the upper surface of the intermetallic dielectric layer A method that includes [a certain feature].

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