Wafer alignment method and chip manufacturing method

Abstract

To provide an alignment method for a wafer capable of identifying a direction in which a boundary of a plurality of devices extends without complicating handling of the wafer and capable of positioning the direction in which the boundary extends, in a predetermined direction.SOLUTION: After a region which is thinned by removing a part of a substrate at a rear face side is formed, a front face side is imaged from the rear face side of the thinned region using an infrared camera, and an image to be used for identifying a direction in which a boundary of a plurality of devices extends is formed. In such a case, a portion which is residual without being thinned is included in a wafer, thereby identifying the direction in which the boundary of the plurality of devices extends without reducing rigidity of the wafer. As a result, the direction in which the boundary extends can be positioned in a predetermined direction without complicating handling of the wafer.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an alignment method for a wafer including a substrate having an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices formed on the surface of the substrate.

Background Art

[0002] Chips of devices such as ICs (Integrated Circuits) are essential components in various electronic devices such as mobile phones and personal computers. Such chips are manufactured, for example, by dividing a wafer including a substrate made of a semiconductor material such as single crystal silicon and a plurality of devices formed on the surface of the substrate along the boundaries of the plurality of devices.

[0003] The division of the wafer along this boundary is performed, for example, in a dicing device such as a cutting device or a laser processing device. Specifically, in the dicing device, after positioning the wafer so that the direction in which the boundaries of the plurality of devices extend coincides with a predetermined direction, the wafer is divided by linearly processing the wafer along this predetermined direction.

[0004] Note that when the wafer is divided in this way, processing debris (cutting chips or debris) may be generated and adhere to the plurality of devices. In this case, the quality of the chips manufactured by dividing the wafer may deteriorate. Therefore, the wafer may be divided with a protective tape attached to prevent the attachment of processing debris to the plurality of devices.

[0005] However, when a protective tape is attached to the wafer, it becomes difficult to grasp the direction in which the boundaries of the plurality of devices extend from the surface side of the wafer, that is, through the protective tape. In view of this point, the direction in which the boundaries of the plurality of devices extend may be grasped from the back side of the wafer using light having a wavelength that penetrates the substrate (for example, infrared light when the wafer is made of single crystal silicon) (see, for example, Patent Document 1).

[0006] Furthermore, in order to miniaturize chips, chips are sometimes manufactured by bonding the surfaces of a pair of wafers together to form a bonded wafer, and then dividing this bonded wafer (see, for example, Patent Document 2). When bonding a pair of wafers in this way, it is necessary to accurately overlap the boundaries of multiple devices on each wafer.

[0007] In order to stack a pair of wafers in this way, it is necessary to understand the direction in which the boundaries of multiple devices extend on each wafer in the pair. For example, as mentioned above, the direction in which the boundaries of multiple devices on each wafer extend can be determined from the back side of each wafer in the pair by using light of a wavelength that penetrates the substrate. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2011-35111 [Patent Document 2] Japanese Patent Publication No. 2008-153499 [Overview of the project] [Problems that the invention aims to solve]

[0009] The substrate contained in a wafer is generally doped with impurity elements to reduce electrical resistivity, etc. For example, since the electrical resistivity of pure single-crystal silicon is 1000 Ω·cm or more, substrates made of single-crystal silicon are generally doped with impurity elements so that the electrical resistivity is between 1 Ω·cm and 10 Ω·cm.

[0010] Furthermore, such substrates may be doped with a large amount of impurity elements so that their electrical resistivity is between 0.001 Ω·cm and 1 Ω·cm. However, when a substrate is doped with a large amount of impurity elements, light becomes less likely to pass through the substrate, making it difficult to determine the direction in which the boundaries of multiple devices extend from the back side of the wafer.

[0011] Such problems can be solved, for example, by grinding the back side of the substrate to thin the entire substrate. However, in this case, the rigidity of the wafer may decrease, making it difficult to handle. For example, when a wafer is thinned in this way, it becomes more prone to warping or bending, which may make it difficult to bond this wafer to another wafer.

[0012] In view of these points, an object of the present invention is to provide a wafer alignment method that can identify the direction in which the boundaries of multiple devices extend without complicating wafer handling, and position the direction in which these boundaries extend in a predetermined direction. [Means for solving the problem]

[0013] According to one aspect of the present invention, a wafer alignment method comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices formed on the surface of the substrate, comprising an attachment step of attaching a protective member to the wafer to protect the plurality of devices, and removing a part or all of the back side of the outer peripheral region of the substrate, It has a cross-sectional shape in which the outer edge of its reverse side is located at the outermost point. Thinned area On the substrate A wafer alignment method is provided, comprising: a removal step of forming; an imaging step, after the removal step, using an infrared camera to image the front side from the back side of the thinned region to form an image used to identify the direction in which the boundaries of the plurality of devices extend; and an alignment step, after the imaging step, positioning the wafer so that the direction in which the boundaries extend coincides with a predetermined direction. Alternatively, the wafer alignment method of the present invention may be a wafer alignment method comprising a substrate having an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices and alignment marks formed on the surface of the substrate, comprising: an attachment step of attaching a protective member to the wafer to protect the plurality of devices; a removal step of forming a thinned region on the substrate having a cross-sectional shape in which the outer edge of the back surface is located furthest outward by removing the back surface of the region of the substrate that overlaps with the alignment marks; an imaging step after the removal step of using an infrared camera to image the front surface from the back surface of the thinned region to form an image used to identify the direction to be grasped by referring to the alignment marks; and an alignment step after the imaging step of positioning the wafer so that the direction to be grasped by referring to the alignment marks coincides with a predetermined direction. In these wafer alignment methods, the imaging step may be performed with the wafer held on a chuck table whose holding surface contacts the back surface of the substrate.

[0014] Alternatively, the wafer alignment method of the present invention may be a wafer alignment method comprising a substrate having an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices formed on the surface of the substrate, comprising: an attachment step of attaching a protective member to the wafer to protect the plurality of devices; a removal step of forming a thinned region on the substrate by removing a part or all of the back side of the outer peripheral region of the substrate; an imaging step after the removal step of using an infrared camera to image the back side to the front side of the thinned region with respect to the back side of the substrate while the wafer is held on a chuck table whose holding surface contacts the back side of the substrate, thereby forming an image used to identify the direction in which the boundaries of the plurality of devices extend; and an alignment step after the imaging step of positioning the wafer so that the direction in which the boundaries extend coincides with a predetermined direction. Alternatively, This invention The wafer alignment method A wafer alignment method comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices and alignment marks formed on the surface of the substrate, comprising: an attachment step of attaching a protective member to the wafer to protect the plurality of devices; a removal step of forming a thinned region on the substrate by removing the back side of the region of the substrate that overlaps with the alignment marks; and after the removal step, using an infrared camera, With the wafer held in place on a chuck table whose holding surface contacts the back surface of the substrate. A wafer alignment method comprising: an imaging step of imaging the front side from the back side of the thinned region to form an image used to identify the direction to be grasped by referring to the alignment mark; and an alignment step of positioning the wafer after the imaging step so that the direction to be grasped by referring to the alignment mark matches a predetermined direction. It is fine .

[0015] The wafer alignment method described above is: The method further includes a peeling step of peeling the protective member off the wafer after the removal step, and a bonding step of bonding the wafer to a support wafer positioned at a predetermined location after the peeling step and the alignment step. But stomach. Furthermore, in the removal step of the wafer alignment method described above, the thinned region may be formed on the substrate using an annular cutting blade attached to the tip of a rotatable spindle. Also, in the wafer alignment method described above, the thickness of the thinned region may be 300 μm or less.

[0016] According to another aspect of the present invention, a method for manufacturing chips is provided, in which, after performing the wafer alignment method described above, the wafer is linearly processed and divided along the boundaries of the plurality of devices using a cutting apparatus or a laser processing apparatus to produce chips.

[0017] Alternatively, the chip manufacturing method of the present invention may be a chip manufacturing method for manufacturing a chip from a wafer comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices formed on the surface of the substrate, comprising: an attachment step of attaching a protective member to the wafer to protect the plurality of devices; a removal step of forming a thinned region on the substrate by removing a part or all of the back side of the outer peripheral region of the substrate; an imaging step after the removal step of using an infrared camera to image the front side from the back side of the thinned region to form an image used to identify the direction in which the boundaries of the plurality of devices extend; an alignment step after the imaging step of positioning the wafer so that the direction in which the boundaries extend coincides with a predetermined direction; and a division step after the alignment step of dividing the wafer linearly along the boundaries of the plurality of devices using a cutting device or a laser processing device. Alternatively, the chip manufacturing method of the present invention may be a chip manufacturing method for manufacturing a chip from a wafer comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices and alignment marks formed on the surface of the substrate, comprising: an attachment step of attaching a protective member to the wafer to protect the plurality of devices; a removal step of forming a thinned region on the substrate by removing the back side of the region of the substrate that overlaps with the alignment marks; an imaging step after the removal step of using an infrared camera to image the front side from the back side of the thinned region to form an image used to identify the direction grasped by referring to the alignment marks; an alignment step after the imaging step of positioning the wafer so that the direction grasped by referring to the alignment marks coincides with a predetermined direction; and a division step after the alignment step of dividing the wafer linearly along the boundaries of the plurality of devices using a cutting device or a laser processing device. [Effects of the Invention]

[0018] In this invention, after forming a thinned region by removing a portion of the back side of the substrate, an infrared camera is used to image the front side of this thinned region from the back side to form an image used to identify the direction in which the boundaries of multiple devices extend.

[0019] In this case, since the wafer contains the remaining portion without being thinned, it is possible to identify the direction in which the boundaries of the plurality of devices extend without reducing the stiffness of the wafer. As a result, it is possible to position the direction in which this boundary extends in a predetermined direction without making the handling of the wafer difficult.

Brief Description of the Drawings

[0020] [Figure 1] FIG. 1(A) is a perspective view schematically showing an example of a wafer, and FIG. 1(B) is a cross-sectional view schematically showing a cross-section of the wafer shown in FIG. 1(A). [Figure 2] FIG. 2 is a flowchart schematically showing an example of a method for processing a wafer after performing wafer alignment. [Figure 3] FIG. 3(A) is a cross-sectional view schematically showing the state of the sticking step, FIG. 3(B) is a partial cross-sectional side view schematically showing the state of the removing step, and FIG. 3(C) is a cross-sectional view schematically showing the state of the peeling step. [Figure 4] FIG. 4(A) is a partial cross-sectional side view schematically showing the state of the imaging step, FIG. 4(B) is a partial cross-sectional side view schematically showing the state of the alignment step, and FIG. 4(C) is a partial cross-sectional side view schematically showing the state of the bonding step. [Figure 5] FIG. 5 is a perspective view schematically showing another example of a wafer. [Figure 6] FIG. 6 is a flowchart schematically showing another example of a method for processing a wafer after performing wafer alignment. [Figure 7] FIG. 7 is a flowchart schematically showing yet another example of a method for processing a wafer after performing wafer alignment. [Figure 8] FIG. 8 is a partial cross-sectional side view schematically showing the state of the dicing step.

Embodiments for Carrying Out the Invention

[0021] Embodiments of the present invention will be described with reference to the attached drawings. Figure 1(A) is a schematic perspective view showing an example of a wafer, and Figure 1(B) is a schematic cross-sectional view showing a cross-section of the wafer shown in Figure 1(A). The wafer 11 shown in Figures 1(A) and 1(B) has a disc-shaped substrate 13 made of a semiconductor material such as silicon, which includes a generally parallel surface 13a and a back surface 13b.

[0022] This substrate 13 is highly doped with impurity elements, and its electrical resistivity is between 0.001 Ω·cm and 1 Ω·cm. In addition, notches 13c are formed on the side surface of the substrate 13, which are used to indicate a specific crystal orientation of the semiconductor material constituting the substrate 13.

[0023] Furthermore, multiple devices 15 are arranged in a matrix on the surface 13a of the substrate 13. That is, the boundaries between the multiple devices 15 extend in a grid pattern. Each of the multiple linear portions included in these boundaries is also called a planned division line.

[0024] Figure 2 is a schematic flowchart illustrating an example of a method for processing wafer 11 after alignment. In short, Figure 2 is a schematic flowchart illustrating an example of a method for manufacturing a bonded wafer, in which wafer 11 is bonded to another wafer after alignment.

[0025] In this method, first, protective members to protect multiple devices 15 are attached to the wafer 11 (attachment step: S1). Figure 3(A) is a schematic cross-sectional view showing the attachment step (S1). In this attachment step (S1), the protective members 17 are attached to the wafer 11 such that the multiple devices 15 are covered by the protective members 17, which have a diameter approximately equal to that of the wafer 11.

[0026] The protective member 17 comprises, for example, a film-like base material and an adhesive layer (glue layer) provided on the base material. The base material is made of, for example, a polyolefin, polyvinyl chloride, or polyethylene terephthalate resin. The adhesive layer is made of, for example, an epoxy or acrylic adhesive.

[0027] Next, a thinned region is formed on the substrate 13 by removing the back surface 13b of the outer peripheral region of the substrate 13 (removal step: S2). Figure 3(B) is a schematic partial cross-sectional side view showing the removal step (S2). This removal step (S2) is carried out, for example, in the cutting apparatus 2 shown in Figure 3(B).

[0028] This cutting apparatus 2 has a cylindrical support shaft 4. The upper part of this support shaft 4 is connected to the center of a disc-shaped chuck table 6, which has a diameter longer than the wafer 11. The lower part of the support shaft 4 is connected to a rotational drive source (not shown), such as a motor. When this rotational drive source is operated, the support shaft 4 and the chuck table 6 rotate around a straight line that passes through the center of the chuck table 6 and is aligned vertically as the axis of rotation.

[0029] Furthermore, the chuck table 6 has a frame 6a made of a metal material such as stainless steel. This frame 6a has a disc-shaped bottom wall and an annular side wall that extends upward from the outer peripheral region of the bottom wall. A disc-shaped porous plate (not shown) made of porous ceramics and having a diameter approximately the same as the inner diameter of the recess is fixed in the recess defined by the bottom wall and the side wall of the frame 6a.

[0030] Furthermore, the porous plate of the chuck table 6 is connected to a suction source (not shown), such as an ejector, via a flow path formed in the frame 6a. When this suction source is activated, a suction force acts on the space near the upper surface of the porous plate (the holding surface of the chuck table 6).

[0031] Furthermore, the support shaft 4 and the chuck table 6 are connected to a first horizontal movement mechanism (not shown). When this first horizontal movement mechanism is operated, the support shaft 4 and the chuck table 6 move along a direction perpendicular to the vertical direction (first horizontal direction).

[0032] Furthermore, a cutting unit 8 is provided above the chuck table 6. This cutting unit 8 is connected to a second horizontal movement mechanism and a vertical movement mechanism. When the second horizontal movement mechanism is operated, the cutting unit 8 moves along a direction (second horizontal direction) that is perpendicular to both the vertical direction and the first horizontal direction. When the vertical movement mechanism is operated, the cutting unit 8 moves along the vertical direction, that is, the cutting unit 8 moves up and down.

[0033] The cutting unit 8 has a cylindrical spindle 10 that extends along the second horizontal direction. A cutting blade 12 having an annular cutting edge is mounted at the tip of the spindle 10. This cutting blade 12 is, for example, a hub-type cutting blade. A hub-type cutting blade consists of an annular base made of metal or the like, and an annular cutting edge along the outer edge of the base.

[0034] Furthermore, this cutting edge is made of an electroformed grinding wheel in which abrasive grains, such as diamond or cubic boron nitride (cBN), are fixed with a binder such as nickel. Alternatively, the cutting blade 12 may be a washer-type cutting blade. A washer-type cutting blade is made of an annular cutting edge in which abrasive grains are fixed with a binder such as metal, ceramics, or resin.

[0035] Furthermore, the base end of the spindle 10 is connected to a rotational drive source (not shown), such as a motor. When this rotational drive source operates, the spindle 10 and the cutting blade 12 rotate around a straight line passing through the center of the spindle 10 and aligned with the second horizontal direction as the axis of rotation.

[0036] When removing the back surface 13b of the outer peripheral region of the substrate 13 in the cutting apparatus 2, first, the wafer 11 is brought into the holding surface of the chuck table 6 with the protective member 17 facing downwards, so that the center of the wafer 11 aligns with the center of the holding surface of the chuck table 6. Next, the suction source communicating with the porous plate of the chuck table 6 is activated. As a result, the wafer 11 is held in place by the chuck table 6 via the protective member 17.

[0037] Next, the first horizontal movement mechanism and / or the second horizontal movement mechanism are operated so that the cutting blade 12 is positioned directly above the outer peripheral region of the wafer 11. Then, the rotational drive source connected to the base end of the spindle 10 is operated so that the spindle 10 and the cutting blade 12 are rotated.

[0038] Next, while the cutting blade 12 is still rotating, the vertical movement mechanism is operated so that the lower end of the cutting blade 12 is positioned lower than the back surface 13b of the substrate 13 and higher than the front surface 13a. This causes the cutting blade 12 to cut into the back surface 13b side of the outer peripheral region of the substrate 13.

[0039] Next, while the spindle 10 and cutting blade 12 are rotating, the rotation drive source connected to the support shaft 4 is operated to rotate the chuck table 6 (see Figure 3(B)). As a result, the back surface 13b of the outer peripheral region of the substrate 13 is removed, forming a thinned region on the substrate 13. This completes the removal step (S2).

[0040] In the removal step (S2), the entire back surface 13b of the outer peripheral region of the substrate 13 may be removed, or only a portion thereof may be removed. That is, the rotation angle of the chuck table 6 when the cutting blade 12 has cut into the back surface 13b of the outer peripheral region of the substrate 13 may be 360° or more, or less than 360°.

[0041] Furthermore, the thinned region formed on the substrate 13 in the removal step (S2) is an area that is imaged from its back side to its front side using an infrared camera, so it is preferable that it be thin. Specifically, the thickness of this thinned region is preferably 300 μm or less, more preferably 150 μm or less, and most preferably 70 μm or less.

[0042] Next, the protective member 17 is peeled off from the wafer 11 (peeling step: S3). Figure 3(C) is a schematic cross-sectional view showing the peeling step (S3). This peeling step (S3) is carried out, for example, by applying an external force to the wafer 11 and the protective member 17 to separate the wafer 11 on which the thinned region 19 is formed from the protective member 17.

[0043] Next, an infrared camera is used to image the front side of the thinned region 19 from the back side to form an image (imaging step: S4). Figure 4(A) is a schematic partial cross-sectional side view showing the imaging step (S4). This imaging step (S4) is performed, for example, in the bonding apparatus 14 shown in Figure 4(A).

[0044] This bonding apparatus 14 has a cylindrical upper support shaft 16. The lower part of this upper support shaft 16 is connected to the center of a disc-shaped upper chuck table 18, which has a diameter shorter than that of the wafer 11. The upper part of the upper support shaft 16 is connected to a rotational drive source (not shown), such as a motor. When this rotational drive source is operated, the upper support shaft 16 and the upper chuck table 18 rotate around a straight line that passes through the center of the upper chuck table 18 and is aligned vertically as the axis of rotation.

[0045] Furthermore, the upper chuck table 18 has a frame 18a made of a metal material such as stainless steel. This frame 18a has a disc-shaped bottom wall and an annular side wall that extends downward from the outer peripheral region of the bottom wall. A disc-shaped porous plate (not shown) made of porous ceramics and having a diameter approximately the same as the inner diameter of the recess is fixed in the recess defined by the bottom wall and the side wall of the frame 18a.

[0046] Furthermore, the porous plate of the upper chuck table 18 is connected to a suction source (not shown), such as an ejector, via a flow path formed in the frame 18a. When this suction source is activated, a suction force acts on the space near the lower surface of the porous plate (the holding surface of the upper chuck table 18).

[0047] Furthermore, an upper infrared camera 20 is provided on the side of the upper chuck table 18. This upper infrared camera 20 includes, for example, an infrared light source such as an LED (Light Emitting Diode), an objective lens, and an image sensor such as a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0048] Furthermore, the upper support shaft 16, the upper chuck table 18, and the upper infrared camera 20 are connected to a third horizontal movement mechanism (not shown). When this third horizontal movement mechanism is operated, the upper support shaft 16, the upper chuck table 18, and the upper infrared camera 20 move along a direction perpendicular to the vertical direction (third horizontal direction).

[0049] Furthermore, the upper support shaft 16, the upper chuck table 18, and the upper infrared camera 20 are connected to a vertical movement mechanism (not shown). When this vertical movement mechanism is operated, the upper support shaft 16, the upper chuck table 18, and the upper infrared camera 20 move along the vertical direction; that is, the upper support shaft 16, the upper chuck table 18, and the upper infrared camera 20 move up and down.

[0050] Furthermore, a disc-shaped lower chuck table 22 having a diameter approximately equal to that of the upper chuck table 18 is provided below the upper chuck table 18. This lower chuck table 22 has a frame 22a made of a metal material such as stainless steel.

[0051] The frame 22a has a disc-shaped bottom wall and an annular side wall extending upward from the outer peripheral region of the bottom wall. A disc-shaped porous plate (not shown), made of porous ceramics and having a diameter approximately the same as the inner diameter of the recess, is fixed in the recess defined by the bottom wall and the side wall of the frame 22a.

[0052] Furthermore, the porous plate of the lower chuck table 22 is connected to a suction source (not shown), such as an ejector, via a flow path formed in the frame 22a. When this suction source is activated, a suction force acts on the space near the upper surface of the porous plate (the holding surface of the lower chuck table 22).

[0053] Furthermore, a lower infrared camera 24 is provided on the side of the lower chuck table 22. This lower infrared camera 24 includes, for example, an infrared light source such as an LED (Light Emitting Diode), an objective lens, and an image sensor such as a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0054] Furthermore, the central part of the lower chuck table 22 is connected to the upper part of the lower support shaft 26. The lower part of the lower support shaft 26 is connected to a rotational drive source (not shown), such as a motor. When this rotational drive source is operated, the lower chuck table 22 and the lower support shaft 26 rotate around a straight line passing through the center of the lower chuck table 22 and aligned vertically as the axis of rotation.

[0055] Furthermore, the lower chuck table 22, the lower infrared camera 24, and the lower support shaft 26 are connected to a fourth horizontal movement mechanism (not shown). When this fourth horizontal movement mechanism is operated, the lower chuck table 22, the lower infrared camera 24, and the lower support shaft 26 move along the vertical direction and a direction perpendicular to the third horizontal direction (fourth horizontal direction).

[0056] When forming an image in the bonding apparatus 14 by imaging the front side from the back side of the thinned region 19 of the substrate 13, first, the holding surface of the upper chuck table 18 is brought into contact with the back side 13b of the substrate 13 so that the center of the holding surface of the upper chuck table 18 is aligned with the center of the wafer 11.

[0057] Next, the suction source communicating with the porous plate of the upper chuck table 18 is activated. This holds the wafer 11 in place on the upper chuck table 18. Then, the upper infrared camera 20 images the front side of the thinned region 19 of the substrate 13 from the back side. This forms an image that is used to determine the direction in which the boundaries of the multiple devices 15 extend. This completes the imaging step (S4).

[0058] Next, the directions in which the boundaries of the multiple devices 15 extend are aligned to a predetermined direction (alignment step: S5). Figure 4(B) is a schematic partial cross-sectional side view showing the alignment step (S5). This alignment step (S5) is performed, for example, in the bonding apparatus 14 described above.

[0059] Specifically, in this alignment step (S5), the image formed in the imaging step (S4) is used to operate a rotational drive source connected to the upper part of the upper support shaft 16 so that the direction in which a specific division line included in the boundary of the multiple devices 15 extending in a grid extends is parallel to, for example, the third horizontal direction.

[0060] Next, wafer 11 is bonded to another wafer (support wafer) positioned at a predetermined location (bonding step: S6). Figure 4(C) is a schematic partial cross-sectional side view showing the bonding step (S6). This bonding step (S6) is performed, for example, in the bonding apparatus 14 described above.

[0061] Specifically, in this bonding step (S6), first, the support wafer 21 is brought onto the holding surface of the lower chuck table 22 so that its center aligns with the center of the holding surface of the lower chuck table 22. The support wafer 21 has a diameter approximately equal to that of the wafer 11 and includes a substrate 23 made of a semiconductor material such as silicon.

[0062] The substrate 23 is either undoped with impurity elements or doped at a low concentration, and its electrical resistivity is 1 Ω·cm or higher. Furthermore, multiple devices 25 are arranged in a matrix on the surface 23a of the substrate 23. That is, the boundaries between the multiple devices 25 extend in a grid pattern.

[0063] Next, the suction source communicating with the porous plate of the lower chuck table 22 is activated. This holds the support wafer 21 in place on the lower chuck table 22. Then, the lower infrared camera 24 images the outer peripheral region of the substrate 23 from the back side to the front side.

[0064] This creates an image that is used to identify the direction in which the boundaries of multiple devices 25 extend. Furthermore, if the concentration of impurity elements in the substrate 23 is low, it is possible to image the front side of the outer peripheral region of the substrate 23 from the back side without forming a thinned region on the substrate 23.

[0065] Next, using this image, a rotary drive source connected to the lower part of the lower support shaft 26 is operated so that the direction in which a specific division line included in the boundary of multiple devices 25 extending in a grid extends is parallel to, for example, the third horizontal direction. Then, adhesive 27 is supplied onto the support wafer 21. This adhesive 27 is, for example, an acrylic adhesive or an epoxy adhesive.

[0066] Next, the third horizontal movement mechanism and / or the fourth horizontal movement mechanism are operated so that the center of the wafer 11 is positioned directly above the center of the support wafer 21. Then, the vertical movement mechanism is operated to bring the wafer 11 closer to the support wafer 21. This causes the wafer 11 to be bonded to the support wafer 21.

[0067] In the method shown in Figure 2, a thinned region 19 is formed by removing the back surface 13b of the outer peripheral region of the substrate 13. Then, an upper infrared camera 20 is used to image the front surface of the thinned region 19 from the back surface to form an image used to identify the direction in which the boundaries of the multiple devices 15 extend.

[0068] In this case, since the portion that remains without thinning is included in the wafer 11, the direction in which the boundaries of the multiple devices 15 extend can be determined without reducing the rigidity of the wafer 11. As a result, it becomes possible to bond the wafer 11 to the support wafer 21 without making the handling of the wafer 11 more difficult.

[0069] The method shown in Figure 2 is one embodiment of the present invention, and the methods of the present invention are not limited to those shown in Figure 2. For example, in the present invention, the peeling step (S3) may be performed at any time after the removal step (S2) and before the bonding step (S6). That is, it may be performed after the imaging step (S4) or the alignment step (S5).

[0070] Furthermore, the wafer used in the present invention is not limited to the wafer 11 shown in Figures 1(A) and 1(B). Figure 5 is a schematic perspective view showing another example of the wafer of the present invention.

[0071] The wafer 29 shown in Figure 5 has the same structure as the wafer 11 shown in Figures 1(A) and 1(B), except that the surface 31a of the substrate 31 has not only multiple devices 33 but also a pair of alignment marks 35a and 35b formed on it. Therefore, the following description of wafer 29, which is common to wafer 11, will be omitted.

[0072] This pair of alignment marks 35a and 35b are annular patterns and are formed, for example, by irradiating the substrate 31 with a laser beam. Furthermore, the alignment marks 35a and 35b are formed such that the straight line connecting their centers is parallel to a specific planned division line that is included in the boundary of the multiple devices 33.

[0073] For example, the alignment mark 35a is formed so as to be located in a region slightly inside the notch 31b formed on the side surface of the substrate 31, and the alignment mark 35b is positioned in a region slightly inside the portion of the side surface of the substrate 31 opposite the notch 31b.

[0074] Figure 6 is a schematic flowchart illustrating an example of a method for manufacturing a bonded wafer, in which wafer 29 is bonded to another wafer after alignment. The method shown in Figure 6 has the same steps as the wafer manufacturing method shown in Figure 2, except that the location of the thinned region formed on the substrate 31 is different. Therefore, the following explanation will omit the steps that are common to the method shown in Figure 2.

[0075] In the method shown in Figure 6, a thinned area is formed on the substrate by removing the back side of the region that overlaps with the alignment marks of the substrate 31 (removal step: S7). This removal step (S7) is performed, for example, in the cutting apparatus 2 shown in Figure 3(B).

[0076] In the method shown in Figure 6, during the imaging step (S4), the thinned area of ​​the substrate 31 is imaged from the back side to the front side to form an image showing alignment marks 35a and 35b. This image is then used to identify the direction in which a specific division line included in the boundary of multiple devices 15 extends.

[0077] Furthermore, in the present invention, the method for processing wafers 11 and 29 after alignment is not limited to a method for manufacturing bonded wafers in which wafers 11 and 29 are bonded to a support wafer 21.

[0078] Figure 7 is a schematic flowchart illustrating another example of a method for processing wafer 11 after wafer 11 alignment. In short, Figure 7 is a schematic flowchart illustrating an example of a chip manufacturing method in which wafer 11 is divided after wafer 11 alignment to produce chips.

[0079] In the method shown in Figure 7, after performing the above-described attachment step (S1), removal step (S2), imaging step (S4), and alignment step (S5), the wafer 11 is linearly processed and divided along the boundaries of the multiple devices 15 (dividing step: S8).

[0080] Figure 8 is a schematic partial cross-sectional side view showing the splitting step (S8). This splitting step (S8), as well as the imaging step (S4) and the alignment step (S5), are performed, for example, in the cutting apparatus 28 shown in Figure 8. This cutting apparatus 28 has a cylindrical support shaft 30. The upper part of this support shaft 30 is connected to the center of a disc-shaped chuck table 32, which has a diameter longer than that of the wafer 11.

[0081] Furthermore, the lower part of the support shaft 30 is connected to a rotational drive source (not shown), such as a motor. When this rotational drive source is operated, the support shaft 30 and the chuck table 32 rotate around a straight line that passes through the center of the chuck table 32 and is aligned vertically as the axis of rotation.

[0082] Furthermore, the chuck table 32 has a structure similar to the chuck table 6 shown in Figure 3(B). The porous plate of the chuck table 32 is connected to a suction source (not shown), such as an ejector, via a flow path formed in the frame 32a. When this suction source is operated, a suction force acts on the space near the upper surface of the porous plate (the holding surface of the chuck table 32).

[0083] Furthermore, the support shaft 30 and the chuck table 32 are connected to a fifth horizontal movement mechanism (not shown). When this fifth horizontal movement mechanism is operated, the support shaft 30 and the chuck table 32 move along a direction perpendicular to the vertical direction (fifth horizontal direction).

[0084] Furthermore, a cutting unit 34 is provided above the chuck table 32. This cutting unit 34 is connected to a sixth horizontal movement mechanism and a vertical movement mechanism. When the sixth horizontal movement mechanism is operated, the cutting unit 34 moves along a direction (sixth horizontal direction) that is perpendicular to both the vertical direction and the fifth horizontal direction. When the vertical movement mechanism is operated, the cutting unit 34 moves along the vertical direction, that is, the cutting unit 34 moves up and down.

[0085] The cutting unit 34 has a structure similar to that of the cutting unit 8 shown in Figure 3(B). The base end of the spindle 36 of the cutting unit 34 is connected to a rotational drive source (not shown), such as a motor. When this rotational drive source operates, the spindle 36 and the cutting blade 38 rotate around a straight line passing through the center of the spindle 36 and along the sixth horizontal direction as the axis of rotation.

[0086] Furthermore, in the cutting device 28, an infrared camera (not shown) is provided adjacent to the cutting unit 34 in the fifth horizontal direction. This infrared camera has the same structure as the upper infrared camera 20 shown in Figure 4(A), etc. This infrared camera is also connected to the sixth horizontal movement mechanism and the vertical movement mechanism, similar to the cutting unit 34, and moves together with the cutting unit 34.

[0087] When performing the imaging step (S4), alignment step (S5), and division step (S8) in the cutting apparatus 28, first, the wafer 11 is placed on the holding surface of the chuck table 6 with the protective member 17 facing downwards, so that the center of the wafer 11 aligns with the center of the holding surface of the chuck table 32.

[0088] Next, the suction source communicating with the porous plate of the chuck table 32 is activated. This holds the wafer 11 to the chuck table 32 via the protective member 17. Then, the fifth horizontal movement mechanism and / or the sixth horizontal movement mechanism are activated so that the infrared camera, which is positioned adjacent to the cutting unit 34, is positioned directly above the thinned region 19 of the substrate 13 of the wafer 11.

[0089] Next, an infrared camera captures images of the front side of the thinned region 19 of the substrate 13 from the back side to form an image. Then, using this image, a rotary drive source connected to the lower part of the support shaft 30 is operated so that the direction in which a specific division line included in the boundary of a plurality of devices 15 extending in a grid pattern extends is parallel to, for example, the fifth horizontal direction.

[0090] Next, the fifth horizontal movement mechanism moves the support shaft 30 and the chuck table 32, and / or the sixth horizontal movement mechanism moves the cutting unit 34, so that the cutting blade 38 is positioned in a fifth horizontal direction relative to a division line perpendicular to the specific division line.

[0091] Next, the vertical movement mechanism is operated so that the lower end of the cutting blade 38 is positioned lower than the surface 13a of the substrate 13 and higher than the holding surface of the chuck table 32. Then, the rotational drive source connected to the base end of the spindle 10 is operated so that the spindle 36 and the cutting blade 38 are rotated.

[0092] Next, while the cutting blade 38 is still rotating, the fifth horizontal movement mechanism moves the support shaft 30 and the chuck table 32 so that the lower end of the cutting blade 38 passes from one end to the other in the fifth horizontal direction of the wafer 11 (see Figure 8). As a result, the wafer 11 is processed and divided in a straight line.

[0093] Then, in the method shown in Figure 7, the wafer cutting is repeated until the wafer 11 is divided along all of the boundaries of the multiple devices 15. As a result, multiple chips are manufactured from the wafer 11.

[0094] Furthermore, the structures and methods of the embodiments described above can be modified as appropriate without departing from the scope of the present invention. [Explanation of symbols]

[0095] 2:Cutting device 4: Support shaft 6: Chuck table (6a: Frame) 8: Cutting Unit 10: Spindle 11: Wafer 12: Cutting blade 13: Substrate (13a: Front surface, 13b: Back surface, 13c: Notch) 14: Lamination device 15: Devices 16: Upper support shaft 17: Protective component 18: Upper chuck table (18a: Frame) 19: Thinned area 20: Upper infrared camera 21: Support wafer 22: Lower chuck table (22a: Frame) 23: Circuit board 24: Lower infrared camera 25: Devices 26: Lower support shaft 27: Adhesive 28:Cutting equipment 29: Wafer 30: Support shaft 31: Substrate (31a: Surface, 31b: Notch) 32: Chuck table (32a: Frame) 33: Device 34: Cutting Unit 35a, 35b: Alignment marks 36: Spindle 38: Cutting blade

Claims

1. A wafer alignment method comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices formed on the surface of the substrate, A bonding step of attaching protective members to the wafer to protect the plurality of devices, A removal step in which a thinned region is formed on the substrate by removing part or all of the back side of the outer peripheral region of the substrate, thereby having a cross-sectional shape in which the outer edge of the back side is located furthest outwards, Following the removal step, an imaging step is performed in which an infrared camera is used to image the front side of the thinned region from the back side to the front side to form an image used to identify the direction in which the boundaries of the plurality of devices extend. Following the imaging step, an alignment step is performed to position the wafer so that the direction in which the boundary extends coincides with a predetermined direction. A wafer alignment method comprising [a specific feature / feature].

2. A wafer alignment method comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices and alignment marks formed on the surface of the substrate, A bonding step of attaching protective members to the wafer to protect the plurality of devices, A removal step in which the back side of the substrate is removed from the region overlapping with the alignment mark, thereby forming a thinned region on the substrate having a cross-sectional shape in which the outer edge of the back side is located furthest outwards, Following the removal step, an imaging step is performed in which an infrared camera is used to image the front side of the thinned area from the back side to the front side, and an image is formed which is used to identify the direction to be grasped by referring to the alignment mark. Following the imaging step, an alignment step is performed to position the wafer so that the orientation, which is grasped by referring to the alignment mark, aligns with a predetermined direction. A wafer alignment method comprising [a specific feature / feature].

3. The wafer alignment method according to claim 1 or 2, wherein the imaging step is performed while the wafer is held on a chuck table whose holding surface contacts the back surface of the substrate.

4. A wafer alignment method comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices formed on the surface of the substrate, A bonding step of attaching protective members to the wafer to protect the plurality of devices, A removal step in which a thinned region is formed on the substrate by removing part or all of the back side of the outer peripheral region of the substrate, Following the removal step, an imaging step is performed in which an infrared camera is used to image the thinned area from the back side to the front side while the wafer is held on a chuck table with a holding surface in contact with the back side of the substrate, thereby forming an image used to identify the direction in which the boundaries of the plurality of devices extend. Following the imaging step, an alignment step is performed to position the wafer so that the direction in which the boundary extends coincides with a predetermined direction. A wafer alignment method comprising [a specific feature / feature].

5. A wafer alignment method comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices and alignment marks formed on the surface of the substrate, A bonding step of attaching protective members to the wafer to protect the plurality of devices, A removal step in which a thinned area is formed on the substrate by removing the back side of the area of ​​the substrate that overlaps with the alignment mark, Following the removal step, an imaging step is performed in which an infrared camera is used to image the front side of the thinned area from the back side while the wafer is held on a chuck table with a holding surface in contact with the back side of the substrate, thereby forming an image used to identify the direction to be grasped by referring to the alignment mark. Following the imaging step, an alignment step is performed to position the wafer so that the orientation, which is grasped by referring to the alignment mark, aligns with a predetermined direction. A wafer alignment method comprising [a specific feature / feature].

6. Following the removal step, a peeling step is performed to peel the protective member off the wafer, A wafer alignment method according to any one of claims 1 to 5, further comprising a bonding step of bonding the wafer to a support wafer positioned at a predetermined location after the peeling step and the alignment step.

7. The wafer alignment method according to any one of claims 1 to 6, wherein in the removal step, the thinned region is formed on the substrate using an annular cutting blade mounted on the tip of a rotatable spindle.

8. The wafer alignment method according to any one of claims 1 to 7, wherein the thickness of the thinned region is 300 μm or less.

9. A method for manufacturing chips, comprising performing the wafer alignment method described in claim 1 or 4, and then using a cutting apparatus or laser processing apparatus to linearly process and divide the wafer along the boundaries of the plurality of devices.

10. A method for manufacturing a chip from a wafer comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices formed on the surface of the substrate, A bonding step of attaching protective members to the wafer to protect the plurality of devices, A removal step in which a thinned region is formed on the substrate by removing part or all of the back side of the outer peripheral region of the substrate, Following the removal step, an imaging step is performed in which an infrared camera is used to image the front side of the thinned region from the back side to the front side to form an image used to identify the direction in which the boundaries of the plurality of devices extend. Following the imaging step, an alignment step is performed to position the wafer so that the direction in which the boundary extends coincides with a predetermined direction. Following the alignment step, a division step is performed in which the wafer is linearly processed and divided along the boundaries of the plurality of devices using a cutting device or a laser processing device. A method for manufacturing a chip equipped with the following features.

11. A method for manufacturing a chip from a wafer comprising a substrate with an electrical resistivity of 0.001 Ω·cm or more and 1 Ω·cm or less, and a plurality of devices and alignment marks formed on the surface of the substrate, A bonding step of attaching protective members to the wafer to protect the plurality of devices, A removal step in which a thinned area is formed on the substrate by removing the back side of the area of ​​the substrate that overlaps with the alignment mark, Following the removal step, an imaging step is performed in which an infrared camera is used to image the front side of the thinned area from the back side to the front side, and an image is formed which is used to identify the direction to be grasped by referring to the alignment mark. Following the imaging step, an alignment step is performed to position the wafer so that the orientation, which is grasped by referring to the alignment mark, aligns with a predetermined direction. Following the alignment step, a splitting step is performed in which the wafer is linearly processed and divided along the boundaries of the plurality of devices using a cutting apparatus or laser processing apparatus. A method for manufacturing a chip equipped with the following features.

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