Semiconductor device and method for manufacturing a semiconductor device

Abstract

To suppress the extension of peeling of a sealing member.SOLUTION: A front surface of a wiring board 26c includes an impression area 23a1 that is rougher than other areas, A front surface of a sealing body 30 that faces the front surface of the wiring board 26c includes a recess 30b that directly faces the impression region 23a1. This improves the adhesion between the sealing body 30 and the impression region 23a1 of the wiring board 26c. Furthermore, a thickness of the sealing body 30 on the impression region 23a1 is thinner than other parts because the recess 30b is formed. Therefore, peeling of the sealing body 30 in the impression region 23a1 is prevented. Therefore, when the extension of the peeling passes through the impression area 23a1, the extension of the peeling is suppressed by the impression area 23a1. The peeling of the sealing body 30 around a semiconductor chip 10 is suppressed.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device includes a power semiconductor chip, an insulating circuit board on which the power semiconductor chip is disposed, and a lead frame, and is sealed with a sealing member. The power semiconductor chip uses a switching element of a power device. The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above semiconductor device, the adhesion between the sealing member and the components of the semiconductor device (power semiconductor chip, insulating circuit board, lead frame) sealed with the sealing member is not high. Therefore, peeling of the sealing member from the components easily occurs. When peeling occurs and spreads, the insulation of the semiconductor device deteriorates, and there is a risk that moisture will enter from the peeling location. Thus, the reliability of the semiconductor device deteriorates.

[0005] The present invention has been made in view of such points, and an object thereof is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the spread of peeling of the sealing member is suppressed.

Means for Solving the Problems

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising a semiconductor chip, a conductive plate to which the semiconductor chip is bonded to the front surface, and a sealing member for sealing the semiconductor chip and the conductive plate, wherein the front surface of the conductive plate includes an indentation region that is rougher than other regions, and the sealing front surface of the sealing member facing the front surface of the conductive plate includes a recess that directly faces the indentation region.

[0007] Furthermore, according to one aspect of the present invention, a preparation step of preparing a mold containing a semiconductor chip, a conductive plate, a pressing pin with a roughened pressing surface at its tip, a sealing member, and a cavity; a mold setting step of setting the conductive plate on which the semiconductor chip is arranged into the cavity of the mold; an indentation forming step of pressing the front surface of the conductive plate with the pressing surface of the pressing pin within the cavity to form an indentation region on the front surface of the conductive plate that is rougher than other regions; and filling the cavity with the sealing member while pressing the conductive plate with the pressing surface, and once the cavity is sealed with the sealing member, the pressing pin is moved away from the front surface of the conductive plate in a direction substantially perpendicular to it. Let go The sealing process, A recess forming step involves maintaining the pressing pin in a position away from the conductive plate, removing the sealing member before it has completely solidified, and forming a recess on the sealing surface of the sealing member that faces the front surface of the conductive plate, and which is directly opposite the indentation region. A method for manufacturing a semiconductor device is provided. [Effects of the Invention]

[0008] According to the disclosed technology, the extension of delamination of the sealing member is suppressed, thereby preventing a decrease in the reliability of the semiconductor device. [Brief explanation of the drawing]

[0009] [Figure 1] This is an external view of the semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] This is a longitudinal cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] This is a longitudinal cross-sectional view of the main part of the semiconductor device according to the first embodiment. [Figure 5]This is a flowchart illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 6] This figure shows the assembly process included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] This figure shows the mold setting process (immediately after setting) included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] This figure shows the mold setting process (heating) included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] This figure shows the indentation formation step included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 10] This is a diagram (part 1) showing a pressing pin used in the indentation formation step included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 11] This is a diagram (part 2) showing the pressing pin used in the indentation formation step included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 12] This is a longitudinal cross-sectional view of a key part after the indentation formation step included in the manufacturing method of a semiconductor device according to the first embodiment. [Figure 13] This figure shows the sealing step included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 14] This figure shows the sealing step (during the removal of the pressing pin) included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 15] This figure shows the sealing step (after removal of the pressing pin) included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 16] This figure illustrates the formation location of the indentation region on the semiconductor device according to the first embodiment. [Figure 17] This is a cross-sectional view of a semiconductor device according to the first embodiment (modified example 1-1). [Figure 18] This is a longitudinal cross-sectional view of the main part of the semiconductor device according to the first embodiment (modified example 1-1). [Figure 19] This is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 20]It is a longitudinal sectional view of a semiconductor device according to a second embodiment. [Figure 21] It is a longitudinal sectional view of a semiconductor device according to a second embodiment (Modification 2-1).

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following description, "front surface" and "upper surface" represent the surfaces facing the upper side (+Z direction side) in the semiconductor device in the figure. Similarly, "up" represents the direction of the upper side (+Z direction side) in the semiconductor device in the figure. "Back surface" and "lower surface" represent the surfaces facing the lower side (-Z direction side) in the semiconductor device 1 in the figure. Similarly, "down" represents the direction of the lower side (-Z direction side) in the semiconductor device 1 in the figure. The same directionality is meant in other drawings as necessary. "Front surface", "upper surface", "up", "back surface", "lower surface", "down", "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the gravitational direction. Also, in the following description, "main component" means the case where it contains 80 vol% or more.

[0011] [First Embodiment] The semiconductor device 1 according to the first embodiment will be described with reference to FIGS. 1 to 4. FIG. 1 is an external view of the semiconductor device according to the first embodiment. Note that FIG. 1(A) is a side view of the semiconductor device 1 in FIG. 1(B) viewed in the +Y direction. FIG. 1(B) is a plan view of the semiconductor device 1. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 3 is a longitudinal sectional view of the semiconductor device according to the first embodiment. Note that FIG. 2 is a cross-sectional view taken along the dashed line Z-Z in FIG. 1(A). FIG. 3 is a cross-sectional view taken along the dashed line Y1-Y1 in FIG. 2. Also, in FIG. 2, the illustration of the oxide film is omitted. FIG. 4 is a longitudinal sectional view of the main part of the semiconductor device according to the first embodiment. Further, FIG. 4 shows an enlarged view of the periphery including the indentation region 23a1 in FIG. 3.

[0012] First, as shown in Figure 1, the semiconductor device 1 is enclosed by a sealant 30, forming a three-dimensional shape. The sealant 30 is surrounded on its front side, back side, and all four sides by its top surface 31, its bottom surface 32 opposite the top surface 31, its long sides 33, 35, and its short sides 34, 36. The sealant 30 also has two fastening holes 30a formed in each of its sides.

[0013] The upper surface 31 and the lower surface 32 are rectangular in shape when viewed from above. The upper surface 31 and the lower surface 32 are parallel to the XY plane and have the same shape. The ends of the upper surface 31 in the ±X direction are bent in the -Z direction. The ends of the lower surface 32 in the ±X direction are bent in the +Z direction.

[0014] The short sides 34 and 36 connect the short sides (+Y and -Y directions, respectively) of the top surface 31 and bottom surface 32 at approximately right angles (parallel to the XZ plane). The short sides 34 and 36 have the same shape and form a hexagon in side view (see Figure 1(A)). The long sides 33 and 35 connect the long sides of the top surface 31 and bottom surface 32 at approximately right angles (parallel to the YZ plane). The long sides 33 and 35 have the same shape and form a rectangle in side view.

[0015] The two fastening holes 30a are on the short sides 34, 36 and may be holes that penetrate the sealing body 30 formed along a center line C parallel to the long sides 33, 35. These fastening holes 30a are used when fastening the semiconductor device 1 to a predetermined location with bolts. The diameter of the fastening holes 30a does not need to be large enough for the bolts to pass through. The location of the fastening holes 30a is just an example. The semiconductor device 1 is placed, for example, on a cooling unit, and bolts are inserted through the fastening holes 30a to fasten it to the cooling unit. The cooling unit cools the back surface of the semiconductor device 1 that is in contact with it. Examples of cooling units include a heat dissipation base substrate, a heat sink, and a water cooling device.

[0016] Furthermore, multiple recesses 30b are formed on the upper surface 31 of the sealant 30. The recesses 30b are formed in a line along a center line parallel to the long sides 33 and 35 of the upper surface 31 of the sealant 30, and are positioned closer to the long side 33 from the center line. The recesses 30b do not penetrate the sealant 30, but are recesses that extend from the upper surface 31 of the sealant 30 by 5% to 80% of the thickness of the sealant 30. Details of the recesses 30b will be described later.

[0017] The connection points between the upper surface 31 and lower surface 32 of the sealant 30, the short sides 34 and 36, and the long sides 33 and 35 may be chamfered with R-chamfers or C-chamfers. Note that the images show the case where both ends of the upper surface 31 and lower surface 32 of the sealant 30 in the ±X direction are bent. The ends of the upper surface 31 and lower surface 32 in the ±X direction do not necessarily have to be bent, and the entire surface may be a flat plate with a single plane. In this case, the short sides 34 and 36 form a rectangular shape when viewed from the side. Therefore, the sealant 30 may be in the shape of a rectangular parallelepiped.

[0018] The encapsulant 30 includes, for example, a thermosetting resin and a filler contained in the thermosetting resin. The thermosetting resin is, for example, an epoxy resin, a phenolic resin, or a maleimide resin. An example of such an encapsulant is an epoxy resin containing a filler. Inorganic materials are used as the filler. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride.

[0019] The semiconductor device 1 has multiple main current lead frames 21 and multiple control lead frames 22 extending from the long sides 33 and 35 of the encapsulant 30. The multiple main current lead frames 21 and multiple control lead frames 22 may be bent in the middle. The ends of the bent multiple main current lead frames 21 and bent multiple control lead frames 22 may extend in the +Z direction. In this embodiment, when there is no particular distinction between the main current lead frames and control lead frames, they will be described as the main current lead frames 21 and control lead frames 22.

[0020] The semiconductor device 1 includes a metal base substrate 25, which will be described later, containing the encapsulant 30. The back surface of the metal base substrate 25 is in the same plane as the bottom surface 32 of the encapsulant 30 and is exposed from the bottom surface 32 (see, for example, Figure 3). The back surface of the metal base substrate 25 may protrude outward (in the -Z direction) from the bottom surface 32 of the encapsulant 30.

[0021] Such a semiconductor device 1 has components as shown in Figures 2 and 3 sealed by a encapsulant 30. Specifically, the semiconductor device 1 includes six semiconductor chips 10, a control IC (Integrated Circuit) 11, a main current lead frame 21 (including main current lead frames 21a to 21g), a control lead frame 22 (including control lead frames 22a to 22c), and a metal base substrate 25.

[0022] Furthermore, in the semiconductor device 1, the control lead frame 22, control IC 11, semiconductor chip 10, and main current lead frame 21 are electrically connected by wires as appropriate. In Figure 2, a wire 24a directly connecting the semiconductor chip 10 and the main current lead frame 21 is shown.

[0023] The semiconductor chip 10 may include a switching element consisting of a power MOSFET, which is mainly composed of silicon carbide. Such a semiconductor chip 10 has a gate electrode as a control electrode 10a and a source electrode as a main electrode, which is an output electrode 10b, on its front surface. The control electrode 10a is located in the center of the side of the front surface, and the output electrode 10b is located in the center of the front surface. The semiconductor chip 10 also has a drain electrode as a main electrode, which is an input electrode, on its back surface.

[0024] Alternatively, the semiconductor chip 10 may include an RC (Reverse Conducting)-IGBT switching element composed mainly of silicon. An RC-IGBT incorporates both an IGBT and an FWD (Free Wheeling Diode) within a single chip. The semiconductor chip 10 also has a gate electrode as a control electrode 10a and an emitter electrode as a main electrode output electrode 10b on its front surface, and a collector electrode as an input electrode for the main electrode on its back surface.

[0025] The thickness of the semiconductor chip 10 is, for example, between 180 μm and 220 μm, with an average of approximately 200 μm. Furthermore, Figure 2 only shows a case where six semiconductor chips 10 are provided. The number of chips is not limited to six; it can be provided according to the specifications of the semiconductor device 1.

[0026] Alternatively, instead of the six semiconductor chips 10, a semiconductor chip containing six sets of switching elements and a semiconductor chip containing diode elements may be used. Examples of semiconductor chips containing switching elements are power MOSFETs and IGBTs. Such semiconductor chips have, for example, a drain electrode (collector electrode in the case of IGBTs) as an input electrode on the back surface, and a gate electrode as a control electrode and a source electrode (emitter electrode in the case of IGBTs) as an output electrode on the front surface. Examples of semiconductor chips containing diode elements are FWDs such as SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes. Such semiconductor chips have a cathode electrode as an input electrode on the back surface and an anode electrode as an output electrode on the front surface.

[0027] Multiple control ICs 11 are arranged on the control lead frame 22 via connecting members. The control ICs 11 are also directly connected to the control electrodes 10a of the semiconductor chip 10 via wires (see wire 24b in Figure 3). The control ICs 11 input control signals to the control electrodes 10a of the semiconductor chip 10 in response to control signals input from the control lead frame 22.

[0028] The main current lead frame 21 has an oxide film 23a formed on its surface. Such a main current lead frame 21 includes main current lead frames 21a to 21g. The main current lead frames 21a to 21d integrally include joint portions 21a1 to 21d1, connecting portions 21a2 to 21d2, and terminal portions 21a3 to 21d3. The joint portions 21a1 to 21d1 are joined to the wiring boards 26a to 26d. This joining may be, for example, a solder joint or an ultrasonic joint. The joint portions 21a1 to 21d1 are flat and parallel to the wiring boards 26a to 26d. The connecting portions 21a2 to 21d2 are inclined with respect to the wiring boards 26a to 26d and connect the joint portions 21a1 to 21d1 and the terminal portions 21a3 to 21d3. The terminal sections 21a3 to 21d3 are located in the +Z direction relative to the wiring boards 26a to 26d (the lower surface 32 of the encapsulant 30). The terminal sections 21a3 to 21d3 extend outward (in the -X direction) from the long side surface 33 of the encapsulant 30. In addition, the main current lead frames 21e to 21g are located at the same height as the terminal sections 21a3 to 21d3 when viewed from the side. The main current lead frames 21e to 21g extend outward (in the -X direction) from the long side surface 33 of the encapsulant 30.

[0029] The control lead frame 22 has an oxide film 23b formed on its surface. In a plan view, the control lead frame 22 is positioned on the long side 35 of the metal base substrate 25. The control lead frame 22 is located at the same height as the terminal portions 21a3 to 21d3 and the main current lead frames 21e to 21g. Such a control lead frame 22 includes control lead frames 22a to 22c. Note that in the control lead frame 22 shown in Figure 2, all control lead frames except for control lead frames 22b and 22c are referred to as control lead frame 22a.

[0030] The control lead frames 22b and 22c include control die pad sections 22b1 and 22c1, linking sections 22b2 and 22c2, and terminal sections 22b3, 22c3, and 22c4. Multiple control die pad sections 22b1 and 22c1 are included in the control lead frames 22b and 22c, respectively. Control ICs 11 are provided in each of the control die pad sections 22b1 and 22c1. The linking sections 22b2 and 22c2 link the control die pad sections 22b1 and 22c1 with the terminal sections 22b3, 22c3, and 22c4. The linking sections 22b2 and 22c2 are parallel to the long side surface 35 and include portions to which the control die pad sections 22b1 and 22c1 are connected. One end of terminal portion 22b3 is connected to linkage portion 22b2, and the other end of terminal portion 22b3 extends outward (+X direction) from the long side surface 35 of the sealing body 30. One end of terminal portions 22c3 and 22c4 is connected to linkage portion 22c2, and the other ends of terminal portions 22c3 and 22c4 extend outward (+X direction) from the long side surface 35 of the sealing body 30.

[0031] Such main current lead frames 21 and control lead frames 22 are constructed primarily from a metal with excellent conductivity. Such metals are copper or copper alloys. To improve corrosion resistance, the main current lead frames 21 and control lead frames 22 may be plated. Examples of plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0032] The metal base substrate 25 has a rectangular shape in plan view, and an oxide film 23a is formed on all surfaces except the semiconductor chip 10 and the back surface. The metal base substrate 25 has wiring boards 26a to 26d, which are specific examples of conductive boards, an insulating layer 27, and a heat sink 28. The wiring boards 26a to 26d are mainly composed of a metal with excellent conductivity. Such a metal is copper or a copper alloy. The wiring boards 26a to 26d may be plated to improve corrosion resistance. Examples of plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The wiring boards 26a to 26d are formed in a single row along the ±Y direction on the front surface of the insulating layer 27. The main current lead frame 21 is bonded to the wiring boards 26a to 26d.

[0033] The wiring board 26a is roughly rectangular in plan view. The wiring board 26a extends to the long side on the +X direction and the short side on the +Y direction of the insulating layer 27. Notched regions are formed at the corners on the -X and -Y directions of the wiring board 26a. Three semiconductor chips 10 are arranged in a row on the front surface of the wiring board 26a via a bonding member (not shown). The wiring boards 26b to 26d are roughly L-shaped in plan view. The wiring boards 26b to 26d extend to the long side on the +X direction of the insulating layer 27. Semiconductor chips 10 are each arranged in a row on the front surface of the wiring boards 26b to 26d via a bonding member (not shown). The six semiconductor chips 10 are arranged with their control electrodes 10a facing the +X direction (long side surface 35).

[0034] The bonding member used to join the semiconductor chip 10 to the wiring boards 26a to 26d may be solder or sintered metal. The solder is made of lead-free solder mainly composed of a predetermined alloy. The predetermined alloy is, for example, at least one of the following alloys: a tin-silver alloy, a tin-zinc alloy, or a tin-antimony alloy. The solder may also contain additives such as copper, bismuth, indium, nickel, germanium, cobalt, or silicon. The sintered metal is made of a metal mainly composed of silver. Similarly, the control IC 11 may also be joined to the control die pad portions 22b1 and 22c1 of the control lead frames 22b and 22c using a bonding member.

[0035] Such wiring boards 26a to 26d are produced by etching a conductive plate or foil formed on one side of the insulating layer 27, or by laminating a conductive plate to one side of the insulating layer 27. The thickness of the wiring boards 26a to 26d is preferably 0.10 mm or more and 1.00 mm or less, and more preferably 0.20 mm or more and 0.50 mm or less. Note that wiring boards 26a to 26d are examples. The number, shape, size, etc. of the wiring boards may be appropriately selected as needed.

[0036] The insulating layer 27 is composed of either epoxy resin, epoxy resin mixed with inorganic filler, polyimide, or polytetrafluoroethylene. The thickness of the insulating layer 27 is preferably 0.09 mm or more and 0.15 mm or less.

[0037] The heat sink 28 is made of an alloy containing at least one of the following materials, such as aluminum, iron, silver, copper, or other materials with excellent thermal conductivity. Furthermore, to improve corrosion resistance, a plating material can be formed on the surface of the heat sink 28. Examples of plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys. As previously described, the back surface of the heat sink 28 is exposed in a plane with the lower surface 32 of the sealant 30. A cooler (not shown) can be attached to the back surface of the heat sink 28 (the lower surface 32 of the sealant 30) via solder or silver solder to improve heat dissipation. In this case, the cooler is made of an alloy containing at least one of the following materials, such as aluminum, iron, silver, copper, or other materials with excellent thermal conductivity. Examples of coolers include a heat sink with multiple fins and a water-cooled cooling device. The heat sink 28 may also be integrated with such a cooler. In that case, it may be made of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, or alloys containing at least one of these. Furthermore, to improve corrosion resistance, a plating material may be formed on the surface by a plating process. Examples of plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The thickness of the heat sink 28 is preferably 0.1 mm or more and 2.0 mm or less.

[0038] As previously described, an oxide film 23a is formed on the surfaces of the wiring boards 26a to 26d (excluding the semiconductor chip 10) included in the metal base substrate 25. Similarly, an oxide film 23a is also formed on the surfaces of the main current lead frames 21a to 21g joined to the wiring boards 26a to 26d. In addition, an oxide film 23b is formed on the surface of the control lead frame 22 (excluding the control IC 11). The oxide films 23a and 23b are composed of oxides containing copper, for example. The average thickness of the oxide films 23a and 23b is between 20 nm and 30 nm, with an average of approximately 25 nm. Furthermore, an indentation is formed in the indentation region 23a1 of the oxide film 23a. Moreover, a depression 30b is formed on the upper surface 31 of the sealant 30, directly opposite the indentation region 23a1. The recess 30b is concave, extending from the upper surface 31 to the lower surface 32 of the sealant 30 (in the -Z direction). The inner wall of the recess 30b does not necessarily have to be perpendicular to the bottom surface of the recess 30b. The inner wall of the recess 30b may be inclined at approximately ±15° relative to the bottom surface of the recess 30b.

[0039] The following will explain the indentation region 23a1 of the oxide film 23a and the recess 30b of the sealant 30 that is directly opposite the indentation region 23a1, using Figure 4 as an example. In the metal base substrate 25, the oxide film 23a is formed particularly on the surfaces (front and side surfaces) of the wiring boards 26a to 26d. For example, as shown in Figure 4, the oxide film 23a is formed on the wiring board 26c except for the area where the semiconductor chip 10 is placed.

[0040] An indentation is formed in the oxide film 23a of the indentation region 23a1 of the wiring board 26c. That is, the indentation region 23a1 of the wiring board 26c is rougher and has a coarser surface than other regions. The indentation in the oxide film 23a is formed by crushing the oxide film 23a, as will be described later. The wiring board 26c is exposed through the gap in the oxide film 23aa where the indentation is formed in the indentation region 23a1. The sealant 30 seals the surface and gap of the indentation region 23a1 of the oxide film 23a. That is, in the indentation region 23a1, the wiring board 26c is in close contact with the sealant 30 through the gap. The sealant 30 has low adhesion to the oxide film 23a, but high adhesion to the wiring board 26c. For this reason, the sealant 30 is in close contact with the wiring board 26c exposed from the indentation region 23a1 of the oxide film 23a. Therefore, since the sealant 30 adheres closely to the wiring board 26c in the indentation region 23a1, peeling of the sealant 30 in the indentation region 23a1 is prevented, and the extension of peeling of the sealant 30 is also prevented.

[0041] Furthermore, the indentation region 23a1 of the oxide film 23a is rougher than other regions. Therefore, the indentation region 23a1 of the oxide film 23a provides an anchoring effect to the sealant 30, improving its adhesion to the sealant 30. In addition, a depression 30b is formed directly opposite the indentation region 23a1 of the sealant 30. Therefore, the thickness of the sealant 30 in the indentation region 23a1 is thinner than in other parts. As a result, the amount of thermal expansion of the sealant 30 due to heat is smaller in the indentation region 23a1 than in the surrounding regions. Consequently, the thermal stress in the indentation region 23a1 is smaller than in its surroundings. This also prevents delamination of the sealant 30 in the indentation region 23a1. If the delamination spreads in the sealant 30 and passes through the indentation region 23a1, the spread of delamination is suppressed in the indentation region 23a1. Therefore, the peeling does not extend to the vicinity of the semiconductor chip 10, and the peeling of the encapsulant 30 near the semiconductor chip 10 is suppressed.

[0042] In such indentation regions 23a1, it is acceptable for some oxide film 23a to remain on the wiring board 26c, and it is preferable that at least the wiring board 26c is exposed and can make close contact with the sealant 30. It is more preferable that all of the oxide film 23a is removed in the indentation regions 23a1.

[0043] The arithmetic mean roughness of the indentation region 23a1 of the oxide film 23a is approximately half the thickness of the oxide film 23a. Furthermore, the indentation region 23a1 of the oxide film 23a may be thinner than the other regions. This explanation describes the case of the wiring board 26c shown in Figure 4. Regardless of the wiring board 26c, any wiring board with an indentation region 23a1 formed thereon includes the indentation region 23a1 and the recess 30b opposite the indentation region 23a1, similar to Figure 4, thereby suppressing the occurrence of delamination of the sealant 30 and preventing the spread of delamination.

[0044] Next, the manufacturing method of the semiconductor device 1 will be explained using Figure 5. Figure 5 is a flowchart showing the manufacturing method of the semiconductor device according to the first embodiment. First, a preparation step (step S1 in Figure 5) is performed to prepare the components of the semiconductor device 1. The components of the semiconductor device 1 include, for example, a semiconductor chip 10, a control IC 11, a lead frame in which a main current lead frame 21 and a control lead frame 22 are integrally connected by tie bars, a metal base substrate 25, and a sealing member which is the raw material for the sealing body 30. In addition to preparing the components, a manufacturing apparatus used to manufacture the semiconductor device 1 is also prepared. Examples of the manufacturing apparatus include a sealing mold 3 for sealing and a pressing pin 4.

[0045] Next, an assembly process (step S2 in Figure 5) is performed to assemble the semiconductor assembly. The assembly process will now be explained using Figure 6. Figure 6 is a diagram showing the assembly process included in the manufacturing method of the semiconductor device according to the first embodiment. Note that Figure 6 is a cross-sectional view of the location corresponding to Figure 4.

[0046] The junctions 21a1 to 21d1 of the main current lead frames 21a to 21d, which are connected to the lead frame, are joined to the wiring boards 26a to 26d of the metal base substrate 25. The semiconductor chip 10 is joined to the wiring boards 26a to 26d using a bonding member. The control IC 11 is also joined to the control die pads 22b1 and 22c1 of the control lead frames 22b and 22c, which are connected to the lead frame. The output electrode 10b of the semiconductor chip 10 is directly connected to the main current lead frames 21b to 21g, which are connected to the lead frame, with wires. The control electrode 10a of the semiconductor chip 10 and the control IC 11, and the control IC 11 and the control lead frame 22 are also directly connected with wires. In this way, the semiconductor assembly 2 shown in Figure 6 is assembled.

[0047] Next, a mold setting process (step S3 in Figure 5) is performed in which the semiconductor assembly 2 is set in the sealing mold. The mold setting process will now be explained using Figures 7 and 8. Figure 7 shows the mold setting process (immediately after setting) included in the semiconductor device manufacturing method of the first embodiment, and Figure 8 shows the mold setting process (heating) included in the semiconductor device manufacturing method of the first embodiment.

[0048] The sealing mold 3 used in the mold setting process includes a lower mold 3a and an upper mold 3b. The upper mold 3b has an opening (not shown) into which a pressure pin, described later, can be inserted and removed. When the lower mold 3a and the upper mold 3b are placed together, a cavity 3c is formed inside. The lower mold 3a and the upper mold 3b are preheated to a predetermined temperature.

[0049] In the open air, the semiconductor assembly 2 assembled in step S2 is clamped between the lower mold 3a and the upper mold 3b. As a result, the main current lead frame 21 and the control lead frame 22 of the semiconductor assembly 2 are clamped between the lower mold 3a and the upper mold 3b, as shown in Figure 7. The semiconductor chip 10, control IC 11, wires 24a and 24b, and metal base substrate 25 of the semiconductor assembly 2 are housed in the cavity 3c.

[0050] Then, oxide films 23a and 23b begin to form on the surfaces of the components of the semiconductor assembly 2 housed in the cavity 3c of the sealing mold 3. After sufficient time has elapsed, as shown in Figure 8, oxide films 23a and 23b are formed on the surfaces of the components of the semiconductor assembly 2 housed in the cavity 3c of the sealing mold 3. In addition, oxide films may also form on the outside of the sealing mold 3 of the semiconductor assembly 2 on the main current lead frame 21 and control lead frame 22, which are heated by heat conduction.

[0051] Next, an indentation formation process (step S4 in Figure 5) is performed, in which an indentation is formed by pressing with a pressing pin and maintaining the pressure of the pressing pin. The indentation formation process will be explained using Figures 9 and 12, and the pressing pin will be explained using Figures 10 and 11. Figure 9 is a diagram showing the indentation formation process included in the manufacturing method of the semiconductor device according to the first embodiment. Figures 10 and 11 are diagrams showing the pressing pin used in the indentation formation process included in the manufacturing method of the semiconductor device according to the first embodiment. Figures 10(A) and (B) show the pressing surface 4a at the lower end of the pressing pin 4. Figure 10(1) shows a plan view of the pressing surface 4a in Figures 10(A) and (B). Figure 10(2) shows a cross-sectional view of Figure 10(1) along the dashed line YY. Figure 11(A) is an enlarged cross-sectional view of a different pressing surface 4a than that in Figure 10. Figure 11(B) is an enlarged cross-sectional view of the tip of a different pressing surface 4a than that in Figure 10. Figure 12 is a longitudinal cross-sectional view of a key part after the indentation formation step included in the manufacturing method of a semiconductor device according to the first embodiment.

[0052] In step S3, a pressure pin 4 is inserted vertically from the upper mold 3b into the front surface of the metal base substrate 25 included in the semiconductor assembly 2 on which the oxide film 23a has been formed. The pressure pin 4 is columnar in shape and includes a pressure surface 4a at its lower end. The pressure pin 4 can be columnar (rod-shaped), for example, a rectangular prism or a cylindrical shape. When the pressure pin 4 is inserted vertically into the front surface of the metal base substrate 25, the pressure surface 4a is approximately horizontal to the front surface.

[0053] Such a pressing surface 4a is roughened to form irregularities. The pressing surface 4a has irregularities formed in one direction, for example, as shown in Figure 10(A). That is, its cross-section is jagged (multiple inverted V shapes). The pressing surface 4a may include multiple such inverted V shapes and may be formed in random directions, not just one direction. In this case, multiple sharp vertices are formed. The cross-section passing through the vertices becomes inverted V-shaped. The pressing surface 4a may also have multiple spire-shaped spikes formed on it, for example, as shown in Figure 10(B). The pitch between the vertices of the inverted V shapes on the pressing surface 4a in Figure 10(2) is, for example, 5 μm or more and 50 μm or less. The height of the irregularities on the pressing surface 4a is, for example, 5 μm or more and 20 μm or less, with an average of about 10 μm. The diameter of the pressing surface 4a may be, for example, 1.0 mm or more and 1.5 mm or less.

[0054] The pressing surface 4a of the inserted pressing pin 4 contacts the vicinity of the corner on the long side 33 side of the semiconductor chip 10 on the metal base substrate 25. The contact points of the pressing surface 4a with the metal base substrate 25 are the circular marks on the wiring boards 26a to 26d and the insulating layer 27, as illustrated in Figure 2. For example, the pressing surface 4a of the pressing pin 4 contacts the vicinity of the corner of the semiconductor chip 10 on the wiring board 26c of the metal base substrate 25. Furthermore, when the pressing pin 4 is pressed towards the lower mold 3a, the oxide film 23a is crushed by the roughened pressing surface 4a, as shown in Figure 12. As a result, the pressing surface 4a pierces through the oxide film 23a and penetrates the wiring board 26c. The irregularities of the pressing surface 4a are transferred to the oxide film 23a. The pressing pressure of the pressing pin 4 toward the lower mold 3a is maintained in this manner.

[0055] Furthermore, as another example of achieving such pressing with the inverted V-shaped pressing surface 4a shown in Figure 10, the curvature of the tip of the pressing surface 4a may be kept constant, as shown in Figure 11(A). With such a pressing surface 4a, point contact with the metal base substrate 25 is achieved. As a result, the roughened pressing surface 4a penetrates the oxide film 23a and pierces the wiring board 26c.

[0056] Furthermore, the tip of the roughened pressing surface 4a may be flat without curvature (Figure 11(B)). However, if the spacing between the protrusions on the pressing surface 4a, where the tips of the protrusions are flat in this way, is too narrow, the entire pressing surface 4a can be considered substantially flat, and it will not be able to reliably penetrate the oxide film 23a. For the tip of the pressing surface 4a to penetrate the oxide film 23a, the diameter (or width) of each protrusion on the pressing surface 4a must be sufficiently small. This improves the pressure on each protrusion on the pressing surface 4a. Also, within the limited area of ​​the pressing surface 4a of the pressing pin 4, the spacing between the protrusions is configured to be wide in order to make the diameter (or width) of the protrusions sufficiently small. That is, the protrusions on the pressing surface 4a become sparse. With such a pressing surface 4a, point contact with the metal base substrate 25 is achieved. As a result, the roughened pressing surface 4a penetrates the oxide film 23a and pierces the wiring board 26c.

[0057] Next, a sealing process (step S5 in Figure 5) is performed in which a sealing member is filled into the cavity 3c of the sealing mold 3 to seal the inside of the cavity 3c. The sealing process will now be explained using Figures 13 to 15. Figure 13 is a diagram showing the sealing process included in the manufacturing method of the semiconductor device according to the first embodiment. Figure 14 shows the sealing process included in the manufacturing method of the semiconductor device according to the first embodiment (during the removal of the pressing pin), and Figure 15 shows the sealing process included in the manufacturing method of the semiconductor device according to the first embodiment (after the removal of the pressing pin).

[0058] The sealing member 30c is filled into the cavity 3c of the sealing mold 3. The sealing member 30c is made of the same material as the sealing body 30 described above. The sealing member 30c is filled simultaneously, for example, from the sealing mold 3 between the main current lead frames 21 towards the control lead frame 22 side (+X direction). At this time, the sealing mold 3 is heated and maintained at a constant temperature. In addition, the metal base substrate 25 is pressed towards the lower mold 3a side by the pressing pin 4. This prevents displacement of the metal base substrate 25 due to the flow of the sealing member 30c. In this way, as shown in Figure 13, the entire cavity 3c is sealed with the sealing member 30c.

[0059] Before the sealing member 30c has completely solidified, the pressing pin 4 is withdrawn away from the metal base substrate 25 (in the +Z direction). For example, as shown in Figure 14, while the pressing surface 4a of the pressing pin 4 is lifted vertically upward from the wiring board 26c of the metal base substrate 25 and maintained in that position, the unsolidified sealing member 30c enters the indentation region 23a1 after the pressing surface 4a has been withdrawn. In the indentation region 23a1 after the pressing surface 4a has been withdrawn, the oxide film 23a is crushed, and the wiring board 26c is exposed through the gaps in the oxide film 23a. The sealing member 30c that enters the indentation region 23a1 further flows into the wiring board 26c through the gaps in the oxide film 23a.

[0060] The pressure pin 4, which is maintained in a position separated from the metal base substrate 25, is completely removed from the sealing mold 3 after the sealing member 30c has almost solidified. As a result, as shown in Figure 15, a depression 30b is formed on the upper part of the sealing member 30c that is directly facing the indentation region 23a1. The roughened pressing surface 4a of the pressure pin 4 is transferred to the bottom surface of this depression 30b. The arithmetic mean roughness of the bottom surface of the depression 30b is the same as or less than the arithmetic mean roughness of the pressing surface 4a of the pressure pin 4. Also, the arithmetic mean roughness of the oxide film 23a of the indentation region 23a1 is the same as or less than the arithmetic mean roughness of the pressing surface 4a of the pressure pin 4.

[0061] Next, the sealing member 30c solidifies completely to form the sealing body 30, and a mold removal process (step S6 in Figure 5) is performed to remove the sealing mold 3. Once the sealing body 30 has cooled sufficiently, the lower mold 3a and upper mold 3b of the sealing mold 3 are separated and removed. This yields a semiconductor assembly 2 sealed with the sealing body 30. Unnecessary parts of the semiconductor assembly 2, such as burrs on the sealing body 30, tie bars on the lead frame, main current lead frame 21, and control lead frame 22, are removed. This yields the semiconductor device 1 shown in Figures 1 and 2.

[0062] Next, the formation location of the indentation region 23a1 on the metal base substrate 25 will be explained using Figure 16. Figure 16 is a diagram illustrating the formation location of the indentation region on the semiconductor device of the first embodiment. Note that Figure 16 only shows an example of the metal base substrate 25 to illustrate the formation location of the indentation region 23a1. The sealing body 30 and oxide film 23a are not shown. For simplicity, the metal base substrate 25 is rectangular in plan view. That is, the insulating layer 27 and the wiring board 26e formed on the insulating layer 27 are also rectangular in plan view. The wiring board 26e is surrounded by sides 26e1 to 26e4. The corner 26e5 is composed of sides 26e1 and 26e2. The corner 26e6 is composed of sides 26e2 and 26e3. The corner 26e7 is composed of sides 26e3 and 26e4. The corner 26e8 is formed by sides 26e4 and 26e1. Additionally, two semiconductor chips 10 are arranged on the front surface of the wiring board 26e, respectively, along the ±Y directions.

[0063] In such cases, the sealant 30 that seals the metal base substrate 25 often delaminates at the corners 26e5 to 26e8 of the wiring board 26e. Starting from the delamination at the corners 26e5 to 26e8, the delamination extends inward toward the wiring board 26e (extending toward the fan-shaped area starting from the corners 26e5 to 26e8 in Figure 16). If a semiconductor chip 10 is present at the destination of the delamination, delamination of the sealant 30 around the semiconductor chip 10 may occur, potentially causing a malfunction of the semiconductor device 1.

[0064] Therefore, the indentation region 23a1 must be formed in the area of ​​the wiring board 26e facing the corners 26e5 to 26e8 of the semiconductor chip 10. It is sufficient that the indentation region 23a1 be formed in at least one of the areas of the wiring board 26e facing the corners 26e5 to 26e8 of the semiconductor chip 10. In Figure 16, the indentation region 23a1 must be formed within the dashed area of ​​the wiring board 26e on the side of the semiconductor chip 10 facing the corners 26e5 to 26e8. This prevents the delamination occurring at the corners 26e5 to 26e8 of the wiring board 26e from extending to the semiconductor chip 10.

[0065] Furthermore, delamination occurring at the corners 26e5 to 26e8 of the sealant 30 may extend not only toward the inside of the wiring board 26e, but also in the vicinity of the edges 26e1 to 26e4 along the edges 26e1 to 26e4 (extending the peripheral area enclosed by the dashed line including the edges 26e1 to 26e4 in Figure 16). Note that the extension of the peripheral area of ​​the delamination edges 26e1 to 26e4 occurs together with the extension of the delamination toward the inside of the wiring board 26e, or independently. For this reason, at least one indentation region 23a1 may be formed in the area facing the corners 26e5 to 26e8, or in at least one of the peripheral areas of the edges 26e1 to 26e4.

[0066] In the semiconductor device 1 of the first embodiment, the indentation region 23a1 is formed on the long side 33 side with respect to the semiconductor chip 10 on the wiring board 26a to 26d. The indentation region 23a1 may also be formed on the long side 35 side with respect to the semiconductor chip 10 on the wiring board 26a to 26d.

[0067] The semiconductor device 1 includes a semiconductor chip 10, wiring boards 26a to 26d to which the semiconductor chip 10 is bonded, and a sealant 30 that seals the semiconductor chip 10 and the wiring boards 26a to 26d. The front surfaces of the wiring boards 26a to 26d include an indentation region 23a1 that is rougher than other areas, and the upper surface 31 of the sealant 30 facing the front surfaces of the wiring boards 26a to 26d includes a recess 30b that directly faces the indentation region 23a1. This improves the adhesion between the sealant 30 and the indentation region 23a1 of the wiring boards 26a to 26d. Furthermore, the thickness of the sealant 30 on the indentation region 23a1 is thinner than other parts because the recess 30b is formed therein. Therefore, peeling of the sealant 30 in the indentation region 23a1 is prevented. Therefore, when the delamination spreads through the indentation region 23a1, the indentation region 23a1 suppresses the spread of the delamination. Delamination of the encapsulant 30 around the semiconductor chip 10 is suppressed. As a result, the decrease in the reliability of the semiconductor device 1 is suppressed.

[0068] (Extreme Variation 1-1) In Modification 1-1, the case in which an indentation region 23a1 is formed on the insulating layer 27 of the metal base substrate 25 will be explained using Figures 17 and 18. Figure 17 is a cross-sectional view of the semiconductor device of the first embodiment (Modification 1-1). Figure 18 is a longitudinal cross-sectional view of the main part of the semiconductor device of the first embodiment (Modification 1-1). Note that Figure 17 is a cross-sectional view along the dashed line Y2-Y2 in Figure 2. Figure 18 shows an enlarged view of the area including the indentation region 23a1 in Figure 17.

[0069] The pressing pin 4 may be pressed against the insulating layer 27 of the metal base substrate 25. For example, in Figures 17, 18, and 2, an indentation region 23a1 is formed on the short side 36 of the wiring board 26a. In this case, the indentation region 23a1 is formed in the same manner as in the first embodiment.

[0070] As shown in Figure 18, an indentation is formed in the oxide film 23a of the indentation region 23a1 of the insulating layer 27. In this case as well, the insulating layer 27 is exposed through the gap in the oxide film 23a where the indentation is formed in the indentation region 23a1. The indentation region 23a1 of the oxide film 23a acts as an anchor for the sealant 30, improving the adhesion of the sealant 30 to the indentation region 23a1. Furthermore, the sealant 30 seals the gap in the indentation region 23a1 of the oxide film 23a. That is, in the indentation region 23a1, the insulating layer 27 adheres closely to the sealant 30 through this gap. Since the sealant 30 is made of resin, similar to the insulating layer 27, it has high adhesion to the insulating layer 27. Therefore, the sealant 30 adheres closely to the insulating layer 27 in the indentation region 23a1, preventing the sealant 30 from peeling off and preventing the peeling from spreading.

[0071] Furthermore, the indentation region 23a1 of the insulating layer 27 is rougher than other regions. As a result, the indentation region 23a1 of the insulating layer 27 provides an anchoring effect to the sealant 30, improving adhesion to the sealant 30. In addition, a recess 30b is formed directly opposite the indentation region 23a1 of the sealant 30. As a result, the thickness of the sealant 30 in the indentation region 23a1 is thinner than in other parts. This also prevents delamination of the sealant 30 in the indentation region 23a1. If delamination spreads in the sealant 30 and passes through the indentation region 23a1, the spread of delamination is suppressed in the indentation region 23a1. As a result, the spread of delamination does not reach the vicinity of the semiconductor chip 10, and delamination of the sealant 30 near the semiconductor chip 10 is suppressed.

[0072] [Second Embodiment] In the second embodiment, a case in which a lead frame with integrally formed die pads is used instead of a metal base substrate 25 will be described with reference to Figures 19 and 20. Figure 19 is a cross-sectional view of the semiconductor device of the second embodiment, and Figure 20 is a longitudinal cross-sectional view of the semiconductor device of the second embodiment. The following will mainly describe the components that differ from those of the first embodiment. A plan view of the external appearance of the semiconductor device 1a can be found in Figure 1.

[0073] The semiconductor device 1a has components as shown in Figures 19 and 20 sealed by an encapsulant 30. Specifically, the semiconductor device 1a includes six semiconductor chips 10, a control IC 11, a main current lead frame 21 (including main current lead frames 21a to 21g), a control lead frame 22 (including control lead frames 22a to 22c), and an insulating sheet 29.

[0074] The main current lead frame 21 includes main current lead frames 21a to 21g. The main current lead frames 21a to 21d integrally include die pad sections 21a4 to 21d4, which are specific examples of conductive plates, linking sections 21a2 to 21d2, and terminal sections 21a3 to 21d3.

[0075] The die pads 21a4 to 21d4 are provided in place of the wiring boards 26a to 26d of the first embodiment. The die pads 21a4 to 21d4 are formed in a row along the ±Y direction on the front surface of the insulating sheet 29. The die pad 21a4 has a substantially rectangular shape in plan view. Three semiconductor chips 10 are arranged in a row on the front surface of the die pad 21a4 via a bonding member (not shown). The die pads 21b4 to 21d4 have a substantially L-shape in plan view. Semiconductor chips 10 are each arranged in a row on the front surface of the die pads 21b4 to 21d4 via a bonding member (not shown). The six semiconductor chips 10 are arranged with their control electrodes 10a facing the +X direction (long side surface 35).

[0076] The insulating sheet 29 is in the form of a sheet. The insulating sheet 29 also contains a thermosetting resin and an inorganic filler contained in the resin. The thermosetting resin mainly consists of at least one selected from the group including epoxy resin, phenolic resin, melamine resin, and polyimide resin. Preferably, the thermosetting resin mainly consists of epoxy resin. The filler is an inorganic substance mainly consisting of at least one selected from the group including aluminum oxide, aluminum nitride, silicon nitride, and boron nitride, which have high insulating and high thermal conductivity properties. Furthermore, it is preferable that the insulating sheet 29 mainly consists of the same thermosetting resin as the sealant 30. More preferably, the thermosetting resin of the insulating sheet 29 is mainly composed of epoxy resin.

[0077] The insulating sheet 29, along with the die pads 21a4 to 21d4, is sealed within the sealant 30. The back surface of the insulating sheet 29 is in the same plane as the bottom surface 32 of the sealant 30 and is exposed from the bottom surface 32 (see, for example, Figure 3). Alternatively, the exposed back surface of the insulating sheet 29 (the bottom surface 32 of the sealant 30) may protrude in the -Z direction from the bottom surface 32 of the sealant 30.

[0078] Furthermore, in the semiconductor device 1a, an indentation region 23a1 is formed on the short sides 34, 36 of the semiconductor chips 10 at both ends of the die pad portion 21a4, near the corners on the long side 33. In addition, even in this case, a recess 30b is formed on the upper surface 31 of the sealant 30 that is directly opposite the indentation region 23a1.

[0079] Such a semiconductor device 1a can also be manufactured according to the flowchart in Figure 5, similar to the first embodiment. First, a preparation step (step S1 in Figure 5) is performed to prepare the components of the semiconductor device 1a. The components of the semiconductor device 1a include, for example, a semiconductor chip 10, a control IC 11, a lead frame in which a main current lead frame 21 and a control lead frame 22 are integrally connected by tie bars, an insulating sheet 29, and a sealing member which is the raw material for the sealing body 30. The die pads 21a4 to 21d4 are integrally connected to the linkage portions 21a2 to 21d2 of the main current lead frame 21 included in the lead frame. In addition to preparing the components, a manufacturing apparatus used to manufacture the semiconductor device 1a is also prepared. The manufacturing apparatus includes, for example, a sealing mold 3 for sealing and a pressing pin 4.

[0080] Next, the assembly process (step S2 in Figure 5) for assembling the semiconductor assembly is performed. In the semiconductor assembly 2 in Figure 6, instead of the metal base substrate 25, an insulating sheet 29 is placed on the back surface of the die pad portions 21a4 to 21d4 of the main current lead frame 21 included in the lead frame. In addition, the semiconductor chip 10 is bonded to the front surface of the die pad portions 21a4 to 21d4 using a bonding member. Similar to the first embodiment, wire connections are made to the main current lead frame 21 and control lead frame 22 included in the lead frame, the semiconductor chip 10, and the control IC 11.

[0081] Subsequently, after going through steps S3 to S6 in Figure 5, the semiconductor device 1a shown in Figures 19 and 20 is obtained. In this semiconductor device 1a, as with semiconductor device 1, the upper surface 31 of the encapsulant 30 facing the front surface of the die pad portions 21a4 to 21d4 of the encapsulant 30 includes a recess 30b that directly faces the indentation region 23a1. This improves the adhesion between the encapsulant 30 and the indentation region 23a1 of the die pad portions 21a4 to 21d4. Furthermore, the thickness of the encapsulant 30 on the indentation region 23a1 is thinner than other parts because the recess 30b is formed. Therefore, delamination of the encapsulant 30 in the indentation region 23a1 is prevented. As a result, when the extension of delamination passes through the indentation region 23a1, the extension of delamination is suppressed by the indentation region 23a1. Delamination of the encapsulant 30 around the semiconductor chip 10 is suppressed. As a result, the decrease in the reliability of the semiconductor device 1a is suppressed.

[0082] In the case of semiconductor device 1a, if necessary, an indentation region 23a1 may be formed on the insulating sheet 29 in the same manner as in Modification 1-1. The formation method can be the same as in Modification 1-1, using a pressing pin 4.

[0083] (Variation 2-1) In the semiconductor device 1b of Modification 2-1, the case in which the front surfaces of the main current lead frames 21 in the semiconductor device 1a are configured to form a single plane will be explained using Figure 21. Figure 21 is a longitudinal cross-sectional view of the semiconductor device of the second embodiment (Modification 2-1). Below, the components that differ from those of the second embodiment will be mainly described.

[0084] The semiconductor device 1b has components as shown in Figure 21 sealed by an encapsulant 30. Specifically, the semiconductor device 1b includes six semiconductor chips 10, a control IC 11, a main current lead frame 21 (including main current lead frames 21a to 21g), and a control lead frame 22 (including control lead frames 22a to 22c).

[0085] The main current lead frame 21 includes main current lead frames 21a to 21g. The main current lead frames 21a to 21d integrally include die pad sections 21a4 to 21d4, linkage sections 21a2 to 21d2, and terminal sections 21a3 to 21d3. The front surfaces of the die pad sections 21a4 to 21d4, linkage sections 21a2 to 21d2, and terminal sections 21a3 to 21d3 form the same plane. Such a main current lead frame 21 is located at the same height as the control lead frame 22.

[0086] The die pad portions 21a4 to 21d4 are the same as in the second embodiment when viewed from above. In modified example 2-1, the die pad portions 21a4 to 21d4 are configured to be thicker in the -Z direction than the thickness of the linking portions 21a2 to 21d2 and the terminal portions 21a3 to 21d3. Similar to the second embodiment, the semiconductor chip 10 is joined to these die pad portions 21a4 to 21d4 by bonding members. Therefore, in the semiconductor device 1b, the main current lead frame 21 is sealed spaced apart in the +Z direction from the lower surface 32 of the sealing body 30.

[0087] Such a semiconductor device 1b can also be manufactured according to the flowchart in Figure 5, similar to the second embodiment. First, a preparation step (step S1 in Figure 5) is performed to prepare the components of the semiconductor device 1b. The components of the semiconductor device 1b include, for example, a semiconductor chip 10, a control IC 11, a lead frame in which the main current lead frame 21 and the control lead frame 22 are integrally connected by tie bars, and a sealing member which is the raw material for the sealing body 30. The die pads 21a4 to 21d4 are integrally connected to the linkage portions 21a2 to 21d2 of the main current lead frame 21 included in the lead frame. In addition to preparing the components, a manufacturing apparatus used to manufacture the semiconductor device 1b is also prepared. The manufacturing apparatus includes, for example, a sealing mold 3 for sealing and a pressing pin 4.

[0088] Next, the assembly process (step S2 in Figure 5) for assembling the semiconductor assembly is performed. In the semiconductor assembly 2 in Figure 6, instead of the metal base substrate 25, the semiconductor chip 10 is bonded to the front surface of the die pad portions 21a4 to 21d4 of the main current lead frame 21 included in the lead frame using a bonding member. The control IC 11 and wires are connected in the same manner as in the first embodiment.

[0089] Next, a mold setting process (step S3 in Figure 5) is performed in which the semiconductor assembly is set in the sealing mold. Similar to the first embodiment, the sealing mold 3 includes a lower mold 3a and an upper mold 3b. Under atmospheric pressure, the semiconductor assembly assembled in step S2 is held between the lower mold 3a and the upper mold 3b. In the case of Modification 2-1, the main current lead frame 21 has a coplanar front surface and is therefore spaced apart from the lower mold 3a in the +Z direction. When the sealing mold 3 is heated, oxide films 23a and 23b are formed on the surfaces of the components of the semiconductor assembly housed in the cavity 3c of the sealing mold 3. In Modification 2-1, oxide film 23a is formed on the front, back, and side surfaces of the main current lead frame 21.

[0090] Next, an indentation formation process (step S4 in Figure 5) is performed in which an indentation is formed by pressing with a pressure pin and maintaining the pressure of the applied pressure pin. In modified example 2-1, insertion holes for the pressure pin 4 are formed in both the lower mold 3a and the upper mold 3b of the sealing mold 3. Using such a sealing mold 3, the pressure pin 4 is pressed against at least one of the front and back surfaces of the die pad portions 21a4 to 21d4. Figure 21 shows the case where the pressure pin 4 is pressed against both the front and back surfaces of the die pad portion 21c4, forming indentation regions 23a1 and 23a2, respectively.

[0091] Next, a sealing process (step S5 in Figure 5) is performed in which a sealing member is filled into the cavity 3c of the sealing mold 3 to seal the inside of the cavity 3c. After filling the cavity 3c of the sealing mold 3 with the sealing member 30c, before the sealing member 30c completely solidifies, the pressing pins 4 on the front and back surfaces are separated in the direction away from the die pad portions 21a4 to 21d4 (±Z direction) and maintained in that position. As a result, the sealing member 30c, which has not yet completely solidified, enters the indentation regions 23a1 and 23a2 after the pressing surface 4a has been removed. In the indentation regions 23a1 and 23a2 after the pressing surface 4a has been removed, the oxide film 23a is crushed, and the die pad portions 21a4 to 21d4 (shown as die pad portion 21c4 in Figure 21) are exposed through the gaps in the oxide film 23a. The sealing member 30c that enters the indentation regions 23a1 and 23a2 further flows into the die pad portions 21a4 to 21d4 (shown as die pad portion 21c4 in Figure 21) through the gaps in the oxide film 23a.

[0092] The pressure pin 4, which is maintained in a position separated from the die pad portions 21a4~21d4 (shown as die pad portion 21c4 in Figure 21), is completely removed from the sealing mold 3 after the sealing member 30c has almost solidified. As a result, depressions 30b are formed on the upper and lower parts of the sealing member 30c, directly facing the indentation regions 23a1 and 23a2, respectively. In this case as well, the arithmetic mean roughness of the bottom surface of the depression 30b is the same as or smaller than the arithmetic mean roughness of the pressing surface 4a of the pressure pin 4. Furthermore, the arithmetic mean roughness of the oxide film 23a in the indentation regions 23a1 and 23a2 is also the same as or smaller than the arithmetic mean roughness of the pressing surface 4a of the pressure pin 4.

[0093] Subsequently, after going through the process of step S6 in Figure 5, the semiconductor device 1b shown in Figure 21 is obtained. In this semiconductor device 1b, as with semiconductor device 1, the upper surface 31 and lower surface 32 of the sealant 30 that are directly facing the front and back surfaces of the die pad portions 21a4 to 21d4 of the sealant 30 include recesses 30b that are directly facing the indentation regions 23a1 and 23a2. This improves the adhesion between the sealant 30 and the indentation regions 23a1 and 23a2 of the die pad portions 21a4 to 21d4. Furthermore, the thickness of the sealant 30 on the indentation regions 23a1 and 23a2 is thinner than other parts because the recesses 30b are formed. Therefore, delamination of the sealant 30 in the indentation regions 23a1 and 23a2 is prevented. As a result, when the extension of delamination passes through the indentation regions 23a1 and 23a2, the extension of delamination is suppressed by the indentation regions 23a1 and 23a2. The peeling of the encapsulant 30 around the semiconductor chip 10 is suppressed. As a result, the decrease in the reliability of the semiconductor device 1b is suppressed. [Explanation of Symbols]

[0094] 1 Semiconductor device 2 Semiconductor Assembly 3 Sealing mold 3a Lower mold 3b Upper mold 3c cavity 4. Pressing pin 4a Pressing surface 10 Semiconductor Chips 10a Control electrode 10b Output electrode 11 Control ICs 21, 21a, 21b, 21c, 21d, 21e, 21f, 21g Main current lead frames 21a1,21b1,21c1,21d1 Joint 21a2, 21b2, 21c2, 21d2 Linkage section 21a3,21b3,21c3,21d3 Terminal section 21a4, 21b4, 21c4, 21d4 Die pad section 22, 22a, 22b, 22c Control lead frames 22b1, 22c1 Control die pad section 22b2, 22c2 Linkage section 22b3, 22c3, 22c4 Terminal section 23a, 23b Acidification film 23a1, 23a2 Pressure Mark Domain 24a,24b ワイヤ 25 metal circuit board 26a, 26b, 26c, 26d, 26e patch panels 26e1,26e2,26e3,26e4 26e5, 26e6, 26e7, 26e8 Corners 27. Insulation Layer 28 Heat dissipation plate 30 sealing bodies 30a Connecting pore 30b Depression 30c sealing components 31 Above 32 Below 33,35 Long side 34, 36 Short side

Claims

1. Semiconductor chips and A conductive plate on which the semiconductor chip is bonded to the front surface, A sealing member for sealing the semiconductor chip and the conductive plate, Includes, The front surface of the conductive plate includes an indentation region that is rougher than other regions. The sealing surface of the conductive plate of the sealing member facing the front surface includes a recess that directly faces the indentation region. Semiconductor equipment.

2. The conductive plate has an oxide film on its surface excluding the semiconductor chip, and the indentation region of the conductive plate is exposed from the oxide film. The semiconductor device according to claim 1.

3. The conductive plate includes at least one indentation region near the corner of the semiconductor chip facing the corner of the conductive plate. The semiconductor device according to claim 2.

4. The indentation region is included in the peripheral edge of the front surface of the conductive plate, The semiconductor device according to claim 3.

5. The arithmetic mean roughness of the indentation region is half the thickness of the oxide film. The semiconductor device according to any one of claims 2 to 4.

6. The conductive plate is a wiring board included in the substrate, The front surface of the wiring board is on which the semiconductor chip is bonded. The semiconductor device according to any one of claims 2 to 5.

7. The front surface of the wiring board includes the indentation region, The indentation region contains the oxide film. The semiconductor device according to claim 6.

8. The substrate further includes an insulating plate on which the wiring board is formed. The semiconductor device according to claim 6 or 7.

9. The front surface of the insulating plate includes the indentation region, The indented region of the insulating plate contains the oxide film. The semiconductor device according to claim 8.

10. The conductive plate is a die pad portion included in the lead frame, The front surface of the die pad portion is on which the semiconductor chip is bonded. The semiconductor device according to any one of claims 1 to 5.

11. The front surface of the lead frame is a single plane, and is spaced apart from the sealing back surface of the sealing member toward the sealing front surface. At least one of the front and back surfaces of the die pad portion includes the indentation region. If the back surface of the die pad portion includes the indentation region, the sealing back surface of the sealing member includes the recess directly opposite the indentation region on the back surface. The semiconductor device according to claim 10.

12. Preparation steps include preparing a mold containing a semiconductor chip, a conductive plate, a pressing pin with a roughened pressing surface at its tip, a sealing member, and a cavity inside, A mold setting step in which the conductive plate on which the semiconductor chip is arranged is set in the cavity of the mold, An indentation forming step of pressing the front surface of the conductive plate with the pressing surface of the pressing pin within the cavity to form an indentation region on the front surface of the conductive plate that is rougher than other regions, A sealing step in which the sealing member is filled into the cavity while the conductive plate is pressed with the pressing surface, and when the cavity is sealed with the sealing member, the pressing pin is moved away in a direction substantially perpendicular to the front surface of the conductive plate, A recess forming step involves maintaining the pressing pin in a position away from the conductive plate, removing the sealing member before it has completely solidified, and forming a recess on the sealing surface of the sealing member that faces the front surface of the conductive plate, and which is directly opposite the indentation region. A method for manufacturing a semiconductor device containing [a specific component].

13. The surface roughness of the indentation region formed in the indentation forming step is smaller than the surface roughness of the pressing surface of the pressing pin. The method for manufacturing a semiconductor device according to claim 12.

14. In the mold setting process, The mold is preheated. The conductive plate set in the mold is heated so that an oxide film is formed on the surface of the conductive plate, excluding the semiconductor chip. A method for manufacturing a semiconductor device according to claim 12 or 13.

15. In the indentation formation step, The pressing surface of the pressing pin crushes the oxide film on the conductive plate, thereby forming the indentation region on the conductive plate. The method for manufacturing a semiconductor device according to claim 14.

16. In the indentation formation step, The conductive plate has the indentation region formed near at least one corner of the semiconductor chip facing the corner of the conductive plate. The method for manufacturing a semiconductor device according to claim 15.

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