Method for manufacturing high electron mobility transistors with improved performance

Abstract

A method of forming a high electron mobility transistor (HEMT) includes providing a semiconductor structure including a channel layer and a barrier layer stacked in sequence on a substrate, forming a first insulating layer on the barrier layer, and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer includes a modified interface region on the drain access region and / or the source access region such that the sheet resistivity of the drain access region and / or the source access region of the semiconductor structure is between 300 and 400 ohms / sq.

Description

[Technical Field]

[0001] Claim of priority This application claims priority to U.S. Patent Application No. 17 / 325,628, filed on 20 May 2021, whose entire disclosure is incorporated herein by reference.

[0002] The concepts of the present invention described herein relate to semiconductor devices, and more particularly to high electron-mobility transistors. [Background technology]

[0003] Electrical circuits that require high power handling capabilities while operating at high frequencies such as the R band (0.5~1GHz), S band (3GHz), X band (10GHz), Ku band (12~18GHz), K band (18~27GHz), Ka band (27~40GHz), and V band (40~75GHz) are becoming increasingly common. In particular, there is currently a high demand for RF transistor amplifiers used to amplify RF signals at frequencies above 500MHz (including microwave frequencies). These RF transistor amplifiers often need to exhibit high reliability, good linearity, and handle high output power levels.

[0004] RF transistor amplifiers can be implemented in silicon or in wide-bandgap semiconductor materials such as silicon carbide ("SiC") and Group III nitride materials. In this specification, the term "wide-bandgap" refers to semiconductor materials having a bandgap greater than 1.40 eV. As used herein, the term "Group III nitride" refers to semiconductor compounds formed between nitrogen and Group III elements of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). This term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have empirical formulas in which 1 mole of nitrogen is combined with a total of 1 mole of Group III elements.

[0005] Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors. Silicon LDMOS RF transistor amplifiers can exhibit a high level of linearity and can be manufactured relatively inexpensively. Group-III nitride-based RF transistor amplifiers are typically implemented as high electron mobility transistors (HEMTs) mainly in applications that require high output and / or high-frequency operation where LDMOS RF transistor amplifiers may have inherent performance limitations.

[0006] HEMT devices can offer operational advantages in some applications. During operation, a two-dimensional electron gas (2DEG) is formed within the HEMT device at the hetero-junction of two semiconductor materials having different bandgap energies, with the smaller bandgap material having a higher electron affinity. The 2DEG is an accumulation layer within the smaller bandgap material and can contain a very high sheet electron concentration. Further, electrons from the wider bandgap semiconductor material move to the 2DEG layer, enabling high electron mobility due to reduced ionized impurity scattering. This combination of high carrier concentration and high carrier mobility can give the HEMT a very large transconductance and can provide performance advantages over metal oxide semiconductor field effect transistors (MOSFETs) for high-frequency applications.

[0007] High electron mobility transistors fabricated from Group-III nitride-based material systems have the potential to generate large amounts of radio frequency (RF) power due to a combination of material properties including the aforementioned high breakdown field, wide bandgap, large conduction band offset, and / or high saturated electron drift velocity.

[0008] Therefore, HEMT devices can be advantageously used in power amplifiers (PAs). Power amplifiers that include power amplifiers using HEMT devices often suffer from a trade-off between output power and bandwidth. Internal inefficiencies such as parasitic capacitance can affect the switching speed of the device. Smaller transistor geometries can achieve higher operating frequencies, but smaller dimensions can result in reduced current (and power) capacity. Improving the operating characteristics of the amplifier can help to efficiently use the available bandwidth.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

[0010] The embodiments described herein provide improved HEMT devices and methods for forming improved power amplifiers including such HEMT devices.

[0011] According to some embodiments of the present disclosure, a method for forming a high electron mobility transistor (HEMT) includes providing a semiconductor structure including a channel layer and a barrier layer sequentially stacked on a substrate, forming a first insulating layer on the barrier layer, and forming a gate contact, a source contact, and a drain contact on the barrier layer. The interface between the first insulating layer and the barrier layer includes a modified interface region on the drain access region and / or source access region such that the sheet tolerance of the drain access region and / or source access region of the semiconductor structure is between 300 and 400 ω / sq.

[0012] In some embodiments, the bottom surface of the gate contact is offset laterally by 10 to 400 nm from the modified interface region.

[0013] In some embodiments, forming a first insulating layer on top of a barrier layer involves the use of physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), and / or pyrolysis deposition.

[0014] In some embodiments, the method further includes wet etching the upper surface of the barrier layer in an acidic and / or basic chemical bath before forming the first insulating layer.

[0015] In some embodiments, the method further includes ion bombarding the barrier layer, plasma nitriding the barrier layer, plasma oxidation of the barrier layer, H2 plasma treatment of the barrier layer, and / or annealing the barrier layer in a gaseous environment, before forming the first insulating layer.

[0016] In some embodiments, the method further includes forming a spacer between the modified interface region and the gate contact.

[0017] In some embodiments, forming a spacer includes etching a hole in a first insulating layer and forming a spacer on the sidewall of the hole and on the barrier layer, and forming a gate contact includes forming at least a portion of a gate contact on the sidewall of the spacer in the hole.

[0018] In some embodiments, the interface between the spacer and the barrier layer includes interface characteristics different from those of the modified interface region.

[0019] According to some embodiments of the present disclosure, a method for forming a high electron mobility transistor (HEMT) includes providing a semiconductor structure including a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; forming a gate contact on the barrier layer, wherein at least a portion of the gate contact is located within the first insulating layer; and providing a modified interface region between the first insulating layer and the barrier layer, spaced laterally from the bottom surface of the gate contact.

[0020] In some embodiments, the modified interface region is spaced 10 to 400 nm laterally from the bottom surface of the gate contact.

[0021] In some embodiments, the method further includes etching a hole in a first insulating layer and forming a spacer on the sidewall of the hole and on the barrier layer, and forming a gate contact further includes forming at least a portion of the gate contact on the sidewall of the spacer in the hole.

[0022] In some embodiments, the interface between the spacer and the barrier layer contains a different trap concentration than the modified interface region.

[0023] In some embodiments, providing a modified interface region includes wet etching of the upper surface of the barrier layer in an acidic and / or basic chemical bath, ion bombardment of the barrier layer, plasma nitriding of the barrier layer, plasma oxidation of the barrier layer, H2 plasma treatment of the barrier layer, and / or annealing of the barrier layer in a gaseous environment, before forming the first insulating layer.

[0024] In some embodiments, the thickness of the first insulating layer is between 80 nm and 120 nm.

[0025] In some embodiments, the sheet resistance of the drain-access region and / or source-access region of the semiconductor structure beneath the modified interface region is between 300 and 400 Ω / sq.

[0026] According to some embodiments of the present disclosure, a method for forming a high electron mobility transistor (HEMT) includes providing a semiconductor structure on a substrate including a channel layer and a barrier layer on the channel layer, and forming a first insulating layer on the barrier layer, wherein the first insulating layer includes a modified interface region at the interface between the first insulating layer and the barrier layer, forming a spacer on the barrier layer at an opening in the first insulating layer, and forming a gate contact on the barrier layer and the spacer at an opening in the first insulating layer.

[0027] In some embodiments, the method further includes thinning the substrate.

[0028] In some embodiments, the bottom corners of the gate contact are offset from the modified interface region by spacers.

[0029] In some embodiments, the thickness of the first insulating layer is between 80 nm and 120 nm.

[0030] In some embodiments, the width of the bottom surface of the spacer adjacent to the barrier layer is 10 to 400 nm.

[0031] In some embodiments, forming a first insulating layer including a modified interface region includes wet etching of the upper surface of the barrier layer in an acidic and / or basic chemical bath, buffer red oxide etching (BOE) of the upper surface of the barrier layer, ion bombardment of the barrier layer, plasma nitriding of the barrier layer, plasma oxidation of the barrier layer, H2 plasma treatment of the barrier layer, and / or annealing of the barrier layer in a gaseous environment, and depositing a protective layer on the barrier layer.

[0032] In some embodiments, the interface between the spacer and the barrier layer has a trap concentration and / or surface potential different from that of the modified interface region. [Brief explanation of the drawing]

[0033] [Figure 1] This is a schematic plan view of a high electron mobility transistor according to an embodiment of the present disclosure. [Figure 2A] This is a schematic cross-sectional view obtained along line AA in Figure 1. [Figure 2B] This is a detailed cross-sectional view of area A in Figure 2A. [Figure 2C] This is a detailed cross-sectional view of area A in Figure 2A. [Figure 3A] This is a graph of the power density characteristics of the devices according to the embodiments described herein. [Figure 3B] This is a graph of the power added efficiency (PAE) of the devices according to the embodiments described herein. [Figure 3C] This is a graph of the drain efficiency characteristics of the devices according to the examples described herein. [Figure 4A] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4B]This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4C] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4D] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4E] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4F] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4G] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4H] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4I] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4J] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4K] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4L] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4M] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4N] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4O] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4P] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 4Q] This is a schematic cross-sectional view taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device according to an embodiment of the present disclosure. [Figure 5A] This schematic cross-sectional view shows several exemplary methods of packaging the HEMT device according to embodiments of the present disclosure to provide a packaged RF transistor amplifier. [Figure 5B] This schematic cross-sectional view shows several exemplary methods of packaging the HEMT device according to embodiments of the present disclosure to provide a packaged RF transistor amplifier. [Figure 5C] This schematic cross-sectional view shows several exemplary methods of packaging the HEMT device according to embodiments of the present disclosure to provide a packaged RF transistor amplifier. [Modes for carrying out the invention]

[0034] Embodiments of the concepts of the present invention are described in detail below with reference to the accompanying drawings illustrating embodiments of the present invention. However, these concepts of the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so as to convey to those skilled in the art that this disclosure is thorough and complete and that the scope of the concepts of the present invention is fully understood. Throughout, similar numbers refer to similar elements.

[0035] The embodiments of this disclosure relate to high electron-mobility transistors that may exhibit improved performance. In some embodiments, treatments are provided at the interface between the protective layer and the barrier layer in the source and drain access regions of the HEMT device to improve the interface condition between the barrier layer and the protective layer in these regions. The interface treatment may be offset from the gate of the device to further reduce the leakage current of the device and improve the breakdown performance. In some embodiments, the method for manufacturing the device may self-align the gate and the gate offset between the source and drain regions having the interface treatment.

[0036] Figure 1 is a schematic plan view of a HEMT device 300 according to an embodiment of the present disclosure. Figure 2A is a schematic cross-sectional view of the HEMT device 300 taken along line AA in Figure 1. Figures 2B and 2C are detailed cross-sectional views of area A in Figure 2A. Figures 1 and 2A-2C are intended to represent structures for identification and illustrative purposes and are not intended to represent structures to a physical scale.

[0037] Referring to Figures 1 and 2A to 2C, the semiconductor structure 390, such as a semiconductor structure of a group III nitride semiconductor HEMT, can be formed on a substrate 322 such as a silicon carbide (SiC) substrate or a sapphire substrate. The substrate 322 can be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, a 4H polytype of silicon carbide. Other candidate silicon carbide polytypes may include the 3C, 6H, and 15R polytypes. The substrate may also be a high-purity semi-insulating (HPSI) substrate available from Cree, Inc. The term "semi-insulating" is used descriptively in this specification and is not in an absolute sense.

[0038] In some embodiments, the silicon carbide bulk crystal of substrate 322 is approximately 1 × 10⁶ at room temperature. 5It may have a resistivity of ohms·cm or greater. Exemplary SiC substrates that can be used in some embodiments of this disclosure were manufactured, for example, by Cree, Inc. of Durham, North Carolina, the assignee of this disclosure, and methods for manufacturing such substrates are described, for example, in U.S. Reissue Patent No. 34,861, U.S. Patent No. 4,946,547, U.S. Patent No. 5,200,022, and U.S. Patent No. 6,218,680, which are incorporated herein by reference in their entirety. Although silicon carbide can be used as a substrate material, embodiments of this disclosure can utilize any suitable substrate such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, and indium phosphide (InP). The substrate 322 may be a silicon carbide wafer, and the HEMT device 300 may be formed at least partially by wafer-level processing, and the wafer may then be diced to provide a plurality of individual high electron mobility transistors 300.

[0039] The substrate 322 may have a lower surface 322A and an upper surface 322B. In some embodiments, the substrate 322 of the HEMT device 300 may be a thin substrate 322. In some embodiments, the thickness of the substrate 322 (for example, in the vertical Z direction in Figure 2B) may be 100 μm or less. In some embodiments, the thickness of the substrate 322 may be 75 μm or less. In some embodiments, the thickness of the substrate 322 may be 50 μm or less.

[0040] The channel layer 324 is formed on the upper surface 322B of the substrate 322 (or on an optional layer as further described herein), and the barrier layer 326 is formed on the upper surface of the channel layer 324. The channel layer 324 and the barrier layer 326 may each be formed by epitaxial growth in some embodiments. Techniques for epitaxial growth of group III nitrides are described, for example, in U.S. Patents 5,210,051, 5,393,993 and 5,523,589, which are also incorporated herein by reference in their entirety. The channel layer 324 may have a band gap smaller than that of the barrier layer 326, and the channel layer 324 may also have a greater electron affinity than that of the barrier layer 326. The channel layer 324 and the barrier layer 326 may include group III nitride-based materials. In some embodiments, the wafer thickness T W The thickness of the substrate 322, channel layer 324, and barrier layer 326 (for example) may be between 40 μm and about 100 μm. In some embodiments, the wafer thickness T W The wafer thickness T may be between 40 μm and approximately 80 μm. In some embodiments, the wafer thickness T W The wafer thickness T may be approximately 75 μm. W Reducing the cross-sectional area (A2) of the via 325 can enable the formation of vias 325 with smaller cross-sections, which can reduce the overall size of the device 300 and lower the inductance. In some embodiments, the maximum cross-sectional area A2 of the via 325 is 1000 μm² or less.

[0041] In some embodiments, the channel layer 324 is configured such that the energy at the conduction band end of the channel layer 324 is less than the energy at the conduction band end of the barrier layer 326 at the interface between the channel layer 324 and the barrier layer 326. x Ga 1-xIt can be a group-III nitride such as N(0≦x<1). In some embodiments of the present disclosure, x = 0, indicating that the channel layer 324 is GaN. The channel layer 324 may also be other group-III nitrides such as InGaN and AlInGaN. The channel layer 324 may not be doped (``unintentionally doped'') and may be grown to a thickness exceeding about 0.002 μm. The channel layer 324 may also be a multilayer structure such as a superlattice or a combination of GaN, AlGaN, etc. In some embodiments, the channel layer 324 may be under compressive strain.

[0042] In some embodiments, the barrier layer 326 is AlN, AlInN, AlGaN, or AlInGaN or a combination of those layers. The barrier layer 326 may include a single layer or may be a multilayer structure. In some embodiments, the barrier layer 326 may be a thin AlN layer directly above the channel layer 324 and a single or multiple AlGaN layers thereon. In a particular embodiment of the present disclosure, the barrier layer 326 has a sufficient thickness, a sufficiently high aluminum (Al) composition and doping to induce a significant carrier concentration at the interface between the channel layer 324 and the barrier layer 326 by the polarization effect when the barrier layer 326 is embedded under the ohmic contact metal. The barrier layer 326 may have a thickness, for example, from about 0.1 nm to about 30 nm, but not so thick as to cause cracking or large defects therein. In some embodiments, the thickness of the barrier layer is 13 - 18 nm. In some embodiments, the barrier layer 326 is not doped or doped to a concentration less than about 10 19 cm -3 −. In some embodiments, the barrier layer 326 is Al x Ga 1-xN is between 0 and 1 (0 < x < 1). In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present disclosure, the barrier layer 326 includes AlGaN having an aluminum concentration between about 5% and less than about 100%. In certain embodiments of the present disclosure, the aluminum concentration is greater than about 10%. The channel layer 324 and / or the barrier layer 326 can be deposited, for example, by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). As discussed herein, the 2DEG layer is induced within the channel layer 324 at the junction between the channel layer 324 and the barrier layer 326. The 2DEG layer functions as a highly conductive layer that enables conduction between the source region and the drain region of the device, and is beneath each of the source contact 315 and the drain contact 305. The channel layer 324 and the barrier layer 326 form a semiconductor structure 390.

[0043] Although the semiconductor structure 390 is shown together with the channel layer 324 and the barrier layer 326 for illustrative purposes, the semiconductor structure 390 may include additional layers / structures / elements, such as a buffer layer and / or nucleation layer between the channel layer 324 and the substrate 322, and / or a capping layer on the barrier layer 326. HEMT structures including the substrate, channel layer, barrier layer, and other layers are described, for example, in U.S. Patents 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774 and 7,709,269, the disclosures of which are incorporated herein by reference in their entirety. For example, an AlN buffer layer may be formed on the upper surface 322B of the substrate 322 to introduce a suitable crystal structure phase transition between the silicon carbide substrate 322 and the rest of the HEMT device 300. Furthermore, a strain balancing transition layer may be provided, for example, as described in U.S. Patent No. 7,030,428, assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference as if it were fully described herein. Optional buffer layers / nucleation layers / transition layers may be deposited by MOCVD, MBE, and / or HVPE.

[0044] The source contact 315 and drain contact 305 may be formed on the upper surface 326A of the barrier layer 326, or they may be spaced laterally apart from each other. The gate contact 310 may be formed on the upper surface 326A of the barrier layer 326 between the source contact 315 and the drain contact 305. The material of the gate contact 310 may be selected based on the composition of the barrier layer 326, and in some embodiments, it may be a Schottky contact. For example, nickel (Ni), platinum (Pt), nickel silicide (NiSi xConventional materials capable of forming Schottky contacts in gallium nitride-based semiconductor materials such as copper (Cu), palladium (Pd), chromium (Cr), tungsten (W), and / or tungsten silicon nitride (WSiN) may be used.

[0045] The source contact 315 and drain contact 305 may contain metals capable of forming ohmic contacts with gallium nitride-based semiconductor materials. Suitable metals include Ti, W, titanium-tungsten (TiW), silicon (Si), titanium-tungsten nitride (TiWN), tungsten silide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), and NiSi. x This may include heat-resistant metals such as titanium silicide (TiSi), titanium nitride (TiN), WSiN, and Pt. In some embodiments, the source contact 315 may be an ohmic source contact 315. Thus, the source contact 315 and the drain contact 305 may include ohmic contact portions that are in direct contact with the barrier layer 326. In some embodiments, the source contact 315 and / or the drain contact 305 may be formed from multiple layers to form an ohmic contact, which may be provided as described, for example, in U.S. Patent Nos. 8,563,372 and U.S. Patent No. 9,214,352, which have been assigned to the assignees of the present invention, and these disclosures are incorporated herein by reference in whole.

[0046] The source contact 315 can be coupled to a reference signal, such as a ground voltage. Coupling to the reference signal can be achieved by a via 325 extending from the bottom surface 322A of the substrate 322 through the substrate 322 to the top surface 326A of the barrier layer. The via 325 may expose the bottom surface of the ohmic portion 315A of the source contact 315. A back metal layer 335 may be formed on the bottom surface 322A of the substrate 322 and on the sidewall of the via 325. The back metal layer 335 may be in direct contact with the ohmic portion 315A of the source contact 315. In some embodiments, the contact area between the back metal layer 335 and the bottom surface of the ohmic portion 315A of the source contact 315 may be 50 percent or more of the area of ​​the bottom surface of the ohmic portion 315A of the source contact 315. Thus, the back metal layer 335 and the signal coupled to it can be electrically connected to the source contact 315.

[0047] In some embodiments, the source contact 315, drain contact 305, and gate contact 310 may be formed as a plurality of source contacts 315, drain contacts 305, and gate contacts 310 on the substrate 322. Referring to Figure 1, the plurality of drain contacts 305 and source contacts 315 may be arranged alternately on the substrate 322. The gate contacts 310 may be positioned between adjacent drain contacts 305 and source contacts 315 to form a plurality of transistor unit cells, examples of which are shown as 300_A and 300_B in Figure 1. Each of the transistor unit cells 300_A and 300_B may include a source contact 315, a drain contact 305, and a gate contact 310. Figure 1 shows a subset of source contacts 315, drain contacts 305, and gate contacts 310 for ease of explanation, but it will be understood that the HEMT device 300 may have additional structures including additional source contacts 315, drain contacts 305, and gate contacts 310 not shown in Figure 1. As will be understood by those skilled in the art, the HEMT transistor may be formed by the active region between the source contacts 315 and drain contacts 305, under the control of the gate contacts 310 between the source contacts 315 and drain contacts 305.

[0048] Referring to Figure 2B, the first insulating layer 350 may be formed on the barrier layer 326, and the second insulating layer 355 may be formed on the first insulating layer 350. The thickness ID1 of the first insulating layer 350 may be between 80 nm and 120 nm. In some embodiments, the thickness ID1 of the first insulating layer 350 may be about 100 nm. In some embodiments, the first insulating layer 350 is silicon nitride (Si x N y), aluminum nitride (AlN), silicon dioxide (SiO2), and / or other suitable protective materials may be included. The thickness ID2 of the second insulating layer 355 may be between 190 nm and 230 nm. In some embodiments, the thickness ID2 of the second insulating layer 355 may be about 210 nm. In some embodiments, the first insulating layer 350 and the second insulating layer 355 may have a combined thickness of about 310 nm. The thickness of the first insulating layer 350 may affect the gate-source capacitance and gate-drain capacitance, which may affect the switching speed of the device 300. Similarly, the thickness of the second insulating layer 355 may affect the gate-drain capacitance, which may affect the switching speed and gain of the device 300.

[0049] The gate contact 310 may be formed within the first insulating layer 350, and a portion of the gate contact 310 may lie beneath the second insulating layer 355. It will be understood that the present invention is not limited to the specific shape of the gate contact 310 shown in Figures 2A and 2B, and that other shapes of the gate contact 310 and other elements of the device 300 are possible without departing from the embodiments described herein.

[0050] The gate contact 310 may include a first portion 310_1 in the first insulating layer 350 and a second portion 310_2 in the second insulating layer 355 above the first portion 310_1. The width of the second portion 310_2 of the gate contact 310 may exceed the width of the first portion 310_1. In some embodiments, the second portion 310_2 of the gate contact 310 may extend beyond one or more sidewalls of the first portion 310_1 of the gate contact 310 so that the gate contact 310 forms a T-gate and / or gamma gate. On the drain side of the gate contact 310, the second portion 310_2 of the gate contact 310 extends a first distance Γ toward the drain contact 305 beyond the sidewall of the first portion 310_1 of the gate contact 310. D It can only extend up to this distance Γ. DThis may be between 0.05 μm and 0.15 μm. In some examples, Γ D This may be approximately 0.1 μm. On the source side of the gate contact 310, the second portion 310_2 of the gate contact 310 extends a second distance Γ toward the source contact 315, beyond the side wall of the first portion 310_1 of the gate contact 310. S It can only extend up to this distance Γ. S This may be between 0.05 μm and 0.15 μm. In some examples, Γ S This may be approximately 0.1 μm. First distance Γ D This may affect the gate-drain capacitance of device 300, which may affect the switching speed and gain of device 300. Second distance Γ S This may affect the gate-source capacitance of device 300, which could affect the switching speed of device 300.

[0051] The first portion 310_1 of the gate contact 310 may include the lower surface 310A adjacent to the barrier layer 326. (See Figure 2A) G As shown, the length of the lower surface 310A of the gate contact 310 may be between 50 nm and 400 nm. In some embodiments, L G L may be between 120 nm and 180 nm. In some embodiments, L G It may be approximately 150 nm. Length L G L may represent the length of the interface between the gate contact 310 and the barrier layer 326. G This may affect the transconductance and gate parasitic capacitance, which can impact the switching and efficiency of device 300. The side and / or end of the lower surface 310A of the gate contact 310 closest to the drain contact 305 is at a distance L from the end of the drain contact 305 (e.g., the nearest end), as shown in Figure 2A. GD Only the distance L between the lower surface 310A of the gate contact 310 and the drain contact 305 can be separated. GDL may be between 1.75 μm and 2.25 μm. In some examples, L GD The thickness may be approximately 1.98 μm. The side and / or end of the lower surface 310A of the gate contact 310 closest to the source contact 315 is shown in Figure 2A As shown, the distance L from the end of the source contact 315 (for example, the nearest end) is GS Only the distance L between the lower surface 310A of the gate contact 310 and the source contact 315 can be separated. GS L may be between 0.5 μm and 0.7 μm. In some examples, L GS The distance L may be approximately 0.6 μm. GD and L GS This may contribute to the on-resistance of device 300, which may affect device efficiency. In some embodiments, the gate contact 310 may be closer to the source contact 315 than to the drain contact 305.

[0052] The source contact 315, drain contact 305, and gate contact 310 may be formed within the first insulating layer 350. In some embodiments, at least a portion of the gate contact 310 may be on the first insulating layer. In some embodiments, the gate contact 310 may be formed as a T-gate and / or gamma gate, the formation of which is described, in practical examples, in U.S. Patents 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are incorporated herein by reference in their entirety. The second insulating layer 355 may be formed on the first insulating layer 350, as well as on portions of the drain contact 305, gate contact 310, and source contact 315.

[0053] The interface between the first insulating layer 350 and the barrier layer 326 may include physical properties as a result of interface treatments and / or processes used to improve the quality of the interface. The source access region (SAR) of device 300 may include a portion of the semiconductor structure 390 between the gate contact 310 and the source contact 315. Similarly, the drain access region (DAR) of device 300 may include a portion of the semiconductor structure 390 between the gate contact 310 and the drain contact 305. As will be further discussed herein, a modified interface region 375 may be provided in part within and / or on the source and drain access regions (SAR, DAR) to provide non-uniform variations in conductivity, trap concentration, sheet resistance, and / or surface potential in the lateral direction (e.g., the X direction in Figure 2A and / or the direction parallel to the upper surface 326A of the barrier layer 326) between the gate contact 310 and the drain contact 305 (or source contact 315). In some embodiments, the modified interface region 375 may include physical modifications to the interface between the first insulating layer 350 and the barrier layer 326 to, for example, reduce trap concentration or otherwise improve the electrical properties of the interface. Modifications to the interface between the first insulating layer 350 and the barrier layer 326 may affect areas within and / or around the interface. In addition, modifications to the interface between the first insulating layer 350 and the barrier layer 326 may also affect the 2DEG occurring in the channel layer 324 at the junction between the channel layer 324 and the barrier layer 326. For example, as a result of the modified interface region 375, the sheet resistance of the source access region SAR and / or drain access region DAR of the device 300 (e.g., the device 2DEG channel occurring in the channel layer 324 at the junction between the channel layer 324 and the barrier layer 326) may be between 300 and 400 Ω / sq.

[0054] Referring to Figure 2B, the modified interface region 375 is offset from the lower surface 310A of the gate contact 310 by an offset distance O GIt can be separated (for example, offset laterally). In other words, the modified interface region 375 is offset from the lower surface 310A of the gate contact 310. G Within this range, it can be eliminated from the interface between the first insulating layer 350 and the barrier layer 326. Offset O G The wavelength may range from 10 nm to 400 nm. The presence of the modified interface region 375 can improve the conductivity and / or sheet resistance of the active region of device 300 to improve device performance. However, the same properties that can improve device performance when present in the source access region SAR and / or drain access region DAR may result in the presence of leakage current if it is placed too close to the gate contact 310. Increased leakage current may reduce the breakdown performance and / or reliability of device 300. The modified interface region 375 is offset from the lower surface 310A of the gate contact 310. G By separating them only by a small amount, device 300 can have the advantages of improved source and drain access areas (SAR, DAR) while avoiding increased leakage current. Modified interface area 375 and offset O G Methods for providing this will be discussed further herein.

[0055] In some embodiments, the area between the modified interface region 375 and the gate contact 310 (for example, offset O from the gate contact 310) G The interface area between the first insulating layer 350 and the barrier layer 326 within the specified area may be free of interface modification, or may have different interface modification than the modified interface area 375. In other words, the interface modification performed between the first insulating layer 350 and the barrier layer 326 adjacent to the gate contact 310 may be different from the modified interface area 375 over the drain access area DAR and / or source access area SAR.

[0056] As will be further discussed herein, in some embodiments, the offset O from the gate contact 310G The spacer may be provided by a spacer 485. Such an embodiment is shown in Figure 2C. As shown in Figure 2C, the spacer 485 may be located between the first insulating layer 350 and the bottom surface and / or bottom corner of the gate contact 310. The spacer 485 may be formed from the same material as the first insulating layer 350, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the spacer 485 may be formed from a different material than the material of the first insulating layer 350. However, even if formed from the same material, an interface 485I may exist between the first insulating layer 350 and the spacer 485 (for example, as a result of the process used to form the spacer 485). As discussed above, in some embodiments, the spacer 485 may have its own interface modification between the spacer 485 and the barrier layer 326. In some embodiments, the interface modification between the spacer 485 and the barrier layer 326 may be different from the modified interface region 375 between the first insulating layer 350 and the barrier layer 326. For example, in some embodiments, the trap concentration at the interface between the spacer 485 and the barrier layer 326 may be different from the trap concentration at the interface between the first insulating layer 350 and the barrier layer 326.

[0057] In some embodiments, the gate contact 310 may self-align within the modified interface region 375. In other words, the gate contact 310 is self-aligned within the device 3 0 Offset O between the gate contact 310 and the modified interface region 375 on the drain side of 0 G However, device 3 0 Offset O between the gate contact 310 and the modified interface region 375 on the source side of 0 G It may be positioned to be substantially the same as. In some embodiments, the O provided by the self-alignment of the gate contact 310 GThe symmetrical spacing can enable the use of the reduced and / or minimal distance between the modified interface region 375 and the gate contact 310, which allows for an increase and / or maximization of the percentage of channels having a modified interface state.

[0058] Referring again to Figure 2A, the field plate 360 ​​may be formed on the second insulating layer 355. At least a portion of the field plate 360 ​​may be on the gate contact 310. At least a portion of the field plate 360 ​​may be on a portion of the second insulating layer 355 between the gate contact 310 and the drain contact 305. The field plate 360 ​​can reduce the peak electric field of the HEMT device 300, which may result in an increase in breakdown voltage and a reduction in charge trap. The reduction in the electric field may also result in other benefits such as a reduction in leakage current and an improvement in reliability. Field plates and techniques for forming field plates are described as examples in U.S. Patent No. 8,120,064, the disclosure of which is incorporated herein by reference in its entirety.

[0059] On the drain side of the gate contact 310, the field plate 360 ​​extends a distance L from the side wall of the second portion 310_2 of the gate contact 310 toward the drain contact 305, as shown in Figure 2A. F2 It can extend only by a certain distance L. In some embodiments, the distance L F2 This distance L may refer to the distance over which the field plate 360 ​​extends beyond the outermost part of the second portion 310_2 of the gate contact 310 that is closest to the drain contact 305. F2 L may be between 0.3 μm and 0.5 μm. In some examples, L F2 The thickness may be approximately 0.4 μm. The extension distance L of the field plate 360 ​​beyond the gate contact 310. F2This may affect the gate-source capacitance and breakdown voltage of device 300, which may affect the voltage rating and switching speed of device 300.

[0060] A metal contact 365 may be located within the second insulating layer 355. The metal contact 365 may provide interconnections between the drain contact 305, gate contact 310, and source contact 315 and other parts of the HEMT device 300. Each of the metal contacts 365 may be in direct contact with each of the drain contact 305 and / or source contact 315. The metal contacts 365 may include metal or other highly conductive materials, including, for example, copper, cobalt, gold, and / or composite metals. For ease of explanation, the second insulating layer 355, field plate 360, and metal contacts 365 are not shown in Figure 1.

[0061] One or more of the dimensions described with respect to Figures 1 and 2A to 2C may contribute to improvements in device 300. In some embodiments, the configuration of device 300 may enable the device to achieve performance and improvements beyond those of conventional devices. For example, embodiments described herein provide optically defined GaN HEMT technology of 200 nm or less (e.g., 120 nm to 200 nm) with improved RF and reliability performance. For example, embodiments provided herein may have an output power density of 4.6 W / mm or more at an operating frequency of 30 GHz. In some embodiments, the output power density at 30 GHz is between 4.6 W / mm and 4.8 W / mm. Embodiments provided herein may have a peak power added efficiency (PAE) greater than 33% at an operating frequency of 30 GHz. In some embodiments, the peak power added efficiency (PAE) at an operating frequency of 30 GHz may be between 33% and 38%.

[0062] Figure 3A is a graph of the power density characteristics of the device according to the embodiment described herein. Figure 3B is a graph of the power added efficiency (PAE) of the device according to the embodiment described herein. Figure 3C is a graph of the drain efficiency characteristics of the device according to the embodiment described herein.

[0063] Figure 3A shows the output power density of a sample of device 520 ("Improved Device") manufactured according to an embodiment of this disclosure, compared to a sample of the unimproved device 530 ("Related Device"). As shown in Figure 3A, the embodiment of this disclosure exhibits a significant improvement in power density, with sample 520 showing power density values ​​ranging from 4.6 to 4.8 W / mm, compared to sample 530 Related Device which has a maximum power density of approximately 4.3 W / mm. As shown in Figures 3B and 3C, a sample of device 520 ("Improved Device") manufactured according to an embodiment of this disclosure shows comparable PAE (Figure 3) and drain efficiency (Figure 3C) to a sample of the unimproved device 530 ("Related Device"). Thus, HEMT devices according to the embodiment of this disclosure can increase the output power density of the device while maintaining the device's PAE and drain efficiency. The embodiment of this disclosure can provide improved parasitic capacitance, trapping, and power density for high-frequency applications.

[0064] Figures 4A to 4Q are schematic cross-sectional views taken along line BB in Figure 1, illustrating a method for manufacturing a HEMT device, such as the HEMT device 300 in Figures 1 and 2A to 2C, according to embodiments of the present disclosure. In Figures 4A to 4Q, the process of forming the gate contact before the drain and source contacts is shown. This is done for a clearer explanation of the interface modification process and is not intended to limit the embodiments of the present disclosure. In some embodiments, the source and drain contacts may be manufactured first, before the formation of the gate contact.

[0065] Referring to Figure 4A, a substrate 122 is provided, and a semiconductor structure can be formed on the substrate 122. A channel layer 324 is formed on the substrate 122, and a barrier layer 326 is formed on the channel layer 324. The substrate 122 can be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, a 4H polytype of silicon carbide. Other candidate silicon carbide polytypes may include 3C, 6H, and 15R polytypes. The thickness of the substrate 122 may be 100 μm or more.

[0066] Silicon carbide has much closer crystal lattice matching to Group III nitrides (which can be used in channel layer 324 and / or barrier layer 326) than sapphire (Al2O3), which can be a common substrate material for Group III nitride devices. This closer lattice matching can result in higher quality Group III nitride films than those commonly available on sapphire. Silicon carbide also has relatively high thermal conductivity, and therefore the total output power of Group III nitride devices formed on silicon carbide may not be as limited by thermal dissipation of the substrate as similar devices formed on sapphire and / or silicon. Furthermore, semi-insulating silicon carbide substrates can provide device insulation and reduce parasitic capacitance.

[0067] While silicon carbide can be used as a substrate, it should be understood that the embodiments of the present invention can utilize any suitable substrate for substrate 122, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, and indium phosphide (InP).

[0068] Optional buffer layers, nucleation layers, and / or transition layers (not shown) can also be provided on the substrate 122. For example, an AlN buffer layer can be provided to offer a suitable crystal structure phase transition between the silicon carbide substrate and the rest of the device. Furthermore, a strain equilibrium phase transition layer may also be provided.

[0069] Referring further to Figure 4A, the channel layer 324 is provided on the substrate 122. The channel layer 324 may be deposited on the substrate 122 using a buffer layer, a transition layer, and / or a nucleation layer as described above. The channel layer 324 may be under compressive strain. Furthermore, the channel layer 324, and / or the buffer layer, nucleation layer, and / or transition layer, may be deposited by MOCVD, MBE, and / or HVPE. In some embodiments of the present invention, the channel layer 324 may be a group III nitride layer.

[0070] The barrier layer 326 may be a group III nitride layer. In some embodiments of the present invention, the barrier layer 326 may be a highly doped n-type layer. For example, the barrier layer 326 may be about 10 19 cm -3 It may be doped to concentrations below a certain level.

[0071] In some embodiments of the present invention, the barrier layer 326 may have sufficient thickness, Al composition, and / or doping to induce a significant carrier concentration at the interface between the channel layer 324 and the barrier layer 326 by polarization effect when the barrier layer 326 is embedded beneath the ohmic contact metal. Alternatively, the barrier layer 326 may be thick enough to reduce or minimize electron scattering in the channel due to ionizing impurities deposited at the interface between the barrier layer 326 and the subsequently formed first protective layer.

[0072] In some embodiments, the channel layer 324 and the barrier layer 326 may have different lattice constants. For example, the barrier layer 326 may be a relatively thin layer with a smaller lattice constant than the channel layer 324, resulting in the barrier layer 326 "spreading" across the interface between the two layers. Thus, a pseudocrystalline HEMT (pHEMT) device may be provided.

[0073] Referring to Figure 4B, the first protective layer 410 is formed on the barrier layer 326. The first protective layer 410 is silicon nitride (Si x N yThe dielectric material may be aluminum nitride (AlN), silicon dioxide (SiO2), and / or other suitable protective material. Other materials may also be used for the first protective layer 410. For example, the first protective layer 410 may also include magnesium oxide, scandium oxide, aluminum oxide, and / or aluminum oxynitride. Furthermore, the first protective layer 410 may be a single layer or may include multiple layers with uniform and / or non-uniform compositions.

[0074] The first protective layer 410 may be a blanket formed on the barrier layer 326. For example, the first protective layer 410 may be a silicon nitride (SiN) layer formed by high-quality sputtering and / or plasma-excited chemical vapor deposition (PECVD). The first protective layer 410 may be thick enough to protect the underlying barrier layer 326 during the subsequent annealing process following the ohmic contact.

[0075] An interface modifier layer 475 may be provided between the first protective layer 410 and the barrier layer 326. The interface modifier layer 475 provides variations in lateral conductivity, trap concentration, sheet resistance, and / or surface potential in the drain access region (and / or source access region) between the gate and the drain (and / or source). The interface modifier layer 475 can be provided exsitu (before insertion of the structure into the manufacturing environment in which the first protective layer 410 is formed), in situ (in the manufacturing environment in which the first protective layer 410 is formed, but before the formation of the first protective layer 410), and / or during the deposition of the first protective layer.

[0076] Examples of in situ processes that can provide the interface modification layer 475 may include ion collision of the barrier layer 326, plasma nitriding of the barrier layer 326, plasma oxidation of the barrier layer 326, H2 plasma treatment of the barrier layer 326 (which may cause nitrogen deficiency or nitrogen vacancies near the surface of the barrier layer 326), annealing of the barrier layer 326 in a chemically active gas environment (which may include, but is not limited to, forming gas, nitric oxide, nitrogen dioxide, and ammonia), and / or annealing of the barrier layer 326 in a chemically inert gas environment. It will be understood that each of these techniques can be performed individually or in any combination of the above techniques. In some embodiments, these processes may be performed in a process chamber separate from the deposition chamber, but the vacuum can be maintained before moving to the deposition chamber. In some embodiments, these processes may be performed in the deposition chamber itself before the deposition of the protective layer.

[0077] An example of an excitation process that can provide an interface modification layer 475 involves wet etching of the surface of the barrier layer 326 in an acidic and / or basic chemical bath. In some embodiments, buffered oxide etching (BOE) (e.g., buffered HF) may be used. In some embodiments, the BOE may be neutral but can still be used for the removal of native oxides, which may be advantageous in some applications.

[0078] Examples of processes that can be used during the formation of the first protective layer 410 to provide the interface modifying layer 475 include the use of physical vapor deposition (PVD) for forming the first protective layer 410, plasma-excited chemical vapor deposition (PECVD) for forming the first protective layer 410, atomic layer deposition (ALD) for forming the first protective layer 410, plasma-excited atomic layer deposition (PEALD) for forming the first protective layer 410, and / or pyrolysis deposition for forming the first protective layer 410. In some embodiments, one or more of the above deposition techniques can be used in any combination or partial combination to form the first protective layer 410 as a multilayer laminate. In some embodiments, the deposition techniques can be used alone or in combination with one or more of the in situ and / or ex situ processes to provide the interface modifying layer 475.

[0079] Other processes may be used after the formation of the first protective layer 410. For example, a method for providing an interface modification layer 475 after the deposition of the first protective layer 410 may include a modification and / or process that etches and / or otherwise removes a portion of the first protective layer 410 to provide access to the interface between the first protective layer 410 and the barrier layer 326. Such methods are described, for example, in U.S. Patent Application No. 17 / 325, 488 (Agent Reference No. 5308.3152), assigned to the assignee of the present invention, and these disclosures are incorporated herein by reference as if they were fully described herein.

[0080] Referring to Figure 4C, a mask 440 may be formed on the first protective layer 410. The mask 440 may include holes H positioned at the gate contact locations.

[0081] Referring to Figure 4D, etching (e.g., isotropic etching) can be performed using the mask 440. Etching may remove a portion of the first protective layer 410 exposed by holes H in the mask 440, exposing the barrier layer 326. Etching may also remove a portion of the interface modification layer 475 at the interface between the removed portion of the first protective layer 410 and the barrier layer 326. For example, etching may remove a portion of the barrier layer 326 and / or the first protective layer 410 containing interface modification provided in an earlier process (e.g., Figure 4B). In some embodiments, the properties of the interface modification layer 475 in the etched region may be removed and / or modified by exposing the barrier layer 326 to the atmosphere through the etching process. Etching of the interface modification layer 475 can form a modified interface region 375. As a result of the modified interface region 375, the sheet resistance of the source access region and / or drain access region of device 300 can be 300-400 Ω / sq.

[0082] Referring to Figure 4E, the mask 440 may be removed to expose a portion of the surface of the first protective layer 410 and the barrier layer 326 within the etched holes H in the first protective layer 410.

[0083] Referring to Figure 4F, a spacer layer 445 may be conformally formed on a portion of the surface of the first protective layer 410 and the barrier layer 326 within the etched holes H in the first protective layer 410. In some embodiments, the spacer layer 445 may be made of the same or similar material as the first protective layer 410. For example, the spacer layer 445 may be silicon nitride (Si x N y The spacer layer may also be a dielectric material such as aluminum nitride (AlN), silicon dioxide (SiO2), and / or other suitable protective material. For example, the spacer layer 445 may also contain magnesium oxide, scandium oxide, aluminum oxide, and / or aluminum oxynitride. Furthermore, the spacer layer 445 may be a single layer or may consist of multiple layers with uniform and / or non-uniform compositions.

[0084] The spacer layer 445 may be a blanket formed on the first protective layer 410 and the barrier layer 326. For example, the spacer layer 445 may be a silicon nitride (SiN) layer formed by high-quality sputtering and / or plasma-excited chemical vapor deposition (PECVD). Due to etched holes in the first protective layer 410, the height of the spacer layer 445 on the portion of the upper surface of the first protective layer 410 may be greater than the height of the spacer layer 445 on the upper surface of the barrier layer 326 in the etched holes in the first protective layer 410. As will be understood by those skilled in the art, the formation of the spacer layer 445 in the first protective layer 410 can provide a distinct interface that can be detected in the finished device, even if the spacer layer 445 and the first protective layer 410 are formed from the same material.

[0085] In some embodiments, the spacer layer 445 may be formed to have interface modifications to the barrier layer 326 that are different from those to the modified interface region 375. For example, the deposition process used to form the spacer layer 445 may include the use of PVD, PECVD, ALD, PEALD, and / or other pyrolysis deposition techniques. In some embodiments, one or more of the above deposition techniques can be used in any combination or partial combination to form the spacer layer 445 as a multilayer laminate. In some embodiments, excitu and / or incitu processes, such as those discussed herein with respect to the formation of the interface modification layer 475 (e.g., Figure 4B), may be used during the formation of the spacer layer 445.

[0086] For example, the process used to form the spacer layer 445 may include ion collision of the barrier layer 326, plasma nitriding of the barrier layer 326, plasma oxidation of the barrier layer 326, H2 plasma treatment of the barrier layer 326 (which may cause nitrogen deficiency or nitrogen vacancies near the surface of the barrier layer 326), annealing of the barrier layer 326 in a chemically active gas environment (which may include, but is not limited to, the formation of forming gas, nitric oxide, nitrogen dioxide, and ammonia), and / or annealing of the barrier layer 326 in a chemically inert gas environment. In some embodiments, the process used to form the spacer layer 445 may include wet etching of the surface of the barrier layer 326 in acidic and / or basic chemical baths, and / or in the use of BEO.

[0087] Referring to Figures 4G and 4H, etching 480 (e.g., isotropic etching 480) may be performed on the spacer layer 445. Etching 480 allows a portion of the barrier layer 326 to be exposed through holes H in the first protective layer 410. In addition, a portion of the previous spacer layer 445 may remain as spacer 485. The spacer layer 445 may be anisotropically etched such that the sidewalls of the remaining spacer 485 are inclined with respect to the upper surface of the barrier layer 326. The shape of the spacer 485 in Figure 4H is illustrative and is not intended to limit the embodiments of this disclosure. As shown in Figure 4H, the bottom surface of the spacer 485 may extend laterally from the first protective layer 410 and cover a portion of the barrier layer 326 exposed by the etched holes H in the first protective layer 410.

[0088] Referring to Figure 4I, the gate contact 310 may be formed within a hole H in the first protective layer 410. The gate contact 310 may be formed within an etched window H and may extend through the first protective layer 410 to contact the exposed portion of the barrier layer 326. The suitable gate material may depend on the composition of the barrier layer 326. However, in some embodiments, Ni, Pt, NiSi xConventional materials capable of forming Schottky contacts on nitride-based semiconductor materials such as Cu, Pd, Cr, TaN, W, and / or WSiN may be used. A portion of the gate contact 310 may extend on the surface of the first protective layer 410. A portion of the gate contact 310 may extend on the surface of the first protective layer 410.

[0089] Figure 4J is Figure 4 I This is an enlarged view of area B. Referring to Figure 4J, the gate contact 310 can be formed on the upper surface of the barrier layer 326 and the first protective layer, and on the side surface of the spacer 485. Due to the presence of the spacer 485, the bottom of the gate contact 310 is offset from the first protective layer 410. G It can be offset horizontally by only O. G As a result, the modified interface region 375 of the first protective layer 410 is offset from the bottom / corner of the gate contact 310. G It can be offset by only O. In some embodiments, the offset O G This may be between 10 nm and 400 nm. As discussed herein, in some embodiments, a portion of the spacer 485 may have its own interface modification that differs from the modified interface region 375 of the first protective layer 410.

[0090] Referring to Figure 4K, the first protective layer 410 (see Figure 4I) may be patterned to form source contacts 315 and drain contacts 305. For example, the first protective layer 410 may be patterned to form windows that expose the barrier layer 326 for the placement of source contacts 315 and drain contacts 305. The windows may be etched using a patterned mask and low-damage etching of the barrier layer 326. Ohmic metal may be formed on the exposed portion of the barrier layer 326. The ohmic metal may be annealed to provide source contacts 315 and drain contacts 305. The formation of source contacts 315, gate contacts 310 and drain contacts 305 results in the patterning of the first protective layer 410 in Figure 4I, which may form the first insulating layer 350.

[0091] As described above, in some embodiments, the source contact 315 and drain contact 305 may be formed before the gate contact 310 is formed. For example, the first protective layer 410 in Figure 4B can be patterned to form the source contact 315 and drain contact 305, as described with respect to Figure 4K, and then the gate contact 310 can be formed as described with respect to Figures 4C to 4J.

[0092] Although the source contact 315 is shown as being on the upper surface of the barrier layer 326 in Figure 4K, it will be understood that the source contact 315, gate contact 310, and / or drain contact 305 may be formed in recesses on the upper surface of the barrier layer 326.

[0093] Referring to Figure 4L, a second protective layer 420 may be formed on the first insulating layer 350, the source contact 315, the gate contact 310, and the drain contact 305. The second protective layer 420 may also be a dielectric layer. In some embodiments, the second protective layer 420 may have a different dielectric index than the first insulating layer 350.

[0094] Referring to Figure 4M, the field plate 360 ​​may be formed on the second protective layer 420. The field plate 360 ​​may overlap the gate contact 310 (for example, in the Z direction in Figure 4M) and extend the distance over the region between the gate and the drain (i.e., the gate-drain region). The overlap of the field plate 360 ​​over the gate contact 310 and the distance over which the field plate 360 ​​extends over the gate-drain region can be varied for optimal results. In some embodiments, the field plate 360 ​​may be electrically connected to the gate contact 310, and it will be understood that field plate structures other than those shown in the figures may be used without departing from the present invention.

[0095] Referring to Figure 4N, the second protective layer 420 may be patterned to form a metal contact 365. For example, the second protective layer 420 may be patterned to form a window that exposes the source contact 315 and / or drain contact 305 for arranging the metal contact 365. The window may be etched using a patterned mask and low-damage etching of the source contact 315 and / or drain contact 305. A conductive metal may be formed on the exposed portions of the source contact 315 and / or drain contact 305 to form the metal contact 365. The formation of the metal contact 365 results in the patterning of the second protective layer 420 in Figure 4L, which may form a second insulating layer 355.

[0096] Referring to Figure 4O, the substrate 122 (see Figure 4N) can be thinned to form a thin substrate 322. In some embodiments, the thickness of the substrate 322 is reduced using a grinder, such as an infeed or creep-feed grinder. In other embodiments, the thickness of the substrate 322 is reduced using lapping, chemical etching, reactive ion etching, or a combination thereof, with or without grinding. In yet another embodiment, etching may be used to process the back surface of the substrate 322 and reduce any damage to the substrate 322 that may result from the thinning operation. Methods for thinning wafers are described, for example, in U.S. Patents 7,291,529, 7,932,111, 7,259,402 and 8,513,686, which have been assigned to the assignees of the present invention, and these disclosures are incorporated herein by reference in their entirety.

[0097] In some embodiments of this disclosure, the substrate 322 is thinned to a thickness between approximately 40 μm and approximately 100 μm. In other embodiments, the substrate 322 is thinned to a thickness between approximately 40 μm and approximately 75 μm.

[0098] Referring to Figure 4P, vias 325 can be formed within the substrate 322, the channel layer 324, and the barrier layer 326. Vias 325 can be formed by wet etching or dry etching. In some embodiments, vias 325 can be anisotropically etched such that the sidewalls of vias 325 are inclined with respect to the upper surface of the substrate 322. Vias 325 can expose the bottom surface of the ohmic portion 315A of the source contact 315. In some embodiments, the source contact 315 can act as an etching stop material during the formation of vias 325.

[0099] Anisotropic etching allows the maximum cross-sectional area A2 of the via 325 to be located in the portion of the via 325 adjacent to the lower surface 322A of the substrate 322 (e.g., the opening of the via 325). In some embodiments, a thicker substrate 322 may result in a wider opening of the via 325, so anisotropic etching may result in a maximum cross-sectional area A2 of the via that is related to the thickness of the substrate 322. Therefore, as illustrated with respect to Figure 4G, thinning the substrate 322 may yield additional benefits by reducing the cross-sectional area A2 of the via 325.

[0100] Referring to Figure 4Q, after the via 325 is formed, the back metal layer 335 may be deposited on the lower surface 322A of the substrate 322, the sidewall of the via 325, and the bottom surface of the ohmic portion 315A of the source contact 315. Thus, the back metal layer 335 may be in direct contact with the ohmic portion of the source contact 315. The back metal layer 335 may contain a conductive metal such as titanium, platinum, and / or gold.

[0101] Figures 5A to 5C are schematic cross-sectional views showing several exemplary ways in which the HEMT device 300 according to embodiments of this disclosure can be packaged to provide packaged transistor amplifiers 200A to 200C, respectively. Figures 5A to 5C show the packaged HEMT device 300 of Figures 1 and 2A to 2C, but it will be understood that any of the HEMT devices according to embodiments of this disclosure can be packaged in the packages shown in Figures 5A to 5C.

[0102] Figure 5A is a schematic side view of the packaged Group III nitride-based transistor amplifier 200A. As shown in Figure 5A, the packaged transistor amplifier 200A includes a HEMT device 300 packaged in an open cavity package 210A. The package 210A includes metal gate leads 222A, metal drain leads 224A, a metal submount 230, a side wall 240, and a lid 242.

[0103] Submount 230 is included in package 2 1 The materials may include those configured to support thermal management of 0A. For example, the submount 230 may include copper and / or molybdenum. In some embodiments, the submount 230 may consist of multiple layers and include vias / interconnections. In an exemplary embodiment, the submount 230 may be a multilayer copper / molybdenum / copper metal flange including a core molybdenum layer with a copper clad layer on any of the main surfaces. In some embodiments, the submount 230 may include a metal heat sink which is part of the lead frame or metal slag. The sidewall 240 and / or lid 242 may be formed from or include an insulating material in some embodiments. The sidewall 240 and / or lid 242 may be formed from or include a ceramic material in some embodiments. In some embodiments, the sidewall 240 and / or lid 242 may be formed from, for example, Al2O3. The lid 242 may be bonded to the sidewall 240 using an epoxy adhesive. The sidewall 240 may be attached to the submount 230 by, for example, brazing. The gate lead wire 222A and the drain lead wire 224A may be configured to extend through the side wall 240, but embodiments of the present invention are not limited thereto.

[0104] The HEMT device 300 is mounted on the upper surface of the metal submount 230 in an air-filled cavity 212 defined by the metal submount 230, ceramic sidewalls 240, and ceramic lid 242. As described above, the gate and drain terminals 132, 134 of the HEMT device 300 are on the upper side of the semiconductor structure 390, and the source terminal 136 is on the lower side of the semiconductor structure 390. The source terminal 136 may be attached to the metal submount 230 using, for example, a conductive die-attaching material (not shown). The metal submount 230 may provide an electrical connection to the source terminal 136 and may also function as a heat dissipation structure for dissipating heat generated in the HEMT device 300. The heat is generated mainly in the upper portion of the HEMT device 300 where relatively high current densities occur, for example in the channel region of the unit cell transistors 300_A, 300_B. This heat can be transferred to the source terminal 136 via the source via 325 and the semiconductor structure 390, and then to the metal submount 230.

[0105] An input matching circuit 250 and / or an output matching circuit 252 may also be mounted within the package 210. The matching circuits 250, 252 may include impedance matching and / or harmonic termination circuits. The impedance matching circuit may be used to match the impedance of the fundamental components of the RF signal input to or output from the transistor amplifier 200A to the impedance at the input or output of the HEMT device 300, respectively. The harmonic termination circuit may be used to ground any harmonics of the fundamental RF signal that may be present at the input or output of the HEMT device 300. Two or more input matching circuits 250 and / or output matching circuits 252 may be provided, and the input and output matching circuits 250, 252 may be mounted on a metal submount 230, as schematically shown in Figure 5A. The gate lead wire 222A may be connected to the input matching circuit 250 by one or more bond wires 254, and the input matching circuit 250 may be connected to the gate terminal 132 of the HEMT device 300 by one or more additional bond wires 254. Similarly, the drain lead wire 224A may be connected to the output matching circuit 252 by one or more bond wires 254, and the output matching circuit 252 may be connected to the drain terminal 134 of the HEMT device 300 by one or more additional bond wires 254. The inductive bond wires 254 may form part of the input and / or output matching circuits 250, 252.

[0106] Figure 5B is a schematic side view of the packaged Group III nitride-based transistor amplifier 200B, which includes the HEMT device 300 of Figures 1 and 2A-2C, packaged within a printed circuit board-based package 210B. The packaged transistor amplifier 200B is very similar to the packaged transistor amplifier 200A in Figure 5A, except that the gate and drain leads 222A and 224A of package 210A are replaced in package 210B with the leads 222B and 224B on the printed circuit board base.

[0107] Package 210B includes a submount 230, a ceramic sidewall 240, and a ceramic lid 242, each of which may be substantially identical to the similarly numbered elements of package 210A discussed above. Package 210B further includes a printed circuit board 220. Conductive traces on the printed circuit board 220 form metal gate lead wires 22B and metal drain lead wires 224B. The printed circuit board 220 may be attached to the submount 230, for example, via a conductive adhesive. The printed circuit board 230 includes a central opening, and the HEMT device 300 is mounted within this opening on the submount 230. Other components of transistor amplifier 200B may be the same as the similarly numbered components of transistor amplifier 200A, and therefore further description is omitted.

[0108] Figure 5C is a schematic side view of another packaged Group III nitride-based transistor amplifier 200C. The transistor amplifier 200C differs from the transistor amplifier 200A in that it includes a different package 210C. Package 210C includes a metal submount 230 (which may be similar to or identical to the submount 230 of similarly numbered packages 210A), as well as metal gate and drain leads 222C, 224C. The transistor amplifier 200C also includes a plastic overmolding 260 that at least partially surrounds the HEMT device 300, the leads 222C, 224C, and the metal submount 230. Other components of the transistor amplifier 200C may be the same as those of similarly numbered components of the transistor amplifier 200A, and therefore further description is omitted.

[0109] Terms such as "first," "second," etc., may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. For example, without departing from the scope of the invention, the first element may be called the second element, and similarly, the second element may be called the first element. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related enumerated items.

[0110] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise explicitly indicated in the context. It will be further understood that, where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0111] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which the present invention pertains. Terms used herein should be construed to have meanings consistent with their meanings in the context of this specification and related art, and it will be further understood that they should not be construed in an idealized or overly formal sense unless expressly defined herein.

[0112] When an element such as a layer, region, or substrate is said to be "on" or "onto" another element, it can be understood that it is directly on or can extend directly onto the other element, or that there may be an intervening element. In contrast, when an element is said to be "directly on" or "directly onto" another element, there is no intervening element. When an element is said to be "connected" or "joined" to another element, it can be understood that it can be directly connected or joined to the other element, or that there may be an intervening element. In contrast, when an element is said to be "directly connected" or "directly joined" to another element, there is no intervening element.

[0113] Relative terms such as “downward,” “upward,” “top,” “bottom,” “horizontal,” “lateral,” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figure. It will be understood that these terms are intended to include various orientations of the device in addition to the orientation shown in the figure.

[0114] Embodiments of the present invention are described herein with reference to schematic cross-sectional views of idealized embodiments (and intermediate structures) of the present invention. Thicknesses of layers and regions in the drawings may be exaggerated for clarity. Furthermore, deformation from the drawn shape should be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be construed as being limited to specific shapes of regions shown herein, and should include, for example, variations in shape due to manufacturing. Similarly, dimensional variations should be expected based on the standard deviation in the manufacturing procedure. Where used herein, “approximately” includes values ​​within 10% of the nominal value.

[0115] Throughout the series, similar numbers refer to similar elements. Therefore, the same or similar numbers may be explained by reference to other drawings, even if they are not mentioned or explained in their corresponding drawings. Furthermore, elements not indicated by reference numbers may be explained by reference to other drawings.

[0116] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized by having a conduction type such as n-type or p-type, which refers to the majority carrier concentration within the layer and / or region. Thus, an N-type material has an equilibrium concentration of negatively charged electrons, while a P-type material has an equilibrium concentration of positively charged pores. Some materials may be designated with "+" or "-" (such as N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate a relatively large ("+") or small ("-") majority carrier concentration compared to another layer or region. However, such notation does not mean that a particular concentration of majority or minority carriers exists within the layer or region.

[0117] Typical embodiments of the present invention are disclosed in the drawings and this specification, and certain terms are used, but they are used only in a general and descriptive sense and are not intended to be limiting, and the scope of the present invention is set out in the following claims.

Claims

1. A method for forming a high electron mobility transistor (HEMT), A semiconductor structure is provided on a substrate, which includes channel layers and barrier layers stacked in sequence. Forming a first insulating layer on the barrier layer, Forming gate contacts, source contacts, and drain contacts on the barrier layer, Includes, The interface between the first insulating layer and the barrier layer includes a modified interface region provided on the drain access region and / or source access region such that the sheet resistance of the drain access region and / or source access region of the semiconductor structure is between 300 and 400 Ω / sq. A method for providing the modified interface region, comprising wet etching the upper surface of the barrier layer in an acidic and / or basic chemical bath before forming the first insulating layer.

2. The bottom surface of the gate contact is offset laterally by 10 to 400 nm from the modified interface region. The method according to claim 1, wherein the distance between the bottom surface of the gate contact and the drain contact is between 1.75 μm and 2.25 μm.

3. The method according to claim 1, wherein forming the first insulating layer on the barrier layer includes using physical vapor deposition (PVD), plasma-accelerated chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-accelerated atomic layer deposition (PEALD), and / or pyrolysis deposition.

4. The method according to any one of claims 1 to 3, further comprising: ion bombarding the barrier layer; plasma nitriding the barrier layer; plasma oxidation of the barrier layer; H2 plasma treatment of the barrier layer; and / or annealing the barrier layer in a gas environment, before forming the first insulating layer.

5. The method according to any one of claims 1 to 3, further comprising forming a spacer between the modified interface region and the gate contact.

6. Forming the aforementioned spacer means Etching holes in the first insulating layer, The spacer is formed on the side wall of the hole and on the barrier layer, Includes, The method according to claim 5, wherein forming the gate contact includes forming at least a portion of the gate contact on the side wall of the spacer in the hole.

7. The method according to claim 5, wherein the interface between the spacer and the barrier layer includes interface characteristics different from those of the modified interface region.

8. A method for forming a high electron mobility transistor (HEMT), A semiconductor structure is provided on a substrate, which includes channel layers and barrier layers stacked in sequence. Forming a first insulating layer on the barrier layer, Etching holes in the first insulating layer, Forming spacers on the side walls of the holes and on the barrier layer, A gate contact is formed on the barrier layer, wherein at least a portion of the gate contact is located within the first insulating layer. A modified interface region is provided between the first insulating layer and the barrier layer, spaced laterally from the bottom surface of the gate contact. Includes, Forming the spacer includes forming a spacer layer in the hole and etching the spacer layer to form the spacer on the side wall of the hole. Forming the gate contact includes forming at least a portion of the gate contact on the side wall of the spacer within the hole, A method for providing the modified interface region, comprising wet etching the upper surface of the barrier layer in an acidic and / or basic chemical bath.

9. The modified interface region is spaced 10 to 400 nm laterally from the bottom surface of the gate contact. The method according to claim 8, wherein the length of the bottom surface of the gate contact is between 50 nm and 400 nm.

10. The method according to claim 8, wherein the interface between the spacer and the barrier layer includes a trap concentration different from that of the modified interface region.

11. The method according to any one of claims 8 to 10, wherein the thickness of the first insulating layer is between 80 nm and 120 nm.

12. A method for forming a high electron mobility transistor (HEMT), A semiconductor structure is provided on a substrate, which includes channel layers and barrier layers stacked in sequence. Forming a first insulating layer on the barrier layer, A gate contact is formed on the barrier layer, wherein at least a portion of the gate contact is located within the first insulating layer. A modified interface region is provided between the first insulating layer and the barrier layer, spaced laterally from the bottom surface of the gate contact. Includes, Providing the modified interface region includes wet etching the upper surface of the barrier layer in an acidic and / or basic chemical bath. The sheet resistance of the drain access region and / or source access region of the semiconductor structure below the modified interface region is between 300 and 400 Ω / sq, in this method.

13. A method for forming a high electron mobility transistor (HEMT), A semiconductor structure is provided on a substrate, including a channel layer and a barrier layer on the channel layer. The first insulating layer is formed on the barrier layer, wherein the first insulating layer includes a modified interface region at the interface between the first insulating layer and the barrier layer. In the opening in the first insulating layer, a spacer is formed on the barrier layer, In the opening within the first insulating layer, a gate contact is formed on the barrier layer and the spacer, Includes, The interface between the spacer and the barrier layer has a first trap concentration different from the second trap concentration of the modified interface region. A method wherein the width of the bottom surface of the spacer adjacent to the barrier layer is 10 to 400 nm.

14. The method according to claim 13, further comprising thinning the substrate.

15. The bottom corner of the gate contact is offset from the modified interface region by the spacer. The method according to claim 13, wherein the length of the bottom surface of the gate contact is between 50 nm and 400 nm.

16. The method according to any one of claims 13 to 15, wherein the thickness of the first insulating layer is between 80 nm and 120 nm.

17. Forming the first insulating layer including the modified interface region is Wet etching of the upper surface of the barrier layer in an acidic and / or basic chemical bath, buffer oxide etching (BOE) of the upper surface of the barrier layer, ion bombardment of the barrier layer, plasma nitriding of the barrier layer, plasma oxidation of the barrier layer, H2 plasma treatment of the barrier layer, and / or annealing of the barrier layer in a gas environment, Depositing a protective layer on the barrier layer, The method according to any one of claims 13 to 15, including

18. The method according to claim 1, wherein the distance between the bottom surface of the gate contact and the source contact is between 0.5 μm and 0.7 μm.

19. The method according to claim 13, wherein the first insulating layer comprises a first material, and the spacer comprises a second material different from the first material.

20. The method according to claim 13, wherein the side wall of the spacer is inclined with respect to the upper surface of the barrier layer.

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