Display device and method for manufacturing a display device

Abstract

To suppress deterioration of reliability.SOLUTION: According to an embodiment, a display includes: a substrate; a lower electrode arranged above the substrate; a rib that has an aperture overlapping the lower electrode; a barrier that has a lower part arranged above the rib and an upper part which is arranged above the lower part and protrudes from the lateral face of the lower part; an organic layer that is arranged above the lower electrode in the aperture and includes a luminescent layer; and an upper electrode that is arranged above the organic layer and comes into contact with the lower part of the barrier. The organic layer includes a first end part located above the rib, and a second end part located above the rib, opposite to the first end part. The thickness of the upper electrode directly above the second end part is larger than the thickness of the upper electrode directly above the first end part.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the display device.

Background Art

[0002] In recent years, display devices applying organic light emitting diodes (OLEDs) as display elements have been put into practical use. Such a display element includes a pixel circuit including a thin film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light emitting layer. In the process of manufacturing such a display element, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a display device and a method for manufacturing the display device capable of suppressing a decrease in reliability.

Means for Solving the Problems

[0005] According to one embodiment, the display device is The device comprises a substrate, a lower electrode positioned above the substrate, a partition wall having a rib having an opening that overlaps with the lower electrode, a lower part positioned above the rib, and an upper part positioned above the lower part and protruding from the side surface of the lower part, an organic layer including a light-emitting layer positioned above the lower electrode in the opening, and an upper electrode positioned above the organic layer and in contact with the lower part of the partition wall, wherein the organic layer has a first end positioned above the rib and a second end positioned above the rib on the opposite side of the first end, and the thickness of the upper electrode directly above the second end is greater than the thickness of the upper electrode directly above the first end.

[0006] According to one embodiment, the method for manufacturing a display device is: A processing substrate is prepared, having a first lower electrode and a second lower electrode, a rib having a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode, and a partition wall including a lower part positioned on the rib between the first and second openings and an upper part positioned on the lower part and protruding from the side surface of the lower part. In a vapor deposition apparatus for forming the first and second upper electrodes, a first organic layer including a first light-emitting layer is formed on the first lower electrode at the first opening, a first upper electrode is formed on the first organic layer, a second organic layer including a second light-emitting layer different from the first light-emitting layer is formed on the second lower electrode at the second opening, and a second upper electrode is formed on the second organic layer. The extension direction of the vapor deposition source is inclined with respect to the normal to the substrate, and a conductive material is vapor-deposited onto the processing substrate while transporting the processing substrate in one direction. The vapor deposition direction when forming the first upper electrode is different from the vapor deposition direction when forming the second upper electrode. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device DSP. [Figure 2] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. [Figure 3]FIG. 3 is a schematic cross-sectional view of the display device DSP along the line III-III in FIG. 2. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the display element 20. [Figure 5] FIG. 5 is a schematic cross-sectional view of the display device DSP along the line A-B in FIG. 2. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device DSP along the line C-D in FIG. 2. [Figure 7] FIG. 7 is a diagram for explaining the vapor deposition apparatus EV. [Figure 8] FIG. 8 is a diagram for explaining the vapor deposition direction D when forming the upper electrode in each sub-pixel. [Figure 9] FIG. 9 is a diagram for explaining the transport direction TD when forming the upper electrode. [Figure 10] FIG. 10 is a diagram for explaining another transport direction TD when forming the upper electrode. [Figure 11] FIG. 1 is a diagram for explaining how the upper electrode is formed. [Figure 12] FIG. 12 is a flowchart for explaining an example of the manufacturing method of the display device DSP. [Figure 13] FIG. 13 is a diagram for explaining step ST1. [Figure 14] FIG. 14 is a diagram for explaining step ST21. [Figure 15] FIG. 15 is a diagram for explaining step ST22. [Figure 16] FIG. 16 is a diagram for explaining step ST23. [Figure 17] FIG. 17 is a diagram for explaining step ST24.

Embodiments for Carrying Out the Invention

[0008] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but it is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each figure, components that exhibit the same or similar functions as those described above with respect to the previously shown figures may be assigned the same reference numerals, and detailed descriptions that are repeated may be omitted as appropriate.

[0009] In addition, in the drawings, for the purpose of facilitating understanding as necessary, the X-axis, Y-axis, and Z-axis that are perpendicular to each other are described. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Looking at various elements parallel to the third direction Z is called a plan view.

[0010] <OO00097>The display device according to the present embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, etc. <0000O98>[[ID=IO]]

[0011] [[ID=II]] Figure 1 is a diagram showing a configuration example of the display device DSP. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0012] In the present embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0013] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a red sub-pixel SP1, a blue sub-pixel SP2, and a green sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.

[0014] The sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source and drain electrodes is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0016] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0017] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element. For example, sub-pixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, sub-pixel SP2 is equipped with a display element 20 that emits light in the blue wavelength range, and sub-pixel SP3 is equipped with a display element 20 that emits light in the green wavelength range.

[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the first direction X.

[0019] When subpixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which subpixels SP1 and SP3 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP2 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, aperture AP3 is larger than aperture AP1, and aperture AP2 is larger than aperture AP3.

[0022] The partition wall 6 overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are arranged between adjacent openings AP1 and AP3 in the second direction Y, and between two adjacent openings AP2 in the second direction Y. The second partition walls 6y are arranged between adjacent openings AP1 and AP2 in the first direction X, and between adjacent openings AP2 and AP3 in the first direction X.

[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole is formed in a grid shape that surrounds the openings AP1, AP2, and AP3. The partition wall 6 can also be said to have openings in the sub-pixels SP1, SP2, and SP3, similar to the rib 5.

[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3.

[0025] In the example in Figure 2, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. The periphery of each of the lower electrodes LE1, LE2, and LE3 overlaps with the rib 5. The outline of the upper electrode UE1 is almost identical to the outline of the organic layer OR1, and the periphery of both the upper electrode UE1 and the organic layer OR1 overlaps with the partition wall 6. The outline of the upper electrode UE2 is almost identical to the outline of the organic layer OR2, and the periphery of both the upper electrode UE2 and the organic layer OR2 overlaps with the partition wall 6. The outline of the upper electrode UE3 is almost identical to the outline of the organic layer OR3, and the periphery of both the upper electrode UE3 and the organic layer OR3 overlaps with the partition wall 6.

[0026] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3. The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display element 20. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of the display element 20.

[0027] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0028] Figure 3 is a schematic cross-sectional view of the DSP display device along the line III-III in Figure 2. A circuit layer 11 is placed on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are positioned on the insulating layer 12. The rib 5 is positioned on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. In other words, the ends of the lower electrodes LE1, LE2, and LE3 are positioned between the insulating layer 12 and the rib 5. Between the lower electrodes LE1, LE2, and LE3 that are adjacent to each other, the insulating layer 12 is covered by the rib 5.

[0030] The partition wall 6 includes a lower part (stem) 61 positioned on the rib 5 and an upper part (cap) 62 positioned on the lower part 61. The lower part 61 of the partition wall 6 shown on the left side of the figure is located between opening AP1 and opening AP2. The lower part 61 of the partition wall 6 shown on the right side of the figure is located between opening AP2 and opening AP3. The upper part 62 has a greater width than the lower part 61. As a result, in Figure 3, both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of the partition wall 6 can also be described as overhanging. The part of the upper part 62 that protrudes beyond the lower part 61 is sometimes simply referred to as the protruding part.

[0031] The organic layer OR1 shown in Figure 2 includes a first portion OR1a and a second portion OR1b that are spaced apart from each other, as shown in Figure 3. The first portion OR1a contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps a portion of the rib 5. The second portion OR1b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE1 shown in Figure 2 includes a first portion UE1a and a second portion UE1b that are spaced apart from each other, as shown in Figure 3. The first portion UE1a faces the lower electrode LE1 and is positioned above the first portion OR1a. In addition, the first portion UE1a is in contact with the side surface of the lower part 61. The second portion UE1b is located above the partition wall 6 and is positioned above the second portion OR1b. The first part OR1a and the first part UE1a are located below the upper part 62.

[0032] The organic layer OR2 shown in Figure 2 includes a first portion OR2a and a second portion OR2b that are spaced apart from each other, as shown in Figure 3. The first portion OR2a contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps a portion of the rib 5. The second portion OR2b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE2 shown in Figure 2 includes a first portion UE2a and a second portion UE2b that are spaced apart from each other, as shown in Figure 3. The first portion UE2a faces the lower electrode LE2 and is positioned above the first portion OR2a. In addition, the first portion UE2a is in contact with the side surface of the lower part 61. The second portion UE2b is located above the partition wall 6 and is positioned above the second portion OR2b. The first part OR2a and the first part UE2a are located below the upper part 62.

[0033] The organic layer OR3 shown in Figure 2 includes a first portion OR3a and a second portion OR3b that are spaced apart from each other, as shown in Figure 3. The first portion OR3a contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps a portion of the rib 5. The second portion OR3b is positioned on top of the upper portion 62. Furthermore, the upper electrode UE3 shown in Figure 2 includes a first portion UE3a and a second portion UE3b that are spaced apart from each other, as shown in Figure 3. The first portion UE3a faces the lower electrode LE3 and is positioned above the first portion OR3a. In addition, the first portion UE3a is in contact with the side surface of the lower part 61. The second portion UE3b is located above the partition wall 6 and is positioned above the second portion OR3b. The first part OR3a and the first part UE3a are located below the upper part 62.

[0034] In the example shown in Figure 3, the sub-pixels SP1, SP2, and SP3 include cap layers (optical adjustment layers) CP1, CP2, and CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0035] The cap layer CP1 includes a first portion CP1a and a second portion CP1b that are spaced apart from each other. The first portion CP1a is located at the opening AP1, below the upper portion 62, and positioned above the first portion UE1a. The second portion CP1b is located above the partition wall 6 and positioned above the second portion UE1b.

[0036] The cap layer CP2 includes a first portion CP2a and a second portion CP2b that are spaced apart from each other. The first portion CP2a is located in the opening AP2, below the upper portion 62, and positioned above the first portion UE2a. The second portion CP2b is located above the partition wall 6 and positioned above the second portion UE2b.

[0037] The cap layer CP3 includes a first portion CP3a and a second portion CP3b that are spaced apart from each other. The first portion CP3a is located in the opening AP3, below the upper portion 62, and positioned above the first portion UE3a. The second portion CP3b is located above the partition wall 6 and positioned above the second portion UE3b.

[0038] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE1, SE2, and SE3, respectively. The sealing layer SE1 is in contact with the first portion CP1a, the lower 61 and upper 62 of the partition wall 6, and the second portion CP1b, and continuously covers each component of the sub-pixel SP1. In the illustrated example, the sealing layer SE1 has a closed void V1 below the upper portion 62 of the partition wall 6 (below the protruding portion 621). The void V1 is spaced apart from the partition wall 6. This void V1 is surrounded by the portion of the sealing layer SE1 that is in contact with the side surface of the lower portion 61 of the partition wall 6, the portion that is in contact with the bottom surface of the upper portion 62 of the partition wall 6, and the portion that is in contact with the first portion CP1a. The void V1 is formed along the entire circumference of the partition wall 6 surrounding the opening AP1, but may be partially absent. The void V1 is closed throughout. The sealing layer SE2 is in contact with the first portion CP2a, the lower 61 and upper 62 of the partition wall 6, and the second portion CP2b, and continuously covers each component of the sub-pixel SP2. The sealing layer SE2 has a closed void V2 below the upper 62 of the partition wall 6 (below the protrusion 622). The void V2 is located on the opposite side of the void V1, with the partition wall 6 shown on the left side of the figure in between. The void V2 is formed along the entire circumference of the partition wall 6 surrounding the opening AP2, but may be partially absent. The void V2 is closed throughout. The sealing layer SE3 is in contact with the first portion CP3a, the lower 61 and upper 62 of the partition wall 6, and the second portion CP3b, and continuously covers each component of the sub-pixel SP3. The sealing layer SE3 has a closed void V3 below the upper 62 of the partition wall 6 (below the protruding portion 623). The void V3 is located on the opposite side of the void V2, with the partition wall 6 shown on the right side of the figure in between. The void V3 is formed along the entire circumference of the partition wall 6 surrounding the opening AP3, but may be partially absent. The void V3 is closed throughout.

[0039] The sealing layers SE1, SE2, and SE3 are covered by a protective layer 13.

[0040] In the example shown in Figure 3, on the partition wall 6 between sub-pixels SP1 and SP2, the second portion OR1b of organic layer OR1 is separated from the second portion OR2b of organic layer OR2, the second portion UE1b of upper electrode UE1 is separated from the second portion UE2b of upper electrode UE2, the second portion CP1b of cap layer CP1 is separated from the second portion CP2b of cap layer CP2, and the sealing layer SE1 is separated from the sealing layer SE2. The protective layer 13 is positioned between the second portions OR1b and OR2b, between the second portions UE1b and UE2b, between the second portions CP1b and CP2b, and between the sealing layer SE1 and the sealing layer SE2.

[0041] Furthermore, on the partition wall 6 between sub-pixels SP2 and SP3, the second portion OR2b of the organic layer OR2 is separated from the second portion OR3b of the organic layer OR3, the second portion UE2b of the upper electrode UE2 is separated from the second portion UE3b of the upper electrode UE3, the second portion CP2b of the cap layer CP2 is separated from the second portion CP3b of the cap layer CP3, and the sealing layer SE2 is separated from the sealing layer SE3. The protective layer 13 is positioned between the second portions OR2b and OR3b, between the second portions UE2b and UE3b, between the second portions CP2b and CP3b, and between the sealing layers SE2 and SE3.

[0042] The insulating layer 12 is an organic insulating layer. The ribs 5 and the sealing layers SE1, SE2, and SE3 are inorganic insulating layers.

[0043] The sealing layers SE1, SE2, and SE3 are formed, for example, from the same inorganic insulating material. Rib 5 is formed of silicon nitride (SiNx), which is an example of an inorganic insulating material. Alternatively, rib 5 may be formed as a single layer of any of the following inorganic insulating materials: silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Furthermore, rib 5 may be formed as a laminate of at least two combinations of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. The sealing layers SE1, SE2, and SE3 are formed from silicon nitride (SiNx), which is an example of an inorganic insulating material. Alternatively, the sealing layers SE1, SE2, and SE3 may be formed as single layers of other inorganic insulating materials, such as silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Furthermore, the sealing layers SE1, SE2, and SE3 may be formed as laminates of at least two combinations of silicon nitride layers, silicon oxide layers, silicon oxynitride layers, and aluminum oxide layers. Therefore, the sealing layers SE1, SE2, and SE3 may be formed from the same material as the ribs 5.

[0044] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the first portions UE1a, UE2a, and UE3a of each upper electrode. Both the lower part 61 and the upper part 62 of the partition wall 6 may be conductive.

[0045] The thickness T5 of rib 5 is sufficiently small compared to the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness T5 of rib 5 is between 200 nm and 400 nm.

[0046] Directly above the lower electrode LE1 overlapping the opening AP1, the sealing layer SE1 has a thickness T1. Directly above the lower electrode LE2 overlapping the opening AP2, the sealing layer SE2 has a thickness T2. Directly above the lower electrode LE3 overlapping the opening AP3, the sealing layer SE3 has a thickness T3. Thicknesses T1, T2, and T3 are approximately equivalent. The thickness T61 of the lower part 61 of bulkhead 6 (thickness from the top surface of rib 5 to the bottom surface of upper part 62) is greater than the thickness T5 of rib 5.

[0047] The lower electrodes LE1, LE2, and LE3 may be formed from a transparent conductive material such as ITO, or they may have a laminated structure of a metallic material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, and UE3 may also be formed from a transparent conductive material such as ITO.

[0048] When the potentials of the lower electrodes LE1, LE2, and LE3 are relatively higher than the potentials of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 correspond to the anodes, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes. Also, when the potentials of the upper electrodes UE1, UE2, and UE3 are relatively higher than the potentials of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 correspond to the anodes, and the lower electrodes LE1, LE2, and LE3 correspond to the cathodes.

[0049] The organic layers OR1, OR2, and OR3 contain multiple functional layers. Furthermore, the first portion OR1a and the second portion OR1b of organic layer OR1 contain an emissive layer EM1 formed from the same material. The first portion OR2a and the second portion OR2b of organic layer OR2 contain an emissive layer EM2 formed from the same material. The emissive layer EM2 is formed from a different material than the emissive layer EM1. The first portion OR3a and the second portion OR3b of organic layer OR3 contain an emissive layer EM3 formed from the same material. The emissive layer EM3 is formed from a different material than the emissive layers EM1 and EM2. The materials forming the emissive layer EM1, the emissive layer EM2, and the emissive layer EM3 are materials that emit light in different wavelength ranges.

[0050] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of transparent thin films. The multilayer structure may include thin films formed of inorganic materials and thin films formed of organic materials. Furthermore, these multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0051] The protective layer 13 is formed by a multilayer structure of transparent thin films, and for example, the thin films include thin films formed of inorganic materials and thin films formed of organic materials.

[0052] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the first portions UE1a, UE2a, and UE3a of each upper electrode that are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0053] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 of the first portion OR1a of the organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 of the first portion OR2a of the organic layer OR2 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 of the first portion OR3a of the organic layer OR3 emits light in the green wavelength range.

[0054] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0055] Figure 4 shows an example of the configuration of the display element 20. The lower electrode LE shown in Figure 4 corresponds to the lower electrodes LE1, LE2, and LE3 in Figure 3, respectively. The organic layer OR shown in Figure 4 corresponds to the organic layers OR1, OR2, and OR3 in Figure 3, respectively. The upper electrode UE shown in Figure 4 corresponds to the upper electrodes UE1, UE2, and UE3 in Figure 3, respectively.

[0056] The organic layer OR comprises a carrier adjustment layer CA1, an emissive layer EM, and a carrier adjustment layer CA2. Carrier adjustment layer CA1 is located between the lower electrode LE and the emissive layer EM, and carrier adjustment layer CA2 is located between the emissive layer EM and the upper electrode UE. Carrier adjustment layers CA1 and CA2 contain multiple functional layers. The following explanation will use the case where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode as an example.

[0057] The carrier adjustment layer CA1 includes functional layers such as a hole injection layer F11, a hole transport layer F12, and an electron blocking layer F13. The hole injection layer F11 is placed on the lower electrode LE, the hole transport layer F12 is placed on top of the hole injection layer F11, the electron blocking layer F13 is placed on top of the hole transport layer F12, and the light emission layer EM is placed on top of the electron blocking layer F13.

[0058] The carrier adjustment layer CA2 includes, as functional layers, a hole blocking layer F21, an electron transport layer F22, and an electron injection layer F23. The hole blocking layer F21 is located on top of the light-emitting layer EM, the electron transport layer F22 is located on top of the hole blocking layer F21, the electron injection layer F23 is located on top of the electron transport layer F22, and the upper electrode UE is located on top of the electron injection layer F23.

[0059] Furthermore, the carrier adjustment layers CA1 and CA2 may include other functional layers, such as a carrier generation layer, as needed, in addition to the functional layers described above, or at least one of the functional layers may be omitted.

[0060] Figure 5 is a schematic cross-sectional view of the display device DSP along the AB line in Figure 2. The cross-sectional view shown in Figure 5 includes multiple sub-pixels SP2 arranged in the second direction Y. Note that the substrate, circuit layer, and protective layer shown in Figure 3 are omitted.

[0061] Let's focus on the sub-pixel SP2 located in the center of the figure. The first portion OR2a of the organic layer OR2 has an end P11 along the second direction Y and an end P12 on the opposite side of end P11. Ends P11 and P12 are located above the rib 5 and spaced apart from the lower part 61 of the partition wall 6. Furthermore, ends P11 and P12 are located directly below the upper part 62 of the partition wall 6. Moreover, ends P11 and P12 are located directly below the void V2 formed in the sealing layer SE2.

[0062] In the first portion UE2a of the upper electrode UE2, the thickness T12 directly above the end P12 is greater than the thickness T11 directly above the end P11 (T12 > T11). Also, the first portion UE2a is in contact with the lower part 61 of the partition wall 6 facing the end P12 in the second direction Y. The first portion UE2a may be in contact with the lower part 61 facing the end P11 in the second direction Y, or it may not be in contact with the lower part 61 facing the end P11. The contact area between the lower part 61 facing the end P12 and the first portion UE2a is greater than the contact area between the lower part 61 facing the end P11 and the first portion UE2a.

[0063] The sealing layer SE2 covers the first portion CP2a and the second portion CP2b of the cap layer CP2. Between the end P12 and the partition wall 6, the first portion UE2a is exposed from the first portion CP2a of the cap layer CP2 and is covered by the sealing layer SE2.

[0064] The second portion OR2b of the organic layer OR2, the second portion UE2b of the upper electrode UE2, and the second portion CP2b of the cap layer CP2 are formed as a laminate and are arranged over the entire upper surface 62A of the upper part 62 of the partition wall 6.

[0065] In the sub-pixel SP2 located on the right side of the figure, the first portion OR2a of the organic layer OR2 also has an end P13. Directly above the end P13, the thickness of the first portion UE2a of the upper electrode UE2 is equivalent to the thickness T11 directly above the end P11, and is smaller than the thickness T12, although this will not be described in detail.

[0066] In the example shown in Figure 5, for example, end P11 corresponds to the first end, and end P12 corresponds to the second end.

[0067] Figure 6 is a schematic cross-sectional view of the display device DSP along the CD line in Figure 2. The cross-sectional view shown in Figure 6 includes sub-pixels SP1 and SP3 arranged alternately in the second direction Y. Note that the substrate, circuit layer, and protective layer shown in Figure 3 are omitted.

[0068] Let's focus on the sub-pixel SP1 located on the left side of the figure. The first portion OR1a of the organic layer OR1 has an end P21 along the second direction Y and an end P22 on the opposite side of end P21. Ends P21 and P22 are located above the rib 5 and spaced apart from the lower part 61 of the partition wall 6. Furthermore, ends P21 and P22 are located directly below the upper part 62 of the partition wall 6. Moreover, ends P21 and P22 are located directly below the void V1 formed in the sealing layer SE1.

[0069] In the first portion UE1a of the upper electrode UE1, the thickness T22 directly above the end P22 is greater than the thickness T21 directly above the end P21 (T22 > T21). Also, the first portion UE1a is in contact with the lower part 61 of the partition wall 6 facing the end P22 in the second direction Y. The first portion UE1a may be in contact with the lower part 61 facing the end P21 in the second direction Y, or it may not be in contact with the lower part 61 facing the end P21. The contact area between the lower part 61 facing the end P22 and the first portion UE1a is greater than the contact area between the lower part 61 facing the end P21 and the first portion UE1a.

[0070] The sealing layer SE1 covers the first portion CP1a and the second portion CP1b of the cap layer CP1. Between the end P22 and the partition wall 6, the first portion UE1a is exposed from the first portion CP1a of the cap layer CP1 and is covered by the sealing layer SE1.

[0071] The second portion OR1b of the organic layer OR1, the second portion UE1b of the upper electrode UE1, and the second portion CP1b of the cap layer CP1 are formed as a laminate, exposing a portion of the upper surface 62A of the upper part 62 of the partition wall 6.

[0072] Let's focus on the sub-pixel SP3 located on the right side of the figure. The first portion OR3a of the organic layer OR3 has an end P23 along the second direction Y and an end P24 opposite to end P23. Ends P23 and P24 are located above the rib 5 and spaced apart from the lower part 61 of the partition wall 6. Furthermore, ends P23 and P24 are located directly below the upper part 62 of the partition wall 6. Moreover, ends P23 and P24 are located directly below the void V3 formed in the sealing layer SE3.

[0073] In the first portion UE3a of the upper electrode UE3, the thickness directly above end P23 is greater than the thickness directly above end P24. Also, the first portion UE3a is in contact with the lower part 61 of the partition wall 6 facing end P23 in the second direction Y. The first portion UE3a may be in contact with the lower part 61 facing end P24 in the second direction Y, or it may not be in contact with the lower part 61 facing end P24. The contact area between the lower part 61 facing end P23 and the first portion UE3a is greater than the contact area between the lower part 61 facing end P24 and the first portion UE3a.

[0074] Between end P23 and partition wall 6, the first portion UE3a is exposed from the first portion CP3a of the cap layer CP3 and is covered by the sealing layer SE3.

[0075] The second portion OR3b of the organic layer OR3, the second portion UE3b of the upper electrode UE3, and the second portion CP3b of the cap layer CP3 are formed as a laminate, exposing a portion of the upper surface 62A of the upper part 62 of the partition wall 6.

[0076] In the example shown in Figure 6, focusing on subpixel SP1, end P21 corresponds to the first end, and end P22 corresponds to the second end. Also, focusing on subpixel SP3, end P23 corresponds to the second end, and end P24 corresponds to the first end.

[0077] Next, we will explain the deposition apparatus EV used to form the upper electrode.

[0078] Figure 7 is a diagram illustrating the vapor deposition apparatus EV. The vapor deposition apparatus EV comprises a transport mechanism 100 and a vapor deposition source 110.

[0079] The transport mechanism 100 transports the processing substrate SUB. The processing substrate SUB here is a substrate 10 on which a circuit layer 11, an insulating layer 12, a lower electrode LE, ribs 5, partition walls 6, and an organic layer OR are formed. The transport direction TD of the processing substrate SUB by the transport mechanism 100 is indicated by the arrow in the figure.

[0080] The deposition source 110 emits a conductive material M for forming the upper electrode. The extension direction of the deposition source 110 is inclined with respect to the normal to the substrate 10, as shown by the dotted line in the figure. The extension direction here refers to, for example, the direction in which the sleeve 120, which restricts the radiation direction of the conductive material M, extends. The angle θ between the normal to the substrate 10 and the extension direction of the deposition source 110 is, for example, between 5° and 40°. The deposition direction D of the conductive material M by the deposition source 110 is shown by an arrow in the figure. The deposition direction D is the direction from the bottom 111 of the deposition source 110 toward the opening 112 of the deposition source 110. The deposition direction D is opposite to the transport direction TD.

[0081] In such a deposition apparatus EV, the deposition source 110 is fixed, and the conductive material M is deposited onto the processing substrate SUB while it is transported in one direction. As a result, an upper electrode is formed on the organic layer OR. The conductive material M is an alloy of magnesium and silver.

[0082] Figure 8 is a diagram illustrating the deposition direction D when forming the upper electrode in each subpixel. In the sub-pixel SP1, the aperture AP1 of the rib 5 overlaps the lower electrode LE1, and the organic layer OR1 is formed on top of the lower electrode LE1 at the aperture AP1. The deposition direction D1 when forming the upper electrode UE1 on top of the organic layer OR1 is indicated by the arrow in the figure. In the sub-pixel SP2, the aperture AP2 of the rib 5 overlaps the lower electrode LE2, and the organic layer OR2 is formed on top of the lower electrode LE2 at the aperture AP2. The deposition direction D1 when forming the upper electrode UE2 on top of the organic layer OR2 is the same direction as the deposition direction D1 when forming the upper electrode UE1 in the sub-pixel SP1, as indicated by the arrow in the figure. In the sub-pixel SP3, the aperture AP3 of the rib 5 overlaps with the lower electrode LE3, and the organic layer OR3 is formed on top of the lower electrode LE3 at the aperture AP3. The deposition direction D2 when forming the upper electrode UE3 on top of the organic layer OR3 is different from the deposition direction D1 when forming the upper electrode UE1 on the sub-pixel SP1, as shown by the arrow in the figure. These deposition directions D1 and D2 are approximately parallel to the direction in which the lower electrodes LE1 and LE3 are aligned (second direction Y), and are in opposite directions to each other.

[0083] Figure 9 is a diagram illustrating the transport direction TD when forming the upper electrode. The illustrated example shows the transport direction TD of the processing substrate SUB when forming the upper electrode UE1 of the sub-pixel SP1 or the upper electrode UE2 of the sub-pixel SP2. The processing substrate SUB has one end SUBA along the transport direction TD and the other end SUBB on the opposite side of the one end SUBA. In the illustrated example, the processing substrate SUB is introduced into the deposition apparatus EV with the one end SUBA as the leading edge. In the deposition apparatus EV, the conductive material M emitted from the deposition source 110 is deposited while the processing substrate SUB is transported with the one end SUBA as the leading edge.

[0084] Figure 10 is a diagram illustrating another transport direction TD when forming the upper electrode. The illustrated example shows the transport direction TD of the processing substrate SUB when forming the upper electrode UE3 of the sub-pixel SP3. For example, when forming the upper electrode UE3 after forming the upper electrode UE1 or UE2, the processing substrate SUB is transported with one end SUBA as the leading edge, and then rotated 180° in the plane of the substrate before forming the upper electrode UE3, so that the other end SUBB becomes the leading edge and is introduced into the deposition apparatus EV. In the deposition apparatus EV, the conductive material M emitted from the deposition source 110 is deposited while the processing substrate SUB is transported with the other end SUBB as the leading edge. Thus, the transport direction of the processing substrate SUB when forming the upper electrode UE1 or UE2 is different from the transport direction of the processing substrate SUB when forming the upper electrode UE3.

[0085] Figure 11 is a diagram illustrating the process of forming the upper electrode. The upper part of Figure 11 shows the processing substrate SUB before the upper electrode is formed (before it is introduced into the deposition apparatus). The lower part of Figure 11 shows the processed substrate SUB after the upper electrode UE has been formed. The tip of the arrow indicating the transport direction TD corresponds to the trailing end of the arrow indicating the deposition direction D, and the trailing end of the arrow indicating the transport direction TD corresponds to the tip of the arrow indicating the deposition direction D.

[0086] The conductive material M emitted from the deposition source 110 is shielded by the partition wall 6 at the rear end of the deposition direction D, while it wraps around to the lower part 61 of the partition wall 6 at the front end of the deposition direction D. Therefore, focusing on the upper electrode UE of a sub-pixel, it becomes thicker at the front end of the deposition direction D and thinner at the rear end. At the front end of the deposition direction D, the upper electrode UE makes reliable contact with the lower part 61 of the partition wall 6, and the two are electrically connected. As a result, electrical connection failures between the upper electrode UE and the lower part 61 are suppressed compared to the case where the extension direction of the deposition source 110 is parallel to the normal of the substrate 10. In addition, at the front end of the deposition direction D, more conductive material M wraps around to the lower part 61, increasing the contact area between the upper electrode UE and the lower part 61 and reducing contact resistance. Therefore, a decrease in reliability can be suppressed.

[0087] In the examples shown in Figures 7 to 11 above, the opening AP1 corresponds to the first opening, the opening AP3 corresponds to the second opening, the lower electrode LE1 corresponds to the first lower electrode, the lower electrode LE3 corresponds to the second lower electrode, the organic layer OR1 corresponds to the first organic layer, the organic layer OR3 corresponds to the second organic layer, the light-emitting layer EM1 corresponds to the first light-emitting layer, the light-emitting layer EM3 corresponds to the second light-emitting layer, the upper electrode UE1 corresponds to the first upper electrode, the upper electrode UE3 corresponds to the second upper electrode, the cap layer CP1 corresponds to the first cap layer, the cap layer CP3 corresponds to the second cap layer, the sealing layer SE1 corresponds to the first sealing layer, and the sealing layer SE3 corresponds to the second sealing layer. The examples of the deposition apparatus EV shown in Figures 7, 9, 10, and 11 correspond to a configuration in which the processing substrate SUB is transported with its deposition surface positioned above the substrate 10 (face-up) and the deposition source 110 is configured to radiate the conductive material M downwards, but are not limited to this configuration. For example, the deposition apparatus EV may be configured in which the processing substrate SUB is transported with its deposition surface positioned below the substrate 10 (face-down) and the deposition source 110 is configured to radiate the conductive material M upwards. Alternatively, the deposition apparatus EV may be configured in which the processing substrate SUB is transported in a vertical position and the deposition source 110 is configured to radiate the conductive material M sideways.

[0088] Next, we will describe an example of a manufacturing method for a display device DSP.

[0089] Figure 12 is a flowchart illustrating an example of a manufacturing method for a display device DSP. The manufacturing method described herein broadly includes the steps of preparing a processing substrate SUB to serve as the base for sub-pixels SPα, SPβ, and SPγ (step ST1), forming sub-pixel SPα (step ST2), forming sub-pixel SPβ (step ST3), and forming sub-pixel SPγ (step ST4). Note that sub-pixels SPα, SPβ, and SPγ here refer to any of the sub-pixels SP1, SP2, and SP3 described above.

[0090] In step ST1, first, a processing substrate SUB is prepared on the substrate 10, with the lower electrodes LEα, LEβ, LEγ, ribs 5, and partition walls 6 formed on top of it. As shown in Figure 3, a circuit layer 11 and an insulating layer 12 are also formed between the substrate 10 and the lower electrodes LEα, LEβ, LEγ.

[0091] In step ST2, first, a first thin film 31 including an emissive layer EMα is formed on the processing substrate SUB (step ST21). Then, a first resist 41 patterned in a predetermined shape is formed on the first thin film 31 (step ST22). Subsequently, a portion of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST23). After that, the first resist 41 is removed (step ST24). This forms a sub-pixel SPα. The sub-pixel SPα comprises a display element 21 having the first thin film 31 of a predetermined shape.

[0092] In step ST3, first, a second thin film 32 including an emissive layer EMβ is formed on the processing substrate SUB (step ST31). Then, a second resist 42 patterned in a predetermined shape is formed on the second thin film 32 (step ST32). Subsequently, a portion of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST33). After that, the second resist 42 is removed (step ST34). This forms a sub-pixel SPβ. The sub-pixel SPβ comprises a display element 22 having a second thin film 32 of a predetermined shape.

[0093] In step ST4, first, a third thin film 33 including an emissive layer EMγ is formed on the processing substrate SUB (step ST41). Then, a third resist 43 patterned in a predetermined shape is formed on the third thin film 33 (step ST42). Subsequently, a portion of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST43). After that, the third resist 43 is removed (step ST44). This forms a sub-pixel SPγ. The sub-pixel SPγ comprises a display element 23 having a third thin film 33 of a predetermined shape.

[0094] The light-emitting layers EMα, EMβ, and EMγ are formed from materials that emit light in different wavelength ranges.

[0095] Detailed illustrations of the second thin film 32, the light-emitting layer EMβ, the display element 22, the third thin film 33, the light-emitting layer EMγ, and the display element 23 are omitted.

[0096] Steps ST1 and ST2 will be explained below with reference to Figures 13 to 17. Note that each cross-section shown in Figures 13 to 17 corresponds, for example, to the cross-section along line III-III in Figure 2.

[0097] First, in step ST1, a processing substrate SUB is prepared as shown in Figure 13. The process of preparing the processing substrate SUB includes the steps of forming a circuit layer 11 on a substrate 10, forming an insulating layer 12 on the circuit layer 11, forming the lower electrode LEα of the sub-pixel SPα, the lower electrode LEβ of the sub-pixel SPβ, and the lower electrode LEγ of the sub-pixel SPγ on the insulating layer 12, forming ribs 5 having openings APα, APβ, and APγ that overlap with the lower electrodes LEα, LEβ, and LEγ respectively, and forming a partition wall 6 including a lower part 61 placed on the ribs 5 and an upper part 62 placed on the lower part 61 and protruding from the side surface of the lower part 61. Note that in Figures 12 to 17, the substrate 10 and circuit layer 11 below the insulating layer 12 are not shown.

[0098] Next, in step ST21, as shown in Figure 14, a first thin film 31 is formed over sub-pixels SPα, SPβ, and SPγ. The process of forming the first thin film 31 includes forming an organic layer OR10 containing an emissive layer EMα on a processing substrate SUB, forming an upper electrode UE10 on the organic layer OR10, forming a cap layer CP10 on the upper electrode UE10, and forming a sealing layer SE10 on the cap layer CP10. In other words, in the illustrated example, the first thin film 31 includes the organic layer OR10, the upper electrode UE10, the cap layer CP10, and the sealing layer SE10. The process of forming the upper electrode UE10 is performed using the deposition apparatus EV described with reference to Figures 7 to 11.

[0099] The organic layer OR10 includes organic layers OR11, OR12, OR13, OR14, and OR15. All of the organic layers OR11, OR12, OR13, OR14, and OR15 contain the luminescent layer EMα. Organic layer OR11 is formed to cover the lower electrode LEα. Organic layer OR12 is spaced apart from organic layer OR11 and is located above the upper part 62 of the partition wall 6 between the lower electrodes LEα and LEβ. Organic layer OR13 is spaced apart from organic layer OR12 and is formed to cover the lower electrode LEβ. Organic layer OR14 is spaced apart from organic layer OR13 and is located above the upper part 62 of the partition wall 6 between the lower electrodes LEβ and LEγ. Organic layer OR15 is spaced apart from organic layer OR14 and is formed to cover the lower electrode LEγ.

[0100] The upper electrode UE10 includes upper electrodes UE11, UE12, UE13, UE14, and UE15. The upper electrode UE11 is located on the organic layer OR11 and is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEα and LEβ. The upper electrode UE12 is spaced apart from the upper electrode UE11 and is located on the organic layer OR12 between the lower electrodes LEα and LEβ. The upper electrode UE13 is spaced apart from the upper electrode UE12 and is located on the organic layer OR13. In the illustrated example, the upper electrode UE13 is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEα and LEβ, and between the lower electrodes LEβ and LEγ, but it may be in contact with either one of the lower parts 61. The upper electrode UE14 is spaced apart from the upper electrode UE13 and is located on the organic layer OR14 between the lower electrodes LEβ and LEγ. The upper electrode UE15 is spaced apart from the upper electrode UE14, located on the organic layer OR15, and is in contact with the lower part 61 of the partition wall 6 between the lower electrodes LEβ and LEγ.

[0101] The cap layer CP10 includes cap layers CP11, CP12, CP13, CP14, and CP15. The cap layer CP11 is located above the upper electrode UE11. The cap layer CP12 is spaced apart from the cap layer CP11 and is located above the upper electrode UE12. The cap layer CP13 is spaced apart from the cap layer CP12 and is located above the upper electrode UE13. The cap layer CP14 is spaced apart from the cap layer CP13 and is located above the upper electrode UE14. The cap layer CP15 is spaced apart from the cap layer CP14 and is located above the upper electrode UE15.

[0102] The sealing layer SE10 is formed to cover the cap layers CP11, CP12, CP13, CP14, CP15, and the partition wall 6. The sealing layer SE10 covering the partition wall 6 is in contact with the lower part of the upper part 62 and with the side surface of the lower part 61. The sealing layer SE10 has a void Vα facing the sub-pixel SPα of the partition wall 6, a void Vβ facing the sub-pixel SPβ of the partition wall 6, and a void Vγ facing the sub-pixel SPγ of the partition wall 6.

[0103] Next, in step ST22, as shown in Figure 15, a first resist 41 is formed on the sealing layer SE10. The first resist 41 covers the sub-pixel SPα. That is, the first resist 41 is positioned directly above the lower electrode LEα, the organic layer OR11, the upper electrode UE11, and the cap layer CP11. The first resist 41 also extends upward from the sub-pixel SPα to the partition wall 6. Between the sub-pixel SPα and the sub-pixel SPβ, the first resist 41 is positioned on the sub-pixel SPα side (left side in the figure), and the sealing layer SE10 is exposed on the sub-pixel SPβ side (right side in the figure). In the illustrated example, the first resist 41 exposes the sealing layer SE10 at sub-pixels SPβ and SPγ.

[0104] Subsequently, in step ST23, as shown in Figure 16, etching is performed using the first resist 41 as a mask to remove a portion of the first thin film 31. First, the encapsulation layer SE10 exposed from the first resist 41 is removed. Then, the cap layer CP10 exposed from the first resist 41 and the encapsulation layer SE10 is removed. Next, the upper electrode UE10 exposed from the first resist 41, the encapsulation layer SE10, and the cap layer CP10 is removed. Finally, the organic layer OR10 exposed from the first resist 41, the encapsulation layer SE10, the cap layer CP10, and the upper electrode UE10 is removed.

[0105] As a result, the lower electrode LEβ is exposed in the sub-pixel SPβ, and the lower electrode LEγ is exposed in the sub-pixel SPγ. Regarding the partition wall 6 between the sub-pixels SPα and SPβ, directly above the upper part 62, the organic layer OR12, upper electrode UE12, cap layer CP12, and sealing layer SE10 remain on the sub-pixel SPα side, while the organic layer OR12, upper electrode UE12, cap layer CP12, and sealing layer SE10 are removed on the sub-pixel SPβ side. Therefore, the sub-pixel SPβ side of the partition wall 6 is exposed. Furthermore, the partition wall 6 between sub-pixels SPβ and SPγ is also exposed.

[0106] Subsequently, in step ST24, the first resist 41 is removed as shown in Figure 17. This exposes the sealing layer SE10 of the sub-pixel SPα. Through these steps ST21 to ST24, the display element 21 is formed in the sub-pixel SPα. The display element 21 consists of a lower electrode LEα, an organic layer OR11 including an emissive layer EMα, an upper electrode UE11, and a cap layer CP11. The display element 21 is also covered by the sealing layer SE10.

[0107] A laminate is formed on the partition wall 6 between the sub-pixels SPα and SPβ, consisting of an organic layer OR12 containing a light-emitting layer EMα, an upper electrode UE12, and a cap layer CP12. This laminate is covered with a sealing layer SE10. In addition, the portion of the partition wall 6 on the side of the sub-pixels SPα is covered with the sealing layer SE10.

[0108] In the example described above, the sub-pixel SPα is one of the sub-pixels SP1, SP2, or SP3 shown in Figure 2. For example, if sub-pixel SPα corresponds to sub-pixel SP1, then the lower electrode LEα corresponds to the lower electrode LE1, the organic layer OR11 corresponds to the first part OR1a of the organic layer OR1, the organic layer OR12 corresponds to the second part OR1b of the organic layer OR1, the light-emitting layer EMα corresponds to the light-emitting layer EM1, the upper electrode UE11 corresponds to the first part UE1a of the upper electrode UE1, the upper electrode UE12 corresponds to the second part UE1b of the upper electrode UE1, the cap layer CP11 corresponds to the first part CP1a of the cap layer CP1, the cap layer CP12 corresponds to the second part CP1b of the cap layer CP1, and the sealing layer SE10 corresponds to the sealing layer SE1.

[0109] As described above, according to this embodiment, it is possible to provide a display device and a method for manufacturing a display device that can suppress a decrease in reliability and improve manufacturing yield.

[0110] All display devices and methods for manufacturing display devices that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices and methods for manufacturing display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0111] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0112] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0113] DSP…display device 10...Substrate 12...Insulating layer 5...Rib 6...Bulkhead 61...Lower 62...Upper SP1, SP2, SP3, SPα, SPβ, SPγ... Sub-pixels 20, 21, 22, 23… Display elements (organic EL elements) LE, LE1, LE2, LE3, LEα, LEβ, LEγ... Lower electrode (anode) UE, UE1, UE2, UE3, UE10... Upper electrode (cathode) OR,OR1,OR2,OR3,OR10…Organic layer CP, CP1, CP2, CP3, CP10… Cap layers SE, SE1, SE2, SE3, SE10…Sealing layer

Claims

1. circuit board and A first lower electrode and a second lower electrode are positioned above the substrate and aligned in a second direction, A rib having a first opening that overlaps with the first lower electrode and a second opening that overlaps with the second lower electrode, A partition wall having a lower portion positioned between the first and second openings of the rib, and an upper portion positioned above the lower portion and protruding from the side surface of the lower portion, Displaced on the first lower electrode in the first aperture, the first organic layer includes a first light-emitting layer, Displaced on the second lower electrode in the second aperture, a second organic layer including a second light-emitting layer, A first upper electrode is placed on the first organic layer and is in contact with the lower part of the partition wall, The second upper electrode is disposed on the second organic layer and is in contact with the lower part of the partition wall, The first organic layer has a first end located on the rib and a second end located on the rib and opposite to the first end, The lower part of the partition wall is formed of a conductive material. The contact area between the lower part facing the second end and the first upper electrode is greater than the contact area between the lower part facing the first end and the first upper electrode. The second organic layer has a third end located on the rib and a fourth end located on the rib and opposite to the third end, The contact area between the lower part facing the third end and the second upper electrode is greater than the contact area between the lower part facing the fourth end and the second upper electrode. The first end, the second end, the third end and the fourth end are aligned in the second direction, The second end is closer to the second opening in the second direction compared to the first end. The third end is closer to the first opening in the second direction compared to the fourth end. Display device.

2. The display device according to claim 1, wherein the first light-emitting layer and the second light-emitting layer emit light in different wavelength ranges from each other.

3. The display device according to claim 2, wherein the second end and the third end are opposite each other with the lower part in between.

4. The display device according to claim 1, wherein the first end and the second end are located directly below the upper part of the partition wall.

5. moreover, A first cap layer disposed on the first upper electrode, It comprises a first sealing layer that covers the first cap layer and is in contact with the lower part of the partition wall, The display device according to claim 1, wherein the first sealing layer covers the first upper electrode between the second end and the partition wall.

6. The first sealing layer has a closed void below the upper part of the partition wall, The display device according to claim 5, wherein the first end and the second end are located directly below the gap.

7. Each of the first organic layer, the first upper electrode, and the first cap layer has a first portion located below the upper part of the partition wall and a second portion located above the upper part and spaced apart from the first portion. The display device according to claim 5, wherein the first sealing layer is in contact with the first and second portions of the first cap layer.

8. The second portion of each of the first organic layer, the first upper electrode, and the first cap layer is formed as a laminate. The display device according to claim 7, wherein the laminate is arranged over the entire upper surface of the upper part of the partition wall.

9. The second portion of each of the first organic layer, the first upper electrode, and the first cap layer is formed as a laminate. The display device according to claim 7, wherein the laminate has a portion of the upper surface of the upper part of the partition wall exposed.

10. The display device according to claim 5, wherein the first sealing layer is formed of an inorganic insulating material.

11. The display device according to claim 5, wherein the first sealing layer is formed of silicon nitride.

12. The display device according to claim 1, wherein the ribs are formed of an inorganic insulating material.

13. The display device according to claim 1, wherein the ribs are formed of silicon nitride.

14. A processing substrate is prepared, having a first lower electrode and a second lower electrode, a rib having a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode, and a partition wall including a lower part positioned on the rib between the first and second openings and an upper part positioned on the lower part and protruding from the side surface of the lower part. In the first opening, a first organic layer including a first light-emitting layer is formed on the first lower electrode. A first upper electrode is formed on the first organic layer. In the second opening, a second organic layer including a second light-emitting layer different from the first light-emitting layer is formed on the second lower electrode. A second upper electrode is formed on the second organic layer. In a vapor deposition apparatus for forming the first upper electrode and the second upper electrode, the extension direction of the vapor deposition source is inclined with respect to the normal to the substrate, and a conductive material is deposited onto the processing substrate while the processing substrate is transported in one direction. The deposition direction when forming the first upper electrode is different from the deposition direction when forming the second upper electrode. The transport direction of the processing substrate when forming the first upper electrode is different from the transport direction of the processing substrate when forming the second upper electrode. A method for manufacturing a display device, comprising rotating the processing substrate 180° within the substrate surface after forming the first upper electrode and before forming the second upper electrode.

15. The method for manufacturing a display device according to claim 14, wherein the conductive material is an alloy of magnesium and silver.

16. The angle between the normal and the extension direction of the deposition source is 5° or more and 40° or less. A method for manufacturing a display device according to claim 14.

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