Semiconductor devices including face-to-face and back-to-back junction dies

Abstract

The present invention provides a semiconductor memory device and a method for manufacturing the same that achieve high I / O density, low thermal resistance, and improved manufacturing yield while reducing the overall cost and complexity of the stacking process. [Solution] The semiconductor device 100 includes a plurality of semiconductor dies 1 to 4 stacked in a three-dimensional structure. The first semiconductor die 1 and the second semiconductor die 2 are joined by a face-to-face bonding process performed by fusion bonding technology, and the dielectric layers 12 and 22 of the semiconductor dies are in direct contact. The third semiconductor die 3 is joined to the second semiconductor die 2 by a back-to-back bonding process performed by hybrid bonding technology, and the bonding structures formed on the back surfaces of the semiconductor dies are bonded to each other. Conductive vias are formed through the semiconductor dies to establish vertical electrical interconnections.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to three-dimensional (3D) stacked semiconductor memory devices including wafer-level bonding technologies such as fusion bonding and hybrid bonding, and methods of manufacturing the same.

Background Art

[0002] Due to the demand for high-performance computing (HPC), artificial intelligence (AI), and big data applications, the need for memory devices with higher bandwidth and larger storage capacity has been continuously increasing. Three-dimensional (3D) stacked memory architectures such as high-bandwidth memory (HBM) have been developed to meet these requirements by vertically stacking multiple memory dies to increase memory density and improve data transfer speed.

[0003] Conventional die-to-die (D2D) or chip-to-chip stacking technologies typically use flip-chip bonding using microbumps and through-silicon vias (TSVs). However, such methods face limitations including an increase in thermal resistance due to the presence of microbumps, a decrease in I / O density limited by the bump pitch, and an increase in manufacturing cost associated with the bump formation and alignment processes. Furthermore, these structures are susceptible to thermal stress and affect reliability.

[0004] To address these issues by providing fine-pitch interconnects and improved thermal performance, advanced bonding technologies such as wafer-to-wafer (W2W) hybrid bonding have been proposed. Hybrid bonding combines direct dielectric-to-dielectric bonding and metal-to-metal bonding, enabling high-density interconnects without the need for solder bumps. However, achieving high manufacturing yield using hybrid bonding remains challenging due to stringent requirements for wafer surface flatness and cleanliness, as well as alignment accuracy.

[0005] Furthermore, relying entirely on hybrid bonding to stack multiple memory dies can lead to increased manufacturing complexity and costs. To optimize manufacturing efficiency and cost-effectiveness, improved stacking architectures and bonding technologies that combine the advantages of different bonding methods while addressing these limitations are still needed.

[0006] Therefore, there is a need for semiconductor memory devices and related manufacturing methods that can achieve high I / O density, low thermal resistance, and improved manufacturing yield while reducing the overall cost and complexity of the stacking process. [Overview of the project]

[0007] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first semiconductor die, a second semiconductor die bonded to the first semiconductor die, a third semiconductor die bonded to the second semiconductor die, a fourth semiconductor die bonded to the third semiconductor die, a first conductive via, and a second conductive via. The first semiconductor die includes a first substrate having a bottom surface, a first dielectric layer on the bottom surface of the first substrate, and a first interconnection structure within the first dielectric layer. The second semiconductor die includes a second substrate having an top surface and a bottom surface, a second dielectric layer on the top surface of the second substrate, a second interconnection structure within the second dielectric layer, a third dielectric layer on the bottom surface of the second substrate, and a third interconnection structure passing through the third dielectric layer. The first conductive via extends continuously from the third interconnection structure to the first interconnection structure. The third semiconductor die includes a third substrate having an upper and lower surface, a fourth dielectric layer on the lower surface of the second substrate, a fourth interconnection structure within the fourth dielectric layer, a fifth dielectric layer on the upper surface of the third substrate, and a fifth interconnection structure that passes through the fifth dielectric layer and is connected to the third interconnection structure. The fourth semiconductor die includes a fourth substrate having an upper surface, a sixth dielectric layer on the upper surface of the fourth substrate, and a sixth interconnection structure within the sixth dielectric layer. The second conductive via extends continuously from the fifth interconnection structure to the sixth interconnection structure.

[0008] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first semiconductor die having a front side, and a second semiconductor die joined to the first semiconductor die by a face-to-face junction, having a front side facing the first semiconductor die and a back side facing the opposite side of the first semiconductor die, wherein the first junction structure comprises a second semiconductor die disposed on the back side of the second semiconductor die, a first conductive via passing through the second semiconductor die and configured to electrically connect a first metal wire in the first semiconductor die to a second metal wire in the second semiconductor die, and a front side joined to the second semiconductor die by a back-to-back junction, facing the opposite side of the second semiconductor die, and a second A third semiconductor die having a back side facing a semiconductor die, the second junction structure includes a third semiconductor die disposed on the back side of the third semiconductor die, a fourth semiconductor die bonded to the third semiconductor die by face-to-face bonding and having a front side facing the third semiconductor die, and a second conductive via passing through the third semiconductor die and configured to electrically connect a third metal wire in the third semiconductor die to a fourth metal wire in the fourth semiconductor die, wherein the first junction structure and the second junction structure are in contact with each other and are configured to electrically connect the first conductive via and the second conductive via as a single unit.

[0009] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The method includes the steps of: joining the surface side of a first semiconductor die to the surface side of a second semiconductor die; thinning the second semiconductor die; forming a first conductive via passing through the second semiconductor die; forming a first junction structure on the back side of the second semiconductor die; joining the surface side of a third semiconductor die to the surface side of a fourth semiconductor die; thinning the third semiconductor die; forming a second conductive via passing through the third semiconductor die; forming a second junction structure on the back side of the third semiconductor die; and joining the first junction structure to the second junction structure.

[0010] The above provides a fairly general overview of the features and technical advantages of the Disclosure, and is intended to facilitate a better understanding of the detailed description of the Disclosure below. Additional features and advantages of the Disclosure are described below and form the subject matter of the claims of the Disclosure. It will be understood by those skilled in the art that the disclosed concepts and particular embodiments can be readily used as a basis for modifying or designing other structures or processes to accomplish the same objectives of the Disclosure. It will also be understood by those skilled in the art that such equivalent structures will not deviate from the spirit and scope of the Disclosure as set forth in the appended claims. [Brief explanation of the drawing]

[0011] In relation to the drawings, this disclosure can be more fully understood by referring to the detailed description and claims, and throughout the drawings, similar reference numbers refer to similar elements.

[0012] [Figure 1] These are schematic cross-sectional views of semiconductor devices according to several embodiments of this disclosure.

[0013] [Figure 2A] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2B] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2C] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2D] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2E] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2F] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2G] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2H]The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2I] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2J] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2K] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2L] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2M] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices. [Figure 2N] The present disclosure shows several embodiments of methods for manufacturing semiconductor devices.

[0014] [Figure 3] This is a flowchart illustrating a method for manufacturing semiconductor devices according to several embodiments. [Modes for carrying out the invention]

[0015] Hereinafter, embodiments or examples of the present disclosure shown in the drawings will be described using specific languages. It should be understood that this does not limit the scope of the present disclosure. Any changes or modifications to the embodiments described herein, and further applications of the principles described herein, will be considered to be generally conceivable to those skilled in the art in which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if one embodiment shares the same reference numeral.

[0016] This specification uses terms such as first, second, and third to describe various elements, components, regions, layers, or sections, but it should be understood that these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, without departing from the teachings of the concept of the present invention, the first element, first component, first region, first layer, or first section discussed below can be referred to as the second element, second component, second region, second layer, or second section.

[0017] The terms used in this specification are for the sole purpose of describing particular embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Further, the terms "comprises" and "comprising" as used herein, when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0018] The present disclosure provides a semiconductor device that includes a plurality of semiconductor dies stacked within a three-dimensional (3D) structure. The device includes at least a first semiconductor die and a second semiconductor die joined by a face-to-face bond, and each die includes a substrate, a dielectric layer disposed on a surface of the substrate, and an interconnect structure embedded in the dielectric layer. The face-to-face bond between the first semiconductor die and the second semiconductor die is achieved by a fusion bond without using conductive bumps, thereby reducing the bonding cost and improving the thermal dissipation.

[0019] The third semiconductor die is bonded to the second semiconductor die by a back-to-back junction. The third semiconductor die includes a front and a back surface having a junction structure that includes a dielectric layer and a metal layer. The junction structure of the third semiconductor die is bonded to a corresponding junction structure on the back surface of the second semiconductor die using a hybrid junction, enabling electrical connection between the dies.

[0020] The fourth semiconductor die is further bonded to the third semiconductor die by face-to-face bonding. Conductive vias are formed through the semiconductor dies and their respective dielectric layers to establish vertical electrical interconnections between the stacked dies. A via-last process is applied to form through-silicon vias (TSVs) after die stacking, improving manufacturing yield by minimizing total thickness variation (TTV) across the stacked structure.

[0021] By integrating fusion bonding and hybrid bonding technologies in a hybrid stacked architecture, the disclosed semiconductor devices achieve higher I / O density, lower thermal resistance, improved manufacturing yield, and reduced manufacturing costs compared to conventional stacking technologies.

[0022] Figure 1 is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. As shown in Figure 1, the semiconductor device 100 may include semiconductor dies 1, 2, 3 and 4 and conductive vias 5, 6 and 7. Semiconductor die 1 may be laminated on conductive die 2. Semiconductor die 2 may be laminated on semiconductor die 3. Semiconductor die 3 may be laminated on semiconductor die 4.

[0023] In some embodiments, semiconductor dies 1, 2, 3 and / or 4 may be memory dies such as dynamic random access memory (DRAM) dies or high-bandwidth memory (HBM) dies. In other embodiments, semiconductor dies 1, 2, 3 and / or 4 may, alternatively, be logic dies configured to perform data processing functions, controller dies configured to manage memory access and data I / O operations, mixed-signal dies including analog and digital circuits, or accelerator dies designed for artificial intelligence (AI) or machine learning (ML) applications. Thus, semiconductor dies 1, 2, 3 and / or 4 may broadly include memory devices, logic devices, or other semiconductor devices suitable for high-performance computing (HPC), AI, and big data applications.

[0024] The semiconductor die 1 may include a semiconductor substrate 11 and a dielectric layer 12 disposed on the surface 112 (e.g., lower surface) of the semiconductor substrate 11. In some embodiments of this disclosure, the dielectric layer 12 includes an intermetallic dielectric layer. Multiple interconnection structures, such as metal wires 131 and 132, may be embedded within the dielectric layer 12. The side of the semiconductor die 1 on which the metal wires 131 and 132 are located is called the active side (e.g., frontside) of the semiconductor die 1. Conversely, the side of the semiconductor die 1 opposite the active side is called the inactive side (e.g., backside). The metal wires 131 and 132 can be fabricated by any suitable forming process (e.g., etching lithography, damascene, dual damascene, etc.) and can be formed using suitable conductive materials such as copper, aluminum, aluminum alloys, and copper alloys.

[0025] Furthermore, additional junction structures may be located on the surface 111 (e.g., the top surface) of the semiconductor substrate 11. The additional junction structure may include a junction dielectric layer 14, a junction pad 151 (e.g., a metal pad) exposed on the surface 141 (e.g., the top surface) of the junction dielectric layer 14, and a junction via 152 (e.g., a through via) electrically connected to the junction pad 151. The junction via 152 may extend through the junction dielectric layer 14 and be exposed on the surface 142 (e.g., the bottom surface) of the junction dielectric layer 14. The junction pad 151 and the junction via 152 may jointly form an interconnection structure for the additional junction structure.

[0026] As shown in Figure 1, the conductive via 7 may extend through the semiconductor substrate 11 of the semiconductor die 1. Specifically, the conductive via 7 extends continuously from the surface 111 of the semiconductor substrate 11 into the dielectric layer 12 located on the surface 112 of the semiconductor substrate 11. The conductive via 7 is electrically connected to both the bonding pad 151 and the metal wire 131, thereby electrically connecting the bonding pad 151 to the metal wire 131. In other words, the conductive via 7 is configured to establish an electrical connection between the bonding structure on the back side of the semiconductor die 1 and the interconnection structure on the front side of the semiconductor die 1. In some embodiments of this disclosure, the conductive material of the conductive via 7 includes tungsten, titanium, aluminum, copper, and any combination thereof.

[0027] As shown in Figure 1, the semiconductor die 2 is stacked beneath the semiconductor die 1. The semiconductor die 2 may include a semiconductor substrate 21 and a dielectric layer 22 disposed on the surface 211 (e.g., upper surface) of the semiconductor substrate 21. In some embodiments of this disclosure, the dielectric layer 22 includes an intermetallic dielectric layer. Multiple interconnection structures, such as metal wires 231 and 232, may be embedded within the dielectric layer 22. The side of the semiconductor die 2 on which the metal wires 231 and 232 are located is called the active side (e.g., front side) of the semiconductor die 2. Conversely, the side of the semiconductor die 2 opposite to the active side is called the inactive side (e.g., back side). The metal wires 231 and 232 can be fabricated by any suitable forming process (e.g., etching lithography, damascene, dual damascene, etc.) and can be formed using suitable conductive materials such as copper, aluminum, aluminum alloys, and copper alloys.

[0028] Furthermore, additional bonding structures may be located on the surface 212 (e.g., the bottom surface) of the semiconductor substrate 21. The additional bonding structure may include a bonding dielectric layer 24, a bonding pad 251 (e.g., a metal pad) exposed on the surface 242 (e.g., the bottom surface) of the bonding dielectric layer 24, and a bonding via 252 (e.g., a through via) electrically connected to the bonding pad 251. The bonding via 252 may extend through the bonding dielectric layer 24 and be exposed on the surface 241 (e.g., the top surface) of the bonding dielectric layer 24. The bonding pad 251 and the bonding via 252 may jointly form an interconnection structure for the additional bonding structure.

[0029] As shown in Figure 1, the conductive via 5 may extend through the semiconductor substrate 21 of the semiconductor die 2. Specifically, the conductive via 5 extends continuously from the surface 212 of the semiconductor substrate 21, through the dielectric layer 22 located on the surface 211 of the semiconductor substrate 21, and further extends into the dielectric layer 12 of the semiconductor die 1. The conductive via 5 is electrically connected to the bonding pad 251, bonding via 252, metal wires 231 and 232, and metal wire 132, thereby electrically connecting the bonding pad 251 to the metal wires 231 and 232, and the metal wires 231 and 232 to the metal wire 132. In other words, the conductive via 5 is configured to establish electrical connections between the bonding structure on the back side of the semiconductor die 2, the interconnection structure on the front side of the semiconductor die 2, and the interconnection structure on the front side of the semiconductor die 1. In some embodiments, the conductive via 5 may include a conductive material selected from tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), or a combination thereof.

[0030] Furthermore, the conductive via 5 may include a first portion 51 and a second portion 52. The first portion 51 of the conductive via 5 may extend from the surface 212 of the semiconductor substrate 21 to the metal wires 231 and 232 in the dielectric layer 22, and the second portion 52 of the conductive via 5 may extend from the metal wires 231 and 232 in the dielectric layer 22 to the metal wire 132 in the dielectric layer 12. That is, the first portion 51 of the conductive via 5 is configured to electrically connect the junction structure on the back side of the semiconductor die 2 to the interconnection structure on the front side of the semiconductor die 2, and the second portion 52 of the conductive via 5 is configured to electrically connect the interconnection structure on the front side of the semiconductor die 2 to the interconnection structure on the front side of the semiconductor die 1. In some embodiments of this disclosure, the cross-sectional width of the first portion 51 is greater than the cross-sectional width of the second portion 52.

[0031] As shown in Figure 1, semiconductor die 1 and semiconductor die 2 may also be joined to each other by a face-to-face bonding process. Specifically, the surface side of semiconductor die 1, which includes interconnection structures (e.g., metal wires 131, 132), is joined to the surface side of semiconductor die 2, which also includes interconnection structures (e.g., metal wires 231, 232). In some embodiments, face-to-face bonding between semiconductor die 1 and semiconductor die 2 is performed by a fusion bonding process. In the fusion bonding process, the respective surfaces of semiconductor die 1 and semiconductor die 2 are planarized and activated, and then the joint is formed by direct contact without the use of conductive bumps or adhesives. Fusion bonding can be achieved by annealing the stacked semiconductor dies at a high temperature to strengthen the joint and improve the structural integrity of the stack.

[0032] Therefore, the dielectric layer 12 of semiconductor die 1 and the dielectric layer 22 of semiconductor die 2 can come into contact with each other. In some embodiments of this disclosure, the conductive via 5 can be substantially aligned with the conductive via 7.

[0033] As shown in Figure 1, the semiconductor die 3 is stacked beneath the semiconductor die 2. The semiconductor die 2 may include a semiconductor substrate 31 and a dielectric layer 32 disposed on the surface 312 (e.g., bottom surface) of the semiconductor substrate 31. In some embodiments of this disclosure, the dielectric layer 32 includes an inter-metal dielectric layer. Multiple interconnection structures, such as metal wires 331 and 332, may be embedded within the dielectric layer 32. The side of the semiconductor die 3 on which the metal wires 331 and 332 are located is called the active side (e.g., front side) of the semiconductor die 3. Conversely, the side of the semiconductor die 3 opposite the active side is called the inactive side (e.g., back side). The metal wires 331 and 332 can be fabricated by any suitable forming process (e.g., etching lithography, damascene, dual damascene, etc.) and can be formed using suitable conductive materials such as copper, aluminum, aluminum alloys, and copper alloys.

[0034] Furthermore, additional bonding structures may be located on the surface 311 (e.g., the top surface) of the semiconductor substrate 31. The additional bonding structure may include a bonding dielectric layer 34, a bonding pad 351 (e.g., a metal pad) exposed on the surface 341 (e.g., the top surface) of the bonding dielectric layer 34, and a bonding via 352 (e.g., a through via) electrically connected to the bonding pad 351. The bonding via 352 may extend through the bonding dielectric layer 34 and be exposed on the surface 342 (e.g., the bottom surface) of the bonding dielectric layer 34. The bonding pad 351 and the bonding via 352 may jointly form an interconnection structure for the additional bonding structure.

[0035] As shown in Figure 1, semiconductor die 2 and semiconductor die 3 are joined to each other by a back-to-back bonding process. Specifically, the bonding structure located on the back side of semiconductor die 2 is bonded to the bonding structure located on the back side of semiconductor die 3. In some embodiments, the back-to-back bonding between semiconductor die 2 and semiconductor die 3 is performed by a hybrid bonding process. The bonding structure of semiconductor die 2 includes a bonding dielectric layer 24 and a bonding pad 251 (e.g., a metal pad), and the bonding structure of semiconductor die 3 includes a bonding dielectric layer 34 and a bonding pad 351 (e.g., a metal pad). In the hybrid bonding process, the bonding dielectric layer 24 of semiconductor die 2 is bonded to the bonding dielectric layer 34 of semiconductor die 3, and the bonding pad 251 of semiconductor die 2 is electrically connected to the bonding pad 351 of semiconductor die 3. This bonding method allows semiconductor die 2 and semiconductor die 3 to be mechanically joined and electrically interconnected without the use of solder bumps or adhesives.

[0036] The semiconductor die 4 is stacked beneath the semiconductor die 3. The semiconductor die 4 may include a semiconductor substrate 41 and a dielectric layer 42 disposed on the surface 411 (e.g., top surface) of the semiconductor substrate 41. In some embodiments of this disclosure, the dielectric layer 42 includes an intermetallic dielectric layer. Multiple interconnection structures, such as metal wires 431, may be embedded within the dielectric layer 42. The side of the semiconductor die 4 on which the metal wires 431 are located is called the active side (e.g., front side) of the semiconductor die 4. Conversely, the side of the semiconductor die 4 opposite the active side is called the inactive side (e.g., back side). The metal wires 431 can be fabricated by any suitable forming process (e.g., etching lithography, damascene, dual damascene, etc.) and can be formed using a suitable conductive material such as copper, aluminum, aluminum alloys, or copper alloys.

[0037] As shown in Figure 1, semiconductor die 3 and semiconductor die 4 may also be joined to each other by a face-to-face bonding process. Specifically, the surface side of semiconductor die 3, which includes interconnection structures (e.g., metal wires 331, 332), is joined to the surface side of semiconductor die 4, which also includes interconnection structures (e.g., metal wire 431). In some embodiments, face-to-face bonding between semiconductor die 3 and semiconductor die 4 is performed by a fusion bonding process. In the fusion bonding process, the respective surfaces of semiconductor die 3 and semiconductor die 4 are planarized and activated, and then the bond is formed by direct contact without the use of conductive bumps or adhesives. Fusion bonding can be achieved by annealing the stacked semiconductor dies at a high temperature to strengthen the bond and improve the structural integrity of the stack.

[0038] Therefore, the dielectric layer 32 of the semiconductor die 3 and the dielectric layer 42 of the semiconductor die 4 can come into contact with each other.

[0039] As shown in Figure 1, the conductive via 6 may extend through the semiconductor substrate 31 of the semiconductor die 2. Specifically, the conductive via 6 extends continuously from the surface 311 of the semiconductor substrate 31, passes through the dielectric layer 32 located on the surface 312 of the semiconductor substrate 31, and further extends into the dielectric layer 42 of the semiconductor die 4. The conductive via 6 is electrically connected to the bonding pad 351, bonding via 352, metal wires 331 and 332, and metal wire 431, thereby electrically connecting the bonding pad 351 to the metal wires 331 and 332, and the metal wires 331 and 332 to the metal wire 431. In other words, the conductive via 6 is configured to establish an electrical connection between the bonding structure on the back side of the semiconductor die 3, the interconnection structure on the front side of the semiconductor die 3, and the interconnection structure on the front side of the semiconductor die 4. In some embodiments, the conductive via 6 may include a conductive material selected from tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), or a combination thereof.

[0040] Furthermore, the conductive via 6 may include a first portion 61 and a second portion 62. The first portion 61 of the conductive via 6 may extend from the surface 312 of the semiconductor substrate 31 to the metal wires 331 and 332 in the dielectric layer 32, and the second portion 62 of the conductive via 6 may extend from the metal wires 331 and 332 in the dielectric layer 32 to the metal wire 421 in the dielectric layer 42. That is, the first portion 61 of the conductive via 6 is configured to electrically connect the junction structure on the back side of the semiconductor die 3 to the interconnection structure on the front side of the semiconductor die 3, and the second portion 62 of the conductive via 6 is configured to electrically connect the interconnection structure on the front side of the semiconductor die 3 to the interconnection structure on the front side of the semiconductor die 4. In some embodiments of this disclosure, the cross-sectional width of the first portion 61 is greater than the cross-sectional width of the second portion 62.

[0041] In some embodiments of this disclosure, the thickness d4 of the semiconductor substrate 41 is greater than the thickness d3 of the semiconductor substrate 31, the thickness d4 of the semiconductor substrate 41 is greater than the thickness d2 of the semiconductor substrate 21, and the thickness d4 of the semiconductor substrate 41 is greater than the thickness d1 of the semiconductor substrate 11. That is, the thickness D4 of the semiconductor die 4 may be greater than the thickness D3 of the semiconductor die 3, the thickness D4 of the semiconductor die 4 may be greater than the thickness D2 of the semiconductor die 2, and the thickness D4 of the semiconductor die 4 may be greater than the thickness D1 of the semiconductor die 1.

[0042] Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, and 2N illustrate methods for manufacturing semiconductor devices according to some embodiments of this disclosure.

[0043] As shown in Figure 2A, semiconductor dies 81 and 82 are provided. Semiconductor 81 is identical or similar to semiconductor die 1 shown in Figure 1. Semiconductor die 81 may include an active layer 811 on its surface side. That is, the surface of semiconductor die 81 may be the active surface of semiconductor die 81. Semiconductor 82 is identical or similar to semiconductor die 2 shown in Figure 1. Semiconductor die 82 may include an active layer 821 on its surface side. That is, the surface of semiconductor die 82 may be the active surface of semiconductor die 82.

[0044] As shown in Figure 2B, semiconductor die 81 and semiconductor die 82 are joined to each other by a face-to-face bonding process. Specifically, the surface of semiconductor die 81 is joined to the surface of semiconductor die 82. The face-to-face bonding process may be carried out by fusion bonding technology.

[0045] The fusion bonding process may include the following steps: First, the bonding surfaces of semiconductor die 81 and semiconductor die 82 are planarized to achieve a surface roughness of less than 1 nm, for example by chemical mechanical polishing (CMP). Next, the bonding surfaces are cleaned to remove contaminants and particles, ensuring high surface energy and cleanliness. Subsequently, the bonding surfaces are activated, for example by plasma treatment, to enhance the formation of hydrogen bonds between the surfaces. After activation, the surfaces of semiconductor die 81 and semiconductor die 82 are aligned and brought into contact at room temperature, allowing initial hydrogen bonds to form between the surfaces. Finally, the bonded semiconductor dies are subjected to an annealing process at a high temperature, for example, 200°C to 400°C, to convert the initial hydrogen bonds into stronger covalent bonds, thereby improving the mechanical strength and stability of the bonded structure.

[0046] This fusion bonding process permanently joins semiconductor die 81 and semiconductor die 82 to each other without the need for an intermediate adhesive layer or solder bumps.

[0047] As shown in Figure 2C, a portion of the semiconductor die 82 is removed. In particular, a portion of the substrate surrounding the semiconductor die 82 is selectively removed to thin the semiconductor die 82. Substrate removal may be performed by grinding, chemical mechanical polishing (CMP), etching, or a combination thereof.

[0048] As shown in Figure 2D, a conductive via 801 is formed. The conductive via 801 extends from the back surface 822 of the semiconductor die 82, passes through the active layer 821, and can further extend into the active layer 811. The conductive via 801 is identical or similar to the conductive via 5 shown in Figure 1.

[0049] As shown in Figure 2E, the junction structure 825 is formed on the back surface 822 of the semiconductor die 82. The junction structure 825 is identical or similar to the junction structure located on the front surface 212 of the semiconductor substrate 21 of the semiconductor die 2 shown in Figure 1. The junction structure 825 is electrically connected to the conductive via 801. That is, the conductive via 801 is configured to electrically connect the back surface of the semiconductor die 82 to the interconnection structures in the active layers 821 and 811, thereby establishing a vertical electrical interconnection across the stacked semiconductor dies.

[0050] As shown in Figure 2F, semiconductor dies 83 and 84 are provided. Semiconductor 83 is identical or similar to semiconductor die 3 shown in Figure 1. Semiconductor die 83 may include an active layer 831 on its surface side. That is, the surface of semiconductor die 83 may be the active surface of semiconductor die 83. Semiconductor 84 is identical or similar to semiconductor die 4 shown in Figure 1. Semiconductor die 84 may include an active layer 841 on its surface side. That is, the surface of semiconductor die 84 may be the active surface of semiconductor die 84.

[0051] As shown in Figure 2G, semiconductor die 83 and semiconductor die 84 are joined to each other by a face-to-face bonding process. Specifically, the surface of semiconductor die 83 is joined to the surface of semiconductor die 84. The face-to-face bonding process may be carried out by fusion bonding technology.

[0052] The fusion bonding process may include the following steps: First, the bonding surfaces of semiconductor die 83 and semiconductor die 84 are planarized to achieve a surface roughness of less than 1 nm, for example by chemical mechanical polishing (CMP). Next, the bonding surfaces are cleaned to remove contaminants and particles, ensuring high surface energy and cleanliness. Subsequently, the bonding surfaces are activated, for example by plasma treatment, to enhance the formation of hydrogen bonds between the surfaces. After activation, the surfaces of semiconductor die 83 and semiconductor die 84 are aligned and brought into contact at room temperature, allowing initial hydrogen bonds to form between the surfaces. Finally, the bonded semiconductor dies are subjected to an annealing process at a high temperature, for example, 200°C to 400°C, to convert the initial hydrogen bonds into stronger covalent bonds, thereby improving the mechanical strength and stability of the bonded structure.

[0053] This fusion bonding process permanently joins semiconductor die 83 and semiconductor die 84 to each other without the need for an intermediate adhesive layer or solder bumps.

[0054] As shown in Figure 2H, a portion of the semiconductor die 83 is removed. In particular, a portion of the substrate of the semiconductor die 83 is selectively removed to thin the semiconductor die 83. Substrate removal may be performed by a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof.

[0055] As shown in Figure 2I, a conductive via 802 is formed. The conductive via 802 extends from the back surface 832 of the semiconductor die 83, passes through the active layer 831, and can further extend into the active layer 841. The conductive via 802 is identical or similar to the conductive via 6 shown in Figure 1.

[0056] As shown in Figure 2J, the junction structure 835 is formed on the back surface 832 of the semiconductor die 83. The junction structure 835 is identical or similar to the junction structure located on the front surface 311 of the semiconductor substrate 31 of the semiconductor die 3 shown in Figure 1. The junction structure 835 is electrically connected to the conductive via 802. That is, the conductive via 802 is configured to electrically connect the back surface of the semiconductor die 83 to the interconnection structures in the active layers 831 and 841, thereby establishing a vertical electrical interconnection across the stacked semiconductor dies.

[0057] As shown in Figure 2K, the junction structures of semiconductor die 81 and semiconductor die 82 are further junctioned to the junction structures of semiconductor die 83 and semiconductor die 84 by a back-to-back junction process between semiconductor die 82 and semiconductor die 83. In particular, the junction structure 825 of semiconductor die 82 is junctioned to the junction structure 835 of semiconductor die 83. In some embodiments, the back-to-back junction between semiconductor die 82 and semiconductor die 83 is performed by a hybrid junction technique.

[0058] The bonding structure 825 of semiconductor die 82 and the bonding structure 835 of semiconductor die 83 each include a bonding dielectric layer and a bonding metal layer. In the hybrid bonding process, the bonding dielectric layers of the two semiconductor dies are planarized, for example, by chemical mechanical polishing (CMP) to achieve a highly smooth surface. Subsequently, the bonding surface can be cleaned to remove contaminants and particles, and surface activation can be performed to increase the bonding strength. After surface treatment, bonding structures 825 and 835 are aligned and brought into contact under controlled temperature and pressure conditions. During bonding, the bonding dielectric layers are bonded to each other to form a robust mechanical interface, and the bonding metal layer is electrically connected to establish an electrical interconnection between semiconductor die 82 and semiconductor die 83. The hybrid bonding process enables high-density and fine-pitch electrical connections without the use of solder bumps or adhesive layers, thereby improving the electrical performance and structural reliability of the stacked semiconductor devices.

[0059] As shown in Figure 2L, a portion of the semiconductor die 81 is removed. In particular, a portion of the substrate of the semiconductor die 81 is selectively removed in order to thin the semiconductor die 83. Substrate removal may be performed by a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof.

[0060] As shown in Figure 2M, a conductive via 803 is formed. The conductive via 803 can extend from the back surface 812 of the semiconductor die 81 into the active layer 811. The conductive via 803 is identical or similar to the conductive via 7 shown in Figure 1.

[0061] As shown in Figure 2N, a junction structure 815 is formed on the back surface 812 of the semiconductor die 81. The junction structure 815 is identical or similar to the junction structure located on the front surface 111 of the semiconductor substrate 11 of the semiconductor die 1 shown in Figure 1. The junction structure 815 is electrically connected to a conductive via 803. That is, the conductive via 803 is configured to electrically connect the back surface of the semiconductor die 81 to the interconnection structure in the active layer 811, thereby establishing a vertical electrical interconnection across the stacked semiconductor dies.

[0062] Following the manufacturing process, the semiconductor device 800 is formed as shown in Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, and 2N (see Figure 2N). In some embodiments of this disclosure, the semiconductor device 800 is identical or similar to the semiconductor device 100 shown in Figure 1.

[0063] Following the manufacturing process shown in Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, and 2N, a flow chart 9 as shown in Figure 3 is constructed.

[0064] Step 91 provides two semiconductor dies 81 and 82. Each semiconductor die includes a surface-side active layer having interconnection structures and device elements. The surfaces of the semiconductor dies are prepared for bonding.

[0065] In step 92, the surface of semiconductor die 81 is bonded to the surface of semiconductor die 82 by a fusion bonding process. The bonding surfaces are planarized, cleaned, surface activated (e.g., by plasma treatment), aligned, and then bonded at room temperature. A subsequent annealing process is performed to convert the initial hydrogen bonds into covalent bonds, thereby forming a strong mechanical and electrical bond without the use of solder bumps or adhesives.

[0066] In step 93, the back side of the semiconductor die 82 is selectively thinned by grinding, chemical mechanical polishing (CMP), or etching to reduce the substrate thickness. After thinning, conductive vias 801 are formed from the back side of the semiconductor die 82, passing through its active layer and extending into the active layer of the semiconductor die 81 to establish a vertical electrical interconnection. Furthermore, a junction structure 825 is formed on the thinned back surface of the semiconductor die 82. The junction structure includes a junction dielectric layer and a junction metal layer electrically connected to the conductive vias 801, enabling back-side connectivity for subsequent bonding processes.

[0067] Step 94 provides two semiconductor dies 83 and 84, each having a surface-side active layer. The surfaces of the semiconductor dies 83 and 84 are fused using a process similar to that used for semiconductor dies 81 and 82, including planarization, cleaning, surface activation, alignment, and annealing.

[0068] In step 95, the back side of the semiconductor die 83 is thinned by grinding, CMP, or etching. After thinning, conductive vias 802 are formed from the back side of the semiconductor die 83 and extended into the active layer of the semiconductor die 84. Subsequently, a junction structure 835 including a junction dielectric layer and a junction metal layer is formed on the back side of the semiconductor die 83 and electrically connected to the conductive vias 802.

[0069] In step 96, semiconductor die 82 and semiconductor die 83 are joined to each other by a back-to-back bonding process. Specifically, the bonding structure 825 of semiconductor die 82 is bonded to the bonding structure 835 of semiconductor die 83. In some embodiments, the back-to-back bonding process is performed by a hybrid bonding technique. In the hybrid bonding process, the bonding dielectric layers of the semiconductor dies are planarized, cleaned, and surface activated to ensure strong adhesion. The bonding structures 825 and 835 are aligned and brought into contact under controlled temperature and pressure conditions. The bonding dielectric layers are bonded to provide mechanical integrity, and the bonding metal layers are electrically connected to establish a vertical electrical interconnection between semiconductor die 82 and semiconductor die 83 without the use of solder bumps or adhesive layers.

[0070] In step 97, the back surface of the semiconductor die 81 is selectively thinned by grinding, CMP, or etching. After thinning, conductive vias 803 are formed from the back surface of the semiconductor die 81 and extended into its active layer. Subsequently, a junction structure 815 including a junction dielectric layer and a junction metal layer is formed on the back surface of the semiconductor die 81 and electrically connected to the conductive vias 803, enabling external electrical connection or further packaging.

[0071] In step 98, the manufacturing of semiconductor device 800 is completed. Semiconductor device 800 includes multiple semiconductor dies stacked by face-to-face fusion bonding and back-to-back hybrid bonding. The device features high input / output (I / O) density, improved thermal management, and enhanced structural reliability, making it suitable for advanced applications such as high-performance computing (HPC) and artificial intelligence (AI).

[0072] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first semiconductor die, a second semiconductor die bonded to the first semiconductor die, a third semiconductor die bonded to the second semiconductor die, a fourth semiconductor die bonded to the third semiconductor die, a first conductive via, and a second conductive via. The first semiconductor die includes a first substrate having a bottom surface, a first dielectric layer on the bottom surface of the first substrate, and a first interconnection structure within the first dielectric layer. The second semiconductor die includes a second substrate having an top surface and a bottom surface, a second dielectric layer on the top surface of the second substrate, a second interconnection structure within the second dielectric layer, a third dielectric layer on the bottom surface of the second substrate, and a third interconnection structure passing through the third dielectric layer. The first conductive via extends continuously from the third interconnection structure to the first interconnection structure. The third semiconductor die includes a third substrate having an upper and lower surface, a fourth dielectric layer on the lower surface of the second substrate, a fourth interconnection structure within the fourth dielectric layer, a fifth dielectric layer on the upper surface of the third substrate, and a fifth interconnection structure that passes through the fifth dielectric layer and is connected to the third interconnection structure. The fourth semiconductor die includes a fourth substrate having an upper surface, a sixth dielectric layer on the upper surface of the fourth substrate, and a sixth interconnection structure within the sixth dielectric layer. The second conductive via extends continuously from the fifth interconnection structure to the sixth interconnection structure.

[0073] Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first semiconductor die having a front side, and a second semiconductor die joined to the first semiconductor die by a face-to-face junction, having a front side facing the first semiconductor die and a back side facing the opposite side of the first semiconductor die, wherein the first junction structure comprises a second semiconductor die disposed on the back side of the second semiconductor die, a first conductive via passing through the second semiconductor die and configured to electrically connect a first metal wire in the first semiconductor die to a second metal wire in the second semiconductor die, and a front side joined to the second semiconductor die by a back-to-back junction, facing the opposite side of the second semiconductor die, and a second A third semiconductor die having a back side facing a semiconductor die, the second junction structure includes a third semiconductor die disposed on the back side of the third semiconductor die, a fourth semiconductor die bonded to the third semiconductor die by face-to-face bonding and having a front side facing the third semiconductor die, and a second conductive via passing through the third semiconductor die and configured to electrically connect a third metal wire in the third semiconductor die to a fourth metal wire in the fourth semiconductor die, wherein the first junction structure and the second junction structure are in contact with each other and are configured to electrically connect the first conductive via and the second conductive via as a single unit.

[0074] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The method includes the steps of: joining the surface side of a first semiconductor die to the surface side of a second semiconductor die; thinning the second semiconductor die; forming a first conductive via passing through the second semiconductor die; forming a first junction structure on the back side of the second semiconductor die; joining the surface side of a third semiconductor die to the surface side of a fourth semiconductor die; thinning the third semiconductor die; forming a second conductive via passing through the third semiconductor die; forming a second junction structure on the back side of the third semiconductor die; and joining the first junction structure to the second junction structure.

[0075] The above provides a fairly general overview of the features and technical advantages of the Disclosure, and is intended to facilitate a better understanding of the detailed description of the Disclosure below. Additional features and advantages of the Disclosure are described below and form the subject matter of the claims of the Disclosure. It will be understood by those skilled in the art that the disclosed concepts and particular embodiments can be readily used as a basis for modifying or designing other structures or processes to accomplish the same objectives of the Disclosure. It will also be understood by those skilled in the art that such equivalent structures will not deviate from the spirit and scope of the Disclosure as set forth in the appended claims.

Claims

1. First semiconductor die, A second semiconductor die bonded to the first semiconductor die by face-to-face bonding, A first conductive via extending into the first semiconductor die through the second semiconductor die, The third semiconductor die, A fourth semiconductor die bonded to the third semiconductor die by face-to-face bonding, The present invention includes a second conductive via extending through the third semiconductor die into the fourth semiconductor die, A semiconductor device in which the second semiconductor die is joined to the third semiconductor die by a back-to-back junction.

2. The first semiconductor die is A first substrate having a lower surface facing the second semiconductor die, The first dielectric layer located on the lower surface of the first substrate, The semiconductor device according to claim 1, comprising a first interconnection structure in the first dielectric layer.

3. The second semiconductor die is A second substrate having an upper surface facing the first semiconductor die and a lower surface facing the third semiconductor die, The second dielectric layer on the upper surface of the second substrate, The second interconnection structure within the aforementioned second dielectric layer, The third dielectric layer located on the lower surface of the second substrate, The present invention includes a third interconnection structure extending through the third dielectric layer, The semiconductor device according to claim 2, wherein the first conductive via extends from the third interconnection structure to the first interconnection structure.

4. The semiconductor device according to claim 3, wherein the first conductive via includes a first portion extending from the third interconnection structure to the second interconnection structure and a second portion extending from the second interconnection structure to the first interconnection structure, the cross-sectional width of the first portion being greater than the cross-sectional width of the second portion.

5. The third semiconductor die is A third substrate having an upper surface facing the second semiconductor die and a lower surface facing the fourth semiconductor die, The fourth dielectric layer located on the lower surface of the third substrate, The fourth interconnection structure within the aforementioned four dielectric layers, The fifth dielectric layer on the upper surface of the third substrate, The semiconductor device according to claim 1, comprising a fifth interconnection structure extending through the fifth dielectric layer.

6. The fourth semiconductor die is A fourth substrate having an upper surface facing the third semiconductor die, The sixth dielectric layer on the upper surface of the fourth substrate, The invention includes a sixth interconnection structure within the sixth dielectric layer, The semiconductor device according to claim 5, wherein the second conductive via extends from the fifth interconnection structure to the sixth interconnection structure.

7. The semiconductor device according to claim 6, wherein the second conductive via includes a third portion extending from the fifth interconnection structure to the fourth interconnection structure and a fourth portion extending from the fourth interconnection structure to the sixth interconnection structure, the cross-sectional width of the third portion being greater than the cross-sectional width of the fourth portion.

8. The semiconductor device according to claim 2, further comprising a seventh dielectric layer on the upper surface of the first substrate and a seventh interconnection structure extending through the seventh dielectric layer, wherein the third conductive via extends from the first interconnection structure to the seventh interconnection structure.

9. The semiconductor device according to claim 8, wherein the seventh interconnection structure is exposed on the upper surface of the seventh dielectric layer facing away from the first semiconductor die.

10. The semiconductor device according to claim 1, wherein the thickness of the fourth semiconductor die is greater than the thickness of the first semiconductor die, the thickness of the fourth semiconductor die is greater than the thickness of the second semiconductor die, and the thickness of the fourth semiconductor die is greater than the thickness of the third semiconductor die.

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