Semiconductor device, display device, and electronic device

Abstract

Provided is a semiconductor device having a reduced circuit area. This semiconductor device has first and second cell arrays and a first conversion circuit. The first cell array has first and second cells in the same row, and the second cell array has third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first wiring and a third wiring, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. In addition, the sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting a current corresponding to the product of held data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively. The first conversion circuit has a function of causing data corresponding to the total amount of current flowing through the second and third wirings to flow to the fourth and fifth wirings.

Description

Semiconductor device, display device, and electronic device

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof.

[0003] Currently, the development of integrated circuits that mimic the workings of the human brain is actively progressing. Such integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." Such integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with extremely low power consumption compared to von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] There have also been attempts to use a computing device that configures an artificial neural network to, for example, correct an image displayed on a display device. For example, Patent Document 1 discloses a display device that uses a computing circuit that configures an artificial neural network to adjust the brightness and color tone of a displayed image to suit the preferences of the viewer.

[0006] JP 2018-36639 A

[0007] M. Kang et al. , “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No. 2, p. 642-655. J. Zhang et al. , “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No. 4, p. 915-924.

[0008] An example of an arithmetic device that configures an artificial neural network is an arithmetic circuit that performs a product-sum operation by adding analog currents corresponding to the product of weighting coefficients and input data. Because this arithmetic circuit uses analog currents for calculation, the circuit size and circuit area can be made smaller than arithmetic circuits configured with digital circuits. Furthermore, by designing this arithmetic circuit so that the analog current used in the calculation is small, the power consumption of the arithmetic circuit can be reduced.

[0009] The arithmetic circuit may have a configuration having a cell array in which arithmetic cells are arranged in a matrix, each cell multiplying a weighting factor by input data and outputting the product as an analog current. For example, by adding up the analog currents output from the arithmetic cells arranged in a column, the amount of the added analog current can be treated as the sum of the products of the weighting factor and the input data, allowing for faster calculations than when a digital circuit is used to perform a product-sum operation.

[0010] In a hierarchical neural network, which is a type of artificial neural network, the number of neurons varies from layer to layer. For example, the number of neurons in a layer corresponds to the number of products to be added in a product-sum operation. Therefore, in the above-mentioned arithmetic circuit, the number of arithmetic cells required for each calculation (each layer) varies. Therefore, when a product-sum operation is performed in each layer of a hierarchical neural network using an arithmetic circuit with the same cell array size, some arithmetic cells may not be used in the operation. In other words, increasing the number of arithmetic cells in the cell array of the arithmetic circuit is suitable for large-scale calculations (calculations involving a large number of products to be added), but for small-scale calculations (calculations involving a small number of products to be added), the number of unused arithmetic cells increases, resulting in lower calculation efficiency per area.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area.An object of one embodiment of the present invention is to provide a semiconductor device in which calculation efficiency per area is not reduced even when small-scale calculations are performed.An object of one embodiment of the present invention is to provide a display device including any of the above-described semiconductor devices.An object of one embodiment of the present invention is to provide an electronic device including the above-described display device.An object of one embodiment of the present invention is to provide a novel semiconductor device, a novel display device, or a novel electronic device.

[0012] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems.

[0013] (1) One aspect of the present invention is a semiconductor device including a first cell array, a second cell array, and a first conversion circuit. The first cell array includes a first cell and a second cell arranged in the same row as the first cell. The second cell array includes a third cell and a fourth cell arranged in the same row as the third cell. The first conversion circuit includes a plurality of input terminals and a plurality of output terminals. The first cell is electrically connected to a first wiring and a second wiring, and the second cell is electrically connected to the first wiring and a third wiring. Each of the plurality of input terminals of the first conversion circuit is electrically connected to the second wiring and the third wiring, and each of the plurality of output terminals of the first conversion circuit is electrically connected to a fourth wiring and a fifth wiring. The third cell is electrically connected to the fourth wiring and a sixth wiring, and the fourth cell is electrically connected to the fifth wiring and a seventh wiring. The sixth wiring is electrically connected to the seventh wiring. The first cell has a function of passing a first current through the second wiring in an amount corresponding to the product of first data held in the first cell and second data input to the first cell from the first wiring, and the second cell has a function of passing a second current through the third wiring in an amount corresponding to the product of third data held in the second cell and fourth data input to the second cell from the first wiring. The first conversion circuit has a function of passing fifth data through the fourth wiring in an amount corresponding to the total amount of current flowing from the second wiring, and a function of passing sixth data through the fifth wiring in an amount corresponding to the total amount of current flowing from the third wiring. The third cell has a function of passing a third current through the sixth wiring in an amount corresponding to the product of the seventh data held in the third cell and the fifth data input to the third cell from the fourth wiring, and the fourth cell has a function of passing a fourth current through the seventh wiring in an amount corresponding to the product of the eighth data held in the fourth cell and the sixth data input to the fourth cell from the fifth wiring.

[0014] (2) Alternatively, according to one aspect of the present invention, in the configuration (1), a second conversion circuit may be further included. In particular, the second conversion circuit preferably has an input terminal and an output terminal, and the input terminal of the second conversion circuit is preferably electrically connected to the sixth wiring. Furthermore, the second conversion circuit preferably has a function of outputting ninth data corresponding to the total amount of current flowing from the sixth wiring to the output terminal of the second conversion circuit.

[0015] (3) Alternatively, one aspect of the present invention may be configured as described in (1) or (2) above, further including a fifth cell, a sixth cell, and a seventh cell. In particular, the first cell, the second cell, the third cell, and the fourth cell preferably each include a first transistor, a second transistor, and a first capacitor. The fifth cell, the sixth cell, and the seventh cell preferably each include a third transistor, a fourth transistor, and a second capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, the gate of the first transistor is preferably electrically connected to a first terminal of the first capacitor and a first terminal of the second transistor, and the first terminal of the first transistor is preferably electrically connected to a second terminal of the second transistor. In the first cell, the first terminal of the first transistor is preferably electrically connected to a second wiring, and the second terminal of the first capacitor is preferably electrically connected to a first wiring. In the second cell, it is preferable that the first terminal of the first transistor is electrically connected to the third wiring, and the second terminal of the first capacitor is electrically connected to the first wiring. In the third cell, it is preferable that the first terminal of the first transistor is electrically connected to the sixth wiring, and the second terminal of the first capacitor is electrically connected to the fourth wiring. In the fourth cell, it is preferable that the first terminal of the first transistor is electrically connected to the seventh wiring, and the second terminal of the first capacitor is electrically connected to the fifth wiring. In each of the fifth cell, the sixth cell, and the seventh cell, it is preferable that the gate of the third transistor is electrically connected to the first terminal of the second capacitor and the first terminal of the fourth transistor, and the first terminal of the third transistor is electrically connected to the second terminal of the fourth transistor. In the fifth cell, it is preferable that the first terminal of the third transistor is electrically connected to the first wiring, and the second terminal of the second capacitor is electrically connected to the first wiring. In the sixth cell, it is preferable that the first terminal of the third transistor is electrically connected to the fourth wiring and the second terminal of the second capacitor is electrically connected to the fourth wiring. In the seventh cell, it is preferable that the first terminal of the third transistor is electrically connected to the fifth wiring and the second terminal of the second capacitor is electrically connected to the fifth wiring.

[0016] (4) Alternatively, according to one embodiment of the present invention, in the above-described (3), the semiconductor device may include a first circuit and a second circuit, the first circuit being electrically connected to the first wiring, and the second circuit being electrically connected to the fourth wiring and the fifth wiring. In particular, it is preferable that the first circuit has a function of inputting second data to the first wiring, and the second circuit has a function of causing current to flow through the fourth wiring and the fifth wiring.

[0017] (5) Another embodiment of the present invention is a display device including a first layer including the semiconductor device described in any one of (1) to (4) above and a second layer including a display portion, in which the second layer has a region overlapping with the first layer.

[0018] (6) Another embodiment of the present invention is an electronic device including the display device according to (5) above and a housing.

[0019] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are each an example of a semiconductor device. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0020] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connection relationships other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, and layers).

[0021] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (for example, inverters, NAND circuits, and NOR circuits), signal conversion circuits (for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (for example, power supply circuits (for example, step-up circuits and step-down circuits), and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (for example, circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0023] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0024] This specification also deals with a circuit configuration in which multiple elements are electrically connected to wiring (a wiring that supplies a constant potential or a wiring that transmits a signal). For example, if X and a wiring are directly connected and Y and the wiring are directly connected, this specification may state that X and Y are directly electrically connected.

[0025] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By defining the order of connections in a circuit configuration using expressions similar to these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limited to these. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, and layers).

[0026] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0027] Furthermore, in this specification, a "resistance element" can refer to, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, etc. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," and "region having a resistance value." Conversely, terms such as "resistance," "load," and "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0028] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0029] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, terms such as source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification.

[0030] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, for example, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0031] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is shown on a circuit diagram, this includes two or more resistors electrically connected in series. For example, when a single capacitor is shown on a circuit diagram, this includes two or more capacitors electrically connected in parallel. For example, when a single transistor is shown on a circuit diagram, this includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a single switch is shown on a circuit diagram, this includes two or more transistors, with the switch including two or more transistors electrically connected in series or parallel, and the gates of the respective transistors electrically connected to each other.

[0032] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal or a wiring can also be referred to as a node.

[0033] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0034] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0035] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, a statement such as "current is input to element A" can be rephrased as "current is output from element A."

[0036] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0037] Furthermore, in this specification, terms indicating arrangement, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0038] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0039] Furthermore, in this specification, the terms "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0040] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator."

[0041] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0042] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, the terms "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Vice versa, the term "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0043] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may result in, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like. When the semiconductor is an oxide semiconductor, examples of impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, examples of impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0044] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or three or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch or a mechanical switch can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0047] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0048] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0049] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device preferably has one light-emitting unit between a pair of electrodes, and the light-emitting unit includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, the light-emitting layers may be selected so that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the light-emitting device as a whole emits white light can be obtained. When three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers may be combined to produce a configuration in which the light-emitting device as a whole emits white light.

[0050] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0051] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0052] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0053] According to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. According to one embodiment of the present invention, a semiconductor device in which calculation efficiency per area is not reduced even when small-scale calculations are performed can be provided. According to one embodiment of the present invention, a display device including any of the above-described semiconductor devices can be provided. According to one embodiment of the present invention, an electronic device including the above-described display device can be provided. According to one embodiment of the present invention, a novel semiconductor device, a novel display device, or a novel electronic device can be provided.

[0054] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0055] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 2 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 3 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 4A is a block diagram showing an example of the configuration of a circuit included in a semiconductor device, FIG. 4B is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device, and FIG. 4C is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. FIGS. 5A to 5D are circuit diagrams showing an example of the configuration of a circuit included in a semiconductor device. FIG. 6 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. FIG. 7 is a timing chart showing an example of the operation of the semiconductor device. FIG. 8 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. FIG. 9 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 10 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. FIG. 11 is a circuit diagram showing an example of the configuration of a semiconductor device. FIGS. 12A and 12B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. FIG. 13 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 14 is a block diagram showing an example of the configuration of a display device. FIG. 15 is a diagram explaining an example of the configuration of a display device. FIGS. 16A and 16B are diagrams explaining a hierarchical neural network. FIG. 17 is a schematic cross-sectional view showing an example of the configuration of a display device. 18A to 18D are schematic diagrams showing a configuration example of a light-emitting device. FIG. 19 is a cross-sectional view showing a configuration example of a display device. FIGS. 20A and 20B are cross-sectional views showing a configuration example of a display device. FIGS. 21A and 21B are cross-sectional views showing a configuration example of a display device. FIGS. 22A and 22B are cross-sectional views showing a configuration example of a display device. FIGS. 23A and 23B are cross-sectional views showing a configuration example of a display device. FIGS. 24A to 24F are cross-sectional views showing an example of a method for manufacturing a display device. FIG. 25A is a circuit diagram showing a configuration example of a pixel circuit included in a display device, and FIG. 25B is a perspective view showing a configuration example of a pixel circuit included in a display device. FIGS. 26A to 26D are circuit diagrams showing a configuration example of a pixel circuit included in a display device. FIGS. 27A to 27D are circuit diagrams showing a configuration example of a pixel circuit included in a display device.28A and 28B are plan views showing configuration examples of a light-emitting device and a light-receiving device included in a display device. FIGS. 29A to 29D are cross-sectional schematic views showing configuration examples of a light-emitting device, a light-receiving device, and connection electrodes included in a display device. FIGS. 30A to 30G are plan views showing an example of a pixel. FIGS. 31A to 31F are plan views showing an example of a pixel. FIGS. 32A to 32H are plan views showing an example of a pixel. FIGS. 33A to 33D are plan views showing an example of a pixel. FIGS. 34A to 34D are plan views showing an example of a pixel, and FIG. 34E is a cross-sectional view showing an example of a display device. FIGS. 35A and 35B are diagrams showing configuration examples of a display module. FIGS. 36A to 36F are diagrams showing configuration examples of an electronic device. FIGS. 37A to 37D are diagrams showing configuration examples of an electronic device. FIGS. 38A to 38C are diagrams showing configuration examples of an electronic device.

[0056] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0057] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0058] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0059] In addition, the content (or even a part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even a part of the content) described in that embodiment and one or more other content (or even a part of the content) described in another embodiment.

[0060] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0061] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0062] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0063] In addition, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view, for example, is a diagram showing the appearance of a surface (cut surface) obtained by cutting a configuration horizontally. Furthermore, hidden lines (e.g., dashed lines) may be included in the plan view to show the positional relationship of multiple elements included in the configuration or the overlapping relationship of the multiple elements. Note that, in this specification, the term "plan view" may be replaced with the terms "projection view," "top view," or "bottom view." Depending on the situation, a plan view may refer to a surface (cut surface) obtained by cutting a configuration in a direction other than the horizontal direction, rather than a surface (cut surface) obtained by cutting the configuration horizontally.

[0064] In addition, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view is, for example, a view showing a surface (cut surface) of a configuration cut in a vertical direction. In this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Depending on the situation, a cross-sectional view may refer to a surface (cut surface) of a configuration cut in a direction other than the vertical direction, rather than a surface (cut surface) cut in a vertical direction.

[0065] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0066] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0067] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0068] 1 is a block diagram illustrating a configuration example of an arithmetic circuit that is a semiconductor device of one embodiment of the present invention. The arithmetic circuit has, for example, a function of calculating a sum of products of a plurality of first data and a plurality of second data, and a function of performing a function operation using the sum of products as an input value. The sum-of-products operation circuit also has, for example, a function of performing an operation of a hierarchical neural network.

[0069] 1 includes, as an example, an area L1 and an area L2. Each of the areas L1 and L2 includes, as an example, a cell array CA, a circuit WCS, a circuit WSD, and a circuit ITS. Furthermore, unlike the area L2, the area L1 includes a circuit XCS.

[0070] In each of the regions L1 and L2, the cell array CA has, as an example, a plurality of arithmetic cells arranged in a matrix. Furthermore, as an example, the cell array CA is divided into a plurality of subarrays. Specifically, for example, in each of the regions L1 and L2, the plurality of arithmetic cells arranged in the cell array CA are divided into subarrays SA_1 to SA_p (where p is an integer of 2 or greater).

[0071] In the region L1, each of the subarrays SA_1 to SA_p has, as an example, a plurality of cells IM that function as calculation cells. In particular, in each of the subarrays SA_1 to SA_p included in the region L1, the cells IM are arranged in a matrix of m rows and n columns (m is an integer equal to or greater than 1, and n is an integer equal to or greater than 1). Therefore, in FIG. 1, the cell array CA is provided with m×n×p cells IM.

[0072] In region L2, each of subarrays SA_1 to SA_p has, for example, a plurality of cells IM that function as calculation cells. In particular, in each of subarrays SA_1 to SA_p included in region L2, the cells IM are arranged in a matrix of n rows and k columns (k is an integer equal to or greater than 1). Therefore, in FIG. 1, the cell array CA is provided with n×k×p cells IM.

[0073] Here, by setting k = n, the number of columns of the cell array CA in region L1 becomes equal to the number of columns of the cell array CA in region L2. By making the number of columns of the cell array CA in region L1 equal to the number of columns of the cell array CA in region L2, the cells IM can be arranged efficiently when the arithmetic circuit 10 is viewed as a whole, and therefore the area required to form the arithmetic circuit 10 can be reduced.

[0074] Note that the brackets [, ] attached to the cell IM shown in FIG. 1 indicate the address within the subarray in which the cell IM is located. For example, cell IM[x, y] indicates that the cell IM[x, y] is located in row x and column y of the subarray.

[0075] In the region L1, the circuit WCS is electrically connected to the wirings WCL[1]_1 to WCL[n]_1 and the wirings WCL[1]_p to WCL[n]_p, for example. Although not shown in FIG. 1 , when p is 3 or greater, the circuit WCS is also electrically connected to the wirings WCL[1] to WCL[n] in subarrays SA other than the subarrays SA_1 and SA_p. Furthermore, the circuit ITS is electrically connected to the wirings WCL[1]_1 to WCL[n]_1 and the wirings WCL[1]_p to WCL[n]_p, for example. Although not shown in FIG. 1 , when p is 3 or greater, the circuit ITS is also electrically connected to the wirings WCL[1] to WCL[n] in subarrays SA other than the subarrays SA_1 and SA_p.

[0076] Furthermore, each of the wirings WCL[1]_1 to WCL[n]_1 is electrically connected to a cell IM included in the subarray SA_1. Specifically, the wiring WCL[1]_1 is electrically connected to the cells IM[1,1] to IM[m,1] arranged in the first column of the subarray SA_1, and the wiring WCL[n]_1 is electrically connected to the cells IM[1,n] to IM[m,n] arranged in the nth column of the subarray SA_1. Furthermore, each of the wirings WCL[1]_p to WCL[n]_p is electrically connected to a cell IM included in the subarray SA_p. Specifically, wiring WCL[1]_p is electrically connected to cells IM[1,1] to IM[m,1] arranged in the first column of subarray SA_p, and wiring WCL[n]_p is electrically connected to cells IM[1,n] to IM[m,n] arranged in the nth column of subarray SA_p.

[0077] In the region L1, the circuit XCS is, for example, electrically connected to the wirings XCL[1] to XCL[m].

[0078] The wirings XCL[1] to XCL[m] are electrically connected to the cells IM included in each of the subarrays SA_1 to SA_p. Specifically, the wiring XCL[1] is electrically connected to the cells IM[1,1] to IM[1,n] arranged in the first row of each of the subarrays SA_1 to SA_p. The wiring XCL[m] is electrically connected to the cells IM[m,1] to IM[m,n] arranged in the mth row of each of the subarrays SA_1 to SA_p.

[0079] In the region L1, the circuit WSD is electrically connected to the wirings WSL[1] to WSL[m], for example.

[0080] The wirings WSL[1] to WSL[m] are electrically connected to the cells IM included in each of the subarrays SA_1 to SA_p. Specifically, the wiring WSL[1] is electrically connected to the cells IM[1,1] to IM[1,n] arranged in the first row of each of the subarrays SA_1 to SA_p. The wiring WSL[m] is electrically connected to the cells IM[m,1] to IM[m,n] arranged in the mth row of each of the subarrays SA_1 to SA_p.

[0081] The circuit ITS included in the region L1 is electrically connected to the wirings OL[1]_1 to OL[n]_1 and the wirings OL[1]_p to OL[n]_p. Although not shown in FIG. 1, when p is 3 or greater, the circuit ITS is also electrically connected to the wirings OL[1]_s to OL[n]_s (where s is an integer greater than or equal to 2 and less than or equal to p-1).

[0082] Furthermore, each of the wirings OL[1]_1 to OL[n]_1 included in region L1 is electrically connected to each of the wirings XCL[1]_1 to XCL[n]_1 included in region L2 in a one-to-one relationship, and each of the wirings OL[1]_p to OL[n]_p included in region L1 is electrically connected to each of the wirings XCL[1]_p to XCL[n]_p included in region L2 in a one-to-one relationship.

[0083] In the region L2, the circuit WCS is electrically connected to, for example, wirings WCL[1]_1 to WCL[k]_1 and wirings WCL[1]_p to WCL[k]_p. Note that although not shown in FIG. 1, when p is 3 or more, the circuit WCS is also electrically connected to wirings WCL[1] to WCL[n] in subarrays SA other than the subarrays SA_1 and SA_p.

[0084] Furthermore, wiring WCL[1]_1 is electrically connected to wiring WCL[1]_p. Although not shown in FIG. 1 , when p is 3 or more, wirings WCL[1]_2 to WCL[1]_p-1 extending in the first column of each of different sub-arrays SA are electrically connected to wiring WCL[1]_1. Furthermore, wiring WCL[k]_1 is electrically connected to wiring WCL[k]_p. Although not shown in FIG. 1 , when p is 3 or more, wirings WCL[k]_2 to WCL[k]_p-1 extending in the k-th column of each of different sub-arrays SA are electrically connected to wiring WCL[k]_1.

[0085] Furthermore, each of the wirings WCL[1]_1 to WCL[k]_1 is electrically connected to a cell IM included in the subarray SA_1. Specifically, the wiring WCL[1]_1 is electrically connected to the cells IM[1,1] to IM[n,1] arranged in the first column of the subarray SA_1, and the wiring WCL[k]_1 is electrically connected to the cells IM[1,k] to IM[n,k] arranged in the kth column of the subarray SA_1. Furthermore, each of the wirings WCL[1]_p to WCL[k]_p is electrically connected to a cell IM included in the subarray SA_p. Specifically, wiring WCL[1]_p is electrically connected to cells IM[1,1] to IM[n,1] arranged in the first column of subarray SA_p, and wiring WCL[k]_p is electrically connected to cells IM[1,k] to IM[n,k] arranged in the kth column of subarray SA_p.

[0086] In region L2, wirings XCL[1]_1 to XCL[n]_1 are electrically connected to cells IM included in the subarray SA_1. Specifically, wiring XCL[1]_1 is electrically connected to cells IM[1,1] to IM[1,k] arranged in the first row of the subarray SA_1. Wiring XCL[n]_1 is electrically connected to cells IM[n,1] to IM[n,k] arranged in the nth row of the subarray SA_1. Wirings XCL[1]_p to XCL[n]_p are electrically connected to cells IM included in the subarray SA_p. Specifically, wiring XCL[1]_p is electrically connected to cells IM[1,1] to IM[1,k] arranged in the first row of the subarray SA_p. The wiring XCL[n]_p is electrically connected to the cells IM[n,1] to IM[n,k] arranged in the n-th row of the subarray SA_p.

[0087] In the region L2, the circuit WSD is electrically connected to the wirings WSL[1] to WSL[n], for example.

[0088] The wirings WSL[1] to WSL[n] are electrically connected to the cells IM included in each of the subarrays SA_1 to SA_p. Specifically, the wiring WSL[1] is electrically connected to the cells IM[1,1] to IM[1,k] arranged in the first row of each of the subarrays SA_1 to SA_p. The wiring WSL[n] is electrically connected to the cells IM[n,1] to IM[n,k] arranged in the nth row of each of the subarrays SA_1 to SA_p.

[0089] In the region L2, the wirings WCL[1]_1 to WCL[k]_1 are electrically connected to the circuit ITS. The circuit ITS is electrically connected to the wirings OL[1] to OL[k].

[0090] Next, the cell IM, the circuit WCS, the circuit XCS, the circuit WSD, and the circuit ITS included in the arithmetic circuit 10 in FIG. 1 will be described.

[0091] The cells IM in the regions L1 and L2 each have a function of holding first data, for example, and outputting a current corresponding to the product of the first data and the second data to the wiring WCL when a signal representing second data is input to the cells IM.

[0092] For example, the circuit WCS in the region L1 has a function of supplying a signal (e.g., a current and / or a voltage) corresponding to the first data to the wirings WCL[1]_1 to WCL[n]_1 and the wirings WCL[1]_p to WCL[n]_p. Note that when p is 3 or greater, the circuit WCS also has a function of supplying a signal corresponding to the first data to the wirings WCL[1] to WCL[n] in subarrays SA other than the subarray SA_1 and the subarray SA_p. Furthermore, for example, the circuit WCS in the region L2 has a function of supplying a signal (e.g., a current and / or a voltage) corresponding to the first data to the wirings WCL[1]_1 to WCL[k]_1 and the wirings WCL[1]_p to WCL[k]_p. That is, the circuit WCS has a function of supplying the first data to be stored in the cell IM when the write transistor included in the cell IM is on.

[0093] For example, the circuit XCS in the region L1 has a function of supplying a signal (e.g., one or both of a current and a voltage) corresponding to second data or reference data (to be described later) to the wirings XCL[1] to XCL[m]. That is, in the arithmetic circuit 10 in FIG. 1 , the circuit XCS has a function of supplying a signal (e.g., one or both of a current and a voltage) corresponding to the second data or reference data to each of the cells IM included in the cell array CA in the region L1.

[0094] For example, the circuit WSD in region L1 has a function of selecting a row of the cell array CA to which the first data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[m] when writing first data to each cell of the cell array CA. For example, the circuit WSD can supply a high-level potential to the wiring WSL[1] and a low-level potential to the wirings WSL[2] (not shown) to WSL[m] to turn on a write transistor having a gate electrically connected to the wiring WSL[1] and turn off write transistors having gates electrically connected to each of the wirings WSL[2] to WSL[m]. Similarly to the circuit WSD in region L1, for example, the circuit WSD in region L2 has a function of selecting a row of the cell array CA to which the first data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[n] when writing first data to each cell of the cell array CA.

[0095] For example, the circuit ITS in the region L1 has a function of converting the amount of current input from each of the wirings WCL[1]_1 to WCL[n]_1 and the wirings WCL[1]_p to WCL[n]_p into a voltage value. Meanwhile, for example, the amount of current flowing from the wiring WCL[1]_1 to the circuit ITS is the sum of the amounts of current output from each of the cells IM[1,1] to IM[m,1] in the first column of the subarray SA_1. That is, the sum of the amounts of current corresponds to the result of multiplying and accumulating the multiple first data held in each of the cells IM[1,1] to IM[m,1] and the multiple second data input to each of the cells IM[1,1] to IM[m,1]. Therefore, the circuit ITS generates a voltage value corresponding to the sum of the multiple first data and the multiple second data from the sum of the amounts of current. The circuit ITS may also have a function of converting the voltage value into a current amount.

[0096] The circuit ITS also has a function of transmitting the voltage, a current converted from the voltage, or the like, as a signal to each of the wirings OL[1]_1 to OL[n]_1 and the wirings OL[1]_p to OL[n]_p. Specifically, the circuit ITS has a function of outputting a signal corresponding to the amount of current input from the wiring WCL[1]_1 to the wiring OL[1]_1. Similarly, the circuit ITS has a function of outputting a signal corresponding to the amount of current input from the wiring WCL[n]_1 to the wiring OL[n]_1, outputting a signal corresponding to the amount of current input from the wiring WCL[1]_p to the wiring OL[1]_p, and outputting a signal corresponding to the amount of current input from the wiring WCL[n]_p to the wiring OL[n]_p.

[0097] For example, the circuit ITS in the region L2 has a function of converting the amount of current input from each of the wirings WCL[1]_1 to WCL[k]_1 and the wirings WCL[1]_p to WCL[k]_p into a voltage value. Meanwhile, for example, the amount of current flowing from the wirings WCL[1]_1 and WCL[1]_p to the circuit ITS is the sum of the amounts of current output from the cells IM[1,1] to IM[n,1] in the first column of each of the subarrays SA_1 to SA_p. That is, since the total amount of the current corresponds to the result of multiplying and adding the multiple first data held in the cells IM[1,1] to IM[n,1] of the subarrays SA_1 to SA_p by the multiple second data input to the cells IM[1,1] to IM[n,1] of the subarrays SA_1 to SA_p, respectively, the circuit ITS generates a voltage value corresponding to the multiply and add of the multiple first data and the multiple second data from the total amount of the current. The circuit ITS may also have a function of converting the voltage value into the amount of current.

[0098] The circuit ITS also has a function of transmitting the voltage, a current converted from the voltage, or the like, as a signal to each of the wirings OL[1] to OL[k]. Specifically, the circuit ITS has a function of outputting a signal corresponding to the amount of current input from the wirings WCL[1]_1 to WCL[1]_p to the wiring OL[1]. Similarly, the circuit ITS has a function of outputting a signal corresponding to the amount of current input from the wirings WCL[k]_1 to WCL[k]_p to the wiring OL[k]_1.

[0099] In particular, in each of the regions L1 and L2, the circuit ITS may have a function of performing a function operation using a sum of products of a plurality of first data and a plurality of second data as an input value. The circuit ITS may also output the result of the function operation as a signal (e.g., a current and / or a voltage) to the wirings OL[1]_1 to OL[n]_1 and the wirings OL[1]_p to OL[n]_p (wirings OL[1] to OL[k]). The above-described function may be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function.

[0100] As described above, by dividing the cell array CA included in region L2 into subarrays SA_1 to SA_p and inputting a plurality of results of operations performed by the cell array CA included in region L1 and the circuit ITS as signals in the row direction of each of the subarrays SA_1 to SA_p, the cells IM can be efficiently arranged in the arithmetic circuit 10. Furthermore, by setting k=n, the cells IM can be arranged more efficiently. This allows the number of cells IM not used in the operation to be reduced during the operation of the arithmetic circuit 10, thereby increasing the operation efficiency per area of ​​the arithmetic circuit 10.

[0101] 1 illustrates cells IM as arithmetic cells in the cell array CA of the arithmetic circuit 10, but depending on the arithmetic method, dummy arithmetic cells, reference arithmetic cells, etc. may be required in addition to cells IM. Therefore, the arithmetic circuit 10 of FIG. 1 may be provided with separate dummy arithmetic cells or reference arithmetic cells depending on the arithmetic method.

[0102] The arithmetic circuit 10A in FIG. 2 is a modified example of the arithmetic circuit 10 in FIG. 1, and has a circuit configuration in which a reference arithmetic cell is required for a product-sum operation.

[0103] In the region L1, the cell array CA includes, for example, subarrays SA_1 to SA_p, as well as a subarray SAr, which includes, for example, cells IMref[1] to IMref[m].

[0104] For example, the cells IMref[1] to IMref[m] are electrically connected to the wirings WSL[1] to WSL[m] in a one-to-one relationship, respectively. Also, for example, the cells IMref[1] to IMref[m] are electrically connected to the wirings XCL[1] to XCL[m] in a one-to-one relationship, respectively.

[0105] In the region L2, the cell array CA includes, for example, subarrays SAr_1 to SAr_p in addition to subarrays SA_1 to SA_p. The subarrays SAr_1 to SAr_p each include, for example, cells IMref[1] to IMref[n].

[0106] For example, the cells IMref[1] to IMref[n] included in the subarray SAr_1 are electrically connected to the wirings WSL[1] to WSL[n] in a one-to-one relationship. For example, the cells IMref[1] to IMref[n] included in the subarray SAr_1 are electrically connected to the wirings XCL[1]_1 to XCL[n]_1 in a one-to-one relationship. For example, the cells IMref[1] to IMref[n] included in the subarray SAr_p are electrically connected to the wirings WSL[1] to WSL[n] in a one-to-one relationship. For example, the cells IMref[1] to IMref[n] included in the subarray SAr_p are electrically connected to the wirings XCL[1]_p to XCL[m]_p in a one-to-one relationship.

[0107] Next, specific configuration examples of the cell IM and the cell IMref will be described.

[0108] Fig. 3 is a circuit diagram showing a specific example of the configuration of each of the cells IM and IMref of the arithmetic circuit 10A of Fig. 2. Fig. 3 excerpts the subarrays SAr and SA_s (where s is an integer between 1 and p). Fig. 3 also excerpts the circuits WCS, XCS, WSD, and ITS to show their electrical connections with the cell array CA.

[0109] Each of cells IM[1,1] to IM[m,n] has, as an example, a transistor F1, a transistor F2, and a capacitance C5, and each of cells IMref[1] to IMref[m] has, as an example, a transistor F1m, a transistor F2m, and a capacitance C5m.

[0110] In particular, it is preferable that the sizes (e.g., channel length, channel width, transistor configuration, etc.) of the transistor F1 included in each of the cells IM[1,1] to IM[m,n] are equal to each other, and it is also preferable that the sizes of the transistor F2 included in each of the cells IM[1,1] to IM[m,n] are equal to each other. It is also preferable that the sizes of the transistor F1m included in each of the cells IMref[1] to IMref[m] are equal to each other, and it is also preferable that the sizes of the transistor F2m included in each of the cells IMref[1] to IMref[m] are equal to each other. It is also preferable that the sizes of the transistor F1 and the transistor F1m are equal to each other, and it is also preferable that the sizes of the transistor F2 and the transistor F2m are equal to each other.

[0111] By making the transistors equal in size, the electrical characteristics of the transistors can be made approximately equal. Therefore, by making the size of the transistor F1 included in each of the cells IM[1,1] to IM[m,n] equal and making the size of the transistor F2 included in each of the cells IM[1,1] to IM[m,n] equal, the cells IM[1,1] to IM[m,n] can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the source, drain, and gate of the transistor F1, the potentials of the source, drain, and gate of the transistor F2, and the potentials input to each of the cells IM[1,1] to IM[m,n]. Furthermore, by making the size of the transistor F1m included in each of the cells IMref[1] to IMref[m] equal and making the size of the transistor F2m included in each of the cells IMref[1] to IMref[m] equal, for example, the operations and results of the operations of the cells IMref[1] to IMref[m] can be made substantially identical. Under the same conditions, the cells IMref[1] to IMref[m] can perform substantially the same operations. Here, the same conditions refer to, for example, the potentials of the source, drain, and gate of the transistor F1m, the potentials of the source, drain, and gate of the transistor F2m, and the potentials input to the cells IMref[1] to IMref[m].

[0112] Unless otherwise specified, the transistors F1 and F1m are considered to ultimately operate in a linear region when they are in an on state. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to voltages within a range in which they operate in a linear region. However, one aspect of the present invention is not limited to this. For example, one or both of the transistors F1 and F1m may operate in a saturation region when they are in an on state, or may operate in both a linear region and a saturation region.

[0113] Furthermore, unless otherwise specified, the transistors F2 and F2m are considered to operate in the subthreshold region (i.e., in the transistor F2 or F2m, the gate-source voltage is lower than the threshold voltage, more preferably, the drain current increases exponentially with the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are considered to include cases where they are appropriately biased to voltages within the range in which they operate in the subthreshold region. Therefore, the transistors F2 and F2m also include cases where they operate such that an off-current (sometimes called a leakage current) flows between the source and drain.

[0114] For example, one or both of the transistors F1 and F1m are preferably OS transistors. In addition, the channel formation regions of one or both of the transistors F1 and F1m are preferably oxides containing at least one of indium, gallium, and zinc. Alternatively, an oxide containing at least one of indium, an element M (e.g., aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) and zinc may be used instead of the oxide. It is more preferable that one or both of the transistors F1 and F1m have the structure of the transistor described in Embodiment 6.

[0115] By using an OS transistor as one or both of the transistors F1 and F1m, leakage current of one or both of the transistors F1 and F1m can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when one or both of the transistors F1 and F1m are off, leakage current from the retention node to the write word line can be significantly reduced, thereby reducing the number of refresh operations for the potential of the retention node. Furthermore, reducing the number of refresh operations can reduce the power consumption of the arithmetic circuit. Furthermore, by significantly reducing the leakage current from the retention node to the wiring WCL or XCL, the cell can retain the potential of the retention node for a long time, thereby improving the arithmetic accuracy of the arithmetic circuit.

[0116] Furthermore, by using an OS transistor for one or both of the transistors F2 and F2m, the transistors can operate over a wide current range in the subthreshold region, thereby reducing current consumption. Furthermore, by using an OS transistor for the transistors F2 and F2m, the transistors can be manufactured simultaneously with the transistors F1 and F1m, which may shorten the manufacturing process of the arithmetic circuit. One or both of the transistors F2 and F2m can be a transistor containing silicon in a channel formation region (hereinafter referred to as a Si transistor) other than an OS transistor. Examples of silicon that can be used include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and single crystal silicon.

[0117] Incidentally, when semiconductor devices and the like are highly integrated on a chip, the chip may generate heat due to the operation of the circuits. This heat increases the temperature of the transistor, which may change the characteristics of the transistor, resulting in, for example, a change in field-effect mobility or a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, so their field-effect mobility is less likely to change due to temperature changes, and their operating frequency is less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that their drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, the use of OS transistors makes it easy to perform calculations even in high-temperature environments. Therefore, when configuring a semiconductor device that is resistant to heat generation due to operation, it is preferable to use OS transistors as the transistors.

[0118] In each of the cells IM[1,1] to IM[m,n], the first terminal of the transistor F1 is electrically connected to the gate of the transistor F2. The first terminal of the transistor F2 is electrically connected to the wiring VE. The first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2.

[0119] In each of the cells IMref[1] to IMref[m], the first terminal of the transistor F1m is electrically connected to the gate of the transistor F2m. The first terminal of the transistor F2m is electrically connected to the wiring VE. The first terminal of the capacitor C5m is electrically connected to the gate of the transistor F2m.

[0120] 3, back gates are illustrated for the transistors F1, F2, F1m, and F2m. Although the connection configuration of the back gates is not illustrated, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and back gate of the transistor F1 may be electrically connected, or the gate and back gate of the transistor F1m may be electrically connected. Furthermore, for example, in a transistor having a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit or the like, and a potential may be applied to the back gate of the transistor from the external circuit or the like.

[0121] 3 has a back gate, the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistors F1 and F2 shown in FIG. 3 may have a structure without a back gate, that is, a single-gate transistor. Furthermore, some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0122] 3, the transistors F1 and F2 are n-channel transistors, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, some or all of the transistors F1 and F2 may be replaced with p-channel transistors.

[0123] The above-described modifications to the transistor structures and polarities are not limited to the transistors F1 and F2, but also apply to, for example, transistors F1m and F2m, as well as to transistors described elsewhere in the specification or illustrated in other drawings.

[0124] The wiring VE is a wiring for passing current between the first terminal and the second terminal of the transistor F2 of each of the cells IM[1,1], IM[m,1], IM[1,n], and IM[m,n], and also functions as a wiring for passing current between the first terminal and the second terminal of the transistor F2 of each of the cells IMref[1] and IMref[m]. As an example, the wiring VE functions as a wiring for supplying a constant voltage. The constant voltage may be, for example, a low-level potential or a ground potential.

[0125] In the cell IM[1,1], the second terminal of the transistor F1 is electrically connected to the wiring WCL[1]_s, and the gate of the transistor F1 is electrically connected to the wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1]_s, and the second terminal of the capacitor C5 is electrically connected to the wiring XCL[1]. In FIG. 3 , the node NN[1,1] is the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 in the cell IM[1,1].

[0126] In the cell IM[m,1], the second terminal of the transistor F1 is electrically connected to the wiring WCL[1]_s, and the gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1]_s, and the second terminal of the capacitor C5 is electrically connected to the wiring XCL[m]. In FIG. 3 , the node NN[m,1] is the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 in the cell IM[m,1].

[0127] In the cell IM[1,n], the second terminal of the transistor F1 is electrically connected to the wiring WCL[n]_s, and the gate of the transistor F1 is electrically connected to the wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n]_s, and the second terminal of the capacitor C5 is electrically connected to the wiring XCL[1]. In FIG. 3 , the node NN[1,n] is the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 in the cell IM[1,n].

[0128] In the cell IM[m,n], the second terminal of the transistor F1 is electrically connected to the wiring WCL[n]_s, and the gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n]_s, and the second terminal of the capacitor C5 is electrically connected to the wiring XCL[m]. In FIG. 3 , the node NN[m,n] is the connection point between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 in the cell IM[m,n].

[0129] In the cell IMref[1], the second terminal of the transistor F1m is electrically connected to the wiring XCL[1]_s, and the gate of the transistor F1m is electrically connected to the wiring WSL[1]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[1], and the second terminal of the capacitor C5 is electrically connected to the wiring XCL[1]_s. Note that in FIG. 3, the node NNref[1] is the connection point between the first terminal of the transistor F1m, the gate of the transistor F2m, and the first terminal of the capacitor C5 in the cell IMref[1].

[0130] In the cell IMref[m], the second terminal of the transistor F1m is electrically connected to the wiring XCL[m]_s, and the gate of the transistor F1m is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[m], and the second terminal of the capacitor C5 is electrically connected to the wiring XCL[m]_s. Note that in FIG. 3, the node NNref[m] is the connection point between the first terminal of the transistor F1m, the gate of the transistor F2m, and the first terminal of the capacitor C5 in the cell IMref[m].

[0131] Note that nodes NN[1,1] to NN[m,n] and nodes NNref[1] to NNref[m] function as holding nodes for the respective cells.

[0132] In cells IM[1,1] to IM[m,n], for example, when transistor F1 is in an on state, transistor F2 is diode-connected. When transistor F1 is in an on state and a current of an amount I flows from wiring WCL to the second terminal of transistor F2, with the constant voltage provided by wiring VE serving as ground potential (GND), the potential of the gate (node ​​NN) of transistor F2 is determined according to the current amount I. Note that, because transistor F1 is in an on state, the potential of the second terminal of transistor F2 is ideally equal to the potential of the gate (node ​​NN) of transistor F2. By turning transistor F1 off, the potential of the gate (node ​​NN) of transistor F2 is maintained. This allows transistor F2 to pass a current of an amount I between its source and drain, depending on the ground potential of the first terminal of transistor F2 and the potential of the gate (node ​​NN) of transistor F2. In this specification, this operation is referred to as "setting the amount of current flowing between the source and drain of the transistor F2 of the cell IM to I (programming)."

[0133] Next, specific configuration examples of the circuit WCS, the circuit XCS, the circuit WSD, the circuit ITS, and the cell IMref will be described.

[0134] <<Circuit WCS>> The circuit WCS includes, for example, a circuit SWS1 and a circuit WCG_s. The circuit WCG_s also includes, for example, circuits WCSa[1] to WCSa[n].

[0135] The circuit SWS1 includes, for example, switches SW3[1] to SW3[n]. A first terminal of the switch SW3[1] is electrically connected to the wiring WCL[1]_s, a second terminal of the switch SW3[1] is electrically connected to the circuit WCSa[1], and a control terminal of the switch SW3[1] is electrically connected to the wiring SWL1. A first terminal of the switch SW3[n] is electrically connected to the wiring WCL[n]_s, a second terminal of the switch SW3[n] is electrically connected to the circuit WCSa[n], and a control terminal of the switch SW3[n] is electrically connected to the wiring SWL1.

[0136] For example, the wiring SWL1 functions as a wiring for switching between an on state and an off state of each of the switches SW3[1] to SW3[n]. Therefore, a high-level potential or a low-level potential is supplied to the wiring SWL1.

[0137] Each of the switches SW3[1] to SW3[n] may be, for example, an electrical switch such as an analog switch or a mechanical switch. Furthermore, a transistor applicable to the transistor F1 or the transistor F2 may be used as one of the electrical switches. In particular, the transistor is preferably, for example, an OS transistor.

[0138] As described above, the circuit SWS1 functions as a circuit that turns on or off the state between the circuit WCG_s and each of the wirings WCL[1]_s to WCL[n]_s. That is, the circuit SWS1 uses the switches SW3[1] to SW3[n] as switching elements to switch the state between conduction and non-conduction between the circuit WCG_s and each of the wirings WCL[1]_s to WCL[n]_s.

[0139] The circuit WCG_s has a function of supplying a signal of an amount corresponding to the first data to the wirings WCL[1]_s to WCL[n]_s. That is, when the switches SW3[1] to SW3[n] are on, the circuit WCG_s supplies the first data to be stored in each cell IM of the cell array CA. Note that in the case of the arithmetic circuit 10A in FIG. 3, the signal is preferably a current.

[0140] For example, the circuit WCG_s can have the configuration shown in Fig. 4A. Note that Fig. 4A also illustrates a circuit SWS1, a switch SW3, a wiring SWL1, and a wiring WCL in order to show electrical connection of the circuit WCG_s with peripheral circuits.

[0141] The circuit WCG_s has, for example, the same number of circuits WCSa as the number of columns of the sub-array SA. That is, in the case of the arithmetic circuit 10A shown in FIGS.

[0142] The circuit SWS1 also has the same number of switches SW3 as the number of wirings WCL, i.e., n switches SW3.

[0143] 4A can be any one of the switches SW3[1] to SW3[n] included in the arithmetic circuit 10A in Fig. 3. Similarly, the wiring WCL can be any one of the wirings WCL[1] to WCL[n] included in the arithmetic circuit 10A in Fig. 3.

[0144] Therefore, the wirings WCL[1] to WCL[n] are electrically connected to separate circuits WCSa via separate switches SW3.

[0145] The circuit WCSa shown in FIG. 4A includes, as an example, a switch SWW. A first terminal of the switch SWW is electrically connected to a second terminal of the switch SW3, and the second terminal of the switch SWW is electrically connected to a wiring VINIL1. The wiring VINIL1 functions as a wiring that applies an initialization potential to the wiring WCL, and the initialization potential can be a ground potential (GND), a low-level potential, or a high-level potential. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCL, and is turned off otherwise.

[0146] The switch SWW may be, for example, an electrical switch such as an analog switch or a transistor. When a transistor is used as the switch SWW, the transistor may have a structure similar to that of the transistor F1 or the transistor F2. In addition to an electrical switch, a mechanical switch may also be used.

[0147] 4A includes a plurality of current sources CS. Ｋ value) (K is an integer of 1 or more) as a current amount. In this case, the circuit WCSa has a function of outputting the first data of Ｋ The circuit WCSa has, for example, one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the K-th bit as a current. Ｋ−１ There are individual ones.

[0148] 4A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the switch SW3 of the circuit SWS1. The terminal T2 of one current source CS is electrically connected to the wiring DW[1], and the terminals T2 of the two current sources CS are electrically connected to the wiring DW[2]. Ｋ−１ Each of the terminals T2 of the current sources CS is electrically connected to a wiring DW[K].

[0149] The multiple current sources CS of the circuit WCSa each supply the same constant current I Ｗｕｔ from the terminal T1. In practice, errors may occur during the manufacturing stage of the arithmetic circuit 10A due to variations in the electrical characteristics of the transistors included in each current source CS. Therefore, the constant current I output from each of the terminals T1 of the multiple current sources CS is Ｗｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit WCSa is Ｗｕｔ The following explanation will be given assuming that there is no error.

[0150] The wirings DW[1] to DW[K] are electrically connected to a current source CS and receive a constant current I Ｗｕｔ Specifically, for example, when a high-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] outputs a constant current I Ｗｕｔ flows to the second terminal of the switch SW3, and when a low-level potential is applied to the wiring DW[1], the current source CS electrically connected to the wiring DW[1] Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[2], the two current sources CS electrically connected to the wiring DW[2] do not output a total of 2I Ｗｕｔ When a constant current of 2I flows through the second terminal of the switch SW3 and a low-level potential is applied to the wiring DW[2], the current source CS electrically connected to the wiring DW[2] flows through the second terminal of the switch SW3 and a low-level potential is applied to the wiring DW[2]. Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[K], the constant current of the second Ｋ−１ The current sources CS are a total of 2 Ｋ−１ I Ｗｕｔ When a constant current of 1 V flows through the second terminal of the switch SW3 and a low-level potential is applied to the wiring DW[K], the current source CS electrically connected to the wiring DW[K] is Ｋ−１ IＷｕｔ It does not output a constant current.

[0151] The current flowing from one current source CS electrically connected to the wiring DW[1] corresponds to the value of the first bit, the current flowing from two current sources CS electrically connected to the wiring DW[2] corresponds to the value of the second bit, and the amount of current flowing from K current sources CS electrically connected to the wiring DW[K] corresponds to the value of the Kth bit. Here, consider the circuit WCSa when K is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wiring DW[1] and a low-level potential is applied to the wiring DW[2]. At this time, a constant current I is supplied from the circuit WCSa to the second terminal of the switch SW3 of the circuit SWS1. Ｗｕｔ Furthermore, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is applied to the wiring DW[1] and a high level potential is applied to the wiring DW[2]. At this time, a constant current of 2I flows from the circuit WCSa to the second terminal of the switch SW3 of the circuit SWS1. Ｗｕｔ Furthermore, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high-level potential is applied to the wiring DW[1] and the wiring DW[2]. At this time, a constant current of 3I flows from the circuit WCSa to the second terminal of the switch SW3 of the circuit SWS1. Ｗｕｔ Furthermore, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low-level potential is applied to the wiring DW[1] and the wiring DW[2]. At this time, no constant current flows from the circuit WCSa to the second terminal of the switch SW3 of the circuit SWS1.

[0152] 4A illustrates the circuit WCSa when K is an integer of 3 or more, but when K is 1, the circuit WCSa in FIG. 4A may be configured without the current source CS electrically connected to the wirings DW[2] to DW[K]. When K is 2, the circuit WCSa in FIG. 4A may be configured without the current source CS electrically connected to the wirings DW[3] to DW[K].

[0153] Next, a specific example of the configuration of the current source CS will be described.

[0154] The current source CS1 shown in FIG. 5A is a circuit that can be applied to the current source CS included in the circuit WCSa in FIG. 4A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0155] A first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, a second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2, a second terminal of the transistor Tr2 is electrically connected to the terminal T1, and a gate of the transistor Tr2 is electrically connected to the terminal T2, which is also electrically connected to the wiring DW.

[0156] The wiring DW is any one of the wirings DW[1] to DW[K] in FIG. 4A.

[0157] The wiring VDDL functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential.

[0158] When the constant voltage applied by the wiring VDDL is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. In this case, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the subthreshold current range flows between the first and second terminals of the transistor Tr1. When the transistor Tr1 is an OS transistor, the amount of the current is, for example, 1.0×10 −８ A or less, and 1.0 × 10 −１２ A or less is more preferable, and 1.0 × 10 −１５It is more preferable that the current is equal to or less than 1 A. Furthermore, for example, it is more preferable that the current is in a range that increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the current range when operating in the subthreshold region. Note that the current is the above-mentioned I Ｗｕｔ , or I described below Ｘｕｔ is equivalent to

[0159] The transistor Tr2 functions as a switching element. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 functions as a drain, and the second terminal of the transistor Tr2 functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is turned on when a high-level potential is input to the gate of the transistor Tr2, and is turned off when a low-level potential is input to the gate of the transistor Tr2. Specifically, when the transistor Tr2 is on, a current in the subthreshold region flows from the second terminal of the transistor Tr1 to the terminal T1. When the transistor Tr2 is off, the current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

[0160] Note that a circuit applicable to the current source CS included in the circuit WCSa of FIG. 4A is not limited to the current source CS1 of FIG. 5A. For example, while the current source CS1 is configured such that the back gate of transistor Tr2 is electrically connected to the second terminal of transistor Tr2, the back gate of transistor Tr2 may be electrically connected to another wiring. An example of such a configuration is shown in FIG. 5B. In the current source CS2 shown in FIG. 5B, the back gate of transistor Tr2 is electrically connected to wiring VTHL. By electrically connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit or the like, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0161] For example, the current source CS1 has a configuration in which the back gate of transistor Tr1 is electrically connected to the second terminal of transistor Tr1, but a configuration in which a capacitor is used to maintain a voltage between the back gate of transistor Tr2 and the second terminal of transistor Tr2 is also possible. Such a configuration example is shown in FIG. 5C . The current source CS3 shown in FIG. 5C includes transistors Tr1 and Tr2, as well as transistor Tr3 and a capacitor C6. The current source CS3 differs from the current source CS1 in that the second terminal of transistor Tr1 is electrically connected to the back gate of transistor Tr1 via capacitor C6 and that the back gate of transistor Tr1 is electrically connected to the first terminal of transistor Tr3. The current source CS3 also has a configuration in which the second terminal of transistor Tr3 is electrically connected to wiring VTL and the gate of transistor Tr3 is electrically connected to wiring VWL. The current source CS3 can apply a high-level potential to the line VWL to turn on the transistor Tr3, thereby establishing a conductive state between the line VTL and the back gate of the transistor Tr1. At this time, a predetermined potential can be input from the line VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the line VWL to turn off the transistor Tr3, the capacitor C6 can maintain the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1. In other words, by determining the voltage applied to the back gate of the transistor Tr1 by the line VTL, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C6.

[0162] 5D may be used as the current source CS included in the circuit WCSa of FIG. 4A. Current source CS4 is configured such that the back gate of transistor Tr2 in current source CS3 of FIG. 5C is electrically connected to the wiring VTHL instead of the second terminal of transistor Tr2. In other words, current source CS4, like current source CS2 of FIG. 5B, can vary the threshold voltage of transistor Tr2 depending on the potential provided by wiring VTHL.

[0163] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0164] 5A to 5D as the current source CS included in the circuit WCSa of Fig. 4A, the circuit WCSa can output a current corresponding to the K-bit first data. The amount of the current can be, for example, the amount of current flowing between the first terminal and the second terminal within a range in which the transistor F1 operates in the subthreshold region.

[0165] 4B may be used as the circuit WCSa in Fig. 4A. The circuit WCSa in Fig. 4B has a configuration in which the current source CS in Fig. 5A is connected to each of the wirings DW[1] to DW[K]. When the channel width of the transistor Tr1[1] is w[1], the channel width of the transistor Tr1[2] is w[2], and the channel width of the transistor Tr1[K] is w[K], the ratio of the channel widths is w[1]:w[2]:w[K]=1:2:2. Ｋ−１ Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCSa shown in FIG. 4B can output a current corresponding to the K-bit first data, similar to the circuit WCSa in FIG. 4A.

[0166] Note that the transistor Tr1 (including transistors Tr1[1] to Tr1[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3 can be, for example, a transistor that can be used for the transistor F1 or the transistor F2. In particular, OS transistors are preferably used for the transistor Tr1 (including transistors Tr1[1] to Tr1[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3.

[0167] <<Circuit XCS>> The circuit XCS includes, for example, circuits XCSa[1] to XCSa[m].

[0168] In FIG. 3, the circuit XCSa[1] is, for example, electrically connected to the wiring XCL[1], and the circuit XCSa[m] is, for example, electrically connected to the wiring XCL[m].

[0169] The circuit XCSa has a function of supplying a signal having an amount corresponding to the second data to the wirings XCL[1]_s to XCL[n]_s. Note that in the case of the arithmetic circuit 10A in FIG. 3, the signal is preferably a current.

[0170] Fig. 4C is a block diagram showing an example of a circuit XCS that can be applied to the arithmetic circuit 10A of Fig. 2 and Fig. 3. Note that Fig. 4C also shows wiring XCL to show electrical connection between the circuit XCS and peripheral circuits.

[0171] The circuit XCS has, for example, the same number of circuits XCSa and switches SW5 as the number of wirings XCL. That is, the circuit XCS has m circuits XCSa and m switches SW5.

[0172] 4C can be any one of the wirings XCL[1] to XCL[m] included in the arithmetic circuit 10A in Fig. 3. Therefore, the wirings XCL[1] to XCL[m] are electrically connected to first terminals of different switches SW5, and different circuits XCSa are electrically connected to second terminals of the m switches SW5.

[0173] Depending on the circuit configuration of the arithmetic circuit, the circuit XCS in FIG. 4C may be configured without the switch SW5.

[0174] The circuit XCSa shown in FIG. 4C includes, as an example, a switch SWX. A first terminal of the switch SWX is electrically connected to the wiring XCL, and a second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 functions as a wiring that applies an initialization potential to the wiring XCL, and the initialization potential can be a ground potential (GND), a low-level potential, or a high-level potential. The initialization potential applied by the wiring VINIL2 may be equal to the potential applied by the wiring VINIL1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL, and is turned off otherwise.

[0175] The switch SWX may be, for example, a switch applicable to the switch SWW.

[0176] The circuit configuration of the circuit XCSa in Fig. 4C can be substantially the same as that of the circuit WCSa in Fig. 4A. Specifically, the circuit XCSa has a function of outputting reference data as a current amount and a function of outputting L bits (2 Ｌ and a function of outputting second data of the value (L is an integer of 1 or more) as a current amount. In this case, the circuit XCSa has a function of outputting second data of the value (L is an integer of 1 or more) as a current amount. Ｌ The circuit XCSa has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and two current sources CS that output information corresponding to the value of the Lth bit as a current. Ｌ−１ There are individual ones.

[0177] Incidentally, the reference data output as a current by the circuit XCSa can be, for example, information in which the value of the first bit is "1" and the values ​​of the second and subsequent bits are "0".

[0178] In FIG. 4C, the terminal T2 of one current source CS is electrically connected to the wiring DX[1], and each of the terminals T2 of the two current sources CS is electrically connected to the wiring DX[2]. Ｌ−１ Each of the terminals T2 of the current sources CS is electrically connected to the wiring DX[L].

[0179] The multiple current sources CS included in the circuit XCSa are each supplied with the same constant current I Ｘｕｔ from the terminal T1. The wirings DX[1] to DX[L] are electrically connected to the current sources CS and I Ｘｕｔ That is, the circuit XCSa has a function of causing a current amount corresponding to L-bit information transmitted from the wirings DX[1] to DX[L] to flow through the wiring XCL.

[0180] Specifically, consider the circuit XCSa when L is set to 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", a high-level potential is applied to the wiring DX[1] and a low-level potential is applied to the wiring DX[2]. At this time, a constant current I is applied from the circuit XCSa to the wiring XCL. Ｘｕｔ Furthermore, for example, when the value of the first bit is "0" and the value of the second bit is "1", a low level potential is applied to the wiring DX[1] and a high level potential is applied to the wiring DX[2]. At this time, a constant current of 2I flows from the circuit XCSa to the wiring XCL. Ｘｕｔ Furthermore, for example, when the value of the first bit is "1" and the value of the second bit is "1", a high-level potential is applied to the wiring DX[1] and the wiring DX[2]. At this time, a constant current of 3I flows from the circuit XCSa to the wiring XCL. Ｘｕｔflows. Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", a low level potential is applied to the wiring DX[1] and the wiring DX[2]. At this time, no constant current flows from the circuit XCSa to the wiring XCL. Note that in this specification and the like, this may be rephrased as a current of zero amount flows from the circuit XCSa to the wiring XCL. Also, the current of zero amount, I, output by the circuit XCSa Ｘｕｔ , 2I Ｘｕｔ , 3I Ｘｕｔ The second data output by the circuit XCSa can be, in particular, the amount of current I Ｘｕｔ can be the reference data output by the circuit XCSa.

[0181] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCSa, the constant current I output from each of the terminals T1 of the multiple current sources CS is Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCSa is Ｘｕｔ The following explanation will be given assuming that there is no error.

[0182] 5A to 5D can be applied as the current source CS of the circuit XCSa, similar to the current source CS of the circuit WCSa. In this case, the wiring DW shown in FIGS. 5A to 5D can be replaced with the wiring DX. This allows the circuit XCSa to pass a current in the subthreshold current range through the wiring XCL as reference data or L-bit second data.

[0183] 4C can be configured similarly to the circuit WCSa shown in FIG. 4B. In this case, the circuit WCSa shown in FIG. 4B can be replaced with the circuit XCSa, the wiring DW[1] with the wiring DX[1], the wiring DW[2] with the wiring DX[2], the wiring DW[K] with the wiring DX[L], the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0184] <<Circuit WSD>> As described above, when writing first data to the cells IM[1,1] to IM[m,n], the circuit WSD has a function of selecting a row of the cell array CA to which the first data is to be written by supplying a predetermined signal to the wirings WSL[1] to WSL[m]. For example, the circuit WSD can supply a high-level potential to the wiring WSL[1] and a low-level potential to the wirings WSL[2] (not shown) to WSL[m] to turn on the transistor F1 having a gate electrically connected to the wiring WSL[1] and turn off the transistor F1 having a gate electrically connected to each of the wirings WSL[2] to WSL[m], thereby selecting the cell IM electrically connected to the wiring WSL[1] as the cell IM to which the first data is to be written.

[0185] 3, the circuit ITS includes, for example, a circuit SWS2 and a circuit ITG_s. The circuit ITG_s also includes, for example, conversion circuits ITRZ[1] to ITRZ[n].

[0186] The circuit SWS2 includes, for example, switches SW4[1] to SW4[n]. A first terminal of the switch SW4[1] is electrically connected to the wiring WCL[1]_s, a second terminal of the switch SW4[1] is electrically connected to the input terminal of the conversion circuit ITRZ[1], and a control terminal of the switch SW4[1] is electrically connected to the wiring SWL2. A first terminal of the switch SW4[n] is electrically connected to the wiring WCL[n]_s, a second terminal of the switch SW4[n] is electrically connected to the input terminal of the conversion circuit ITRZ[n], and a control terminal of the switch SW4[n] is electrically connected to the wiring SWL2.

[0187] In addition, for example, the output terminal of the conversion circuit ITRZ[1] is electrically connected to a wiring OL[1]_s, and the output terminal of the conversion circuit ITRZ[n] is electrically connected to a wiring OL[n]_s.

[0188] For example, the wiring SWL2 functions as a wiring for switching between an on state and an off state of each of the switches SW4[1] to SW4[n]. Therefore, a high-level potential or a low-level potential is supplied to the wiring SWL2.

[0189] As each of the switches SW4[1] to SW4[n], for example, a switch that can be applied to the switches SW3[1] to SW3[n] can be used.

[0190] As described above, the circuit SWS2 has a function of bringing the wirings WCL[1]_s to WCL[n]_s and the circuit ITG_s into a conductive state or a non-conductive state. That is, the circuit SWS1 uses the switches SW4[1] to SW4[n] as switching elements to switch the conductive state or the non-conductive state between the circuit ITS and each of the wirings WCL[1]_s to WCL[n]_s.

[0191] Each of the conversion circuits ITRZ[1] to ITRZ[n] has a function of converting a current input to an input terminal into a voltage corresponding to the amount of current and outputting the voltage from an output terminal. The voltage can be, for example, an analog voltage or a digital voltage. Each of the conversion circuits ITRZ[1] to ITRZ[n] may include a functional arithmetic circuit. In this case, for example, the arithmetic circuit may perform a function calculation using the converted voltage, and the calculation result may be output to the wirings OL[1]_s to OL[n]_s.

[0192] The conversion circuit ITRZ1 shown in Fig. 6 is an example of a circuit that can be applied to the conversion circuits ITRZ[1] to ITRZ[n] in Fig. 3. Note that Fig. 6 also illustrates a circuit SWS2, a wiring WCL, a wiring SWL2, a switch SW4, and a wiring OL to show electrical connection between the conversion circuit ITRZ1 and peripheral circuits. The wiring WCL is any one of the wirings WCL[1] to WCL[n] included in the arithmetic circuit 10A in Fig. 3, the switch SW4 is any one of the switches SW4[1] to SW4[n] included in the arithmetic circuit 10A in Fig. 3, and the wiring OL is any one of the wirings OL[1]_s to OL[n]_s included in the arithmetic circuit 10A in Fig. 3.

[0193] 6 is electrically connected to the wiring WCL via a switch SW4. The conversion circuit ITRZ1 is also electrically connected to the wiring OL. The conversion circuit ITRZ1 converts the amount of current flowing from the conversion circuit ITRZ1 to the wiring WCL or the amount of current flowing from the wiring WCL to the conversion circuit ITRZ1 into an analog voltage, converts the analog voltage into a digital voltage and then into an analog current, and outputs the analog current to the wiring OL.

[0194] The conversion circuit ITRZ1 in FIG. 6 includes, for example, a load LE, an operational amplifier OP1, an analog-to-digital conversion circuit ADC, and a circuit ZCSa.

[0195] The inverting input terminal of the operational amplifier OP1 is electrically connected to a first terminal of the load LE and a second terminal of the switch SW4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to a wiring VRL. The output terminal of the operational amplifier OP1 is electrically connected to a second terminal of the load LE and an input terminal of the analog-to-digital conversion circuit ADC. The output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the circuit ZCSa via a wiring DZ. The circuit ZCSa is electrically connected to a wiring OL.

[0196] The wiring VRL functions as a wiring that applies a constant voltage, which may be, for example, a ground potential (GND) or a low-level potential.

[0197] The load LE may be, for example, a resistor, a diode, or a transistor.

[0198] In the conversion circuit ITRZ1, the configuration of the operational amplifier OP1 and the load LE allows the amount of current flowing from the line WCL via the switch SW4 to the inverting input terminal of the operational amplifier OP1 and the first terminal of the load LE, or the amount of current flowing from the inverting input terminal of the operational amplifier OP1 and the first terminal of the load LE to the line WCL via the switch SW4, to be converted into an analog voltage. In addition, the analog voltage is input to the input terminal of the analog-to-digital conversion circuit ADC.

[0199] In particular, by setting the constant voltage provided by the wiring VRL to the ground potential (GND), the inverting input terminal of the operational amplifier OP1 becomes a virtual ground, and therefore the analog voltage output to the wiring OL can be a voltage based on the ground potential (GND).

[0200] For example, the analog-to-digital converter circuit ADC has a function of receiving an analog voltage at an input terminal of the analog-to-digital converter circuit ADC and outputting a digital voltage corresponding to the analog voltage to a wiring DZ.

[0201] Here, the wiring DZ may be one or more wirings. The number of wirings DZ is determined, for example, by the resolution of the analog-digital conversion circuit ADC. For example, if the resolution of the analog-digital conversion circuit ADC is 1 bit, the number of wirings DZ may be one. Also, for example, if the resolution of the analog-digital conversion circuit ADC is 8 bits, the number of wirings DZ may be eight.

[0202] For example, the circuit ZCSa has a function of generating an analog current based on a digital voltage input to the wiring DZ and outputting the analog current to the wiring OL. Specifically, for example, the circuit ZCSa can have a circuit configuration similar to that of the circuit WCSa in FIG. 4A, the circuit WCSa in FIG. 4B, or the circuit XCSa in FIG. 4C. When the circuit XCSa in FIG. 4C is used as the circuit ZCSa, the wirings DX[1] to DX[K] shown in FIG. 4C can be replaced with the wiring DZ.

[0203] 4C is used as the circuit ZCSa, a new logic circuit (not shown) may be provided in the circuit ZCSa. In particular, it is preferable that the input terminals of the logic circuit are electrically connected to the wirings DZ, and that the control terminal of the switch SWX is electrically connected to the output terminal of the logic circuit. Furthermore, it is preferable that the logic circuit be configured such that, when the digital value input to the wiring DZ is "0," the logic circuit outputs a signal that turns the switch SWX on to the output terminal of the logic circuit, and when the digital value input to the wiring DZ is other than "0," the logic circuit outputs a signal that turns the switch SWX off to the output terminal of the logic circuit. This allows the circuit ZCSa to output a potential corresponding to "0" (the potential provided by the wiring VINIL2) to the wiring OL when the digital value input to the wiring DZ is "0."

[0204] Furthermore, the analog-to-digital conversion circuit ADC can be regarded as one of the above-mentioned function-based arithmetic circuits. Therefore, if an arithmetic circuit of a different function system is to be used in the conversion circuit ITRZ1, the analog-to-digital conversion circuit ADC can be replaced with a circuit that performs the desired function operation. Note that the circuit that performs the function operation is preferably configured so that the input is an analog voltage and the output is a digital voltage.

[0205] 3 shows the circuit configuration of region L1 of arithmetic circuit 10A, but the circuit configuration of region L2 of arithmetic circuit 10A in FIG. 2 refers to the individual circuit configurations of arithmetic circuit 10A described in FIG. 3. That is, for example, circuit WCS in region L2 can have the same configuration as circuit WCS in region L1, circuit WSD in region L2 can have the same configuration as circuit WSD in region L1, and circuit ITS in region L2 can have the same configuration as circuit ITS in region L1. Furthermore, subarrays SAr_1 to SAr_p in region L2 can have the same configuration as subarray SAr in region L1.

[0206] The current output from the circuit ITS in region L1 is input to the wirings XCL[1]_1 to XCL[n]_1 and the wirings XCL[1]_p to XCL[n]_p, which extend to the cell array CA in region L2. That is, in region L2, a product-sum operation can be performed on the first data transmitted from the circuit WCS in region L2 and the second data, using the operation result transmitted from the circuit ITS in region L1 as the second data. The circuit ITS in region L2 can also perform a function operation using the result of the product-sum operation as an input value and output the result to the wirings OL[1] to OL[k].

[0207] <Operation Example 1 of Arithmetic Circuit> Next, an operation example of the arithmetic circuit 10A shown in FIG. 3 will be described.

[0208] 7 shows a timing chart of an operation example of the arithmetic circuit 10A of FIG. 7. The timing chart of FIG. 7 shows fluctuations in the potentials of the wiring SWL1, the wiring SWL2, the wiring WSL[i] (i is an integer of 1 to m-1 inclusive), the wiring WSL[i+1], the wiring XCL[i], the wiring XCL[i+1], the node NN[i,j] (j is an integer of 1 to n-1 inclusive), the node NN[i+1,j], the node NNref[i], and the node NNref[i+1] from time T11 to time T23 and in the vicinity thereof. Furthermore, the timing chart of FIG. 7 shows fluctuations in the potentials of the wiring SWL1, the wiring SWL2, the wiring WSL[i] (i is an integer of 1 to m-1 inclusive), the wiring WSL[i+1], the wiring XCL[i], the wiring XCL[i+1], the node NN[i,j] (j is an integer of 1 to n-1 inclusive), the node NN[i+1,j], the node NNref[i], and the node NNref[i+1] from time T11 to time T23 and in the vicinity thereof. Ｆ２[i, j] and the amount of current I flowing between the first terminal and the second terminal of the transistor F2m included in the cell IMref[i] Ｆ２ｍ [i] and the amount of current I flowing between the first terminal and the second terminal of the transistor F2 included in the cell IM[i+1, j]. Ｆ２ [i+1, j] and the amount of current I flowing between the first terminal and the second terminal of the transistor F2m included in the cell IMref[i+1] Ｆ２ｍ The variations of [i+1] and [i+2] are also shown.

[0209] 4A is used as the circuit WCS of the arithmetic circuit 10A, and the circuit XCS of FIG. 4C is used as the circuit XCS of the arithmetic circuit 10A. The circuit XCS may be configured without the switch SW5, i.e., the wiring XCL and the circuit XCSa may be directly and electrically connected. Alternatively, in this operation example, the switch SW5 of the circuit XCS may be always on during operation.

[0210] In this operation example, the potential of the wiring VE is set to the ground potential GND. Before time T11, the potentials of the nodes NN[i,j], NN[i+1,j], NNref[i], and NNref[i+1] are set to the ground potential GND as an initial setting. Specifically, for example, the initialization potential of the wiring VINIL1 in FIG. 4A is set to the ground potential GND, and the switches SWW, SW3, and the transistors F1 included in the cells IM[i,j] and IM[i+1,j] are turned on, thereby setting the potentials of the nodes NN[i,j] and NN[i+1,j] to the ground potential GND. Furthermore, for example, by setting the initialization potential of the wiring VINIL2 in FIG. 4C to the ground potential GND and turning on the switch SWX and the transistors F1m included in the cells IMref[i,j] and IMref[i+1,j], the potentials of the nodes NNref[i,j] and NNref[i+1,j] can be set to the ground potential GND.

[0211] <<From Time T11 to Time T12>> From time T11 to time T12, a high-level potential (denoted as High in FIG. 7) is applied to the wiring SWL1, and a low-level potential (denoted as Low in FIG. 7) is applied to the wiring SWL2. As a result, a high-level potential is applied to the control terminals of the switches SW3[1] to SW3[n], turning on the switches SW3[1] to SW3[n], and a low-level potential is applied to the gates of the switches SW4[1] to SW4[n], turning off the switches SW4[1] to SW4[n].

[0212] Furthermore, between time T11 and time T12, a low-level potential is applied to the wiring WSL[i] and the wiring WSL[i+1]. As a result, a low-level potential is applied to the gates of the transistors F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning off the respective transistors F1 and F1m. Furthermore, a low-level potential is applied to the gates of the transistors F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning off the respective transistors F1 and F1m.

[0213] 4C is the wiring XCL[i] and the wiring XCL[i+1], the potential of the wiring XCL[i] and the wiring XCL[i+1] can be set to the ground potential GND by setting the initialization potential of the wiring VINIL2 to the ground potential GND and turning on the switch SWX.

[0214] 4A , the first data is not input to the wirings DW[1] to DW[K] in the circuits WCSa electrically connected to the wirings WCL[1]_s to WCL[n]_s via separate switches SW3. In this case, a low-level potential is input to each of the wirings DW[1] to DW[K] in the circuits WCSa in FIG. 4A . In addition, from time T11 to time T12, the second data is not input to the wirings DX[1] to DX[L] in the circuits XCSa electrically connected to the wirings XCL[1] to XCL[m] in the circuits XCSa in FIG. 4C . In this case, a low-level potential is input to each of the wirings DX[1] to DX[L] in the circuits XCSa in FIG. 4C .

[0215] Furthermore, between time T11 and time T12, no current flows through the wiring WCL[j]_s, the wiring XCL[i], and the wiring XCL[i+1]. Ｆ２ [i, j], I Ｆ２ｍ [i], I Ｆ２ [i+1,j], I Ｆ２ｍ [i+1] is 0.

[0216] <<From Time T12 to Time T13>> Between time T12 and time T13, a high-level potential is applied to the wiring WSL[i]. As a result, a high-level potential is applied to the gates of the transistors F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning on the transistors F1 and F1m. Between time T12 and time T13, a low-level potential is applied to the wirings WSL[1] to WSL[m] other than the wiring WSL[i]. As a result, the transistors F1 included in the cells IM[1,1] to IM[m,n] other than the i-th row of the cell array CA and the transistor F1m included in the cells IMref[1] to IMref[m] other than the i-th row of the cell array CA are turned off.

[0217] Furthermore, the ground potential GND continues to be applied to the wirings XCL[1] to XCL[m] from before time T12.

[0218] <<From Time T13 to Time T14>> Between time T13 and time T14, the amount of current I is supplied as first data from the circuit WCSa[j] to the wiring WCL[j]_s via the switch SW3[j]. ０ Specifically, when the wiring WCL shown in FIG. 4A is the wiring WCL[j]_s, a signal corresponding to the first data is input to each of the wirings DW[1] to DW[K], and a current I flows from the circuit WCSa to the second terminal of the switch SW3[j]. ０ That is, the value of the K-bit signal input as the first data is α[i,j] (α[i,j] is set to 0 or more, 2 or more). Ｋ -1 or less), then I ０ [i,j]=α[i,j]×I Ｗｕｔ This becomes:

[0219] When α[i, j] is 0, I ０ Since [i, j]=0, strictly speaking, no current flows from the circuit WCSa to the cell array CA via the switch SW3[j]. ０ It may be written as "a current of [i, j] = 0 flows."

[0220] Between time T13 and time T14, the first terminal of the transistor F1 included in the cell IM[i, j] of the i-th row of the cell array CA is in a conductive state between the first terminal of the transistor F1 and the wiring WCL[j]_s, and the first terminals of the transistors F1 included in the cells IM[1, j] to IM[m, j] other than the i-th row of the cell array CA are in a non-conductive state between the first terminal of the transistor F1 and the wiring WCL[j]_s. Therefore, a current amount I flows from the wiring WCL[j] to the cell IM[i, j]. ０ A current of [i, j] flows.

[0221] Incidentally, when the transistor F1 included in the cell IM[i,j] is turned on, the transistor F2 included in the cell IM[i,j] is configured as a diode connection. Therefore, when a current flows from the wiring WCL[j]_s to the cell IM[i,j], the potentials of the gate of the transistor F2 and the second terminal of the transistor F2 become approximately equal. This potential is determined by the amount of current flowing from the wiring WCL[j] to the cell IM[i,j] and the potential of the first terminal of the transistor F2 (here, GND), etc. In this operation example, the amount of current I flows from the wiring WCL[j] to the cell IM[i,j]. ０ As a result of the current flowing through node NN[i,j], the potential of the gate of transistor F2 (node ​​NN[i,j]) becomes V ｇ [i, j]. That is, in the transistor F2, the gate-source voltage is V ｇ [i, j]-GND, and the current flowing between the first terminal and the second terminal of the transistor F2 is the current I ０ [i, j] is set.

[0222] Here, the threshold voltage of the transistor F2 is V ｔｈ When [i, j], the amount of current I when the transistor F2 operates in the subthreshold region ０ [i, j] can be written as follows:

[0223]

[0224] In addition, I ａ is V ｇ [i, j] is V ｔｈ The drain current when [i, j] is the drain current, and J is a correction coefficient determined by the temperature, device structure, etc.

[0225] Furthermore, between time T13 and time T14, the circuit XCS supplies the wiring XCL[i] with a current amount I as reference data. ｒｅｆ０ Specifically, when the wiring XCL shown in FIG. 4C is the wiring XCL[i], a high-level potential is input to the wiring DX[1] and a low-level potential is input to each of the wirings DX[2] to DX[K], and a current I flows from the circuit XCSa to the wiring XCL[i].ｒｅｆ０ In other words, I ｒｅｆ０ =I Ｘｕｔ This becomes:

[0226] Between time T13 and time T14, the first terminal of the transistor F1m included in the cell IMref[i] and the wiring XCL[i] are in a conductive state, so that a current amount I ｒｅｆ０ A current of flows.

[0227] As with cell IM[i, j], when transistor F1m included in cell IMref[i] is turned on, transistor F2m included in cell IMref[i] is configured as a diode connection. Therefore, when current flows from wiring XCL[i] to cell IMref[i], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i] to cell IMref[i] and the potential of the first terminal of transistor F2m (here, GND), etc. In this operation example, a current amount I flows from wiring XCL[i] to cell IMref[i]. ｒｅｆ０ As a result of this current flowing, the potential of the gate of the transistor F2 (node ​​NNref[i]) becomes V ｇｍ [i], and the potential of the wiring XCL[i] at this time is also V ｇｍ That is, in the transistor F2m, the gate-source voltage is V ｇｍ [i]-GND, and the current flowing between the first terminal and the second terminal of the transistor F2m is the current I ｒｅｆ０ is set.

[0228] Here, the threshold voltage of the transistor F2m is V ｔｈｍ When [i] is set, the amount of current I when the transistor F2m operates in the subthreshold region is ｒｅｆ０ can be written as the following formula:

[0229]

[0230] The correction coefficient J is assumed to be the same as that of the transistor F2 included in the cell IM[i, j]. For example, the device structure and size (channel length, channel width) of the transistors are assumed to be the same. Although the correction coefficient J of each transistor varies due to manufacturing variations, it is assumed that the variation is suppressed to a degree that allows the discussion below to be carried out with sufficient accuracy for practical use.

[0231] Here, the weighting coefficient w[i, j], which is the first data, is defined as follows:

[0232]

[0233] Therefore, Equation (1.2), Equation (1.3), I ０ [i,j]=α[i,j]×I Ｗｕｔ , and I ｒｅｆ０ =I Ｘｕｔ Using this, equation (1.1) can be rewritten as the following equation:

[0234]

[0235] The current I output from the current source CS of the circuit WCSa in FIG. Ｗｕｔ and the current I output by the current source CS of the circuit XCSa of FIG. 4C. Ｘｕｔ If and are equal, then w[i,j] = α[i,j]. That is, I Ｗｕｔ And, I Ｘｕｔ If and are equal, α[i, j] corresponds to the value of the first data, so I Ｗｕｔ And, I Ｘｕｔ Preferably, and are equal to each other.

[0236] <<From Time T14 to Time T15>> Between time T14 and time T15, a low-level potential is applied to the wiring WSL[i]. As a result, a low-level potential is applied to the gates of the transistors F1 included in the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i], turning off the transistors F1 and F1m.

[0237] When the transistor F1 included in the cell IM[i, j] is turned off, a potential difference V ｇ [i, j]-V ｇｍ [i] is held. Also, by turning off the transistor F1 included in the cell IMref[i], the capacitance C5m holds 0, which is the difference between the potential of the gate (node ​​NNref[i]) of the transistor F2m and the potential of the wiring XCL[i]. Note that the voltage held by the capacitance C5m is a non-zero voltage (here, for example, V ｄｓ In this case, the potential of the node NNref[i] is V ｄｓ This can be thought of as the sum of the potentials.

[0238] 4C is the wiring XCL[i], the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0239] Therefore, the potentials of nodes NN[i,1] to NN[i,n] change due to capacitive coupling by capacitance C5 contained in each of cells IM[i,1] to IM[i,n] in the i-th row, and the potential of node NNref[i] changes due to capacitive coupling by capacitance C5m contained in cell IMref[i].

[0240] The amount of change in the potential of the nodes NN[i,1] to NN[i,n] is the potential obtained by multiplying the amount of change in the potential of the wiring XCL[i] by a capacitive coupling coefficient determined by the configuration of each of the cells IM[i,1] to IM[i,n] included in the cell array CA. The capacitive coupling coefficient is calculated, for example, from the capacitance of the capacitor C5, the gate capacitance of the transistor F2, and the parasitic capacitance. In each of the cells IM[i,1] to IM[i,n], when the capacitive coupling coefficient due to the capacitor C5 is P, the potential of the node NN[i,j] of the cell IM[i,j] is calculated by multiplying the potential at the time point between time T14 and time T15 by P(V ｇｍ [i] -GND) decreases.

[0241] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to the capacitive coupling by the capacitor C5m included in the cell IMref[i]. When the capacitive coupling coefficient of the capacitor C5m is p, the same as the capacitor C5, the potential of the node NNref[i] of the cell IMref[i] changes from the potential between time T14 and time T15 to P(V ｇｍ [i] -GND) decreases.

[0242] 7, as an example, P = 1. Therefore, the potential of the node NNref[i] becomes GND between time T15 and time T16.

[0243] As a result, the potential of the node NN[i,j] of the cell IM[i,j] drops, so that the transistor F2 is turned off. Similarly, the potential of the node NNref[i] of the cell IMref[i] drops, so that the transistor F2m is also turned off. Therefore, between time T15 and time T16, Ｆ２ [i, j], I Ｆ２ｍ Each of [i] is 0.

[0244] <<From Time T16 to Time T17>> From time T16 to time T17, a high-level potential is applied to the wiring WSL[i+1]_s. As a result, a high-level potential is applied to the gates of the transistors F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning on the transistors F1 and F1m. Furthermore, between time T16 and time T17, a low-level potential is applied to wirings WSL[1]_s to WSL[m]_s other than wiring WSL[i+1]_s, and transistor F1 included in cells IM[1,1] to IM[m,n] other than the i+1th row of the cell array CA and transistor F1m included in cells IMref[1] to IMref[m] other than the i+1th row are in an off state.

[0245] Furthermore, the ground potential GND has been applied to the lines XCL[1] to XCL[m] continuously since before time T16.

[0246] <<From Time T17 to Time T18>> Between time T17 and time T18, the circuit WCS supplies the current amount I as first data to the cell array CA via the switch SW3[j]. ０ Specifically, when the wiring WCL shown in FIG. 4A is the wiring WCL[j]_s, a signal corresponding to the first data is input to each of the wirings DW[1] to DW[K], and a current of a magnitude I flows from the circuit WCSa to the second terminal of the switch SW3[j]. ０ That is, the value of the K-bit signal input as the first data is changed to α[i+1,j] (α[i+1,j] is 0 to 2). Ｋ -1 or less.) ０ [i+1,j]=α[i+1,j]×I Ｗｕｔ This becomes:

[0247] When α[i+1, j] is 0, I ０Since [i+1, j]=0, strictly speaking, no current flows from the circuit WCSa to the cell array CA via the switch SW3[j]. However, in this specification, I ０ As in the case of [i, j] = 0, ０ It may be written as "a current of [i+1, j] = 0 flows."

[0248] At this time, the first terminal of the transistor F1 included in the cell IM[i+1,j] in the i+1th row of the cell array CA is in a conductive state between the wiring WCL[j]_s, and the first terminal of the transistor F1 included in the cells IM[1,j] to IM[m,j] other than the i+1th row of the cell array CA is in a non-conductive state between the wiring WCL[j]_s, so that a current amount I ０ A current of [i+1, j] flows.

[0249] Incidentally, when transistor F1 included in cell IM[i+1,j] is turned on, transistor F2 included in cell IM[i+1,j] is configured as a diode connection. Therefore, when current flows from wiring WCL[j]_s to cell IM[i+1,j], the potentials of the gate of transistor F2 and the second terminal of transistor F2 become approximately equal. This potential is determined by the amount of current flowing from wiring WCL[j]_s to cell IM[i+1,j] and the potential of the first terminal of transistor F2 (here, GND), etc. In this operation example, a current amount I flows from wiring WCL[j] to cell IM[i+1,j]. ０ As a result of the current flowing through node NN[i+1,j], the potential of the gate of transistor F2 (node ​​NN[i+1,j]) becomes V ｇ [i+1, j]. That is, in the transistor F2, the gate-source voltage is V ｇ [i+1, j]-GND, and the current flowing between the first terminal and the second terminal of the transistor F2 is the current I ０ [i+1, j] is set.

[0250] Here, the threshold voltage of the transistor F2 is V ｔｈWhen [i+1, j], the amount of current I when the transistor F2 operates in the subthreshold region ０ [i+1, j] can be written as follows:

[0251]

[0252] The correction coefficient is set to J, which is the same as that of the transistor F2 included in the cell IM[i, j] and the transistor F2m included in the cell IMref[i].

[0253] In addition, between time T17 and time T18, the circuit XCS supplies the wiring XCL[i+1] with a current amount I as reference data. ｒｅｆ０ Specifically, as in the period from time T13 to time T14, when the wiring XCL shown in FIG. 4C is the wiring XCL[i+1], a high-level potential is input to the wiring DX[1] and a low-level potential is input to each of the wirings DX[2] to DX[K], and a current I flows from the circuit XCSa to the wiring XCL[i+1]. ｒｅｆ０ =I Ｘｕｔ is playing.

[0254] Between time T17 and time T18, a state of conduction is established between the first terminal of the transistor F1m included in the cell IMref[i+1] and the wiring XCL[i+1], so that a current amount I ｒｅｆ０ A current of flows.

[0255] As with cell IM[i+1,j], when transistor F1m included in cell IMref[i+1] is turned on, transistor F2m included in cell IMref[i+1,j] is configured as a diode connection. Therefore, when current flows from wiring XCL[i+1] to cell IMref[i+1], the potentials of the gate of transistor F2m and the second terminal of transistor F2m become approximately equal. This potential is determined by the amount of current flowing from wiring XCL[i+1] to cell IMref[i+1] and the potential of the first terminal of transistor F2m (here, GND). In this operation example, a current amount I flows from wiring XCL[i+1] to cell IMref[i+1]. ｒｅｆ０As a result of this current flowing, the gate of the transistor F2m (node ​​NNref[i+1]) is V ｇｍ [i+1], and the potential of the wiring XCL[i+1] at this time is also V ｇｍ That is, in the transistor F2m, the gate-source voltage is V ｇｍ [i+1]-GND, and the current flowing between the first terminal and the second terminal of the transistor F2m is the current I ｒｅｆ０ is set.

[0256] Here, the threshold voltage of the transistor F2m is V ｔｈｍ When [i+1, j], the amount of current I when the transistor F2m operates in the subthreshold region ｒｅｆ０ can be written as the following formula:

[0257]

[0258] The correction coefficient J is the same as that of the transistor F2 included in the cell IM[i+1, j].

[0259] Here, the weighting coefficient w[i+1, j], which is the first data, is defined as follows:

[0260]

[0261] Therefore, Equation (1.6), Equation (1.7), I ０ [i+1,j]=α[i+1,j]×I Ｗｕｔ , and I ｒｅｆ０ =I Ｘｕｔ Using this, equation (1.5) can be rewritten as the following equation:

[0262]

[0263] The current I output from the current source CS of the circuit WCSa in FIG. Ｗｕｔ and the current I output by the current source CS of the circuit XCSa of FIG. 4C. Ｘｕｔ If and are equal, then w[i+1,j] = α[i+1,j]. That is, I Ｗｕｔ And, I Ｘｕｔ If and are equal, α[i+1, j] corresponds to the value of the first data, so I Ｗｕｔ And, IＸｕｔ Preferably, and are equal to each other.

[0264] <<From Time T18 to Time T19>> Between time T18 and time T19, a low-level potential is applied to the wiring WSL[i+1]. As a result, a low-level potential is applied to the gates of the transistors F1 included in the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA and the gate of the transistor F1m included in the cell IMref[i+1], turning off the transistors F1 and F1m.

[0265] When the transistor F1 included in the cell IM[i+1, j] is turned off, a potential difference V ｇ [i+1, j]-V ｇｍ [i+1] is held. Also, by turning off the transistor F1 included in the cell IMref[i+1], the capacitor C5m holds 0, which is the difference between the potential of the gate of the transistor F2m (node ​​NNref[i+1]) and the potential of the wiring XCL[i+1]. Note that the voltage held by the capacitor C5m is a non-zero voltage (here, for example, V ｄｓ In this case, the potential of the node NNref[i+1] is V ｄｓ This can be thought of as the sum of the potentials.

[0266] 4A is the wiring XCL[i+1], the potential for initialization of the wiring VINIL2 can be set to the ground potential GND by turning on the switch SWX.

[0267] Therefore, the potentials of nodes NN[i,1] to NN[i+1,n] change due to capacitive coupling by capacitor C5 contained in each of cells IM[i+1,1] to IM[i+1,n] in the i+1th row, and the potential of node NNref[i+1] changes due to capacitive coupling by capacitor C5m contained in cell IMref[i+1].

[0268] The change in the potential of the nodes NN[i+1,1] to NN[i+1,n] is calculated by multiplying the change in the potential of the wiring XCL[i+1] by a capacitive coupling coefficient determined by the configuration of each of the cells IM[i+1,1] to IM[i+1,n] included in the cell array CA. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, and the like. When the capacitive coupling coefficient of the capacitor C5 in each of the cells IM[i+1,1] to IM[i+1,n] is set to P, which is the same as the capacitive coupling coefficient of the capacitor C5 in each of the cells IM[i,1] to IM[i,n], the potential of the node NN[i+1,j] of the cell IM[i+1,j] is calculated by multiplying the change in the potential of the wiring XCL[i+1] by P(V ｇｍ [i+1] - GND) decreases.

[0269] Similarly, when the potential of the wiring XCL[i+1] changes, the potential of the node NNref[i+1] also changes due to the capacitive coupling by the capacitor C5m included in the cell IMref[i+1]. When the capacitive coupling coefficient of the capacitor C5m is P, the same as the capacitor C5, the potential of the node NNref[i+1] of the cell IMref[i+1] changes from the potential at the time point between time T18 and time T19 to P(V ｇｍ [i+1] - GND) decreases.

[0270] 7, as an example, P = 1. Therefore, the potential of the node NNref[i+1] becomes GND between time T20 and time T21.

[0271] As a result, the potential of the node NN[i+1,j] of the cell IM[i+1,j] drops, so that the transistor F2 is turned off. Similarly, the potential of the node NNref[i+1] of the cell IMref[i+1] drops, so that the transistor F2m is also turned off. Therefore, between time T19 and time T20, Ｆ２ [i+1,j], I Ｆ２ｍ Each of [i+1] is 0.

[0272] <<From Time T20 to Time T21>> A low-level potential is applied to the wiring SWL1 from time T20 to time T21. As a result, a low-level potential is applied to each of the control terminals of the switches SW3[1] to SW3[n], and each of the switches SW3[1] to SW3[n] is turned off.

[0273] <<From Time T21 to Time T22>> A high-level potential is applied to the wiring SWL2 from time T21 to time T22. As a result, a high-level potential is applied to each control terminal of the switches SW4[1] to SW4[n], and each of the switches SW4[1] to SW4[n] is turned on.

[0274] <<From Time T22 to Time T23>> Between time T22 and time T23, the circuit XCS transmits the current amount I as second data to the wiring XCL[i]. ｒｅｆ０ x[i] times x[i]I ｒｅｆ０ Specifically, for example, when the wiring XCL shown in FIG. 4C is a wiring XCL[i], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] depending on the value of x[i], and a current of x[i]I flows from the circuit XCSa to the wiring XCL[i]. ｒｅｆ０ = x[i]I Ｘｕｔ In this operation example, x[i] corresponds to the value of the second data. At this time, the potential of the line XCL[i] is changed from 0 to V ｇｍ [i]+ΔV[i].

[0275] When the potential of the wiring XCL[i] changes, the potentials of the nodes NN[i,1] to NN[i,n] also change due to capacitive coupling by the capacitor C5 included in each of the cells IM[i,1] to IM[i,n] in the i-th row of the cell array CA. Therefore, the potential of the node NN[i,j] of the cell IM[i,j] is V ｇ [i, j]+PΔV[i].

[0276] Similarly, when the potential of the wiring XCL[i] changes, the potential of the node NNref[i] also changes due to capacitive coupling by the capacitor C5m included in the cell IMref[i]. Therefore, the potential of the node NNref[i] of the cell IMref[i] is V ｇｍ [i]+PΔV[i].

[0277] As a result, the amount of current I flowing between the first terminal and the second terminal of the transistor F2 from time T22 to time T23 is １ [i, j], the amount of current I flowing between the first terminal and the second terminal of the transistor F2m ｒｅｆ１ [i, j] can be written as follows:

[0278]

[0279]

[0280] Note that x[i] is as follows:

[0281]

[0282] Therefore, equation (1.9) can be rewritten as the following equation using equations (1.4) and (1.11).

[0283]

[0284] In other words, the amount of current flowing between the first terminal and the second terminal of transistor F2 included in cell IM[i,j] is proportional to the product of the first data w[i,j] and the second data x[i].

[0285] In addition, between time T22 and time T23, the circuit XCS transmits the current amount I as second data to the wiring XCL[i+1]. ｒｅｆ０x[i+1]I, which is x[i+1] times ｒｅｆ０ Specifically, for example, when the wiring XCL shown in FIG. 4C is the wiring XCL[i+1], a high-level potential or a low-level potential is input to each of the wirings DX[1] to DX[K] depending on the value of x[i+1], and a current of x[i+1] flows from the circuit XCSa to the wiring XCL[i+1]. ｒｅｆ０ = x[i+1]I Ｘｕｔ In this operation example, x[i+1] corresponds to the value of the second data. At this time, the potential of the line XCL[i+1] changes from 0 to V ｇｍ It is assumed that the voltage V changes to [i+1]+ΔV[i+1].

[0286] When the potential of the wiring XCL[i+1] changes, the potentials of the nodes NN[i+1,1] to NN[i+1,n] also change due to capacitive coupling by the capacitor C5 included in each of the cells IM[i+1,1] to IM[i+1,n] in the i+1th row of the cell array CA. Therefore, the potential of the node NN[i+1,j] of the cell IM[i+1,j] is V ｇ [i+1, j]+PΔV[i+1].

[0287] Similarly, when the potential of the wiring XCL[i+1] changes, the potential of the node NNref[i+1] also changes due to capacitive coupling by the capacitor C5m included in the cell IMref[i+1]. Therefore, the potential of the node NNref[i+1] of the cell IMref[i+1] becomes V ｇｍ [i+1]+PΔV[i+1].

[0288] As a result, the amount of current I flowing between the first terminal and the second terminal of the transistor F2 from time T22 to time T23 is １ [i+1, j], the amount of current I flowing between the first terminal and the second terminal of the transistor F2m ｒｅｆ１ [i+1, j] can be written as follows:

[0289]

[0290]

[0291] Note that x[i+1] is expressed as follows:

[0292]

[0293] Therefore, equation (1.13) can be rewritten as the following equation using equations (1.8) and (1.15).

[0294]

[0295] In other words, the amount of current flowing between the first terminal and the second terminal of transistor F2 included in cell IM[i+1,j] is proportional to the product of the first data w[i+1,j] and the second data x[i+1].

[0296] Here, consider the total amount of current flowing from the conversion circuit ITRZ[j] to the cell IM[i, j] and the cell IM[i+1, j] via the switch SW4[j] and the wiring WCL[j]_s. The total amount of current is I Ｓ [j], then I Ｓ [j] can be expressed by the following equation from equations (1.12) and (1.16).

[0297]

[0298] Therefore, the amount of current output from the conversion circuit ITRZ[j] is proportional to the sum of the products of the weighting coefficients w[i,j] and w[i+1,j], which are the first data, and the neuron signal values ​​x[i] and x[i+1], which are the second data.

[0299] In the above example of operation, the sum of the amounts of current flowing through the cells IM[i,j] and IM[i+1,j] is considered, but the sum of the amounts of current flowing through each of the cells IM[1,j] to IM[m,j] may also be considered. In this case, equation (1.17) can be rewritten as the following equation:

[0300]

[0301] Therefore, even in the case of the arithmetic circuit 10A having a cell array CA with three or more rows and multiple columns, it is possible to perform the sum-of-products operation as described above. In this case, the arithmetic circuit 10A selects one of the multiple columns as a current amount Iｒｅｆ０ , and xI ｒｅｆ０ By using a cell that holds the data, it is possible to simultaneously perform multiply-and-accumulate operations for the remaining number of columns among the multiple columns. In other words, by increasing the number of columns in the memory cell array, it is possible to provide a semiconductor device that realizes high-speed multiply-and-accumulate operations.

[0302] 2 described in Configuration Example 2, the configurations of the cell IM and the cell IMref that can be applied to the arithmetic circuit 10A in FIG. 2 are not limited to the cell IM and the cell IMr illustrated in the arithmetic circuit 10A in FIG. 3. The configuration of the semiconductor device of one embodiment of the present invention may be changed depending on the situation as long as the change is within the scope of solving the problem.

[0303] For example, the configurations of the cells IM and IMref shown in Fig. 8 may be applied to the cells IM and IMref of the arithmetic circuit 10A of Fig. 2. Fig. 8 shows, as an example, subarrays SAr and SA_s included in the cell array CA of region L1. Also, similar to the arithmetic circuit 10A of Fig. 3, the subarray SAr has cells IMref[1] to IMref[m], and the subarray SA_s has cells IM[1,1] to IM[m,n].

[0304] Each of cells IM[1,1] to IM[m,n] in Fig. 8 includes a transistor F5 in addition to the circuit elements included in cells IM[1,1] to IM[m,n] in Fig. 3. Also, each of cells IMref[1] to IMref[m] in Fig. 8 includes a transistor F5m in addition to the circuit elements included in cells IMref[1] to IMref[m] in Fig. 3.

[0305] Note that the transistors F5 and F5m can be, for example, transistors applicable to the transistors F1, F2, F1m, and F2m. Therefore, for the configurations of the transistors F5 and F5m, refer to the descriptions of the transistors F1, F2, F1m, and F2m.

[0306] 8, the first terminal of the transistor F1 is electrically connected to the gate of the transistor F2. The first terminal of the transistor F2 is electrically connected to the wiring VE. The first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2. The second terminal of the transistor F2 is electrically connected to the first terminal of the transistor F5. The second terminal of the transistor F5 is electrically connected to the second terminal of the transistor F1.

[0307] 8, the first terminal of the transistor F1m is electrically connected to the gate of the transistor F2m. The first terminal of the transistor F2m is electrically connected to the wiring VE. The first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2m. The second terminal of the transistor F2m is electrically connected to the first terminal of the transistor F5m. The second terminal of the transistor F5m is electrically connected to the second terminal of the transistor F1m.

[0308] In the cell IMref[1] and the cells IM[1,1] to IM[1,n] arranged in the first row of the cell array CA, the gates of the transistors F5 and F5m are electrically connected to the wiring CLL[1]. In the cell IMref[m] and the cells IM[m,1] to IM[m,n] arranged in the mth row of the cell array CA, the gates of the transistors F5 and F5m are electrically connected to the wiring CLL[m].

[0309] For example, each of the wirings CCL[1] to CCL[m] functions as a wiring that applies a constant potential. The constant potential can be, for example, a potential higher than 0 V or a potential higher than ground potential.

[0310] 3, the transistor F2 is electrically connected directly to the wiring WCL, and therefore, a change in the amount of current flowing through the wiring WCL may change the potential of the second terminal of the transistor F2. Also, in the configuration of the cell IMref shown in FIG. 3, the transistor F2m is electrically connected directly to the wiring XCL, and therefore, a change in the amount of current flowing through the wiring XCL may change the potential of the second terminal of the transistor F2m. Therefore, the source-drain voltage of the transistor F2 or the transistor F2m may change, and the amount of current flowing through the transistor F2 or the transistor F2m may change.

[0311] 8, by providing transistor F5 in cell IM, the second terminal of transistor F2 is less likely to be directly affected by changes in the potential of wiring WCL. This makes it possible to prevent sudden changes in the potential of the second terminal of transistor F2 caused by changes in the potential of wiring WCL. Similarly, by providing transistor F5m in cell IM, the second terminal of transistor F2m is less likely to be directly affected by changes in the potential of wiring XCL. This makes it possible to prevent sudden changes in the potential of the second terminal of transistor F2m caused by changes in the potential of wiring XCL.

[0312] That is, the transistor F5 has a function of fixing the potential of the second terminal of the transistor F2 or a function of preventing a sudden change in the potential of the second terminal of the transistor F2. Similarly, the transistor F5m has a function of fixing the potential of the second terminal of the transistor F2m or a function of preventing a sudden change in the potential of the second terminal of the transistor F2m.

[0313] Therefore, by applying the cell IM and cell IMref shown in FIG. 8 to the arithmetic circuit 10A of FIG. 2, the operation of the arithmetic circuit 10A can be stabilized.

[0314] Although Figure 8 illustrates an example configuration of the cell array CA in region L1, the configuration of cells IM and IMref in Figure 8 may also be applied to cells IM and IMref included in the cell array CA in region L2.

[0315] <Configuration Example 4> The configuration of the arithmetic circuit 10A in FIG. 2 described in Configuration Example 2 may be modified depending on the situation.

[0316] For example, the configuration of the arithmetic circuit 10A shown in FIG. 2 may be modified as shown in the configuration of the arithmetic circuit 10AA in FIG. The arithmetic circuit 10AA does not include the circuit ITS in the arithmetic circuit 10A. That is, in the arithmetic circuit 10AA in FIG. 9, the wirings WCL[1]_1 to WCL[n]_1 are directly and electrically connected to the wirings OL[1]_1 to OL[n]_1 in a one-to-one relationship, and the wirings WCL[1]_p to WCL[n]_p are directly and electrically connected to the wirings OL[1]_p to OL[n]_p in a one-to-one relationship. Note that, although not shown in FIG. 9, when p is 3 or more, the wirings WCL[1] to WCL[n] in the subarrays SA other than the subarrays SA_1 and SA_p are electrically connected to the corresponding wirings OL.

[0317] 9, for example, the current flowing from the wiring WCL[1]_1 to the wiring OL[1]_1, that is, the sum of the currents output from the cells IM[1,1] to IM[m,1], can be directly passed to the wiring XCL[1]_1 in the region L2. The same can be said for the wirings WCL other than the wiring WCL[1]_1 in the region L1.

[0318] The arithmetic circuit 10AA in Fig. 9 does not include the circuit ITS, and therefore can reduce the circuit area compared to the arithmetic circuit 10A in Fig. 2. Furthermore, the arithmetic circuit 10AA in Fig. 9 can reduce the power consumption required to drive the circuit ITS compared to the arithmetic circuit 10A in Fig. 2.

[0319] <Configuration Example 5> In the arithmetic circuit 10A of configuration example 2, a configuration example of an arithmetic circuit that performs a product-sum operation of first data that is positive or "0" and second data that is positive or "0" has been shown. However, by changing the circuit configuration of the arithmetic circuit 10A, it is possible to configure an arithmetic circuit that can perform a product-sum operation of first data that is positive, negative, or "0" and second data that is positive or "0".

[0320] The arithmetic circuit 10B shown in Figure 10 is a modified example of the arithmetic circuit 10A shown in Figure 2, and differs from the arithmetic circuit 10A in that multiple cells IMr are provided in each of the subarrays SA_1 to SA_p in region L1 and region L2, and multiple wirings WCLr are provided.

[0321] In each of the subarrays SA_1 to SA_p in the region L1 and the region L2, for example, a cell IMr[i,j] (not shown) in the i-th row and j-th column is provided to form a pair with a cell IM[i,j] (not shown). Therefore, in each of the subarrays SA_1 to SA_p, the arithmetic cells of the cells IM and IMr are arranged in a matrix of m rows and 2n columns. Note that in the arithmetic circuit 10B, one pair of the cell IM[i,j] and the cell IMr[i,j] can hold one first datum.

[0322] Furthermore, in each of the subarrays SA_1 to SA_p in the region L1 and the region L2, for example, a wiring WCLr[j] (not shown) in the j-th column is provided to form a pair with a wiring WCL[j] (not shown). That is, for example, in the subarray SA_1, wirings WCL[1]_1 to WCL[n]_1 and wirings WCLr[1]_1 to WCL[n]r_1 extend in the column direction, and in the subarray SA_p, wirings WCL[1]_p to WCL[n]_p and wirings WCLr[1]_p to WCL[n]r_p extend in the column direction.

[0323] In the subarray SA_s in region L1, the cell IMr[i,j] is electrically connected to the wiring XCL[i] and the wiring WSL[i]. The cell IMr[i,j] is also electrically connected to the wiring WCLr[j]_s. In the subarray SA_s in region L2, the cell IMr[j,h] (h is an integer between 1 and k) is electrically connected to the wiring XCL[j]_s and the wiring WSL[j]. The cell IMr[j,h] is also electrically connected to the wiring WCLr[h]_s.

[0324] 2 , the wiring WCL[1]_1 is electrically connected to the wiring WCL[1]_p. Although not shown, when p is 3 or more, the wiring WCL[1]_1 is electrically connected to each of the wirings WCL[1]_2 to WCL[1]_(p-1) extending to the first column of each of the different subarrays SA. The wiring WCL[k]_1 is electrically connected to the wiring WCL[k]_p. Although not shown, when p is 3 or more, the wiring WCL[k]_1 is electrically connected to each of the wirings WCL[k]_2 to WCL[k]_(p-1) extending to the k-th column of each of the different subarrays SA.

[0325] Furthermore, in region L2, wiring WCLr[1]_1 is electrically connected to wiring WCLr[1]_p. Although not shown, when p is 3 or more, wirings WCLr[1]_2 to WCLr[1]_(p-1) extending in the first column of each of different sub-arrays SA are electrically connected to wiring WCLr[1]_1. Furthermore, wiring WCLr[k]_1 is electrically connected to wiring WCLr[k]_p. Although not shown, when p is 3 or more, wirings WCLr[k]_2 to WCLr[k]_(p-1) extending in the k-th column of each of different sub-arrays SA are electrically connected to wiring WCLr[k]_1.

[0326] In the subarray SA_s in the region L1, the circuit ITS acquires a difference between the amounts of current flowing through the wirings WCL[j]_s and WCLr[j]_s and outputs information corresponding to the difference (for example, a current and / or a voltage) to the wiring OL[j]_s. In the region L2, the circuit ITS acquires the sum of the amounts of current flowing through the wirings WCL[j]_1 to WCL[j]_p located in the j-th column of each subarray SA and the sum of the amounts of current flowing through the wirings WCLr[j]_1 to WCLr[j]_p located in the j-th column of each subarray SA and outputs information corresponding to the difference (for example, a current and / or a voltage) to the wiring OL[j].

[0327] As an example, the cells IM can have the same configuration as the cells IM[1,1] to IM[m,n] included in the cell array CA of the arithmetic circuit 10A in FIG.

[0328] Next, an example of the configuration of the cell IM, cell IMr, cell IMref, etc. that can be applied to the arithmetic circuit 10B in FIG. 10 will be described.

[0329] Fig. 11 is a circuit diagram showing a specific example of the configuration of each of the cells IM, IMr, IMref, circuit WCS, and circuit ITS of the arithmetic circuit 10B of Fig. 10. Note that Fig. 11 excerpts the subarrays SAr and SA_s. Fig. 11 also includes the circuit WCS and circuit WSD to show the electrical connection with the cell array CA.

[0330] Furthermore, cell IMr can have the same configuration as cell IM. Cell IMr in Figure 11 is illustrated as having the same configuration as cell IM, as an example. Furthermore, in order to distinguish between the transistors, capacitances, etc. included in cell IM and cell IMr, the symbols indicating the transistors and capacitances included in cell IMr are appended with "r."

[0331] Specifically, cell IMr has transistor F1r, transistor F2r, and capacitance C5r. Note that transistor F1r corresponds to transistor F1 of cell IM, transistor F2r corresponds to transistor F2 of cell IM, and capacitance C5r corresponds to capacitance C5 of cell IM. Therefore, for the electrical connection configurations of transistor F1r, transistor F2r, and capacitance C5r, please refer to the above description of cells IM[1,1] to IM[m,n].

[0332] In the cell IMr, the connection point between the first terminal of the transistor F1r, the gate of the transistor F2r, and the first terminal of the capacitor C5r is defined as a node NNr.

[0333] In the cell IM[1,j], the second terminal of the capacitor C5 is electrically connected to the wiring XCL[1], the gate of the transistor F1 is electrically connected to the wiring WSL[1], and the second terminals of the transistors F1 and F2 are electrically connected to the wiring WCL[j]_s. In the cell IMr[1,j], the second terminal of the capacitor C5r is electrically connected to the wiring XCL[1], the gate of the transistor F1r is electrically connected to the wiring WSL[1], and the second terminals of the transistors F1r and F2r are electrically connected to the wiring WCLr[j]_s.

[0334] Similarly, in the cell IM[m,j], the second terminal of the capacitor C5 is electrically connected to the wiring XCL[m], the gate of the transistor F1 is electrically connected to the wiring WSL[m], and the second terminals of the transistors F1 and F2 are electrically connected to the wiring WCL[j]_s. Also, in the cell IMr[m,j], the second terminal of the capacitor C5r is electrically connected to the wiring XCL[m], the gate of the transistor F1r is electrically connected to the wiring WSL[m], and the second terminals of the transistors F1r and F2r are electrically connected to the wiring WCLr[j].

[0335] 2, each of the wirings WCL[j] and WCLr[j] functions as a wiring for passing a current from the circuit WCS to the cells IM and IMr, for example, and also functions as a wiring for passing a current from the circuit ITS to the cells IM and IMr.

[0336] 11 , the circuit SWS1 includes a switch SW3[j] and a switch SW3r[j]. The first terminal of the switch SW3[j] is electrically connected to the wiring WCL[j], the second terminal of the switch SW3[j] is electrically connected to a circuit WCSa[j] included in the circuit WCG_s (to be described later), and the control terminal of the switch SW3[j] is electrically connected to the wiring SWL1. The first terminal of the switch SW3r[j] is electrically connected to the wiring WCLr[j], the second terminal of the switch SW3r[j] is electrically connected to a circuit WCSb[j] included in the circuit WCG_s (to be described later), and the control terminal of the switch SW3r[j] is electrically connected to the wiring SWL1.

[0337] 11 includes a circuit WCSa[j] and a circuit WCSb[j], for example. The circuit WCSa[j] and the circuit WCSb[j] in FIG. 11 can be configured, for example, as the circuit WCSa shown in FIG. 4A or 4B.

[0338] 11 , the circuit SWS2 includes a switch SW4[j] and a switch SW4r[j]. A first terminal of the switch SW4[j] is electrically connected to the wiring WCL[j], a second terminal of the switch SW4[j] is electrically connected to a conversion circuit ITRZA[j] (described later), and a control terminal of the switch SW4[j] is electrically connected to the wiring SWL2. A first terminal of the switch SW4r[j] is electrically connected to the wiring WCLr[j], a second terminal of the switch SW4r[j] is electrically connected to the conversion circuit ITRZA[j] (described later), and a control terminal of the switch SW4r[j] is electrically connected to the wiring SWL2.

[0339] 11 includes, as an example, a conversion circuit ITRZA[j]. The conversion circuit ITRZA[j] is a circuit corresponding to the conversion circuit ITRZ[j] in the arithmetic circuit 10A in FIG. 2 and has a function of generating a voltage corresponding to the difference between the amount of current flowing from the conversion circuit ITRZA[j] to the wiring WCL[j] and the amount of current flowing from the conversion circuit ITRZA[j] to the wiring WCLr[j], for example, and outputting the voltage to the wiring OL[j]_s.

[0340] 12A shows a specific configuration example of the conversion circuit ITRZA[j]. The conversion circuit ITRZA1 shown in FIG. 12A is an example of a circuit that can be applied to the conversion circuit ITRZA[j] of FIG. 11. Note that FIG. 12A also shows a circuit SWS2, wiring WCL, wiring WCLr, wiring SWL2, switch SW4, and switch SW4r to show electrical connections between the conversion circuit ITRZA1 and peripheral circuits. Furthermore, the wiring WCL and the wiring WCLr can be, for example, the wiring WCL[j] and the wiring WCLr[j] included in the arithmetic circuit 10B of FIG. 11, respectively, and the switches SW4 and SW4r can be, for example, the switches SW4[j] and SW4r[j] included in the arithmetic circuit 10B of FIG. 11.

[0341] The conversion circuit ITRZA1 in FIG. 12A is electrically connected to the wiring WCL via a switch SW4. The conversion circuit ITRZA1 is also electrically connected to the wiring WCLr via a switch SW4r. The conversion circuit ITRZA1 is also electrically connected to the wiring OL. The conversion circuit ITRZA1 has a function of acquiring a differential current between either the amount of current flowing from the conversion circuit ITRZA1 to the wiring WCL via the switch SW4 or the amount of current flowing from the wiring WCL to the conversion circuit ITRZA1 via the switch SW4, and either the amount of current flowing from the conversion circuit ITRZA1 to the wiring WCLr via the switch SW4r or the amount of current flowing from the wiring WCLr to the conversion circuit ITRZA1 via the switch SW4r. The conversion circuit ITRZA1 also has a function of flowing this differential current between the conversion circuit ITRZA1 and the wiring OL.

[0342] The conversion circuit ITRZA1 in FIG. 12A includes, for example, a transistor F6, a current source CI, a current source CIr, and a current mirror circuit CM.

[0343] The second terminal of the switch SW4 is electrically connected to the first terminal of the current mirror circuit CM and the output terminal of the current source CI, and the second terminal of the switch SW4r is electrically connected to the second terminal of the current mirror circuit CM, the output terminal of the current source CIr, and the first terminal of the transistor F6. The input terminal of the current source CI is electrically connected to the wiring VHE, and the input terminal of the current source CIr is electrically connected to the wiring VHE. The third terminal of the current mirror circuit CM is electrically connected to the wiring VSE, and the fourth terminal of the current mirror circuit CM is electrically connected to the wiring VSE.

[0344] A second terminal of the transistor F6 is electrically connected to the wiring OL, and a gate of the transistor F6 is electrically connected to the wiring SWL3.

[0345] As an example, the current mirror circuit CM has the function of flowing an amount of current corresponding to the potential of the first terminal of the current mirror circuit CM between the first terminal and the third terminal of the current mirror circuit CM and between the second terminal and the fourth terminal of the current mirror circuit CM.

[0346] The wiring VHE functions as, for example, a wiring that applies a constant voltage. Specifically, the constant voltage may be, for example, a high-level potential.

[0347] The wiring VSE functions as, for example, a wiring that applies a constant voltage. Specifically, the constant voltage may be, for example, a low-level potential, a ground potential, or the like.

[0348] The wiring SWL3 functions as a wiring for transmitting a signal for switching the transistor F6 on or off, for example. Specifically, for example, a high-level potential or a low-level potential may be input to the wiring SWL3.

[0349] The current source CI has a function of supplying a constant current between the input terminal and output terminal of the current source CI. Also, the current source CIr has a function of supplying a constant current between the input terminal and output terminal of the current source CIr. Note that in the conversion circuit ITRZA1 of FIG. 12A, it is preferable that the magnitude of the current supplied by the current source CI is equal to the magnitude of the current supplied by the current source CIr.

[0350] Here, an example of the operation of the conversion circuit ITRZA1 in FIG. 12A will be described.

[0351] First, the amount of current flowing from the conversion circuit ITRZA1 to the wiring WCL via the switch SW4 is set to I Ｓ The amount of current flowing from the conversion circuit ITRZA1 to the wiring WCLr via the switch SW4r is I Ｓｒ The amount of current flowing from each of the current sources CI and CIr is expressed as I ０ Let's say.

[0352] I Ｓ is the sum of the amounts of currents flowing through the cells IM[1, j] to IM[m, j] located in the j-th column in the arithmetic circuit 10B of FIG. Ｓｒ is the sum of the amounts of currents flowing through the cells IMr[1,j] to IMr[m,j] located in the j-th column in the arithmetic circuit 10B of FIG.

[0353] When a high-level potential is input to the wiring SWL2, the switches SW4 and SW4r are turned on. Therefore, the amount of current flowing from the first terminal to the third terminal of the current mirror circuit CM is I ０ -I Ｓ In addition, the current mirror circuit CM transfers I from the second terminal of the current mirror circuit CM to the second terminal. ０ -I Ｓ A current of flows.

[0354] Next, a high-level potential is input to the wiring SWL3, and the transistor F6 is turned on. At this time, the amount of current flowing through the wiring OL is I ｏｕｔ Then, I ｏｕｔ =I ０ - (I ０ -I Ｓ ) -I Ｓｒ=I Ｓ -I Ｓｒ This becomes:

[0355] Here, a case will be described in which a product-sum operation is performed between first data that is positive, negative, or "0" and second data that is positive or "0" in the arithmetic circuit 10B of Fig. 11. Note that the first data is stored in the cell IM by referring to the example of storing the first data described above.

[0356] When positive first data is held in the cell IM[i,j] and the cell IMr[i,j], the cell IM[i,j] is set so that a current corresponding to the absolute value of the positive first data flows between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j], and the cell IMr[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2r of the cell IMr[i,j]. When negative first data is held in the circuit CES[i,j], the cell IM[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j], and the cell IMr[i,j] is set so that a current corresponding to the absolute value of the negative first data flows between the first terminal and the second terminal of the transistor F2r of the cell IMr[i,j]. Furthermore, when the first data "0" is held in the circuit CES[i,j], the cell IM[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2 of the cell IM[i,j], and the cell IMr[i,j] is set so that no current flows between the first terminal and the second terminal of the transistor F2r of the cell IMr[i,j].

[0357] Here, when second data is input to each of the wirings XCL[1] to XCL[m] of the arithmetic circuit 10B in FIG. 11, the amount of current flowing between the first terminal and the second terminal of the transistor F2 of the cell IM[i, j] and the amount of current flowing between the first terminal and the second terminal of the transistor F2 of the cell IMr[i, j] are proportional to the second data.

[0358] I Ｓ is the sum of the currents flowing through the cells IM[1,j] to IM[m,j] located in the j-th column. Ｓ can be expressed by the following equation (2.1), for example.Ｓ corresponds to the result of multiply-and-accumulate operation between the absolute value of the positive first data and the second data. Ｓｒ is the sum of the currents flowing through the cells IMr[1,j] to IMr[m,j] located in the j-th column. Ｓｒ is the sum of the currents flowing through the cells IMr, and can be expressed, for example, in the same way as in the following equation (2.2). Ｓｒ corresponds to the result of a multiplication and accumulation operation between the absolute value of the negative first data and the second data.

[0359]

[0360] Therefore, the amount of current I flowing through the wiring OL ｏｕｔ =I Ｓ -I Ｓｒ corresponds to the difference between the result of the sum-of-products operation between the absolute value of the positive first data and the second data and the result of the sum-of-products operation between the absolute value of the negative first data and the second data. ｏｕｔ =I Ｓ -I Ｓｒ corresponds to the result of a product-sum operation between the negative, "0", or positive first data held in cells IM[1,j] to IM[m,j] and cells IMr[1,j] to IMr[m,j] and the second data input to each of wirings XCL[1] to XCL[m].

[0361] Incidentally, when the sum of the currents flowing through the cells IM[1,j] to IM[m,j] is greater than the sum of the currents flowing through the cells IMr[1,j] to IMr[m,j], that is, when I Ｓ Ga I Ｓｒ When it is larger than ｏｕｔ becomes a current amount greater than 0 and flows from the conversion circuit ITRZA1 to the wiring OL. On the other hand, when the sum of the current amounts flowing through the cells IM[1,j] to IM[m,j] is smaller than the sum of the current amounts flowing through the cells IMr[1,j] to IMr[m,j], that is, when I Ｓ Ga I Ｓｒ When the voltage Vcc is smaller than I, there is a case where current does not flow from the wiring OL to the conversion circuit ITRZA1. Ｓ Ga I Ｓｒ When it is smaller than ｏｕｔIt can be considered to be approximately 0. Therefore, the conversion circuit ITRZA1 can be regarded as acting as, for example, a ReLU function.

[0362] Note that the hierarchical neural network will be described later in Embodiment 5.

[0363] Further, as the conversion circuit ITRZA of the arithmetic circuit 10 in FIG. 11, for example, the conversion circuit ITRZA2 shown in FIG. 12B may be applied. The conversion circuit ITRZA2 has a circuit configuration that is a combination of the conversion circuit ITRZA1 in FIG. 12A and the conversion circuit ITRZ1 in FIG. 6. As a result, the amount of current flowing between the first terminal and the second terminal of the transistor F6, corresponding to the result of the sum-of-products operation of the first data and the second data, is converted into an analog voltage by the current-voltage conversion circuit composed of the load LE and the operational amplifier OP1. Further, the analog voltage is converted into a digital voltage by an analog-to-digital conversion circuit, and the digital voltage is converted into an analog current by the circuit ZCSa. Thus, unlike the conversion circuit ITRZA1, the conversion circuit ITRZA2 performs current-voltage conversion, analog-to-digital conversion, and analog current, so that the error in the amount of current output to the wiring OL can be made smaller than that of the conversion circuit ITRZA1.

[0364] <Configuration Example 6> Further, the arithmetic circuit 10A in FIG. 2 described in Configuration Example 2 may be changed to the configuration of the arithmetic circuit 10C shown in FIG. 13. The arithmetic circuit 10C in FIG. 13 is different from the arithmetic circuit 10A in that the circuit XCS is provided in the region L2.

[0365] In the region L2, the circuit XCS is electrically connected to the wirings XCL[1]_1 to XCL[n]_1 and the wirings XCL[1]_p to XCL[n]_p.

[0366] As an example, when writing the first data to the cell IM of the cell array CA in the circuit XCS in the region L2 of the arithmetic circuit 10C, the wiring XCL outputs a current amount I ｒｅｆ０ That is, at times T13 to T15, T17 to T19, etc. of the timing chart in FIG. 7, the circuit XCS outputs a current amount I to the wiring XCL ｒｅｆ０is output, and the potential of the wiring XCL is V ｇｍ To do so.

[0367] Furthermore, as an example, the circuit XCS in region L2 of the arithmetic circuit 10C stops outputting current to the wiring XCL when the cell array CA performs an operation. Specifically, in the circuit XCS of FIG. 4C, the switch SW5 is turned off. Instead, a current corresponding to the result of the operation performed by the cell array CA in region L1 is input to the wiring XCL. In other words, at times T22 to T23 in the timing chart of FIG. 7, a current is supplied to the wiring XCL in region L2 from the circuit ITS in region L1.

[0368] As described above, by configuring the arithmetic circuit 10C, when writing the first data to the cell array CA in the region L2, the circuit XCS in the region L2 can pass a reference current through the wiring XCL. By passing a reference current through the wiring XCL when writing the first data, when a current corresponding to the result of the calculation by the cell array CA in the region L1 is input to the wiring XCL, the first data and the second data can be calculated with high accuracy.

[0369] Although each of the above-described arithmetic circuits 10, 10A, 10B, and 10C is configured to have a circuit WCS for writing first data in each of the regions L1 and L2, for example, the circuit WCS in region L1 may be used to write the first data to a cell IM included in the cell array CA in region L2. In other words, each of the above-described arithmetic circuits 10, 10A, 10B, and 10C may not be configured to have a circuit WCS in region L2, but may be configured such that the circuit WCS in region L1 is electrically connected to a plurality of wirings WCL extending to the cell array CA in region L2.

[0370] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be appropriately combined with other configuration examples or drawings.

[0371] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0372] Embodiment 2 In this embodiment, a structural example of a display device in which a semiconductor device of one embodiment of the present invention and a display portion are combined will be described.

[0373] <Configuration Example 1> Fig. 14 shows a configuration example of a display device that combines the semiconductor device described in the above embodiment with a display unit. The display device 100A shown in Fig. 14 has, as an example, a display unit DSP and a circuit unit SIC. Also, while Fig. 14 shows a sensor PDA, the sensor PDA may be disposed inside or outside the display device 100A.

[0374] In FIG. 14, thick wires are depicted as multiple wires or bus wires.

[0375] 14, the display unit DSP has, as an example, a plurality of pixel circuits PX arranged in a matrix. The pixel circuits PX can be, for example, a liquid crystal display device, or a pixel to which a light-emitting device including an organic EL material or a light-emitting device including a light-emitting diode such as a micro LED is applied. Note that in this embodiment, the pixel circuits PX of the display unit DSP will be described as being applied with a light-emitting device including an organic EL material. The brightness of light emitted from a light-emitting device capable of emitting particularly high brightness light is, for example, 500 cd / m ２ or more, preferably 1000 cd / m ２ More than 10000cd / m ２ More preferably, 2000 cd / m or less ２ More than 5000cd / m ２ The following can be used: Note that circuits that can be applied to the display unit DSP, the pixel circuit PX, and the like will be described in detail in Embodiment 4.

[0376] In addition, in FIG. 14, the circuit unit SIC has a peripheral circuit DRV and a functional circuit MFNC.

[0377] The peripheral circuit DRV functions as a peripheral circuit for driving the display unit DSP, for example. Specifically, the peripheral circuit DRV includes, for example, a source driver circuit 11, a digital-to-analog conversion circuit 12, a gate driver circuit 13, and a level shifter 14.

[0378] 14, the functional circuit MFNC may include, for example, a storage device that stores image data to be displayed on the display unit DSP, a decoder that restores encoded image data, a GPU (Graphics Processing Unit) that processes the image data, a power supply circuit, a correction circuit, and a CPU.

[0379] Furthermore, the display device 100A in FIG. 14 is configured such that, as an example, bus lines BSL are electrically connected to the circuits included in the peripheral circuit DRV and the circuits included in the functional circuit MFNC.

[0380] For example, the source driver circuit 11 has a function of transmitting image data to the pixel circuits PX included in the display unit DSP, and is therefore electrically connected to the pixel circuits PX via wirings SL.

[0381] The digital-analog conversion circuit 12 has a function of converting image data that has been digitally processed by a GPU, a correction circuit, etc., which will be described later, into analog data. The image data converted into analog data is transmitted to the display unit DSP via the source driver circuit 11. Note that the digital-analog conversion circuit 12 may be included in the source driver circuit 11, or the image data may be transmitted in the order of the source driver circuit 11, the digital-analog conversion circuit 12, and the display unit DSP.

[0382] For example, the gate driver circuit 13 has a function of selecting a pixel circuit PX to which image data is to be sent in the display unit DSP, and is therefore electrically connected to the pixel circuit PX via a wiring GL.

[0383] The level shifter 14 has a function of converting signals input to the source driver circuit 11, the digital-to-analog conversion circuit 12, the gate driver circuit 13, etc., to appropriate levels, for example.

[0384] The storage device 21 has a function of storing image data to be displayed on the display unit DSP, for example. The storage device 21 can be configured to store image data as digital data or analog data.

[0385] Furthermore, when image data is stored in the storage device 21, it is preferable to use a nonvolatile memory as the storage device 21. In this case, for example, a NAND type memory or the like can be used as the storage device 21.

[0386] Furthermore, when temporary data generated by the GPU 22, the EL correction circuit 23, the CPU 25, etc. is stored in the storage device 21, it is preferable to use a volatile memory as the storage device 21. In this case, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), etc. can be used as the storage device 21.

[0387] For example, the GPU 22 has a function of performing processing to render image data read from the storage device 21 on the display unit DSP. In particular, the GPU 22 is configured to perform parallel pipeline processing, so that it can quickly process image data to be displayed on the display unit DSP. The GPU 22 can also function as a decoder to restore encoded images.

[0388] The functional circuit MFNC may also include multiple circuits capable of improving the display quality of the display unit DSP. For example, such circuits may include a correction circuit (color adjustment, dimming) that detects color unevenness in an image displayed on the display unit DSP and corrects the color unevenness to create an optimal image. Furthermore, if light-emitting devices using organic EL materials (sometimes referred to as organic EL elements) are used in the pixels of the display unit DSP, the functional circuit MFNC may also include an EL correction circuit that corrects variations in the brightness of the light emitted by the multiple organic EL elements. In the present embodiment, the pixel circuits PX of the display unit DSP are described as using light-emitting devices containing organic EL materials, and therefore the functional circuit MFNC includes an EL correction circuit 23, for example.

[0389] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through a display device (or the voltage applied to the display device) provided in a pixel may be monitored and acquired, and the image displayed on the display unit DSP may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network calculation), and the output result may be used to determine whether or not the image should be corrected.

[0390] Furthermore, AI calculations can be applied not only to image correction but also to up-conversion (down-conversion) of image data, which allows high-quality images to be displayed on the display DSP by up-converting (down-converting) low-resolution image data to match the resolution of the display DSP.

[0391] The above-described artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit MFNC. That is, various correction calculations can be performed using the GPU 22. Examples of the various correction calculations include color shading correction and up-conversion processing (down-conversion processing). As shown in FIG. 14, the GPU 22 may be configured to include a circuit 22a that performs color shading correction and a circuit 22b that performs up-conversion (down-conversion).

[0392] In this specification, a GPU that performs computations for artificial intelligence is referred to as an AI accelerator. That is, in this specification, the GPU provided in the functional circuit MFNC may be described as an AI accelerator.

[0393] As the arithmetic circuit included in the AI ​​accelerator, for example, the arithmetic circuit 10, arithmetic circuit 10A, arithmetic circuit 10B, etc., which are the semiconductor devices of the above-described embodiments, can be applied.

[0394] For example, the timing controller 24 has a function of arbitrarily setting the frame rate at which images are displayed on the display unit DSP. For example, when a still image is displayed on the display unit DSP, the display device 100A can be driven by the timing controller 24 at a lower frame rate. Also, for example, when a moving image is displayed on the display unit DSP, the display device 100A can be driven by the timing controller 24 at an increased frame rate. In other words, by providing the timing controller 24 in the display device 100A, the frame rate can be changed depending on whether the image is a still image or a moving image. In particular, when a still image is displayed on the display unit DSP, the frame rate can be lowered, thereby reducing the power consumption of the display device 100A.

[0395] The CPU 25 has a function of performing general-purpose processing such as, for example, executing an operating system, controlling data, performing various calculations, and executing programs. In the display device 100A, the CPU 25 has a role of issuing commands such as writing or reading image data to or from the storage device 21, correcting image data, and operating a sensor (described later). Furthermore, for example, the CPU 25 may have a function of transmitting control signals to at least one of the circuits included in the functional circuit MFNC, such as the storage device, GPU, correction circuit, timing controller, and high-frequency circuit.

[0396] The CPU 25 may also include a circuit (hereinafter referred to as a backup circuit) that temporarily backs up data. It is preferable that the backup circuit be able to retain the data even if, for example, the supply of power supply voltage is stopped. For example, when a still image is displayed on the display unit DSP, the CPU 25 can suspend its function until an image different from the current still image is displayed. Therefore, by temporarily saving data being processed by the CPU 25 to the backup circuit and then stopping the supply of power supply voltage to the CPU 25 to stop the CPU 25, the dynamic power consumption of the CPU 25 can be reduced. Furthermore, in this specification, a CPU having a backup circuit is referred to as an Noff CPU.

[0397] The sensor controller 26 has a function of controlling the sensor PDA, for example. 14 also illustrates a wiring SNCL as a wiring for electrically connecting the sensor PDA and the sensor controller 26.

[0398] The sensor PDA may be, for example, a touch sensor that may be provided above, below, or inside the display unit DSP.

[0399] Alternatively, the sensor PDA may be, for example, an illuminance sensor. In particular, by acquiring the intensity of external light illuminating the display unit DSP using the illuminance sensor, the brightness (luminance) of the image displayed on the display unit DSP can be changed according to the external light. For example, when the external light is bright, the luminance of the image displayed on the display unit DSP can be increased to improve the visibility of the image. Conversely, when the external light is dark, the luminance of the image displayed on the display unit DSP can be decreased to reduce power consumption.

[0400] Alternatively, the sensor PDA may be, for example, an image sensor, which may acquire an image and display the image on the display unit DSP.

[0401] For example, the power supply circuit 27 has a function of generating voltages to be supplied to circuits included in the peripheral circuit DRV, circuits included in the functional circuit MFNC, pixels included in the display unit DSP, etc. The power supply circuit 27 may also have a function of selecting the circuit to which the voltage is supplied. For example, the power supply circuit 27 can reduce the power consumption of the entire display device 100A by stopping the voltage supply to the CPU 25, GPU 22, etc. during a period when a still image is displayed on the display unit DSP.

[0402] <Configuration Example 2> Here, a configuration example will be described in which the sensor PDA is used as an image sensor in the above-described display device 100A to acquire images of one or both of the eye and the surrounding area of ​​the user viewing the displayed image of the display device 100A. Note that the user's eye refers to, for example, one or both of the eyeball and the pupil, and the surrounding area of ​​the user's eye refers to, for example, one or more selected from the eyelid, the space between the eyebrows, the inner corner of the eye, and the outer corner of the eye.

[0403] For example, the sensor PDA can capture images of one or both of the user's eyes and the surrounding area when viewing the image displayed on the display device 100A. The images of the user's eyes and the surrounding area captured by the sensor PDA are transmitted to the GPU 22 (AI accelerator). The GPU 22 can perform inference processing based on an artificial neural network on the basis of the transmitted images.

[0404] 15 shows an example of an operation in which the sensor PDA captures an image of the user's eye and / or its surroundings, and performs inference processing of the neural network based on the captured image. Specifically, Fig. 15 shows an example in which the user's eye ME and its surroundings are captured by a plurality of light receiving elements PD included in the sensor PDA, and the captured image is transmitted to the GPU 22.

[0405] As the sensor PDA shown in FIG. 15, for example, a light receiving element PD shown in FIG. 28A or FIG. 28B, which will be described later in the fourth embodiment, can be applied.

[0406] As described above, the GPU 22 performs inference processing based on an artificial neural network. Specifically, the GPU 22 performs a multiplication and accumulation operation between the captured image and a weighting coefficient determined in advance through learning, and calculates an activation function using the result of the multiplication and accumulation operation, thereby enabling the inference processing based on an artificial neural network. As a result, the output data D obtained by the GPU 22 is ＯＵＴ For example, "whether the eyes are blinking or not," "how open they are," and "body temperature" can be inferred from the user's eyes ME and their surroundings.

[0407] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0408] Embodiment Mode 3 In this embodiment mode, a hierarchical neural network will be described. Note that the operation of the hierarchical neural network can be performed by using the semiconductor device described in the above embodiment mode.

[0409] <Hierarchical Neural Network> As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network ANN shown in FIG. 16A is an example, and the neural network ANN has first to Rth layers (where R can be an integer equal to or greater than four). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 16A illustrates the (k-1)th layer and the kth layer (where k is an integer equal to or greater than three and equal to or less than R-1) as intermediate layers, and does not illustrate the other intermediate layers.

[0410] Each layer of the neural network ANN has one or more neurons. In FIG. 16A, the first layer has neurons N １ （１） Neuron N ｐ （１） (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N １ （ｋ−１） Neuron Nｍ （ｋ−１） (where m is an integer equal to or greater than 1), and the kth layer has neurons N １ （ｋ） Neuron N ｎ （ｋ） (where n is an integer equal to or greater than 1), and the Rth layer has neurons N １ （Ｒ） Neuron N ｑ （Ｒ） (where q is an integer of 1 or greater).

[0411] In addition, in FIG. 16A, the neuron N １ （１） , neuron N ｐ （１） , neuron N １ （ｋ−１） , neuron N ｍ （ｋ−１） , neuron N １ （ｋ） , neuron N ｎ （ｋ） , neuron N １ （Ｒ） , neuron N ｑ （Ｒ） In addition, the (k-1)th layer neuron N ｉ （ｋ−１） (where i is an integer between 1 and m), and the k-th layer neuron N ｊ （ｋ） (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0412] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output to and from each neuron. ｊ （ｋ） Focus on.

[0413] FIG. 16B shows the k-th layer of neurons N ｊ （ｋ） and neuron N ｊ （ｋ） and the signal input to neuron N ｊ （ｋ） 10 shows the signal output from the

[0414] Specifically, the (k-1)th layer neuron N １ （ｋ−１） Neuron N ｍ （ｋ−１） z １ （ｋ−１） ~z ｍ （ｋ−１） But neuron N ｊ （ｋ） The output is directed to the neuron N ｊ （ｋ） is z １ （ｋ−１） ~z ｍ （ｋ−１） Depending on z ｊ （ｋ） and generate z ｊ （ｋ） is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0415] The degree of signal transmission for signals input from neurons in the previous layer to neurons in the next layer is determined by the connection strength (hereinafter referred to as weighting coefficient) of the synapses connecting those neurons. In a neural network (ANN), signals output from neurons in the previous layer are multiplied by the corresponding weighting coefficient before being input to neurons in the next layer. Let i be an integer between 1 and m, and let m be the number of neurons in the (k-1)th layer. ｉ （ｋ−１） and the k-th layer neuron N ｊ （ｋ） The weight coefficient of the synapse between ｉ （ｋ−１） ｊ （ｋ） Then, the k-th layer neuron N ｊ （ｋ） The signal input to can be expressed by equation (3.1).

[0416]

[0417] That is, the (k-1)th layer neuron N １ （ｋ−１） Neuron N ｍ （ｋ−１） From each of these, the k-th layer neuron N ｊ（ｋ） When a signal is transmitted to z １ （ｋ−１） ~z ｍ （ｋ−１） The weighting coefficients (w １ （ｋ−１） ｊ （ｋ） Or w ｍ （ｋ−１） ｊ （ｋ） ) is multiplied by the k-th layer neuron N ｊ （ｋ） For １ （ｋ−１） ｊ （ｋ） ・z １ （ｋ−１） Or w ｍ （ｋ−１） ｊ （ｋ） ・z ｍ （ｋ−１） At this time, the k-th layer neuron N ｊ （ｋ） The sum of the signals input to ｊ （ｋ） is expressed as equation (3.2).

[0418]

[0419] In addition, the weighting coefficient w １ （ｋ−１） ｊ （ｋ） Or w ｍ （ｋ−１） ｊ （ｋ） and the neuron signal z １ （ｋ−１） ~z ｍ （ｋ−１） A bias may be applied to the result of the sum of products of and. When the bias is b, equation (3.2) can be rewritten as the following equation.

[0420]

[0421] Neuron N ｊ （ｋ） Ha, u ｊ （ｋ） In response to ｊ（ｋ） where neuron N ｊ （ｋ） The output signal z from ｊ （ｋ） is defined as follows:

[0422]

[0423] The function f(u ｊ （ｋ） ) is an activation function in a hierarchical neural network, and can be a step function, a linear ramp function, a sigmoid function, etc. The activation function can be the same for all neurons or different for each layer. In addition, the activation functions of neurons in each layer can be the same or different for each layer.

[0424] The signals, weighting coefficients w, and biases b output by neurons in each layer may be analog or digital values. Digital values ​​may be, for example, binary or ternary. Values ​​with even larger bit counts may also be used. For example, in the case of analog values, activation functions such as linear ramp functions and sigmoid functions may be used. In the case of binary digital values, for example, step functions that output −1 or 1, or 0 or 1 may be used. Furthermore, the signals output by neurons in each layer may be ternary or more. In this case, activation functions with ternary values ​​may be used, such as step functions that output −1, 0, or 1, or step functions that output 0, 1, or 2. Furthermore, for example, activation functions that output five values, such as step functions that output −2, −1, 0, 1, or 2, may be used. Using digital values ​​for at least one of the signals, weighting coefficients w, and biases b output by neurons in each layer can reduce the circuit size, power consumption, and computation speed. Furthermore, by using analog values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, and the bias b, the accuracy of the calculation can be improved.

[0425] In the neural network ANN, an input signal is input to the first layer (input layer), and in each layer from the first layer (input layer) to the last layer (output layer), an output signal is generated based on the signal input from the previous layer using formulas (3.1), (3.2) (or (3.3)), and (3.4), and the output signal is output to the next layer. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network ANN.

[0426] When the circuit included in the region L1 of the arithmetic circuit 10 described in the first embodiment is applied as the hidden layer, the weight coefficient w ｓ［ｋ−１］ （ｋ−１） ｓ［ｋ］ （ｋ） (where s[k-1] is an integer between 1 and m, and s[k] is an integer between 1 and n) is used as first data, and the current amount corresponding to the first data is stored in each cell IM in the same column, and the neuron N in the (k-1)th layer ｓ［ｋ−１］ （ｋ−１） The output signal z from ｓ［ｋ−１］ （ｋ−１） is used as second data, and a current amount corresponding to the second data is passed from the circuit XCS to the wiring XCL of each row, whereby the current amount I input to the conversion circuit ITRZ is Ｓ In addition, by using the value of the sum of products to calculate the value of the activation function, the neuron N in the kth layer can be activated using the value of the activation function as a signal. ｓ［ｋ］ （ｋ） The output signal z ｓ［ｋ］ （ｋ） It can be said that:

[0427] In addition, when the circuit included in the region L2 of the arithmetic circuit 10 described in the first embodiment is applied as the output layer, the weighting coefficient w ｓ［Ｒ−１］ （Ｒ−１） ｓ［Ｒ］ （Ｒ） (where s[R-1] is an integer equal to or greater than 1, and s[R] is an integer equal to or greater than 1 and equal to or less than q) is used as first data, and the current amount corresponding to the first data is stored in each cell IM of the same column, and the neuron N ｓ［Ｒ−１］ （Ｒ−１） The output signal z from ｓ［Ｒ−１］（Ｒ−１） is used as second data, and a current amount corresponding to the second data is passed from the circuit XCS to the wiring XCL of each row, whereby the current amount I input to the conversion circuit ITRZ is Ｓ In addition, by using the value of the sum of products to calculate the value of the activation function, the value of the activation function is used as a signal to activate the neuron N in the Rth layer. ｓ［Ｒ］ （Ｒ） The output signal z ｓ［Ｒ］ （Ｒ） It can be said that:

[0428] The input layer described in this embodiment may function as a buffer circuit that outputs an input signal to the second layer.

[0429] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0430] In this embodiment, a display device that can be included in an electronic device according to one embodiment of the present invention will be described. Note that the display device described in this embodiment can be applied to the display unit DSP described in the above embodiment.

[0431] 17 is a cross-sectional view illustrating an example of a display device according to one embodiment of the present invention. As an example, a display device 100 illustrated in FIG. 17 has a structure in which a pixel circuit, a driver circuit, and the like are provided over a substrate 310.

[0432] Specifically, the display device 100 includes, for example, a circuit layer SICL, a wiring layer LINL, and a pixel layer PXAL. The circuit layer SICL includes, for example, a substrate 310, and a transistor 300 is formed on the substrate 310. A wiring layer LINL is provided above the transistor 300, and wiring is provided in the wiring layer LINL to electrically connect to the transistor 300, a transistor 200 (described later), a light-emitting device 150a, a light-emitting device 150b (described later), and the like. A pixel layer PXAL is provided above the wiring layer LINL, and the pixel layer PXAL includes, for example, the transistor 200, a light-emitting device 150 (the light-emitting device 150a and the light-emitting device 150b in FIG. 17 ), and the like.

[0433] The substrate 310 can be, for example, a semiconductor substrate (e.g., a single-crystal substrate) made of silicon or germanium. Other than a semiconductor substrate, the substrate 310 can also be, for example, a silicon-on-insulator (SOI) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Examples of plastics include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device 100 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate 310.

[0434] In this embodiment, the substrate 310 is described as a semiconductor substrate made of silicon.

[0435] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Therefore, the transistor 300 is a Si transistor. Note that although FIG. 17 illustrates a structure in which one of the source and drain of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366, which will be described later, via the conductor 328, the electrical connection structure of the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention may have a structure in which the gate of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366 via the conductor 328.

[0436] The transistor 300 can be a Fin type by, for example, covering the top surface and the side surfaces in the channel width direction of the semiconductor region 313 with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a Fin type, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0437] Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel transistors may be used.

[0438] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a serving as the source region or the drain region, and the low-resistance region 314b preferably contain a silicon-based semiconductor, particularly single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed of a material containing germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (GaAlAs), gallium nitride (GaN), or the like. Furthermore, each of the above-mentioned regions may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be, for example, a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0439] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0440] Note that the work function is determined by the material of the conductor, and therefore the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0441] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0442] 17 is just an example, and the structure of the transistor 300 is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0443] In the transistor 300 shown in FIG. 17, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0444] As insulators 320, 322, 324, and 326, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride may be used.

[0445] The insulator 322 may function as a planarizing film that planarizes steps caused by the insulator 320 and the transistor 300 covered with the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0446] Furthermore, it is preferable to use a barrier insulating film for the insulator 324 that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to a region above the insulator 324 (for example, a region where the transistor 200, the light-emitting device 150a, the light-emitting device 150b, etc. are provided). Therefore, it is preferable to use an insulating material for the insulator 324 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., that the impurities are less likely to permeate). Depending on the situation, the insulator 324 may be made of an insulating material that prevents the diffusion of nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., the impurities are less likely to permeate through it), or that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0447] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD (Chemical Vapor Deposition) method.

[0448] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, in the TDS analysis, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. and the amount of desorption converted into hydrogen atoms is 10×10 １５ atoms / cm ２ Below 5 × 10, preferably １５ atoms / cm ２ The following is fine.

[0449] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0450] Furthermore, conductors 328 and 330 are embedded in the insulators 320, 322, 324, and 326, respectively, to connect to a light-emitting device or the like provided above the insulator 326. The conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0451] The materials for each plug and wiring (conductor 328 and conductor 330) can be one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the plug and wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0452] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 17 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductors 328 and 330.

[0453] Note that, for example, the insulator 350 is preferably an insulator that has barrier properties against hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. The conductor 356 preferably includes a conductor that has barrier properties against hydrogen, oxygen, and water.

[0454] Note that, for example, tantalum nitride is preferably used as the conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0455] In addition, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order on the insulator 354 and the conductor 356.

[0456] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0457] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, a material that can be used for the insulator 324 can be used for one or both of the insulators 362 and 364.

[0458] Furthermore, openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0459] An insulator 370 and an insulator 372 are stacked in this order on the insulator 364 and the conductor 366 .

[0460] The insulator 370 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 370 can be made of, for example, a material that can be used for the insulator 324.

[0461] The insulator 372 functions as an interlayer insulating film and a planarizing film. Similarly to the insulator 324, the insulator 372 is preferably an insulator having a barrier property against impurities such as water and hydrogen. Therefore, the insulator 372 can be made of a material that can be used for the insulator 324.

[0462] Furthermore, openings are formed in the insulators 370 and 372 in regions that overlap with parts of the conductor 366, and the conductor 376 is provided to fill the openings. The conductor 376 is also formed on the insulator 372. After that, the conductor 376 is patterned into the shape of a wiring, a terminal, or a pad by etching or the like.

[0463] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used as the conductor 376. Note that the conductor 376 is preferably made of the same components as the material used for the conductor 216 included in the pixel layer PXAL, which will be described later.

[0464] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then planarization treatment using a chemical mechanical polishing (CMP) method or the like is performed until the conductor 376 is exposed. In this way, the conductor 376 can be formed on the substrate 310 as a wiring, a terminal, or a pad.

[0465] As the insulator 380, it is preferable to use, for example, a film having barrier properties that prevent the diffusion of impurities such as water and hydrogen, similar to the insulator 324. That is, it is preferable to use, for the insulator 380, a material that can be used for the insulator 324. Alternatively, as the insulator 380, it is possible to use, for example, an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between wirings, similar to the insulator 326. That is, it is possible to use, for the insulator 380, a material that can be used for the insulator 326.

[0466] The pixel layer PXAL, for example, includes a substrate 210, a transistor 200, a light-emitting device 150 (light-emitting device 150a and light-emitting device 150b in FIG. 17 ), and a substrate 102. The pixel layer PXAL also includes, for example, an insulator 220, an insulator 222, an insulator 226, an insulator 250, an insulator 111a, an insulator 111b, an insulator 112, an insulator 113, an insulator 162, and a resin layer 163. The pixel layer PXAL also includes, for example, a conductor 216, a conductor 228, a conductor 230, a conductor 121 (conductor 121a and conductor 121b in FIG. 17 ), a conductor 122, and a conductor 123.

[0467] 17, for example, the insulator 202 functions as a bonding layer together with the insulator 380. The insulator 202 is preferably made of the same material as that used for the insulator 380, for example.

[0468] The substrate 210 is provided above the insulator 202. In other words, the insulator 202 is formed on the lower surface of the substrate 210. As the substrate 210, it is preferable to use, for example, a substrate that can be applied to the substrate 310. Note that in the display device 100 of FIG. 17 , the substrate 310 will be described as a semiconductor substrate made of silicon.

[0469] For example, a transistor 200 is formed on the substrate 210. The transistor 200 functions as a Si transistor because it is formed on the substrate 210, which is a semiconductor substrate made of silicon. Note that the description of the transistor 300 is to be referred to for the configuration of the transistor 200.

[0470] An insulator 220 and an insulator 222 are provided above the transistor 200. The insulator 220 functions as an interlayer insulating film and a planarizing film, similar to the insulator 320. The insulator 222 functions as an interlayer insulating film and a planarizing film, similar to the insulator 322.

[0471] A plurality of openings are provided in the insulator 220 and the insulator 222. The plurality of openings are formed in regions overlapping with the source and drain of the transistor 200 and a region overlapping with the conductor 376. Of the plurality of openings, a conductor 228 is formed in the opening formed in the region overlapping with the source and drain of the transistor 200. Of the remaining openings, an insulator 214 is formed on side surfaces of the opening formed in the region overlapping with the conductor 376, and a conductor 216 is formed in the remaining openings. In particular, the conductor 216 may be called a TSV (Through Silicon Via).

[0472] The conductor 216 or the conductor 228 can be made of, for example, a material that can be used for the conductor 328. In particular, it is preferable that the conductor 216 is made of the same material as the conductor 376.

[0473] The insulator 214 has a function of, for example, electrically insulating the substrate 210 from the conductor 216. Note that as the insulator 214, it is preferable to use a material that can be used for the insulators 320 and 324, for example.

[0474] The insulator 380 and the conductor 376 formed on the substrate 310 and the insulator 202 and the conductor 216 formed on the substrate 210 are joined together by, for example, a bonding process.

[0475] As a pre-process before the bonding process, for example, planarization is performed on the substrate 310 side to make the heights of the surfaces of the insulator 380 and the conductor 376 uniform. Similarly, planarization is performed on the substrate 210 side to make the heights of the insulator 202 and the conductor 216 uniform.

[0476] In the bonding process, when bonding the insulator 380 and the insulator 202, that is, bonding the insulating layers together, a hydrophilic bonding method can be used in which high flatness is achieved by polishing or the like, then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to temporarily bond them, and then the final bonding is performed by dehydrating them through heat treatment.The hydrophilic bonding method also produces bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0477] Furthermore, when bonding conductor 376 and conductor 216, i.e., bonding conductors together, a surface activated bonding method can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact and bonded together. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded together using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0478] By carrying out the above-described bonding process, the conductor 376 on the substrate 310 side can be electrically connected to the conductor 216 on the substrate 210 side. Furthermore, a connection having sufficient mechanical strength can be obtained between the insulator 380 on the substrate 310 side and the insulator 202 on the substrate 210 side.

[0479] When bonding the substrates 310 and 210, since the bonding surfaces of each substrate contain a mixture of insulating and metal layers, a surface activated bonding method and a hydrophilic bonding method may be combined. For example, a bonding method may be used in which the surfaces are polished and then cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment, followed by a hydrophilic treatment. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment.

[0480] Note that bonding methods other than those described above may be used to bond the substrate 310 and the substrate 210. For example, flip-chip bonding may be used to bond the substrate 310 and the substrate 210. Furthermore, when using flip-chip bonding, connection terminals such as bumps may be provided above the conductor 376 on the substrate 310 side or below the conductor 216 on the substrate 210 side. Examples of flip-chip bonding include a method of injecting a resin containing anisotropic conductive particles between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216 to bond them, and a method of bonding them using silver-tin solder. Alternatively, if the bumps and the conductors connected to the bumps are both made of gold, ultrasonic bonding may be used. Furthermore, in addition to the flip-chip bonding method described above, an underfill agent may be injected between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216 to reduce physical stress such as impact and thermal stress. Furthermore, for example, a die bonding film may be used to bond the substrate 310 and the substrate 210 together.

[0481] An insulator 224 and an insulator 226 are stacked in this order on the insulator 222, the insulator 214, the conductor 216, and the conductor 228.

[0482] Like the insulator 324, the insulator 224 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing into a region above the insulator 224. Therefore, it is preferable to use, for example, a material that can be used for the insulator 324 as the insulator 224.

[0483] The insulator 226 is preferably an interlayer film with a low dielectric constant, similar to the insulator 326. Therefore, the insulator 226 is preferably made of a material that can be used for the insulator 326, for example.

[0484] Furthermore, a conductor 230 electrically connected to the transistor 200, the light-emitting device 150, and the like is embedded in the insulator 224 and the insulator 226. The conductor 230 functions as a plug or wiring. For example, a material that can be used for the conductor 328, the conductor 330, and the like can be used as the conductor 230.

[0485] On the insulator 224 and on the insulator 226, the insulator 250, the insulator 111a, and the insulator 111b are stacked in this order.

[0486] The insulator 250 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 250 can be made of, for example, a material that can be used for the insulator 324.

[0487] The insulators 111a and 111b can be formed using various inorganic insulating films such as an insulating oxide film, an insulating nitride film, an oxynitride insulating film, and an insulating nitride oxide film. For example, the insulator 111a is preferably formed using an insulating oxide film or an oxynitride insulating film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. For example, the insulator 111b is preferably formed using a nitride insulating film such as a silicon nitride film or a silicon nitride oxide film. Furthermore, the insulator 111b is preferably formed using a nitride oxide insulating film. More specifically, it is preferable to use a silicon oxide film as the insulator 111a and a silicon nitride film as the insulator 111b. The insulator 111b preferably functions as an etching protective film. Alternatively, the insulator 111a may be formed using a nitride insulating film or a nitride oxide insulating film, and the insulator 111b may be formed using an oxide insulating film or an oxynitride insulating film. Although this embodiment illustrates an example in which a recess is provided in the insulator 111b, the insulator 111b does not necessarily have to be formed using a recess.

[0488] Furthermore, openings are formed in the insulator 250, the insulator 111a, and the insulator 111b in regions that overlap with part of the conductor 230, and the conductor 121 is provided to fill the openings. Note that in this specification and the like, the conductors 121a and 121b shown in FIG. 17 are collectively referred to as the conductors 121. Note that the conductor 121 can be provided using a material similar to that of the conductors 328 and 330.

[0489] In addition, the pixel electrode described in this embodiment mode includes, for example, a material that reflects visible light, and the counter electrode includes a material that transmits visible light.

[0490] The display device 100 is a top-emission type. Light emitted from the light-emitting device is emitted toward the substrate 102. The substrate 102 is preferably made of a material that is highly transparent to visible light.

[0491] A light-emitting device 150a is provided above the conductor 121a, and a light-emitting device 150b is provided above the conductor 121b.

[0492] Here, the light emitting device 150a and the light emitting device 150b will be described.

[0493] The light-emitting device described in this embodiment refers to a self-luminous light-emitting device such as an organic EL element (also called an OLED (organic light-emitting diode)). Note that the light-emitting device electrically connected to the pixel circuit can be a self-luminous light-emitting device such as an LED (light-emitting diode), a micro LED, a QLED (quantum-dot light-emitting diode), or a semiconductor laser.

[0494] The conductor 122a and the conductor 122b can be formed, for example, by forming a conductive film over the insulator 111b, the conductor 121a, the conductor 121b, etc., and then applying photolithography or electron beam lithography to the conductive film.

[0495] The conductor 122a and the conductor 122b function as the anodes of the light-emitting device 150a and the light-emitting device 150b included in the display device 100, respectively, as an example.

[0496] For example, indium tin oxide (sometimes referred to as ITO) can be used as the conductor 122a and the conductor 122b.

[0497] Furthermore, each of the conductors 122a and 122b may have a stacked structure of two or more layers instead of a single layer. For example, a conductor with high visible light reflectivity can be used as the first layer conductor, and a conductor with high light transmissivity can be used as the top layer conductor. Examples of conductors with high visible light reflectivity include silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film). Examples of conductors with high light transmissivity include the aforementioned indium tin oxide. Furthermore, the conductors 122a and 122b may be, for example, a stacked film of aluminum sandwiched between a pair of titanium films (a stacked film of Ti, Al, and Ti in this order), or a stacked film of silver sandwiched between a pair of indium tin oxide films (a stacked film of ITO, Ag, and ITO in this order).

[0498] An EL layer 141a is provided over the conductor 122a, and an EL layer 141b is provided over the conductor 122b.

[0499] It is preferable that the EL layer 141a and the EL layer 141b each have a light-emitting layer that emits light of a different color. For example, the EL layer 141a may have a light-emitting layer that emits light of one of red (R), green (G), and blue (B), and the EL layer 141b may have a light-emitting layer that emits light of one of the remaining two colors. Furthermore, although not shown in FIG. 17 , when an EL layer different from the EL layer 141a and the EL layer 141b is provided, the EL layer may have a light-emitting layer that emits light of the remaining one color. In this way, the display device 100 may have a structure (SBS structure) in which different light-emitting layers for each color are formed on multiple pixel electrodes (the conductors 121a and 121b in FIG. 17 ).

[0500] The combination of colors emitted by the light-emitting layers included in the EL layer 141 a and the EL layer 141 b is not limited to the above, and may also be colors such as cyan, magenta, yellow, etc. Although the above example shows three colors, the number of colors emitted by the light-emitting device 150 included in the display device 100 may be two, three, or four or more.

[0501] The EL layer 141a and the EL layer 141b may each include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0502] In addition, the EL layer 141a and the EL layer 141b can be formed by a method such as a vapor deposition method (vacuum vapor deposition method, etc.), a coating method (for example, a dip coating method, a die coating method, a bar coating method, a spin coating method, and a spray coating method), a printing method (for example, an inkjet method, a screen (stencil printing) method, an offset (lithographic printing) method, a flexographic (relief printing) method, a gravure method, and a microcontact method).

[0503] When the coating method and the printing method are used as the film formation method, the material to be formed into the film can be, for example, a polymer compound (e.g., an oligomer, a dendrimer, and a polymer), a medium molecular compound (a compound in the intermediate range between a low molecular weight and a high molecular weight: a molecular weight of 400 to 4000), or an inorganic compound (e.g., a quantum dot material). The quantum dot material can be a colloidal quantum dot material, an alloy quantum dot material, a core-shell quantum dot material, or a core quantum dot material.

[0504] For example, light emitting device 150a and light emitting device 150b in FIG. 17 can be configured with a plurality of layers such as light emitting layer 4411 and layer 4430, as in light emitting device 150 shown in FIG. 18A.

[0505] The layer 4420 can have, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0506] A structure having a layer 4420, a light-emitting layer 4411, and a layer 4430 provided between a pair of electrodes (conductor 121 and conductor 122 described later) can function as a single light-emitting unit, and in this specification, the structure of Figure 18A is called a single structure.

[0507] 18B shows a modified example of the EL layer 141 included in the light-emitting device 150 shown in Fig. 18A. Specifically, the light-emitting device 150 shown in Fig. 18B includes a layer 4430-1 on the conductor 121, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductor 122 on the layer 4420-2. For example, when the conductor 121 is the anode and the conductor 122 is the cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductor 121 is a cathode and the conductor 122 is an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. Such a layer structure makes it possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0508] Note that a structure in which a plurality of light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between the layer 4420 and the layer 4430 as shown in FIG. 18C is also a variation of the single structure.

[0509] A laminate having multiple layers, such as layer 4420, light-emitting layer 4411, and layer 4430, may be referred to as a light-emitting unit. Multiple light-emitting units may be connected in series via an intermediate layer (charge generation layer). Specifically, as shown in FIG. 18D , multiple light-emitting units, such as light-emitting unit 4400a and light-emitting unit 4400b, may be connected in series via an intermediate layer (charge generation layer) 4440. In this specification, such a structure is referred to as a tandem structure. In this specification, the tandem structure may also be referred to as a stack structure. By forming a light-emitting device into a tandem structure, a light-emitting device capable of emitting high-brightness light can be obtained. By forming a light-emitting device into a tandem structure, improvements in the light-emitting efficiency and lifespan of the light-emitting device can be expected. When the light-emitting device 150 of the display device 100 of Figure 17 has a tandem structure, the EL layer 141 can be configured to include, for example, layer 4420, light-emitting layer 4411, and layer 4430 of light-emitting unit 4400a, intermediate layer 4440, and layer 4420, light-emitting layer 4412, and layer 4430 of light-emitting unit 4400b.

[0510] Furthermore, when displaying white, the SBS structure described above can reduce power consumption compared to the single and tandem structures described above. Therefore, when it is desired to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing processes are easier than those of the SBS structure, allowing for lower manufacturing costs or higher manufacturing yields.

[0511] The light-emitting device 150 can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 141. Furthermore, the color purity can be further improved by providing the light-emitting device 150 with a microcavity structure.

[0512] A light-emitting device that emits white light preferably has a configuration in which two or more types of light-emitting materials are contained in the light-emitting layer. To obtain white light emission, for example, light-emitting materials may be selected such that the respective emissions of the two light-emitting materials are in a complementary color relationship. Alternatively, to obtain white light emission, for example, light-emitting materials may be selected such that the emission color of one selected from three or more light-emitting materials is in a complementary color relationship with the emission color obtained by combining the emissions of the remaining light-emitting materials.

[0513] The light-emitting layer preferably contains two or more types of light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, the light-emitting layer preferably contains two or more types of light-emitting materials, and the light emitted by each of the light-emitting materials preferably contains spectral components of two or more colors of R, G, and B.

[0514] 17, a gap is provided between two EL layers between adjacent light-emitting devices. Specifically, in FIG. 17, a recess is formed between adjacent light-emitting devices, and the insulator 112 covers the side surfaces (side surfaces of the conductor 121a, the conductor 122a, and the EL layer 141a, and side surfaces of the conductor 121b, the conductor 122b, and the EL layer 141b) and the bottom surface (a partial region of the insulator 111b) of the recess. Furthermore, the insulator 162 is formed on the insulator 112 so as to fill the recess. In this manner, the EL layer 141a and the EL layer 141b are preferably provided so as not to be in contact with each other. This can suitably prevent unintended light emission (also known as crosstalk) caused by current (also referred to as lateral leakage current) flowing through the two adjacent EL layers. Therefore, contrast can be improved, and a display device with high display quality can be realized. Furthermore, for example, by configuring the display device so that the lateral leakage current between the light-emitting devices is extremely low, the black display performed by the display device can be a display with extremely little light leakage (also called true black display).

[0515] The EL layers 141a and 141b can be formed by a method using photolithography. For example, an EL film to be the EL layers 141a and 141b is formed on the conductor 122, and then the EL film is patterned by photolithography to form the EL layers 141a and 141b. This also makes it possible to provide a gap between the two EL layers between adjacent light-emitting devices.

[0516] The insulator 112 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulator 112. The insulator 112 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, an aluminum oxide film is preferable because it has a high selectivity with respect to the EL layer in an etching process and has a function of protecting the EL layer in the formation of the insulator 162 described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD (Atomic Layer Deposition) method as the insulator 112, the insulator 112 can have few pinholes and has an excellent function of protecting the EL layer.

[0517] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0518] The insulator 112 can be formed by a sputtering method, a CVD method, a PLD method, or an ALD method. The insulator 112 is preferably formed by an ALD method because it has good coverage.

[0519] The insulator 162 provided on the insulator 112 has the function of planarizing recesses formed in the insulator 112 between adjacent light-emitting devices. In other words, the insulator 162 improves the flatness of the surface on which the conductor 123 (described later) is formed. An insulating layer containing an organic material can be suitably used for the insulator 162. For example, the insulator 162 can be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. Alternatively, the insulator 162 can be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Alternatively, the insulator 162 can be made of, for example, a photosensitive resin. The photosensitive resin can be, for example, a photoresist. The photosensitive resin may be, for example, a positive-type material or a negative-type material.

[0520] The difference in height between the top surface of the insulator 162 and the top surface of the EL layer 141a or 141b is, for example, preferably 0.5 times or less, more preferably 0.3 times or less, the thickness of the insulator 162. For example, the insulator 162 may be provided so that the top surface of the EL layer 141a or 141b is higher than the top surface of the insulator 162. For example, the insulator 162 may be provided so that the top surface of the insulator 162 is higher than the top surface of the light-emitting layer of the EL layer 141a or 141b.

[0521] A conductor 123 is provided over the EL layer 141a, the EL layer 141b, the insulator 112, and the insulator 162. An insulator 113 is provided over each of the light-emitting devices 150a and 150b.

[0522] The conductor 123 functions as, for example, a common electrode for the light-emitting device 150 a and the light-emitting device 150 b. In order to emit light from the light-emitting device 150 upward from the display device 100, the conductor 122 preferably includes a light-transmitting conductive material.

[0523] The conductor 123 is preferably a highly conductive material that is light-transmitting and light-reflective (sometimes called a semi-transparent / semi-reflective electrode). The conductor 122 can be made of, for example, an alloy of silver and magnesium or indium tin oxide.

[0524] The insulator 113 is sometimes referred to as a protective layer, and providing the insulator 113 above each of the light-emitting devices 150a and 150b can improve the reliability of the light-emitting devices. In other words, the insulator 113 functions as a passivation film that protects the light-emitting devices 150a and 150b. Therefore, the insulator 113 is preferably made of a material that prevents the intrusion of water and the like. For example, the insulator 113 can be made of a material that can be used for the insulator 111a or the insulator 111b. Specifically, for example, aluminum oxide, silicon nitride, or silicon nitride oxide can be used for the insulator 113.

[0525] A resin layer 163 is provided on the insulator 113. Furthermore, a substrate 102 is provided on the resin layer 163.

[0526] For example, a light-transmitting substrate is preferably used as the substrate 102. By using a light-transmitting substrate for the substrate 102, light emitted from the light-emitting devices 150a and 150b can be emitted upward from the substrate 102.

[0527] Note that the display device of one embodiment of the present invention is not limited to the configuration of the display device 100 illustrated in Fig. 17. The configuration of the display device of one embodiment of the present invention may be changed as appropriate within the scope of solving the problems.

[0528] For example, the transistor 200 included in the pixel layer PXAL of the display device 100 in Fig. 17 may be a transistor having a metal oxide in a channel formation region (hereinafter referred to as an OS transistor). The display device 100 in Fig. 19 has a configuration in which a transistor 500 (OS transistor) instead of the transistor 200 and a light-emitting device 150 are provided above the circuit layer SICL and the wiring layer LINL of the display device 100 in Fig. 17.

[0529] 19 , the transistor 500 is provided over an insulator 512. The insulator 512 is provided above the insulator 364 and the conductor 366, and a substance having a barrier property against oxygen and hydrogen is preferably used for the insulator 512. Specifically, for example, the insulator 512 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0530] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0531] For example, the insulator 512 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film or a silicon oxynitride film.

[0532] An insulator 514 is provided over the insulator 512, and the transistor 500 is provided over the insulator 514. An insulator 576 is formed over the insulator 512 to cover the transistor 500. An insulator 581 is provided above the insulator 576 to cover the insulator 576.

[0533] The insulator 514 is preferably a film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or a region where circuit elements and the like below the insulator 512 are provided to the region where the transistor 500 is provided. Therefore, the insulator 514 can be made of silicon nitride formed by a CVD method, for example.

[0534] As described above, the transistor 500 illustrated in FIG. 19 is an OS transistor including a metal oxide in a channel formation region. Examples of the metal oxide include an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like). Specifically, for example, an oxide containing indium, gallium, and zinc (sometimes referred to as IGZO) may be used as the metal oxide. For example, an oxide containing indium, aluminum, and zinc (sometimes referred to as IAZO) may be used as the metal oxide. For example, an oxide containing indium, aluminum, gallium, and zinc (sometimes referred to as IAGZO) may be used as the metal oxide. In addition to the above, the metal oxide may be In-Ga oxide, In-Zn oxide, or indium oxide.

[0535] In particular, it is preferable to use a metal oxide functioning as a semiconductor having a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide having a wide band gap, the off-state current of the transistor can be reduced.

[0536] In particular, it is preferable to use a transistor, such as an OS transistor, whose off-state current is sufficiently small even when the source-drain voltage is large as the driving transistor included in the pixel circuit. By using an OS transistor as the driving transistor, the amount of off-state current flowing in the light-emitting device can be reduced when the driving transistor is in an off state, thereby sufficiently reducing the luminance of light emitted from the light-emitting device through which the off-state current flows. Therefore, when a driving transistor with a large off-state current is compared with a driving transistor with a small off-state current, when black is displayed in the pixel circuit, the light emission luminance of the pixel circuit including the driving transistor with a small off-state current can be lower than that of the pixel circuit including the driving transistor with a large off-state current. In other words, by using an OS transistor, it is possible to suppress floating black when black is displayed in the pixel circuit.

[0537] The off-state current of the OS transistor per 1 μm of channel width at room temperature is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ Note that the off-state current of a Si transistor per 1 μm of channel width at room temperature can be 1 fA (1×10 −１５ A) More than 1pA (1×10 −１２ Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0538] Furthermore, in order to increase the light emission luminance of a light-emitting device included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher source-drain withstand voltage than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, a high voltage can be applied between the source and drain of the OS transistor, thereby increasing the amount of current flowing through the light-emitting device and increasing the light emission luminance of the light-emitting device.

[0539] Furthermore, when the transistor operates in the saturation region, the OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. Therefore, the light emission luminance of the light-emitting device can be precisely controlled (the gradation in the pixel circuit can be increased).

[0540] Furthermore, in terms of the saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can flow a constant current (saturation current) that is more stable than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable constant current can be flowed through a light-emitting device, for example, even when the current-voltage characteristics of a light-emitting device containing an EL material vary. In other words, when an OS transistor operates in a saturation region, the source-drain current hardly changes even when the source-drain voltage increases, and thus the light-emitting luminance of the light-emitting device can be stabilized.

[0541] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gray levels," "suppression of variations in light-emitting devices," and the like. Therefore, a display device including the pixel circuit can display a clear and smooth image, and as a result, one or more of image clarity (image sharpness) and a high contrast ratio can be observed. Note that image clarity (image sharpness) may refer to either or both of suppression of motion blur and suppression of black floating. Furthermore, by configuring the driving transistor included in the pixel circuit to have an extremely low off-state current, black display performed by the display device can be achieved with extremely little light leakage (true black display).

[0542] One or both of the insulators 576 and 581 preferably function as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing into the transistor 500 from above the transistor 500. Therefore, at least one of the insulators 576 and 581 preferably contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., impermeability of the impurities is low), or an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., impermeability of the oxygen is low).

[0543] It is preferable that one or both of the insulators 576 and 581 be an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen, and for example, one or more selected from aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium-gallium-zinc oxide, silicon nitride, and silicon nitride oxide can be used.

[0544] Openings for forming a plug or a wiring are provided in the insulator 581, the insulator 576, and one of the source and drain electrodes of the transistor 500. A conductor 540 functioning as a plug or a wiring is formed in the meeting portion.

[0545] For example, the insulator 581 is preferably an insulator that functions as an interlayer film and a planarizing film.

[0546] An insulator 224 and an insulator 226 are formed above the insulator 581 and the conductor 540. Note that for descriptions of insulators, conductors, and circuit elements located above the insulator 224, including the insulator 224, please refer to the description of the display device 100 in FIG. 17 .

[0547] 17 shows a display device formed by bonding a semiconductor substrate on which a light-emitting device 150, a pixel circuit, and the like are formed and a semiconductor substrate on which a driver circuit and the like are formed, and FIG. 19 shows a display device in which the light-emitting device 150, the pixel circuit, and the like are formed on a semiconductor substrate on which a driver circuit is formed, but the display device according to the electronic device of one embodiment of the present invention is not limited to FIG. 17 or 19. The display device according to the electronic device of one embodiment of the present invention may be, for example, a display device having a structure in which only one layer of transistors is formed, instead of a layer structure in which two or more transistors are stacked.

[0548] Specifically, for example, a display device related to the electronic device of one embodiment of the present invention may have a structure including a circuit including a transistor 200 formed over a substrate 210 and a light-emitting device 150 provided above the transistor 200, as in the display device 100 illustrated in Figure 20A. Alternatively, for example, a display device 100 may have a structure in which an insulator 512 is formed over a substrate 501, and the transistor 500 is provided over the insulator 512 and the light-emitting device 150 is provided above the transistor 500, as in the display device 100 illustrated in Figure 20B. Note that as the substrate 501, for example, a substrate applicable to the substrate 310 can be used, and in particular, a glass substrate is preferably used.

[0549] 20A and 20B , the display device according to the electronic device of one embodiment of the present invention may have a structure in which only one layer of transistors is formed and a light-emitting device 150 is provided above the transistor. Although not shown, the display device according to the electronic device of one embodiment of the present invention may have a layer structure in which three or more layers of transistors are formed.

[0550] <Example of Sealing Structure of Display Device> Next, a sealing structure of the light-emitting device 150 that can be applied to the display device 100 of FIG. 17 will be described.

[0551] Fig. 21A is a cross-sectional view showing an example of a sealing structure that can be applied to the display device 100 of Fig. 17. Specifically, Fig. 21A illustrates an edge of the display device 100 of Fig. 17 and materials provided around the edge. Fig. 21A also illustrates an extracted portion of the pixel layer PXAL of the display device 100. Specifically, each of Fig. 21A illustrates an insulator 250, and an insulator, a conductor, and a light-emitting device 150a located above the insulator 250.

[0552] 21A , an opening is provided, for example. As an example, a conductor 121CM is provided in the opening. The conductor 123 is electrically connected to wiring provided below the insulator 250 via the conductor 121CM. This allows a potential (e.g., an anode potential and a cathode potential in the light-emitting device 150a, etc.) to be supplied to the conductor 123, which functions as a common electrode. Note that one or both of the conductors included in the region 123CM and the conductors around the region 123CM may be referred to as a connection electrode.

[0553] Furthermore, for the conductor 121CM, for example, a material that can be used for the conductor 121 can be used.

[0554] 21A, an adhesive layer 164 is provided on or around an end of a resin layer 163. Specifically, the display device 100 is configured so that the insulator 113 and the substrate 102 are bonded to each other via the adhesive layer 164.

[0555] The adhesive layer 164 is preferably made of a material that suppresses the permeation of impurities such as external air components and moisture. By using such a material for the adhesive layer 164, the reliability of the display device 100 can be improved.

[0556] A structure in which the insulator 113 and the substrate 102 are bonded together via the resin layer 163 using the adhesive layer 164 is sometimes called a solid sealing structure. In addition, in the solid sealing structure, if the resin layer 163 has the function of bonding the insulator 113 and the substrate 102 together, similar to the adhesive layer 164, the adhesive layer 164 is not necessarily provided.

[0557] On the other hand, a structure in which the insulator 113 and the substrate 102 are bonded together using the adhesive layer 164 and filled with an inert gas instead of the resin layer 163 is sometimes called a hollow sealing structure (not shown). Examples of the inert gas include nitrogen and argon.

[0558] 21A , two or more adhesive layers may be stacked. For example, as shown in FIG. 21B , an adhesive layer 165 may be provided inside adhesive layer 164 (between adhesive layer 164 and resin layer 163). Stacking two or more adhesive layers can further suppress the permeation of impurities such as moisture, thereby further improving the reliability of display device 100.

[0559] Furthermore, a desiccant may be mixed into the adhesive layer 165. This allows the desiccant to adsorb moisture contained in the adhesive layer 164, the resin layer 163 formed inside the adhesive layer 165, the insulator, the conductor, and the EL layer, thereby improving the reliability of the display device 100.

[0560] Furthermore, although the display device 100 in FIG. 21B has a solid sealing structure, it may have a hollow sealing structure.

[0561] 21A and 21B, an inert liquid may be filled in place of the resin layer 163. Examples of the inert liquid include a fluorine-based inert liquid.

[0562] <Modification of Display Device> One embodiment of the present invention is not limited to the above-described configuration, and the above-described configuration can be modified as appropriate depending on the situation. Modifications of the display device 100 in FIG. 17 will be described below with reference to FIGS. 22A to 23B . Note that FIGS. 22A to 23B illustrate only a portion of the pixel layer PXAL of the display device 100. Specifically, FIGS. 22A to 23B each illustrate the insulator 250, the insulator 111a, the insulators positioned above the insulator 111a, the conductors, the light-emitting device 150a, and the light-emitting device 150b. In particular, FIGS. 22A to 23B also illustrate the light-emitting device 150c, the conductor 121c, the conductor 122c, and the EL layer 141c.

[0563] Note that, for example, the color of light emitted by the EL layer 141c may be different from the colors of light emitted by the EL layer 141a and the EL layer 141b. Furthermore, for example, the display device 100 may be configured such that the number of colors emitted by the light-emitting devices 150a to 150c is two. Furthermore, for example, the display device 100 may be configured such that the number of colors emitted by the light-emitting devices 150 is increased to four or more (not shown).

[0564] 22A , for example, the display device 100 may have a configuration in which the EL layer 142 is formed on the EL layers 141a to 141c. Specifically, for example, in FIG. 18A , when the EL layers 141a to 141c include the layer 4430 and the light-emitting layer 4411, the EL layer 142 may include the layer 4420. In this case, the layer 4420 included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c. Similarly, in FIG. 18C , when the EL layers 141a to 141c include the layer 4430, the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413, the EL layer 142 includes the layer 4420, so that the layer 4420 included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c. Furthermore, for example, in FIG. 18D, when the EL layers 141a to 141c are configured to include the layer 4430, the light-emitting layer 4412, and the layer 4420 of the light-emitting unit 4400b, the intermediate layer 4440, and the layer 4430 and the light-emitting layer 4411 of the light-emitting unit 4400a, the EL layer 142 is configured to include the layer 4420 of the light-emitting unit 4400b, so that the layer 4420 of the light-emitting unit 4400a included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c.

[0565] Furthermore, for example, the insulator 113 may have a stacked structure of two or more layers instead of a single layer in the configuration of the display device 100. For example, the insulator 113 may have a three-layer stacked structure in which an insulator made of an inorganic material is applied as a first layer, an insulator made of an organic material is applied as a second layer, and an insulator made of an inorganic material is applied as a third layer. Figure 22B illustrates a cross-sectional view of a portion of the display device 100 in which the insulator 113 has a multilayer structure including the insulators 113a, 113b, and 113c, where the insulator 113a is an insulator made of an inorganic material, the insulator 113b is an insulator made of an organic material, and the insulator 113c is an insulator made of an inorganic material.

[0566] Furthermore, for example, a microcavity structure (microresonator structure) may be provided in each of the EL layers 141 a to 141 c as a configuration of the display device 100. The microcavity structure refers to a structure in which, for example, a light-transmitting and light-reflective conductive material is used for the conductor 122 that is the upper electrode (common electrode), a light-reflective conductive material is used for the conductor 121 that is the lower electrode (pixel electrode), and the distance between the bottom surface of the light-emitting layer and the top surface of the lower electrode, that is, the film thickness of the layer 4430 in FIG. 18A , is set to a thickness corresponding to the wavelength of the color of light emitted by the light-emitting layer included in the EL layer 141.

[0567] For example, since light reflected by the lower electrode and returned (reflected light) causes significant interference with light directly incident on the upper electrode from the light-emitting layer (incident light), it is preferable to adjust the optical distance between the lower electrode and the light-emitting layer to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the emitted light to be amplified). By adjusting this optical distance, the phases of the reflected light and incident light, each of which has a wavelength λ, can be matched, thereby further amplifying the light emitted from the light-emitting layer. On the other hand, if the reflected light and incident light have a wavelength other than λ, they will no longer match in phase, resulting in attenuation without resonance.

[0568] In the above structure, the EL layer may have a structure having multiple light-emitting layers or a structure having a single light-emitting layer.Furthermore, for example, the above-mentioned tandem light-emitting device structure may be combined with a microcavity structure.

[0569] The microcavity structure makes it possible to increase the light emission intensity of a specific wavelength in the front direction, thereby reducing power consumption. In particular, in the case of XR devices such as VR and AR, light from the light-emitting device is often incident on the eyes of a user wearing the device in the front direction, so it can be said that providing a microcavity structure in a display device for XR devices is preferable. Note that in the case of a display device that displays images using four sub-pixels of red, yellow, green, and blue, in addition to the brightness improvement effect of yellow emission, the microcavity structure that can be applied to all sub-pixels is suitable for each color wavelength, resulting in a display device with good characteristics.

[0570] 23A shows a cross-sectional view of a portion of the display device 100 having a microcavity structure, as an example. Furthermore, when the light-emitting device 150a has a light-emitting layer that emits blue (B) light, the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), it is preferable to increase the thickness of the EL layer 141a, the EL layer 141b, and the EL layer 141c in that order, as shown in FIG. 23A . Specifically, the thickness of the layer 4430 included in each of the EL layers 141a, 141b, and 141c can be determined according to the color of light emitted by each light-emitting layer. In this case, the layer 4430 included in the EL layer 141a is the thinnest, and the layer 4430 included in the EL layer 141c is the thickest.

[0571] 23B shows, as an example, a configuration in which colored layers 166a, 166b, and 166c are included between the resin layer 163 and the substrate 102. Note that the colored layers 166a to 166c can be formed on the substrate 102, for example. Furthermore, when the light-emitting device 150a has a light-emitting layer that emits blue (B), the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), the colored layer 166a is blue, the colored layer 166b is green, and the colored layer 166c is red.

[0572] 23B can be constructed by bonding a substrate 102 provided with colored layers 166a to 166c to a substrate 310 on which light-emitting devices 150a to 150c have been formed, via a resin layer 163. The bonding is preferably performed so that the light-emitting device 150a and the colored layer 166a overlap, the light-emitting device 150b and the colored layer 166b overlap, and the light-emitting device 150c and the colored layer 166c overlap. By providing the colored layers 166a to 166c in the display device 100, for example, light emitted by the light-emitting device 150b does not exit above the substrate 102 via the colored layer 166a or the colored layer 166c, but exits above the substrate 102 via the colored layer 166b. In other words, since it is possible to block light from the light-emitting device 150 of the display device 100 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is considered to be a horizontal plane), it is possible to reduce the dependency of the display device 100 on the viewing angle, and it is possible to prevent a decrease in the display quality of the image displayed on the display device 100 when viewed from an oblique angle.

[0573] The colored layers 166a to 166c formed on the substrate 102 may be covered with a resin called an overcoat layer. Specifically, the display device 100 may be formed by laminating the resin layer 163, the overcoat layer, the colored layers 166a to 166c, and the substrate 102 in this order (not shown). Note that examples of the resin used for the overcoat layer include a thermosetting material that is light-transmitting and based on an acrylic resin or an epoxy resin.

[0574] Furthermore, for example, a black matrix (not shown) may be included in addition to the colored layers as part of the configuration of the display device 100. By providing a black matrix between the colored layers 166a and 166b, between the colored layers 166b and 166c, and between the colored layers 166c and 166a, it is possible to more effectively block light from the light-emitting device 150 of the display device 100 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is considered to be a horizontal plane), thereby more effectively preventing a decrease in the display quality of an image displayed on the display device 100 when the image is viewed obliquely.

[0575] 23B , when the display device has a colored layer, the light-emitting devices 150 a to 150 c included in the display device may all be light-emitting devices that emit white light (not shown). The light-emitting devices may have, for example, a single structure or a tandem structure.

[0576] Although the above-described structure of the display device 100 includes the conductors 121a to 121c as anodes and the conductor 122 as a cathode, the display device 100 may include the conductors 121a to 121c as cathodes and the conductor 122 as an anode. That is, in the manufacturing process described above, the stack order of the hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer included in the EL layers 141a to 141c and the EL layer 142 may be reversed.

[0577] <Structural Example of Insulator 162> Next, a cross-sectional structure of a region including the insulator 162 and its periphery in the display device 100 will be shown.

[0578] 24A shows an example in which the thicknesses of the EL layer 141a and the EL layer 141b are different from each other. The height of the top surface of the insulator 112 on the EL layer 141a side is the same as or approximately the same as the height of the top surface of the EL layer 141a, and on the EL layer 141b side is the same as or approximately the same as the height of the top surface of the EL layer 141b. The top surface of the insulator 112 has a gentle slope, with the EL layer 141a side being higher and the EL layer 141b side being lower. In this way, the heights of the insulators 112 and 162 are preferably the same as the height of the top surfaces of the adjacent EL layers. Alternatively, the top surface may have a flat portion that is the same as the height of the top surface of one of the adjacent EL layers.

[0579] 24B, the upper surface of the insulator 162 has a region higher than the upper surface of the EL layer 141a and the upper surface of the EL layer 141b. The upper surface of the insulator 162 has a shape that gently bulges out toward the center.

[0580] 24C , the display device 100 has a region in which the top surface of the insulator 112 is higher than the top surfaces of the EL layers 141a and 141b. Furthermore, in a region including the insulator 162 and its periphery, the display device 100 has a first region located on at least one of the sacrificial layers 118 and 119. The first region is higher than the top surfaces of the EL layers 141a and 141b, and a part of the insulator 162 is formed in the first region. Furthermore, in a region including the insulator 162 and its periphery, the display device 100 has a second region located on at least one of the sacrificial layers 118 and 119. The second region is higher than the top surfaces of the EL layers 141a and 141b, and a part of the insulator 162 is formed in the second region.

[0581] 24D, the top surface of the insulator 162 has an area that is lower than the top surfaces of the EL layers 141a and 141b. The top surface of the insulator 162 has a gently sloping recessed shape that is concave toward the center.

[0582] 24E, the upper surface of the insulator 112 has a region higher than the upper surface of the EL layer 141a and the upper surface of the EL layer 141b. That is, the insulator 112 protrudes from the surface on which the EL layer 141 is to be formed, forming a convex portion.

[0583] When forming the insulator 112, for example, if the insulator 112 is formed so that the height thereof matches or approximately matches the height of the sacrificial layer, the insulator 112 may be formed in a protruding shape, as shown in FIG. 24E.

[0584] 24F, the upper surface of the insulator 112 has a region that is lower than the upper surfaces of the EL layers 141a and 141b. That is, the insulator 112 forms a recess on the surface on which the EL layer 141 is to be formed.

[0585] In this way, the insulators 112 and 162 can be applied in various shapes.

[0586] <Configuration Example of Pixel Circuit> Here, a configuration example of a pixel circuit that can be provided in the pixel layer PXAL will be described.

[0587] 25A and 25B show a configuration example of a pixel circuit that can be provided in the pixel layer PXAL and a light-emitting device 150 connected to the pixel circuit. Also, FIG. 25A is a diagram showing the connections of each circuit element included in the pixel circuit 400 provided in the pixel layer PXAL, and FIG. 25B is a diagram schematically showing the hierarchical relationship between a circuit layer SICL including a drive circuit 30 and the like, a layer OSL including multiple transistors of the pixel circuit, and a layer EML including a light-emitting device 150. Note that the pixel layer PXAL of the display device 100 shown in FIG. 25B includes, as an example, a layer OSL and a layer EML. Also, the transistors 500A, 500B, 500C, and the like included in the layer OSL shown in FIG. 25B correspond to the transistor 200 in FIG. 17. Also, the light-emitting device 150 included in the layer EML shown in FIG. 25B corresponds to the light-emitting device 150a or the light-emitting device 150b in FIG. 17.

[0588] 25A and 25B include a pixel circuit 400 including a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. The transistors 500A, 500B, and 500C can be, for example, transistors applicable to the transistor 200 described above. That is, the transistors 500A, 500B, and 500C can be Si transistors. Alternatively, the transistors 500A, 500B, and 500C can be, for example, transistors applicable to the transistor 500 described above. That is, the transistors 500A, 500B, and 500C can be OS transistors. In particular, when the transistors 500A, 500B, and 500C are OS transistors, each of the transistors 500A, 500B, and 500C preferably includes a back gate electrode. In this case, the back gate electrode may be supplied with the same signal as the gate electrode, or may be supplied with a different signal from the gate electrode. Note that although the transistors 500A, 500B, and 500C each include a back gate electrode in FIGS. 25A and 25B, the transistors 500A, 500B, and 500C may not include a back gate electrode.

[0589] The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light-emitting device 150, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting device 150.

[0590] The transistor 500A has a first terminal electrically connected to the gate electrode of the transistor 500B, a second terminal electrically connected to the wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of the wiring GL1 that functions as a gate line.

[0591] The transistor 500C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light-emitting device 150, and a gate electrode having a function of controlling the conductive state or non-conductive state based on the potential of the wiring GL2 functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 400 to the drive circuit 30.

[0592] The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

[0593] The light-emitting device 150 includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting device 150.

[0594] This allows the intensity of light emitted by light-emitting device 150 to be controlled in accordance with an image signal applied to the gate electrode of transistor 500B. Furthermore, the reference potential of wiring V0 applied via transistor 500C can suppress variations in the gate-source voltage of transistor 500B.

[0595] Furthermore, the wiring V0 can output a current amount that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 500B or the current flowing through the light-emitting device 150 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the arithmetic circuit 10 described in the above embodiment or the like.

[0596] In the configuration shown as an example in FIG. 25B , the wiring electrically connecting the pixel circuits 400 and the driver circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, enabling the display device 100 to be driven at high speed. This allows a sufficient frame period to be ensured even if the display device 100 has a large number of pixel circuits 400, thereby increasing the pixel density of the display device 100. Furthermore, increasing the pixel density of the display device 100 increases the resolution of the image displayed by the display device 100. For example, the pixel density of the display device 100 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 100 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices such as HMDs, in which the display unit is close to the user.

[0597] 25A and 25B show an example of the pixel circuit 400 including three transistors in total, but the pixel circuit of the electronic device of one embodiment of the present invention is not limited to this. Below, a configuration example of a pixel circuit that can be used for the pixel circuit 400 will be described.

[0598] 26A illustrates a pixel circuit 400A including a transistor 500A, a transistor 500B, and a capacitor 600. 26A also illustrates a light-emitting device 150 connected to the pixel circuit 400A. The pixel circuit 400A is electrically connected to a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM.

[0599] The transistor 500A has a gate electrically connected to a wiring GL, one of its source and drain electrically connected to a wiring SL, and the other electrically connected to the gate of the transistor 500B and one electrode of the capacitor 600. The transistor 500B has one of its source and drain electrically connected to a wiring ANO, and the other electrically connected to the anode of the light-emitting device 150. The capacitor 600 has the other electrode electrically connected to the anode of the light-emitting device 150. The light-emitting device 150 has a cathode electrically connected to a wiring VCOM.

[0600] 26B has a configuration in which a transistor 500C is added to the pixel circuit 400A. A wiring V0 is electrically connected to the pixel circuit 400B.

[0601] The pixel circuit 400C shown in FIG. 26C is an example in which the transistors 500A and 500B in the pixel circuit 400A are transistors whose gates and back gates are electrically connected. The pixel circuit 400D shown in FIG. 26D is an example in which the same transistors are used in the pixel circuit 400B. This can increase the current that the transistors can pass. Note that, although all the transistors in this example have a pair of gates electrically connected, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0602] 27A has a configuration in which a transistor 500D is added to the pixel circuit 400B described above. The pixel circuit 400E is electrically connected to three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines.

[0603] The gate of the transistor 500D is electrically connected to a wiring GL3, one of the source and drain of the transistor 500D is electrically connected to the gate of the transistor 500B, and the other is electrically connected to a wiring V0. The gate of the transistor 500A is electrically connected to a wiring GL1, and the gate of the transistor 500C is electrically connected to a wiring GL2.

[0604] By simultaneously turning on the transistors 500C and 500D, the source and gate of the transistor 500B have the same potential, and the transistor 500B can be turned off. This forcibly cuts off the current flowing through the light-emitting device 150. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0605] 27B is an example in which a capacitor 600A is added to the pixel circuit 400E. The capacitor 600A functions as a storage capacitor.

[0606] 27C and 27D are examples in which transistors whose gates and back gates are electrically connected are applied to the pixel circuit 400E or 400F, respectively. Transistors whose gates and back gates are electrically connected are applied to transistors 500A, 500C, and 500D, and a transistor whose gate is electrically connected to its source is applied to transistor 500B.

[0607] <Plane Schematic View and Cross-Sectional Schematic View of Light-Emitting Device> Figure 28A is a plan schematic view showing a configuration example in which a light-emitting device and a light-receiving device are arranged within one pixel in a display device 100 according to one embodiment of the present invention. The display device 100 includes a plurality of light-emitting devices 150R that emit red light, a plurality of light-emitting devices 150G that emit green light, a plurality of light-emitting devices 150B that emit blue light, and a plurality of light-receiving devices 160. In Figure 28A, to easily distinguish between the light-emitting devices 150, the symbols R, G, and B are assigned within the light-emitting region of each light-emitting device 150. Furthermore, the symbol PD is assigned within the light-receiving region of each light-receiving device 160.

[0608] The light-emitting devices 150R, 150G, 150B, and the light-receiving devices 160 are arranged in a matrix. FIG. 28A shows an example in which the light-emitting devices 150R, 150G, and 150B are arranged in the X direction, and the light-receiving devices 160 are arranged below them. FIG. 28A also shows an example in which the light-emitting devices 150 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 100 shown in FIG. 28A , a pixel 80 can be configured by, for example, a sub-pixel having the light-emitting device 150R, a sub-pixel having the light-emitting device 150G, and a sub-pixel having the light-emitting device 150B arranged in the X direction, and a sub-pixel having the light-receiving device 160 provided below these sub-pixels.

[0609] The light-emitting device 150R, the light-emitting device 150G, and the light-emitting device 150B preferably use an EL element such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that the EL elements have include fluorescent materials, phosphorescent materials, inorganic compounds (quantum dot materials, etc.), and materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials). Note that the TADF material may be a material that is in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in efficiency in the high-brightness region of the light-emitting element.

[0610] For example, a pn-type or pin-type photodiode can be used as the light-receiving device 160. The light-receiving device 160 functions as a photoelectric conversion element that detects light incident on the light-receiving device 160 and generates electric charges. The amount of electric charges generated is determined based on the amount of incident light.

[0611] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound for the light-receiving device 160. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0612] In an electronic device according to one embodiment of the present invention, an organic EL element is used for the light-emitting device 150, and an organic photodiode is used for the light-receiving device 160. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element. Note that the organic EL elements and the organic photodiode are preferably separated from each other by photolithography. This allows the distance between the light-emitting devices, between the organic photodiodes, and between the light-emitting device and the organic photodiode to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0613] 28A shows a conductor 123 that functions as a common electrode and a conductor 121CM that functions as a connection electrode. Here, the conductor 121CM is electrically connected to the conductor 123. The conductor 121CM is provided outside the display section in which the light-emitting devices 150 and the light-receiving devices 160 are arranged. Also in FIG. 28A, the conductor 123 having an area that overlaps with the light-emitting devices 150, the light-receiving devices 160, and the conductor 121CM is shown by dashed lines.

[0614] The conductor 121CM can be provided along the outer periphery of the display unit. For example, it may be provided along one side of the outer periphery of the display unit, or it may be provided over two or more sides of the outer periphery of the display unit. In other words, if the top surface of the display unit has a rectangular shape, the top surface of the conductor 121CM can have a strip-like, L-shaped, U-shaped (square bracket-shaped), square, or the like shape.

[0615] Fig. 28B is a schematic plan view showing an example of the configuration of display device 100, which is a modified example of display device 100 shown in Fig. 28A. Display device 100 shown in Fig. 28B differs from display device 100 shown in Fig. 28A in that it includes light-emitting device 150IR that emits infrared light. Light-emitting device 150IR can emit, for example, near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less).

[0616] 28B , in addition to light-emitting devices 150R, 150G, and 150B, light-emitting device 150IR is arranged in the X direction, and light-receiving device 160 is arranged below light-emitting device 150IR. In addition, light-receiving device 160 has a function of detecting infrared light.

[0617] Fig. 29A is a cross-sectional view corresponding to dashed-dotted line A1-A2 in Fig. 28A, and Fig. 29B is a cross-sectional view corresponding to dashed-dotted line B1-B2 in Fig. 28A. Fig. 29C is a cross-sectional view corresponding to dashed-dotted line C1-C2 in Fig. 28A, and Fig. 29D is a cross-sectional view corresponding to dashed-dotted line D1-D2 in Fig. 28A. Light-emitting device 150R, light-emitting device 150G, light-emitting device 150B, and light-receiving device 160 are provided on insulator 111. Furthermore, when display device 100 includes light-emitting device 150IR, light-emitting device 150IR is provided on insulator 111.

[0618] In this specification and the like, for example, when it is said that "B is on A" or "B is below A", it is not necessary that there is an area where A and B are in contact with each other.

[0619] Fig. 29A shows an example of the cross-sectional configuration of the light-emitting device 150R, the light-emitting device 150G, and the light-emitting device 150B in Fig. 28A. Also, Fig. 29B shows an example of the cross-sectional configuration of the light-receiving device 160 in Fig. 28A.

[0620] The light-emitting device 150R has a conductor 121R functioning as a pixel electrode, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a conductor 123. The light-emitting device 150G has a conductor 121G functioning as a pixel electrode, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a conductor 123. The light-emitting device 150B has a conductor 121B functioning as a pixel electrode, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a conductor 123. The light-receiving device 160 has a conductor 121PD functioning as a pixel electrode, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88P...

Claims

1. A first cell array, a second cell array, and a first conversion circuit, the first cell array includes a first cell and a second cell arranged in the same row as the first cell; the second cell array includes a third cell and a fourth cell arranged in the same row as the third cell; the first conversion circuit has a plurality of input terminals and a plurality of output terminals; The first cell is electrically connected to a first wiring and a second wiring, the second cell is electrically connected to the first wiring and a third wiring; each of a plurality of input terminals of the first conversion circuit is electrically connected to the second wiring and the third wiring; each of the plurality of output terminals of the first conversion circuit is electrically connected to a fourth wiring and a fifth wiring; the third cell is electrically connected to the fourth wiring and a sixth wiring, the fourth cell is electrically connected to the fifth wiring and the seventh wiring; the second wiring, the third wiring, the sixth wiring, and the seventh wiring extend in a column direction; the first cell has a function of causing a first current to flow through the second wiring in an amount corresponding to a product of first data held in the first cell and second data input to the first cell from the first wiring; the second cell has a function of causing a second current to flow through the third wiring in an amount corresponding to a product of third data held in the second cell and fourth data input to the second cell from the first wiring; the first conversion circuit has a function of transmitting fifth data corresponding to a total amount of current flowing from the second wiring to the fourth wiring, and a function of transmitting sixth data corresponding to a total amount of current flowing from the third wiring to the fifth wiring; the third cell has a function of causing a third current to flow through the sixth wiring in an amount corresponding to a product of seventh data held in the third cell and the fifth data input to the third cell from the fourth wiring; the fourth cell has a function of causing a fourth current to flow through the seventh wiring, the fourth current having an amount corresponding to a product of eighth data held in the fourth cell and the sixth data input to the fourth cell from the fifth wiring; The sixth wiring is electrically connected to the seventh wiring. Semiconductor device.

2. In claim 1, A second conversion circuit is provided. the second conversion circuit has an input terminal and an output terminal; an input terminal of the second conversion circuit is electrically connected to the sixth wiring; the second conversion circuit has a function of outputting ninth data corresponding to a total amount of current flowing from the sixth wiring to an output terminal of the second conversion circuit. Semiconductor device.

3. In claim 1 or claim 2, A fifth cell, a sixth cell, and a seventh cell, each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a first capacitance; each of the fifth cell, the sixth cell, and the seventh cell includes a third transistor, a fourth transistor, and a second capacitor; In each of the first cell, the second cell, the third cell, and the fourth cell, a gate of the first transistor is electrically connected to a first terminal of the first capacitance and a first terminal of the second transistor; a first terminal of the first transistor electrically connected to a second terminal of the second transistor; In the first cell, a first terminal of the first transistor is electrically connected to the second wiring; a second terminal of the first capacitor electrically connected to the first wiring; In the second cell, a first terminal of the first transistor is electrically connected to the third wiring; a second terminal of the first capacitor electrically connected to the first wiring; In the third cell, a first terminal of the first transistor is electrically connected to the sixth wiring; a second terminal of the first capacitor is electrically connected to the fourth wiring; In the fourth cell, a first terminal of the first transistor is electrically connected to the seventh wiring; a second terminal of the first capacitor is electrically connected to the fifth wiring; In each of the fifth cell, the sixth cell, and the seventh cell, a gate of the third transistor is electrically connected to a first terminal of the second capacitor and a first terminal of the fourth transistor; a first terminal of the third transistor electrically connected to a second terminal of the fourth transistor; In the fifth cell, a first terminal of the third transistor is electrically connected to the first wiring; a second terminal of the second capacitor electrically connected to the first wiring; In the sixth cell, a first terminal of the third transistor is electrically connected to the fourth wiring; a second terminal of the second capacitor is electrically connected to the fourth wiring; In the seventh cell, a first terminal of the third transistor is electrically connected to the fifth wiring; a second terminal of the second capacitor is electrically connected to the fifth wiring; Semiconductor device.

4. In claim 3, A first circuit and a second circuit, the first circuit is electrically connected to the first wiring, the second circuit is electrically connected to the fourth wiring and the fifth wiring, the first circuit has a function of inputting the second data to the first wiring, The second circuit has a function of causing a current to flow through the fourth wiring and the fifth wiring. Semiconductor device.

5. A display device comprising: a first layer including the semiconductor device according to claim 1 or 2; and a second layer including a display section; The second layer has an area overlapping the first layer. Display device.

6. An electronic device comprising the display device according to claim 5 and a housing.