Semiconductor device

Abstract

Provided is a semiconductor device which has a new configuration. This semiconductor device comprises: a first substrate; a first element layer provided in contact with a second substrate; and a first through-electrode provided to the second substrate and the first element layer. The first element layer has a first memory cell, a first electrode, a second electrode, and a third electrode. The first memory cell has a first transistor. The first transistor has a semiconductor layer which contains a metal oxide in a channel formation region. The first electrode is electrically connected to the third electrode via the second electrode. The third electrode is provided so as to be exposed on the surface of the first element layer. The first through-electrode is provided so as to be exposed on the surface of the second substrate, and is electrically connected to the first electrode. The second substrate and the first element layer are provided so as to be laminated in a direction perpendicular or a substantially perpendicular to the surface of the first substrate. The first transistor is provided in a region overlapping the first through-electrode.

Description

Semiconductor Devices

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0003] Metal oxides have attracted attention as semiconductors that can be used in transistors. It has been reported that transistors having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as “oxide semiconductor transistors” or “OS transistors”) have extremely low off-state current (see, for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been manufactured (see, for example, Non-Patent Documents 3 and 4).

[0004] The manufacturing process of an OS transistor can be incorporated into a conventional CMOS process for a transistor having silicon in a channel formation region (Si transistor), and the OS transistor can be stacked on the Si transistor. For example, Patent Document 1 discloses a structure in which multiple layers of a memory cell array having an OS transistor are stacked on a substrate on which a Si transistor is provided.

[0005] US Patent Application Publication No. 2012 / 0063208

[0006] S. Yamazaki et al. , “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn. J. Appl. Phys. , vol. 53, 04ED18 (2014). K. Kato et al. , “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,”Jpn. J. Appl. Phys. , vol. 51, 021201 (2012). S. Amano et al. , “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” “SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). T. Ishizu et al. , “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran. , vol. 79, pp. 149-156 (2017).

[0007] An OS transistor is suitable as an access transistor for a memory cell or the like because it can be provided in a stacked structure and has an extremely small off-state current. In particular, for a memory device such as a memory cell that requires an improvement in memory density per unit area, a stacked structure of element layers including a plurality of transistors is preferable.

[0008] In a configuration in which element layers are stacked, the number of steps required to fabricate the element increases as the number of layers increases. Therefore, when stacking element layers, it is preferable to electrically connect multiple element layers provided on different substrates with through electrodes such as through silicon vias (TSVs) to integrate them into a single chip.

[0009] However, when connecting multiple element layers fabricated on different substrates with through electrodes such as TSVs, it is difficult to arrange elements such as transistors in the areas where the through electrodes are provided. In a semiconductor device in which element layers are connected with through electrodes such as TSVs, there is a risk that the area in which transistors cannot be arranged will also become large, particularly when the diameter of the opening of the TSV is very large compared to the size of the element. Therefore, in a semiconductor device in which element layers are connected with through electrodes such as TSVs, there is a risk that it will be difficult to improve the memory density per unit area.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can reduce manufacturing costs in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that has excellent low power consumption in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that can reduce the size of a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a novel structure that has excellent reliability and exhibits small fluctuations in the electrical characteristics of a transistor in a semiconductor device that functions as a memory device utilizing an extremely small off-state current.

[0011] The description of multiple problems does not preclude the existence of each other's problems. One embodiment of the present invention does not necessarily solve all of the problems exemplified. Furthermore, problems other than those listed will become apparent from the description in this specification, and such problems may also be problems of one embodiment of the present invention.

[0012] One embodiment of the present invention is a semiconductor device having a first substrate, a first element layer provided in contact with a second substrate, and a first through electrode provided in the second substrate and the first element layer, the first element layer having a first transistor, a first electrode, a second electrode, and a third electrode, the first transistor having a semiconductor layer having a metal oxide in a channel formation region, the first electrode being electrically connected to the third electrode via the second electrode, the third electrode being exposed on the surface of the first element layer, the first through electrode being exposed on the surface of the second substrate and electrically connected to the first electrode, the second substrate and the first element layer being stacked in a direction perpendicular or approximately perpendicular to the surface of the first substrate, and the first transistor being provided in a region overlapping with the first through electrode.

[0013] One embodiment of the present invention is a semiconductor device having a first substrate, a first element layer provided in contact with a second substrate, and a first through electrode provided in the second substrate and the first element layer, the first element layer having a first memory cell, a first electrode, a second electrode, and a third electrode, the first memory cell having a first transistor and a capacitor, the first transistor having a semiconductor layer having a metal oxide in a channel formation region, the first electrode being electrically connected to the third electrode via the second electrode, the third electrode being exposed on a surface of the first element layer, the first through electrode being exposed on a surface of the second substrate and electrically connected to the first electrode, the second substrate and the first element layer being stacked in a direction perpendicular or approximately perpendicular to the surface of the first substrate, and the first transistor and the capacitor being provided in a region overlapping with the first through electrode.

[0014] One aspect of the present invention is a semiconductor device having a first substrate, a first element layer provided in contact with a second substrate, and a first through electrode provided in the second substrate and the first element layer, the first element layer having a first memory cell, a first electrode, a second electrode, and a third electrode, the first memory cell having a first transistor and a magnetic tunnel junction element, the first transistor having a semiconductor layer having a metal oxide in a channel formation region, the first electrode being electrically connected to the third electrode via the second electrode, the third electrode being exposed on a surface of the first element layer, the first through electrode being exposed on a surface of the second substrate and electrically connected to the first electrode, the second substrate and the first element layer being stacked in a direction perpendicular or approximately perpendicular to the surface of the first substrate, and the first transistor and the magnetic tunnel junction element being provided in a region overlapping with the first through electrode.

[0015] In one aspect of the present invention, the magnetic tunnel junction element is preferably a semiconductor device having a stacked structure of a free layer, an insulating layer, and a fixed layer.

[0016] One embodiment of the present invention is a semiconductor device including a first substrate, a first element layer provided in contact with a second substrate, and a first through electrode provided in the second substrate and the first element layer, the first element layer having a plurality of first memory cells, a first circuit, a first electrode, a second electrode, and a third electrode, the first memory cells and the first circuit each having a first transistor, the first transistor having a semiconductor layer having a metal oxide in a channel formation region, the first electrode being electrically connected to the third electrode via the second electrode, the third electrode being exposed on a surface of the first element layer, the first through electrode being exposed on a surface of the second substrate and electrically connected to the first electrode, the second substrate and the first element layer being stacked in a direction perpendicular or approximately perpendicular to the surface of the first substrate, and the first transistor being provided in a region overlapping with the first through electrode.

[0017] In one embodiment of the present invention, a semiconductor device is preferably provided in which a plurality of first memory cells are electrically connected to any one of a plurality of bit lines, and a first circuit has a function of selecting any one of the plurality of bit lines and a function of amplifying and outputting the potential of the selected bit line.

[0018] In one embodiment of the present invention, the semiconductor device preferably has the first memory cell electrically connected to a word line, and the first circuit has a function of amplifying a signal applied to the word line.

[0019] In one aspect of the present invention, the semiconductor device is preferably such that the first substrate is provided with a first peripheral circuit having a function of driving the first transistor.

[0020] In one aspect of the present invention, the semiconductor device is preferably such that the second electrode is an electrode provided in the same layer as the electrode connected to the first transistor.

[0021] In one aspect of the present invention, the second substrate is preferably a silicon substrate.

[0022] In one embodiment of the present invention, the metal oxide preferably contains In, Ga, and Zn.

[0023] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0024] One embodiment of the present invention can provide a semiconductor device or the like having a novel structure. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can reduce manufacturing costs in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that has excellent low power consumption in a semiconductor device that functions as a memory device utilizing an extremely small off-state current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that can reduce the size of the semiconductor device that functions as a memory device utilizing an extremely small off-state current. Alternatively, one embodiment of the present invention can provide a semiconductor device or the like having a novel structure that has excellent reliability and exhibits small fluctuations in the electrical characteristics of a transistor in a semiconductor device that functions as a memory device utilizing an extremely small off-state current.

[0025] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification.

[0026] FIGS. 1A to 1C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 2A and 2B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 3A and 3B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 4A to 4C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 5A to 5C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 6A and 6B are diagrams illustrating a configuration example of a semiconductor device. FIG. 7 is a diagram illustrating a configuration example of a semiconductor device. FIG. 8 is a diagram illustrating a configuration example of a semiconductor device. FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. FIGS. 10A and 10B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 11A and 11B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 12A to 12C are diagrams illustrating a configuration example of a semiconductor device. FIG. 13 is a diagram illustrating a configuration example of an imaging device. FIG. 14 is a diagram illustrating a configuration example of an imaging device. FIGS. 15A and 15B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 16A and 16B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 17A and 17B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 18A to 18C are diagrams illustrating a configuration example of a semiconductor device. 19A and 19B are diagrams showing a configuration example of a semiconductor device. FIG. 20 is a block diagram explaining a configuration example of a semiconductor device. FIG. 21 is a conceptual diagram showing a configuration example of a semiconductor device. FIGS. 22A and 22B are schematic diagrams explaining an example of an electronic component. FIG. 23 is a diagram showing an example of an electronic device.

[0027] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0028] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0029] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0030] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0031] Furthermore, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", or "[m, n]" may be added to the reference numeral. For example, the second wiring GL is described as wiring GL[2].

[0032] 1A to 1C , a configuration example of a semiconductor device according to one embodiment of the present invention will be described. Note that a semiconductor device is a device utilizing semiconductor characteristics, such as a circuit including a semiconductor element (a transistor, a diode, a photodiode, or the like) or a device having the circuit. For example, a semiconductor device using a transistor with extremely low off-state current functions as a memory device.

[0033] 1A to 1C are schematic cross-sectional views of a semiconductor device described in this embodiment. As shown in FIG. 1A, a semiconductor device 10 of one embodiment of the present invention includes a plurality of circuit units 30_1 to 30_N (N is a natural number) over a substrate 25.

[0034] The circuit units 30_1 to 30_N (N is a natural number) may be referred to as a circuit unit layer 30 B. Figures 1B and 1C are schematic cross-sectional views illustrating a circuit unit 30 applicable to the circuit units 30_1 to 30_N.

[0035] The substrate 25 is provided with a peripheral circuit 20 for driving the circuit units. The substrate 25 on which the peripheral circuit 20 is provided is described as a silicon substrate, but this embodiment is not limited to this. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a single-crystal silicon substrate. Materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide) may also be used for the substrate. While FIG. 1A illustrates the peripheral circuit 20 provided on the substrate 25 in a region overlapping with the circuit units 30_1 to 30_N, it may also be provided outside the region of the substrate 25 that overlaps with the circuit units 30_1 to 30_N.

[0036] The circuit unit 30 includes a substrate 50 and an element layer 40 provided in contact with the substrate 50. The element layer 40 includes a memory circuit 60. The memory circuit 60 includes memory cells. The memory circuit 60 includes elements such as transistors.

[0037] The circuit units 30_1 to 30_N are stacked in a direction perpendicular or approximately perpendicular to the surface of the substrate 25. In other words, the element layer 40 and the substrate 50 are stacked in a direction perpendicular or approximately perpendicular to the surface of the substrate 25. This configuration makes it possible to increase the number of circuit units 30_1 to 30_N arranged per unit area. As a result, the memory density of the memory cells included in the memory circuit 60 can be increased.

[0038] 1A, in order to explain the arrangement of each component, the direction perpendicular or approximately perpendicular to the surface of the substrate 25 is defined as the z-axis direction. For ease of understanding, the z-axis direction may be referred to as the direction perpendicular to the surface of the substrate 25 in the specification. Note that "approximately perpendicular" refers to a state in which the components are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0039] The peripheral circuit 20 includes circuits that output signals for driving the circuit units 30_1 to 30_N, such as a row driver and a column driver, etc. The peripheral circuit 20 may also be called a control circuit, a drive circuit, or a circuit.

[0040] A row driver is a circuit that outputs signals to word lines to drive memory cells. Word lines transmit word signals to memory cells. A row driver is sometimes called a word line side drive circuit. The row driver includes a decoder circuit and a buffer circuit for selecting a word line according to a specified address. A column driver is a circuit that outputs signals to bit lines to drive memory cells, outputs data to be written to the memory cells, and amplifies data read from the memory cells to the bit lines. The bit lines transmit data to the memory cells. A column driver is sometimes called a bit line side drive circuit. The column driver includes a sense amplifier, a precharge circuit, a decoder circuit for selecting a bit line according to a specified address, and so on.

[0041] It is preferable that the peripheral circuit 20 drives the memory cells of the memory circuit 60 at high speed. Therefore, it is preferable that the peripheral circuit 20 has transistors that operate at high speed. The transistors in the peripheral circuit 20 are preferably transistors with excellent field-effect mobility and whose channel formation region contains silicon (Si transistors).

[0042] 1B shows a circuit unit 30 applicable to the circuit units 30_1 to 30_N. The circuit unit 30 includes a substrate 50 and an element layer 40 provided in contact with the substrate 50. The substrate 50 is a substrate for forming elements such as transistors included in the element layer 40. A silicon substrate can be used as the substrate 50.

[0043] The element layer 40 has a memory circuit 60, an electrode 41, an electrode 42, and an electrode 43. The substrate 50 and the element layer 40 have a through electrode 44. The through electrode 44 is provided so as to be exposed on the surface of the substrate 50, and is electrically connected to the electrode 41. The through electrode 44 is an electrode that is provided so as to penetrate the substrate 50 after the electrodes 41 to 43 are formed on the substrate 50.

[0044] The electrode 41 is electrically connected to the electrode 43 via the electrode 42. The electrode 43 is provided so as to be exposed on the surface of the element layer 40.

[0045] The electrodes 41 to 43 are electrodes provided on the element layer 40 side of the substrate 50, as in the circuit unit 30b shown in FIG. 1C.

[0046] The electrode 41 is an electrode formed of a conductor and provided on the substrate 50 below the transistors and capacitors included in the memory circuit 60. The electrode 41 is provided at a position where a through electrode 44 (not shown) is provided. Materials that can be used for the electrode 41 include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, as well as alloys containing these metals as their main components. Films containing these materials can be used as a single layer or as a laminate structure. Copper is particularly suitable for the electrode 41.

[0047] The electrode 42 is an electrode formed of a conductor provided in the same layer as the transistor and capacitor included in the memory circuit 60. For example, as shown in FIG. 2A , the electrode 42 is an electrode having a conductor provided in the same layer as the gate electrode or a conductor functioning as the source electrode or drain electrode of the transistor 45 included in the memory circuit 60. Materials that can be used for the electrode 42 include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, as well as alloys containing these metals as their main components. Films containing these materials can be used as a single layer or a stacked layer structure.

[0048] 1C , the electrode 43 is provided at a position where the electrode 42 is provided so as to be exposed on the surface of the element layer 40. Examples of materials that can be used for the electrode 43 include materials similar to those for the electrode 41.

[0049] The through electrode 44 can be formed using a through electrode technology such as a TSV (Through Silicon Via). Specifically, the through electrode 44 can be formed after the circuit unit 30b is attached face-down to the substrate 25 (face-down bonding), as shown in the cross-sectional schematic diagram of FIG. 2B . FIG. 2B illustrates a substrate 25 having the transistor 21 and electrode 22 of the peripheral circuit 20 as the substrate to which the circuit unit 30b is attached. If the substrate 25 is a silicon substrate, the transistor 21 can be a Si transistor. The through electrode 44 is provided to penetrate the substrate 50 and connect to the electrode 43 provided in the element layer 40.

[0050] The through electrodes 44 can be provided by forming holes in the substrate 50 that penetrate the substrate 50 and reach the electrodes 41 of the element layer 40, then forming a base film of titanium nitride or the like, and then forming a conductive layer of Cu or the like inside the holes. An insulating layer of silicon oxide or the like may be provided on the side surfaces of the holes before the base film is formed.

[0051] 3A shows an example of a circuit configuration of a memory cell included in the memory circuit 60. A memory cell 46 shown in FIG. 3A includes a transistor 45 and a capacitor 47. One of the source and the drain of the transistor 45 is connected to a wiring BL (shown by a thick line). The gate of the transistor 45 is connected to a wiring WL. The other of the source and the drain of the transistor 45 is connected to the capacitor 47. Note that the wiring BL may be referred to as a bit line, and the wiring WL may be referred to as a word line.

[0052] In the wiring BL, the through electrode 44 provided to be exposed on the surface of the substrate 50 is a terminal BL. Ｄ The electrode 43 exposed on the surface of the element layer 40 is connected to the terminal BL Ｕ The terminal BL is provided on the element layer 40 side. Ｄand terminal BL Ｕ The through electrodes 44 are electrically connected to the electrodes 41 to 43 , so that the through electrodes 44 can function as terminals provided on the front and back surfaces of the circuit unit 30 .

[0053] 3B is a schematic diagram showing a plurality of circuit units 30_1 to 30_N, each having a memory cell 46, stacked on a substrate 25. As shown in FIG. 3B, a wiring corresponding to the wiring BL (shown by a thick line) is connected to the terminal BL described in FIG. 3A. Ｄ and terminal BL Ｕ , and are connected to the peripheral circuit 20 via the wiring WL. Although not shown, the wiring WL can also be connected to the peripheral circuit 20 in the same manner.

[0054] Note that the transistor 45 provided in the element layer 40 is preferably an OS transistor. An OS transistor has an extremely small off-state current. Therefore, charge corresponding to data written to the memory cell 46 can be held in the capacitor 47 for a long time. That is, data once written in the memory cell 46 can be held for a long time. Therefore, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device of one embodiment of the present invention can be reduced. Furthermore, by providing an OS transistor in a stacked structure, it can be repeatedly manufactured in the vertical direction using the same manufacturing process, which contributes to improving memory density and reducing manufacturing costs.

[0055] The memory cell 46 including the transistor 45 can be called a dynamic oxide semiconductor random access memory (DOSRAM) that uses an OS transistor as a memory. The DOSRAM can be configured with one transistor and one capacitor, which enables high-density memory. Furthermore, the use of an OS transistor can increase the data retention period.

[0056] Although the transistor 45 is illustrated as a transistor having a top-gate structure or a bottom-gate structure without a back gate electrode, the structure of the transistor 45 is not limited thereto. The transistor 45 preferably has a back gate electrode. The threshold voltage of the transistor 45 can be controlled by controlling the potential applied to the back gate electrode. This can increase the on-current and decrease the off-current of the transistor 45, for example.

[0057] The memory cells 46 using OS transistors can be easily integrated because they can be freely arranged even in a region overlapping with the through electrodes 44. Therefore, the number of memory cells arranged per unit area can be increased, leading to an increase in memory density.

[0058] Furthermore, OS transistors have better electrical characteristics than Si transistors in a high-temperature environment. Specifically, OS transistors have a large ratio of on-state current to off-state current even at high temperatures of 125° C. to 150° C., and therefore can perform favorable switching operations.

[0059] The memory cell 46 may be a nonvolatile oxide semiconductor random access memory (NOSRAM). NOSRAM rewrites data by charging and discharging a capacitor, so in principle there is no limit to the number of rewrites, and data can be written and read with low energy. NOSRAM can store data in three or more levels, allowing it to store a larger amount of data per memory cell than DOSRAM.

[0060] Note that the connection between the circuit units 30 is described as a configuration in which the through electrodes 44 and the electrodes 43 are directly connected. For example, as shown in FIG. 4A , a configuration can be adopted in which the through electrodes 44 embedded in an insulating layer 44S and the electrodes 43 embedded in an insulating layer 43S are connected using Cu-Cu bonding. Cu-Cu bonding is a technology for achieving electrical conductivity by connecting Cu (copper) pads together. Alternatively, a configuration in which the through electrodes 44 and the electrodes 43 are directly connected without going through a Cu (copper) pad may be adopted.

[0061] As shown in FIG. 4B, the through electrodes 44 embedded in the insulating layer 44S and the electrodes 43 embedded in the insulating layer 43S can be connected via metal bumps 59 (also called microbumps) provided between the circuit units (shown between the circuit units 30_N and 30_N-1).

[0062] 4C , a configuration may also be adopted in which the circuit units (circuit unit 30_N, circuit unit 30_N-1) are connected to each other by a bonding layer 61, and then the through electrodes 44 and the electrodes 43 are connected. The bonding layer 61 is preferably made of silicon oxide, which not only flattens the surface but also allows hydroxyl groups on the surface of the bonding layer 61 to form bonds with each other. Silicon oxide is preferable because it can improve the flatness of the surface compared to silicon nitride, etc. When the bonding layer 61 is made of silicon oxide, the hydroxyl groups on the silicon oxide surface of the bonding layer 61 are bonded to each other by van der Waals forces, and subsequent heat treatment may generate silicon-oxygen bonds and water molecules.

[0063] By improving the flatness of the bonding layer 61, the circuit units can be bonded together at a temperature in the range of 350° C. to 450° C., without exposing them to high temperatures of 1000° C. or higher. That is, the circuit units can be bonded together without being exposed to high temperatures. This makes it possible to suppress fluctuations in the electrical characteristics of the OS transistors that are caused by exposure of the circuit units to high temperatures. In addition, because the Si transistors are not exposed to high temperatures when the circuit units are bonded together, copper wiring can be used.

[0064] Furthermore, the circuit unit 30 may be configured to enhance the flatness of the surface on which the through electrodes 44 are provided. For example, in the circuit unit 30A shown in FIG. 5A, the flatness of the through electrodes 44A on the surface of the substrate 50 is enhanced.

[0065] Furthermore, in the circuit unit 30, the substrate 50 may have a functional circuit 51 having a transistor 52 in an area where the through electrode 44 is not provided, as in the circuit unit 30B shown in FIG. 5B.

[0066] The functional circuit 51 includes, for example, a circuit for outputting a signal for driving the memory circuit 60 included in the element layer 40. The functional circuit 51 preferably includes a transistor that operates at high speed. The transistor 52 included in the functional circuit 51 is preferably a Si transistor with excellent field-effect mobility. Alternatively, the functional circuit 51 may be a memory circuit, such as a dynamic random access memory (DRAM) including the transistor 52 provided on the substrate 50.

[0067] DRAMs with Si transistors have a higher data transfer rate than DOSRAMs with OS transistors. DOSRAMs with OS transistors can reduce the frequency of data refresh compared to DRAMs with Si transistors, which is effective in reducing power consumption. To achieve both high data transfer rate and low power consumption, it is effective to use a configuration that switches between using DRAM or DOSRAM depending on the data access state.

[0068] Alternatively, the functional circuit 51 may be a sensor circuit provided on the substrate 50. For example, a silicon substrate may be used as the substrate 50, and a photodiode may be provided by adding an impurity element. The sensor circuit may be stacked on the circuit unit 30 having the memory circuit 60.

[0069] Furthermore, in the circuit unit 30, the through electrode 44 may be an electrode that penetrates the substrate 50 and the element layer 40. For example, in a region where the functional circuit 51 is not provided, a through electrode 44B that penetrates the substrate 50 and the element layer 40 may be provided, as in the circuit unit 30C shown in FIG. 5C . The through electrode 44B can be connected to an electrode 43A that is provided in the same layer as the electrode 43.

[0070] 5B, when a functional circuit 51 having a transistor 52 is provided on a substrate 50 and the functional circuit 51 is used as a memory circuit, the element layer 40 may be omitted. In this case, as shown in FIG. 6A, a configuration may be adopted in which the front surface and the back surface are electrically connected by a through electrode 44B that penetrates the substrate 50A.

[0071] As shown in Fig. 6B, the substrate 50A having the functional circuit 51 can be disposed on the circuit unit layer 30_B shown in Fig. 3B. Therefore, a semiconductor device can be formed in which the circuit unit 30 having the memory cell 46 referred to as DOSRAM and the substrate 50A having DRAM are stacked.

[0072] Next, an example of the configuration of the element layer 40 will be described with reference to FIG. 7 which shows an example.

[0073] 7 shows an element layer 40 on a substrate 50. An insulating layer 330 and an electrode 41 are provided on the substrate 50. A transistor 45, a capacitor 47, an electrode 42, and an electrode 43 are provided on the electrode 41.

[0074] The transistor 45 is an OS transistor. The transistor 45 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a pair of conductive layers 325, an insulating layer 326, and a conductive layer 327.

[0075] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 331 to the transistor 45 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0076] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 45, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0077] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor properties. Examples of the metal oxide include In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like). Alternatively, indium oxide, In—Ga oxide, or In—Zn oxide, that is, an oxide semiconductor containing In, Ga, and Zn, may be used as the oxide semiconductor. Note that an oxide semiconductor with a high indium content can increase the on-state current, field-effect mobility, and the like of a transistor.

[0078] The pair of conductive layers 325 are provided over and in contact with the semiconductor layer 321 and function as a source electrode and a drain electrode.

[0079] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like into the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321. The insulating layer 328 can be an insulating film similar to the insulating layer 332.

[0080] Openings reaching the semiconductor layer 321 are provided in the insulating layer 328 and the insulating layer 264. Inside the openings, an insulating layer 323 and a conductive layer 324 are buried, which are in contact with side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325 and an upper surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0081] The top surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are the same or approximately the same, and insulating layers 329 and 265 are provided to cover them.

[0082] The insulating layer 330, the insulating layer 331, the insulating layer 264, and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 45. The insulating layer 329 can be formed using an insulating film similar to the insulating layers 328 and 332.

[0083] One of the pair of conductive layers 325 or the electrode 42 electrically connected to the electrode 41 is provided so as to be embedded in the insulating layer 328, the insulating layer 332, the insulating layer 331, the insulating layer 265, the insulating layer 329, and the insulating layer 264. Here, the electrode 42 preferably includes a conductive layer 274a covering the side and bottom surfaces of the opening and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, the conductive layer 274a is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0084] A capacitor 47 is provided on the insulating layer 265 .

[0085] The capacitor 47 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 47, the conductive layer 245 functions as the other electrode of the capacitor 47, and the insulating layer 243 functions as a dielectric of the capacitor 47.

[0086] The conductive layer 241 is provided over the insulating layer 265 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to one of the source and drain of the transistor 45 by an electrode buried in the insulating layer 265, the insulating layer 329, the insulating layer 264, and the insulating layer 328. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0087] An insulating layer 255a is provided to cover the capacitor 47. An electrode 42C connected to the electrode 42 is provided on the insulating layer 255a, and an electrode 43 is provided thereon. The electrode 42C can be provided in the same manner as the electrode 42. The electrode 43 can be provided in the same manner as the electrode 41. As the insulating layer 255a, various inorganic insulating films such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film can be suitably used.

[0088] 8 will be a cross-sectional schematic diagram illustrating a configuration different from that of the transistor 45 shown in Fig. 7. Fig. 8 shows a vertical channel transistor 45A in which the semiconductor layer of the transistor 45 in Fig. 7 is provided vertically relative to the substrate. Fig. 8 also shows a capacitor 47A having a different shape (deep hole type) from the planar type capacitor 47 shown in Fig. 7.

[0089] 8 includes an element layer 40 having a vertical channel transistor 45A and a deep hole capacitor 47A, which includes an insulating layer 330, an electrode 41, and an insulating layer 331 over a substrate 50. A conductive layer 441 that functions as a wiring BL is provided over the insulating layer 331, and a hole is formed in a stack of an insulating layer 442 and a conductive layer 443. An insulating layer 444 is formed on a side surface of the conductive layer 443 in which the hole is provided. A conductive layer 445, a conductive layer 446, a metal oxide layer 447, a conductive layer 448, an insulating layer 449, and a conductive layer 450 are provided in the hole. A conductive layer 451 is provided over the conductive layer 450.

[0090] Each metal oxide layer, each conductive layer, and each insulating layer can be made of the materials listed as the metal oxide layer, conductive layer, and insulating layer described above with reference to Fig. 7. Each metal oxide layer, each conductive layer, and each insulating layer can be formed by sputtering, CVD, PLD, atomic layer deposition (ALD), or the like.

[0091] The conductive layer 443 functions as a gate of the transistor 45A. The insulating layer 444 functions as a gate insulating film of the transistor 45A. The conductive layer 446 functions as a source electrode or drain electrode of the transistor 45A. The metal oxide layer 447 functions as a semiconductor layer having a channel formation region of the transistor 45A. The conductive layer 448 and the conductive layer 450 function as electrodes of the capacitor 47A.

[0092] In addition, by forming an opening reaching the electrode 41 in the hole where the transistor 45A and the capacitor 47A are provided and providing a conductor corresponding to the electrode 42, the front and back of the circuit unit can be electrically connected.

[0093] 9 illustrates a cross-sectional schematic diagram of a configuration different from the configurations of the transistors 45 and 45A shown in FIGS. 7 and 8. Similar to FIG. 8, FIG. 9 illustrates a vertical channel transistor 45B in which the semiconductor layer of the transistor is disposed vertically relative to the substrate. Unlike FIG. 8, FIG. 9 illustrates a configuration in which the semiconductor layer of the transistor 45B is disposed along the wall surface of a hole. Also, FIG. 9 illustrates a deep hole capacitor 47B having a different configuration from the deep hole capacitor shown in FIG. 8.

[0094] The element layer 40 having the vertical channel transistor 45B and the deep hole capacitor 47B shown in FIG. 9 includes an insulating layer 330, an electrode 41, and an insulating layer 331 over a substrate 50. A conductive layer 461 functioning as a wiring BL is provided over the insulating layer 331, and a hole is formed in a stack of an insulating layer 462 and a conductive layer 463. An insulating layer 464 is formed on the side surfaces of the insulating layer 462 and the conductive layer 463 in which the hole is provided. A metal oxide layer 466 is provided in contact with the conductive layer 465 in the hole, and an insulating layer 467 is buried therein. A conductive layer 468 is provided in contact with the metal oxide layer, and a conductive layer 469, an insulating layer 470, and a conductive layer 471 are provided thereon. A conductive layer 472 is provided over the conductive layer 471.

[0095] Each metal oxide layer, each conductive layer, and each insulating layer can be made of the materials listed as the metal oxide layer, conductive layer, and insulating layer described above with reference to Fig. 7. Each metal oxide layer, each conductive layer, and each insulating layer can be formed by sputtering, CVD, PLD, atomic layer deposition (ALD), or the like.

[0096] The conductive layer 463 functions as a gate of the transistor 45B. The insulating layer 464 functions as a gate insulating film of the transistor 45B. The conductive layers 465 and 468 function as source and drain electrodes of the transistor 45B. The metal oxide layer 466 functions as a semiconductor layer having a channel formation region of the transistor 45B. The conductive layers 469 and 471 function as electrodes of the capacitor 47B.

[0097] In addition, by forming an opening reaching the electrode 41 in the transistor 45B and the hole in which the transistor 45B is provided, and providing a conductor corresponding to the electrode 42, the front and back of the circuit unit can be electrically connected.

[0098] In one embodiment of the present invention, when a plurality of element layers formed on different substrates are connected by through electrodes, elements such as transistors can be arranged in a region where the through electrodes are provided, thereby improving the memory density per unit area of ​​a semiconductor device.

[0099] Furthermore, an OS transistor with extremely low off-state current can be used as a transistor provided in the element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, thereby achieving low power consumption. The OS transistor can be stacked and repeatedly fabricated in the same vertical manufacturing process, thereby reducing manufacturing costs. In one embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, since OS transistors have smaller fluctuations in electrical characteristics than Si transistors even under high-temperature conditions, a semiconductor device can function as a highly reliable memory device with less fluctuations in the electrical characteristics of the transistors when stacked and integrated.

[0100] In this embodiment, a configuration example of a semiconductor device according to one embodiment of the present invention will be described, which is different from that of Embodiment 1. Note that the detailed description of the same parts as those in Embodiment 1 will be omitted as they are incorporated herein by reference.

[0101] 10A is a schematic cross-sectional view of a semiconductor device described in this embodiment. Circuit unit 30M shown in Fig. 10A illustrates a configuration in which element layer 40 of circuit unit 30 described in Embodiment 1 includes memory cells 46M having STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory), which is a memory using magnetic tunnel junction (MTJ) elements that are resistance-change memory elements.

[0102] 10A includes an MTJ element 47M in addition to a transistor 45, which is an OS transistor. In FIG. 10A, the through electrode 44 of the wiring BL is exposed on the surface of the substrate 50. Ｄ The electrode 43 exposed on the surface of the element layer 40 is connected to the terminal BL Ｕ The terminal BL is provided on the element layer 40 side.Ｄ and terminal BL Ｕ 3A, the through electrodes 44 and the electrodes 41 to 43 are electrically connected, so that the through electrodes 44 can function as terminals provided on the front and back surfaces of the circuit unit 30.

[0103] 10B shows a configuration example of a circuit unit section 30M_B having circuit units 30M_1 to 30M_N to which the circuit unit 30M shown in FIG. 10A can be applied, similarly to FIG. 10A. In FIG. 10B, similarly to FIG. 10A, a wiring corresponding to the wiring BL (shown by a thick line) is connected to the terminal BL described in FIG. 10A. Ｄ and terminal BL Ｕ , and are connected to the peripheral circuit 20 via the wiring WL. Although not shown, the wiring WL can also be connected to the peripheral circuit 20 in the same manner.

[0104] 11A shows a circuit diagram of a memory cell 46M including an MTJ element 47M. The memory cell 46M shown in FIG. 11A includes a transistor 45 and an MTJ element 47M. The transistor 45 is an OS transistor with a back gate. The MTJ element 47M includes a free layer 136 (also referred to as a recording layer, free layer, or movable layer) composed of a single layer or stack of ferromagnetic films, a fixed layer 137 (also referred to as a magnetization fixed layer, pinned layer, or reference layer), and an insulating layer 138 (also referred to as a barrier layer, tunnel insulating film, or nonmagnetic layer). In this specification, the free layer 136 of the MTJ element 47M is referred to as one terminal, and the fixed layer 137 is referred to as the other terminal.

[0105] One of the source and drain of the transistor 45 is connected to the wiring BL (or BLB). The gate of the transistor 45 is connected to the wiring WL. The other of the source and drain of the transistor 45 is connected to one terminal of the MTJ element 47M. The other terminal of the MTJ element 47M is connected to the wiring SL. The back gate of the transistor 45 is connected to the wiring BGL. The threshold voltage of the transistor 45 can be changed by the voltage Vbg.

[0106] 11B shows a configuration in which the configuration of the capacitor 47 in the schematic cross-sectional view described in FIG. 7 of the first embodiment is replaced with an MTJ element 47M. In the configuration shown in FIG. 11B, the MTJ element 47M has a free layer 136, a fixed layer 137, and an insulating layer 138 between a conductive layer 241 and a conductive layer 245. The MTJ element shown in FIG. 11B can be used in combination with the vertical channel type transistor 45A described in FIG. 8 or the vertical channel type transistor 45B described in FIG. 9.

[0107] The insulating layer 138 is made of magnesium oxide (MgO) or aluminum oxide (Al ２ O ３ ) or the like may be used. The free layer 136 and the fixed layer 137 may be made of a ferromagnetic material such as iron (Fe) or cobalt (Co), or an alloy thereof. The free layer 136, the fixed layer 137, and the insulating layer 138 may be formed of a single layer or multiple layers. Note that the free layer 136, the fixed layer 137, and the insulating layer 138 may have an insulator or the like on their sidewalls to facilitate processing.

[0108] The MTJ element 47M will now be described with reference to FIGS. 12A to 12C.

[0109] 12A is a schematic diagram of the cross-sectional structure of the MTJ element 47 M. The MTJ element 47 M is composed of a free layer 136 made of a ferromagnetic material and a fixed layer 137 made of a ferromagnetic material, which are separated by an insulating layer 138.

[0110] The fixed layer 137 is a layer in which the magnetization direction, i.e., the spin direction, is fixed, and the free layer 136 is a layer in which the magnetization direction, i.e., the spin direction, is not fixed.

[0111] The resistance value of the MTJ element 47M changes depending on the relative orientation of the magnetization directions (indicated by the arrow symbol 139 in FIG. 12A ) of the free layer 136 and the fixed layer 137. That is, the MTJ element 47M can be in two states depending on the magnetization direction, as shown in FIG. 12A . The resistance change depending on the magnetization direction is called tunnel magnetoresistance (TMR). A state in which the magnetization directions of the free layer 136 and the fixed layer 137 are aligned is called a parallel state. In this state, the resistance value of the MTJ element 47M is minimum, and this state can be represented by “P” or data “0.” A state in which the magnetization directions of the free layer 136 and the fixed layer 137 are opposite is called an antiparallel state. In this state, the resistance value of the MTJ element 47M is maximum, and this state can be represented by “AP” or data “1.” Data can be written as "0" or "1" by controlling the magnetization state of the free layer 136 to be parallel or antiparallel to the fixed layer 137. The MTJ element 47M is a resistance change type memory element that utilizes the phenomenon that resistance changes depending on the magnetization direction.

[0112] The MTJ element 47M is nonvolatile, capable of high-speed rewriting, and in principle has an infinite number of rewriting times. The write current of the MTJ element 47M can be reduced as the element is miniaturized.

[0113] 12B is a diagram showing the principle of writing by the spin transfer method to change the magnetization directions of the free layer 136 and the fixed layer 137 in the MTJ element 47M from an antiparallel state to a parallel state.

[0114] As shown in FIG. 12B, to write from the antiparallel state (“AP”) to the parallel state (“P”), a current I ＡＰ At this time, the electrons flow as a current I ＡＰ (See dotted arrows.) This causes spins 133 to be injected from the pinned layer 137 into the free layer 136. The spin-polarized current acts on the magnetization of the free layer 136, reversing the magnetization of the free layer 136 to the same direction as the pinned layer 137, resulting in a parallel state. The injected spins 133 are shown by dashed arrows.

[0115] FIG. 12C is a diagram showing the principle of writing the magnetization directions of the free layer 136 and the fixed layer 137 in the MTJ element 47M from parallel to antiparallel by the spin transfer method.

[0116] As shown in FIG. 12C, in order to write from the parallel state (“P”) to the antiparallel state (“AP”), contrary to FIG. 12B, a current I Ｐ The injected spins are canceled out in the free layer 136, but the electrons reflected by the insulating layer 138 have magnetization in the opposite direction to that of the free layer 136. The spins reflected by the insulating layer 138 reverse the magnetization of the free layer 136, resulting in an antiparallel state. The reflected spins 133 are shown by dotted arrows.

[0117] The MTJ element 47M reverses the magnetization direction of the free layer 136 relative to the magnetization direction of the fixed layer 137 depending on the direction of the current flowing through it, and when the magnetization directions are parallel to each other, the magnetic resistance decreases. On the other hand, when the magnetization direction of the free layer 136 is antiparallel to the magnetization direction of the fixed layer 137, the magnetic resistance increases. Note that the free layer 136 and the fixed layer 137 in the MTJ element 47M can be interchanged by switching the direction of the current. Note that the current required to reverse the magnetization of the MTJ element 47M can be reduced by miniaturizing the element.

[0118] The OS transistor can be provided in a position overlapping with the through electrode. Therefore, a circuit including an OS transistor can be provided in a position overlapping with the substrate 25 on which the Si transistor is provided. This can suppress an increase in the circuit area due to the inclusion of both a Si transistor and an OS transistor. In addition, a configuration in which an MTJ element is provided over an OS transistor is also effective in suppressing an increase in the circuit area.

[0119] The OS transistor used as the access transistor needs to have a large width to pass a current for writing data to the MTJ element. When a Si transistor is used as the access transistor, both miniaturization and an increase in the write current are required. On the other hand, when an OS transistor is used as the access transistor, it is possible to design the transistor for miniaturization and the OS transistor for an increase in the write current separately for each layer. Therefore, within a limited cell area, it is possible to simultaneously increase the width of the OS transistor and miniaturize the MTJ element. This allows both high integration and low power consumption to be achieved. Furthermore, by increasing the current required for rewriting the MTJ element, data can be written and read more reliably from the MTJ element.

[0120] In addition, the off-state current of an OS transistor is small. Therefore, even if the access transistor is designed to have a large width in the W direction in order to pass a large current, an increase in leakage current when the access transistor is off can be suppressed. Therefore, a memory device with low power consumption can be provided. Furthermore, by applying a potential to the back gate electrode of the OS transistor, fluctuations in electrical characteristics such as threshold voltage can be suppressed.

[0121] FIG. 13 is a block diagram illustrating an imaging device as an example of a semiconductor device having a memory cell 46M including an MTJ element 47M described in this embodiment.

[0122] 13 includes a circuit unit 30 and an optical conversion layer 90 on a substrate 25 having a peripheral circuit 20. The circuit unit 30 has a configuration in which an element layer 40_1 and an element layer 40_2 are stacked on a substrate 50.

[0123] The substrate 50 has a photoelectric conversion device 83. For example, a photodiode or the like can be used as the photoelectric conversion device 83. The photoelectric conversion device 83 is preferably sensitive to visible light. For example, a Si photodiode using silicon for the photoelectric conversion layer can be used as the photoelectric conversion device 83.

[0124] The element layer 40_1 can be provided with, for example, a pixel circuit 81 connected to an optical conversion device and a driver circuit 82 for the pixel circuit. The driver circuit 82 can be formed in the same process as the pixel circuit 81. Note that the above-described photoelectric conversion device 83 can also be considered an element of the pixel circuit 81. By using OS transistors as the transistors included in the element layer 40_1, the transistors can be stacked with the transistors included in the element layer 40_2.

[0125] The element layer 40_2 can be provided with a memory circuit 60 including a plurality of memory cells 46M. When the transistors included in the element layer 40_2 are OS transistors, they can be stacked with the transistors included in the element layer 40_1.

[0126] When multiple transistors are stacked, polishing and bonding steps are required multiple times. Therefore, there are problems such as a large number of steps, the need for dedicated equipment, low yield, and high manufacturing costs. In one embodiment of the present invention, by forming a circuit using OS transistors included in the element layers 40_1 and 40_2 having OS transistors over the substrate 50, which is a Si device, the polishing and bonding steps can be eliminated.

[0127] By configuring the memory circuit 60 to be stacked with the pixel circuits 81 and the photoelectric conversion devices 83, it is possible to perform a global shutter operation in which multiple pixel circuits 81 simultaneously acquire data from the photoelectric conversion devices 83 and sequentially read the data, with a simple circuit configuration.

[0128] As described in the first embodiment, the peripheral circuit 20 of the substrate 25 is provided with a plurality of transistors 21, which are Si transistors. It is desirable for the peripheral circuit 20 to process data from the photoelectric conversion device 83 at high speed. In such a configuration, it is preferable to use transistors with high field-effect mobility. For example, it is preferable to use Si transistors. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single-crystal silicon). It should be noted that the driver circuit 82 of the pixel circuit may be partially or entirely formed of Si transistors.

[0129] The optical conversion layer 90 may include, for example, a color filter 91. The optical conversion layer 90 may also include a microlens array.

[0130] Next, FIG. 14 shows a schematic cross-sectional view having elements applicable to the imaging device 10IS described with reference to FIG.

[0131] As described in the first embodiment, the peripheral circuit 20 of the substrate 25 includes a plurality of transistors 21, which are Si transistors. The substrate 25 also includes electrodes 22, as described in the first embodiment. The electrodes 22 are electrodes for electrically connecting the plurality of transistors 21 to the circuit unit 30 located in the upper layer.

[0132] The element layer 40_2 included in the circuit unit 30 includes electrodes 41 to 43, a transistor 45_3, and an MTJ element 47M. The transistor 45_3 is an OS transistor corresponding to the transistor 45. As described above, the MTJ element 47M includes a free layer 136 made of a ferromagnetic material and a fixed layer 137 made of a ferromagnetic material, which are separated by an insulating layer 138, between the conductive layers 241 and 245.

[0133] The element layer 40_1 included in the circuit unit 30 includes transistors 45_1 and 45_2. The transistors 45_1 and 45_2 are OS transistors that can be used in the pixel circuit 81 and the driver circuit 82.

[0134] The substrate 50 of the circuit unit 30 has a photoelectric conversion device 83. The photoelectric conversion device 83 is a pn junction photodiode formed on the substrate 50, which is a silicon substrate, and has a p-type region 84 and an n-type region 85. The photoelectric conversion device 83 is a buried photodiode, and the thin p-type region 84 provided on the surface side (current extraction side) of the n-type region 85 can suppress dark current and reduce noise.

[0135] The substrate 50 may be configured to have grooves 86 that separate pixels, and an insulating layer provided in the grooves 86. This configuration can prevent carriers generated in the photoelectric conversion device 83 from flowing into adjacent pixels. An anti-reflection film may be provided on the upper surface of the substrate 50.

[0136] The optical conversion layer 90 includes a color filter 91 , a light-shielding layer 92 , and a microlens array 93 .

[0137] The light-shielding layer 92 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used as the light-shielding layer 92. The metal layer may also be laminated with a dielectric film that functions as an anti-reflection film.

[0138] When the photoelectric conversion device 83 is sensitive to visible light, a color filter 91 can be used in the optical conversion layer 90. A color image can be obtained by assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel.

[0139] The microlens array 93 allows light passing through each lens to pass through the color filter 91 directly below and then be irradiated onto the photoelectric conversion device 83. By providing the microlens array 93, concentrated light can be incident on the photoelectric conversion device 83, thereby enabling efficient photoelectric conversion. The microlens array 93 is preferably made of a resin or glass that is highly translucent to light of the target wavelength.

[0140] In one embodiment of the present invention described in this embodiment, when a plurality of element layers formed on different substrates are connected by through electrodes, elements such as transistors can be arranged in a region where the through electrodes are provided, as in Embodiment 1. Therefore, the memory density per unit area of ​​a semiconductor device can be improved.

[0141] Furthermore, an OS transistor with extremely low off-state current can be used as a transistor provided in the element layer. Therefore, the frequency of refreshing data stored in a memory cell can be reduced, thereby achieving low power consumption. The OS transistor can be stacked and repeatedly fabricated in the same vertical manufacturing process, thereby reducing manufacturing costs. In one embodiment of the present invention, transistors constituting a memory cell can be arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. Furthermore, since OS transistors have smaller fluctuations in electrical characteristics than Si transistors even under high-temperature conditions, a semiconductor device can function as a highly reliable memory device with less fluctuations in the electrical characteristics of the transistors when stacked and integrated.

[0142] In this embodiment, a configuration example of a semiconductor device according to one aspect of the present invention will be described, which is different from those of Embodiments 1 and 2. Note that detailed description of the same parts as those of Embodiments 1 and 2 will be omitted as they are incorporated herein by reference.

[0143] In this embodiment, a configuration example in which the element layer 40 has a memory circuit with a vertical channel type memory string will be described.

[0144] 15A is a diagram illustrating the circuit configuration of a memory string, in which a select transistor SST, memory transistors MT1 to MT2k (k is an integer equal to or greater than 1), and a select transistor SDT are electrically connected in series between a wiring BL and a source line SL.

[0145] The memory transistors MT1 to MT2k are transistors corresponding to the word lines WL1 to WL2k. For example, the memory transistor connected to the word line WL1 is the memory transistor MT1. When there is no need to distinguish between the memory transistors MT1 to MT2k, they are referred to as memory transistors MT. The same applies to the other elements.

[0146] The select transistors SST and SDT and the memory transistors MT1 to MT2k are each a vertical channel transistor whose semiconductor layer is made of metal oxide. The memory transistors MT have a charge storage layer and constitute nonvolatile memory cells.

[0147] The gates of the select transistors SST and SDT are electrically connected to select gate lines SGL and DGL, respectively. The gates of the memory transistors MT1 to MT2k are electrically connected to word lines WL1 to WL2k, respectively.

[0148] Next, FIG. 15B is a cross-sectional view illustrating an example of a memory string.

[0149] The element layer 40 having the memory cell strings has an insulating layer 330, an electrode 41 and an insulating layer 331, and a conductive layer 741 on a substrate 50. The conductive layer 742 and the insulating layer 724 are alternately stacked to form a stacked body. A columnar structure having an insulating layer 743, a charge storage layer 744, an insulating layer 745, a metal oxide layer 746, and an insulating layer 747 is provided so as to fill a hole provided in the stacked body.

[0150] In the columnar structure, the lower end of the metal oxide layer 746 is electrically connected to the conductive layer 741, and the upper end of the metal oxide layer 746 is electrically connected to one of the wiring BL and the wiring SL. The vicinity of the region where the conductive layer 742 overlaps with the insulating layer 743, the charge storage layer 744, the insulating layer 745, and the metal oxide layer 746 functions as the memory transistor MT. The vicinity of the region where the conductive layer 742, the insulating layer 747, and the metal oxide layer 746 overlap functions as the select transistors SDT and SST. The memory transistors MT or the select transistors SDT and SST are electrically connected in series, and these constitute a memory string.

[0151] The metal oxide layers, conductive layers, and insulating layers may be formed using the materials listed as examples of the metal oxide layers, conductive layers, and insulating layers described in FIG. 7 of the first embodiment. The metal oxide layers, conductive layers, and insulating layers may be formed using a sputtering method, a CVD method, a PLD method, an atomic layer deposition (ALD), or the like. The charge storage layer may be formed using, for example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium.

[0152] Although not shown, an opening reaching the electrode 41 is formed in the hole where the columnar structure is provided, and a conductor corresponding to the electrode 42 described in embodiment 1 is provided, thereby making it possible to electrically connect the front and back of the circuit unit.

[0153] In one embodiment of the present invention described in this embodiment, when a plurality of element layers formed on different substrates are connected by through electrodes, elements such as transistors can be arranged in a region where the through electrodes are provided, as in Embodiment 1. Therefore, the memory density per unit area of ​​a semiconductor device can be improved.

[0154] Embodiment Mode 4 In this embodiment mode, modifications of circuits applicable to the semiconductor device described in the above Embodiment Mode 1 will be described with reference to FIGS. 16A to 18C. FIG.

[0155] 16A illustrates a configuration example in which another functional circuit is added to the element layer 40 having the memory circuit 60 stacked on the substrate 50 in the configuration explained in FIG. 1A of Embodiment 1. The functional circuit has a function of selecting a wiring that outputs a data signal held in the memory circuit 60 and amplifying the data signal, for example.

[0156] 16A is a block diagram illustrating a semiconductor device 10c in which a functional circuit 62 is added to the element layer 40 of the circuit units 30_1 to 30_N described in Embodiment 1 in addition to a memory circuit 60. Although the memory circuit 60 and the functional circuit 62 are illustrated as being stacked in the element layer 40, they may be provided in the same layer. For example, the memory circuit 60 and the functional circuit 62 may be configured using OS transistors provided in the same layer.

[0157] 16B shows a circuit unit 30c that can be applied to the circuit units 30_1 to 30_N shown in FIG. 16A. The circuit unit 30c includes a substrate 50 and an element layer 40 provided in contact with the substrate 50.

[0158] The element layer 40 has a memory circuit 60, electrodes 41, 42, and 43, as well as a functional circuit 62. The substrate 50 and the element layer 40 have through electrodes 44. The functional circuit 62 is connected to the memory circuit 60 via wiring provided in the same layer as the electrode 42. The functional circuit 62 can be electrically connected to the peripheral circuit 20 and the element layer 40 of another circuit unit 30c via the electrodes 42, 41, 43, and through electrodes 44.

[0159] 17A shows an example of a functional circuit 62 connected to the memory cell 46 included in the memory circuit 60 shown in FIG. 3A. The functional circuit 62 includes an amplifier circuit 63 and a selection circuit 64 connected to each of the wirings BL. The amplifier circuit 63 and the selection circuit 64 can include an OS transistor and a capacitor, similar to the memory circuit 60 included in the element layer 40.

[0160] 17A, the wiring connected to the memory cell 46 is illustrated as wiring LBL, and the wiring selected by the selection circuit 64 is illustrated as wiring GBL. The wiring GBL may be called a global bit line. The wiring LBL may be called a local bit line. The wiring LBL and the wiring GBL function as bit lines for writing or reading data to or from the memory cell. Note that in the drawings, the wiring LBL and the wiring GBL may be illustrated as thick lines or dotted thick lines to improve visibility.

[0161] The amplifier circuit 63 has a function of amplifying and transmitting to the wiring GBL a current or a potential corresponding to the potential of the wiring LBL for connecting the memory cells 46. The selection circuit 64 has a function of selecting a signal corresponding to the current or the potential output from the wiring LBL and transmitting the selected signal to the wiring GBL.

[0162] 17B will describe a specific circuit configuration of a functional circuit 62 including the amplifier circuit 63 and the selection circuit 64 shown in FIG. 17B illustrates transistors 65 to 68 included in the circuit for achieving the amplification function and the selection function. The transistors 65 to 68 can each be formed using OS transistors, and are illustrated as n-channel transistors.

[0163] The transistor 65 is a transistor for controlling the potential of the wiring GBL to correspond to the potential of the wiring LBL during a period when data is read from the memory cell 46. The transistor 66 functions as a switch that receives a selection signal MUX at its gate and is controlled to be turned on or off between its source and drain in accordance with the selection signal MUX. The transistor 67 functions as a switch that receives a write control signal WE at its gate and is controlled to be turned on or off between its source and drain in accordance with the write control signal WE. The transistor 68 functions as a switch that receives a read control signal RE at its gate and is controlled to be turned on or off between its source and drain in accordance with the read control signal RE. The source side of the transistor 68 is supplied with a ground potential GND, which is a fixed potential.

[0164] The transistor 65 can amplify the potential of the wiring GBL to a potential obtained by amplifying the potential of the wiring LBL. The transistor 66 can select a signal corresponding to the current or potential output by the wiring LBL in response to the selection signal MUX and the read control signal RE, and transmit the selected signal to the wiring GBL. The functional circuit 62 includes the transistors 67 and 68, and thus can write and read data to and from the memory cell 46 via the wiring GBL and the wiring LBL.

[0165] A semiconductor device according to one embodiment of the present invention can be manufactured by repeatedly providing transistors in a vertical direction on a substrate using the same manufacturing process. In one embodiment of the present invention, OS transistors constituting memory cells are arranged vertically rather than planarly, thereby improving memory density and miniaturizing the device. By configuring the element layer 40 to include the functional circuit 62, the wiring LBL is connected to the gate of the transistor 65, and a data signal can be read out to the wiring GBL using a slight potential difference in the wiring LBL.

[0166] The functional circuit 62 described in one embodiment of the present invention may have another structure. For example, like a functional circuit 62A included in a circuit unit 30d illustrated in FIG. 18A , an amplifier circuit 63A can be connected to the wiring WL of the memory cell 46.

[0167] The amplifier circuit 63A included in the functional circuit 62A has a function of amplifying and transmitting a control signal applied to the wiring WL for the transistor 45. With this configuration, the on / off state of the transistor 45 can be more reliably controlled using a signal from the peripheral circuit 20 provided on the substrate 25.

[0168] When the circuit units 30_1 to 30_N have, for example, 100 layers or more, the distance between the peripheral circuit 20 and the element layer 40 of the circuit unit in the uppermost layer may be long. In this case, by providing a function for amplifying data in the function circuit 62 provided for each circuit unit, it becomes possible to input and output data between the memory cell in the uppermost layer and the peripheral circuit 20. Specifically, it becomes possible to input and output data between the memory cell 46 in the element layer 40 and the peripheral circuit 20 without a large difference in data write speed and data read speed, regardless of whether the circuit unit is in the uppermost layer or not.

[0169] Note that the amplifier circuit 63A included in the functional circuit 62A can be provided in the element layer 40 by using an OS transistor. For example, a signal from the peripheral circuit 20 can be amplified and output to the wiring WL using an inverter circuit including a transistor 70 and a transistor 71 as illustrated in FIG. 18B. Alternatively, a signal from the peripheral circuit 20 can be amplified and output to the wiring WL using an inverter circuit including a transistor 71 and a resistor 72 as illustrated in FIG. 18C.

[0170] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0171] Fifth Embodiment This embodiment shows an example of an integrated circuit (referred to as an IC chip) having a semiconductor device 10. The semiconductor device 10 can be made into a single IC chip by mounting multiple dies on a packaging substrate. Figures 19A and 19B show an example of the configuration.

[0172] The cross-sectional schematic diagram of an IC chip 100A shown in FIG. 19A includes a substrate 25 on a package substrate 101. As an example, four circuit units 30_1 to 30_4 are stacked on the substrate 25. The package substrate 101 is provided with solder balls 102 for connecting the IC chip 100A to a printed circuit board or the like. The circuit units 30_1 to 30_4 can be stacked by repeatedly forming OS transistors in an element layer 40 in contact with a substrate 50. A peripheral circuit (not shown) provided on the substrate 25 and each circuit included in the circuit units 30_1 to 30_4 can be connected by through-hole electrodes 44 provided through the substrate 50 and element layer 40 of each layer and electrodes 41 to 43 provided in the element layer. Each layer can be electrically connected via through-hole electrodes 44 provided through each layer and metal bumps 59 (also referred to as microbumps) provided between each electrode 43 and each layer.

[0173] As another example, the cross-sectional schematic diagram of an IC chip 100B shown in FIG. 19B has a substrate 25 on a package substrate 101, and, for example, four layers of circuit units 30_1 to 30_4 are stacked on the substrate 25. The peripheral circuit (not shown) provided on the substrate 25 and the memory circuits (not shown) of the circuit units 30_1 to 30_4 are bonded together using through electrodes 44 provided through the substrate 50 and element layer 40 of each layer, and electrodes 43 and through electrodes 44 among electrodes 41 to 43 provided on the element layer. Cu-Cu bonding can be used as a technique for electrically joining different layers using electrodes 43 and through electrodes 44. Cu-Cu bonding is a technique for achieving electrical conductivity by connecting Cu (copper) pads together.

[0174] Sixth Embodiment In this embodiment, details of the peripheral circuit 20 having a circuit for driving the memory circuit 60 functioning as a memory device in the semiconductor device 10 described in the first embodiment will be described.

[0175] 20 is a block diagram showing an example of the configuration of a semiconductor device functioning as a memory device. The semiconductor device 10s has a peripheral circuit 20 and a memory cell array 40MA having a plurality of memory circuits 40p. The peripheral circuit 20 has a row decoder 571, a word line driver circuit 572, a column driver 575, an output circuit 573, and a control logic circuit 574.

[0176] The column driver 575 includes a column decoder 581, a precharge circuit 582, an amplifier circuit 583, and a write circuit 584. The precharge circuit 582 has a function of precharging the wiring BL and the like. The amplifier circuit 583 has a function of amplifying a data signal read from the wiring BL. The amplified data signal is output to the outside of the semiconductor device 10s via the output circuit 573 as a digital data signal RDATA.

[0177] The semiconductor device 10s is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 20, and a high power supply voltage (VIL) for the memory cell array 40MA from the outside as power supply voltages.

[0178] The semiconductor device 10s also receives external control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA. The address signal ADDR is input to a row decoder 571 and a column decoder 581, and WDATA is input to a write circuit 584.

[0179] The control logic circuit 574 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 571 and the column decoder 581. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 574 are not limited to these, and other control signals may be input as needed. For example, a control signal for determining a defective bit may be input, and a data signal read from the address of a specific memory cell may be identified as a defective bit.

[0180] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0181] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 21 shows various storage devices by layer. The higher the layer, the faster the access speed required for the storage device, while the lower the layer, the larger the storage capacity and recording density required for the storage device. Figure 21 shows, from the top layer onward, memories embedded as registers in arithmetic processing units such as CPUs, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), and 3D NAND memories.

[0182] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0183] SRAM is used, for example, as a cache. A cache has the function of storing a copy of the information stored in the main memory. By storing a copy of frequently used data in the cache, the speed of accessing the data can be increased.

[0184] DRAM is used, for example, as main memory. Main memory has the function of storing programs, data, etc. read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm ２ is.

[0185] 3D NAND memory is used, for example, for storage. Storage has the function of storing data that requires long-term storage or various programs used in processing units. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / mm ２ is.

[0186] A semiconductor device functioning as a memory device according to one embodiment of the present invention has high operating speed and can retain data for a long period of time. The semiconductor device according to one embodiment of the present invention can be suitably used as a semiconductor device located in a boundary region 901 including both a layer where a cache is located and a layer where a main memory is located. The semiconductor device according to one embodiment of the present invention can also be suitably used as a semiconductor device located in a boundary region 902 including both a layer where a main memory is located and a layer where a storage is located.

[0187] Embodiment Mode 7 This embodiment mode will show an example of an electronic component and an electronic device in which the semiconductor device or the like described in the above embodiment modes is incorporated.

[0188] <Electronic Component> First, an example of an electronic component incorporating the semiconductor device 10 or the like will be described with reference to FIGS. 22A and 22B.

[0189] FIG. 22A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 22A includes a semiconductor device 10 in which a circuit unit 30 is stacked on a substrate 25 within a mold 711. The semiconductor device 10 described in the first embodiment can be used as the semiconductor device 10. FIG. 22A does not show part of the interior of the electronic component 700 in order to illustrate the interior. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 10 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to form a mounting substrate 704.

[0190] 22B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 10 provided on interposer 731.

[0191] The electronic component 730 shows an example in which the semiconductor device 10 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0192] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 may be a silicon interposer, a resin interposer, or the like.

[0193] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0194] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation on a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form on a resin interposer.

[0195] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0196] Furthermore, in SiP, MCM, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0197] A heat sink (heat dissipation plate) may be provided on top of the electronic component 730. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 10 with that of the semiconductor device 735.

[0198] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 22B shows an example in which electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0199] The electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0200] <Electronic Device> Next, an example of an electronic device including the above electronic components will be described with reference to FIG.

[0201] The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezoelectric sensor, optical sensor, gyro sensor, etc.), a movement mechanism, etc. The electronic component 730 includes a processor and the like, and has the function of controlling these peripheral devices. For example, the electronic component 700 has the function of storing data acquired by the sensors.

[0202] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sounds. The speaker has a function of emitting audio signals such as voice and warning sounds. The robot 7100 can analyze the audio signals input via the microphone and emit the necessary audio signals from the speaker. The robot 7100 can communicate with the user using the microphone and speaker.

[0203] The camera has a function of capturing images of the surroundings of the robot 7100. The robot 7100 also has a function of moving using a movement mechanism. The robot 7100 can capture images of the surroundings using the camera and analyze the images to detect the presence or absence of obstacles when moving.

[0204] The flying object 7120 has a propeller, a camera, a battery, etc., and has the function of flying autonomously. The electronic component 730 has the function of controlling these peripheral devices.

[0205] For example, image data captured by a camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of obstacles when moving. The electronic component 730 can also estimate the remaining battery charge from changes in the battery's charge capacity.

[0206] The cleaning robot 7140 has a display on its top surface, multiple cameras on its sides, a brush, operation buttons, various sensors, etc. Although not shown, the cleaning robot 7140 is equipped with tires, a suction port, etc. The cleaning robot 7140 can move on its own, detect dirt, and suck up the dirt through a suction port provided on its bottom surface.

[0207] For example, the electronic component 730 can analyze images captured by the camera to determine whether there are obstacles such as walls, furniture, steps, etc. Furthermore, if the image analysis detects an object that may become tangled in the brush, such as a wire, the rotation of the brush can be stopped.

[0208] The automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 730 performs control to optimize the driving state of the automobile 7160 based on data such as navigation information, speed, engine condition, gear selection state, and frequency of brake use. For example, image data captured by a camera is stored in the electronic component 700.

[0209] The electronic component 700 and / or the electronic component 730 can be incorporated into a TV device 7200 (television receiver), a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, a game console 7260, etc.

[0210] For example, the electronic component 730 built into the TV device 7200 can function as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

[0211] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by the electronic component 730.

[0212] The PC 7220 and the PC 7230 are examples of a notebook PC and a desktop PC, respectively. A keyboard 7232 and a monitor device 7233 can be connected to the PC 7230 wirelessly or via a wired connection. The game console 7240 is an example of a portable game console. The game console 7260 is an example of a desktop game console. A controller 7262 is connected to the game console 7260 wirelessly or via a wired connection. The electronic component 700 and / or the electronic component 730 can also be incorporated into the controller 7262.

[0213] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0214] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes are provided regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0215] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0216] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0217] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0218] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0219] In addition, in the block diagrams in this specification, components are classified by function and shown as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0220] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0221] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0222] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wirings" are integrally formed.

[0223] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0224] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0225] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0226] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0227] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0228] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, transmission of an electrical signal between A and B is possible.

[0229] 10: semiconductor device, 20: peripheral circuit, 25: substrate, 30_B: circuit unit layer, 30: circuit unit, 40: element layer, 41: electrode, 42: electrode, 43: electrode, 44: through electrode, 50: substrate, 60: memory circuit

Claims

1. A first substrate; a first element layer provided in contact with a second substrate; a first through electrode provided in the second substrate and the first element layer; the first element layer includes a first transistor, a first electrode, a second electrode, and a third electrode; the first transistor has a semiconductor layer having a metal oxide in a channel formation region; the first transistor has a region located between the first electrode and the third electrode; the first electrode is electrically connected to the third electrode via the second electrode; the third electrode is provided and exposed on a surface of the first element layer; the first through electrode is exposed on a surface of the second substrate and is electrically connected to the first electrode; the second substrate and the first element layer are stacked in a direction perpendicular or substantially perpendicular to a surface of the first substrate; The first transistor is provided in a region overlapping the first through electrode and the first electrode.

2. A first substrate; a first element layer provided in contact with a second substrate; a first through electrode provided in the second substrate and the first element layer; the first element layer includes a first memory cell, a first electrode, a second electrode, and a third electrode; the first memory cell includes a first transistor and a capacitor; the first transistor has a semiconductor layer having a metal oxide in a channel formation region; the first transistor has a region located between the first electrode and the third electrode; the first electrode is electrically connected to the third electrode via the second electrode; the third electrode is provided and exposed on a surface of the first element layer; the first through electrode is exposed on a surface of the second substrate and is electrically connected to the first electrode; the second substrate and the first element layer are stacked in a direction perpendicular or substantially perpendicular to a surface of the first substrate; The first transistor and the capacitor are provided in a region overlapping the first through electrode and the first electrode.

3. A first substrate; a first element layer provided in contact with a second substrate; a first through electrode provided in the second substrate and the first element layer; the first element layer includes a first memory cell, a first electrode, a second electrode, and a third electrode; the first memory cell includes a first transistor and a magnetic tunnel junction element; the first transistor has a semiconductor layer having a metal oxide in a channel formation region; the first transistor has a region located between the first electrode and the third electrode; the first electrode is electrically connected to the third electrode via the second electrode; the third electrode is provided and exposed on a surface of the first element layer; the first through electrode is exposed on a surface of the second substrate and is electrically connected to the first electrode; the second substrate and the first element layer are stacked in a direction perpendicular or substantially perpendicular to a surface of the first substrate; The first transistor and the magnetic tunnel junction element are provided in a region overlapping the first through electrode and the first electrode.

4. In claim 3, The magnetic tunnel junction element includes: A semiconductor device having a laminated structure of a free layer, an insulating layer, and a fixed layer.

5. A first substrate; a first element layer provided in contact with a second substrate; a first through electrode provided in the second substrate and the first element layer; the first element layer includes a plurality of first memory cells, a first circuit, a first electrode, a second electrode, and a third electrode; the first memory cell and the first circuit each have a first transistor; the first transistor has a semiconductor layer having a metal oxide in a channel formation region; the first transistor has a region located between the first electrode and the third electrode; the first electrode is electrically connected to the third electrode via the second electrode; the third electrode is provided and exposed on a surface of the first element layer; the first through electrode is exposed on a surface of the second substrate and is electrically connected to the first electrode; the second substrate and the first element layer are stacked in a direction perpendicular or substantially perpendicular to a surface of the first substrate; The first transistor is provided in a region overlapping the first through electrode and the first electrode.

6. In claim 5, The first memory cells are electrically connected to any one of a plurality of bit lines; The first circuit has a function of selecting one of the plurality of bit lines, and a function of amplifying and outputting a potential of the selected bit line.

7. In claim 5 or 6, the first memory cell is electrically connected to a word line; The first circuit has a function of amplifying a signal provided to the word line.

8. In any one of claims 1 to 3 and claim 5, The first substrate is provided with a first peripheral circuit having a function of driving the first transistor.

9. In any one of claims 1 to 3 and claim 5, the second electrode is an electrode provided in the same layer as an electrode connected to the first transistor.

10. In any one of claims 1 to 3 and claim 5, The semiconductor device, wherein the second substrate is a silicon substrate.

11. In any one of claims 1 to 3 and claim 5, The metal oxide comprises In, Ga, and Zn.