Voltage regulator and power conversion device

Abstract

The problem of the present invention is to suppress the ripple of output current without using a large noise filter while maintaining a responsiveness to load variation. This voltage regulator comprises: a plurality of chopper circuits connected in parallel and each outputting, after switching an input voltage, the input voltage from an output terminal via the first inductor of the primary winding of a transformer in which the primary winding and a secondary winding are magnetically coupled; and a second series circuit in which a first series circuit and a third inductor are connected in series and both ends of which are connected to first and second connection points connected to each other, said first series circuit being configured by connecting, in series, the respective second inductors of the secondary windings of the respective transformers of the plurality of chopper circuits. The voltage regulator is provided with a first capacitor connected between the first connection point and the output terminal and a fourth inductor. The fourth inductor is connected between the first connection point and an end of the second inductor connected nearest to the first connection point.

Description

Voltage regulator and power conversion device

[0001] The present disclosure relates to a voltage regulator and a power conversion device including the voltage regulator.

[0002] The power consumption of a central processing unit (CPU) or graphics processing unit (GPU) for a server device changes rapidly depending on its operating state. Therefore, a CPU power supply or GPU power supply must be able to quickly respond to load fluctuations and output a constant voltage with high precision. While interleaved step-down DC-DC converter circuits have been used up until now, trans-inductor voltage regulators (TLVRs) have recently been proposed.

[0003] Non-Patent Documents 1 and 2 disclose the circuit configuration of a TLVR. In a TLVR, the reactors of each phase in an interleaved step-down DCDC converter circuit are replaced with transformers, and the secondary winding of the transformer and a compensation inductor are connected in series to form a loop circuit. When the load fluctuates, an induced current is generated in this loop circuit, allowing the output current of the TLVR to be changed instantaneously.

[0004] Anonymous, "Fast multi-phase trans-inductor voltage regulator," Defensive Publications Series, Art. 2194 [2019}, Published by Technical Disclosure Commons on May 09, 2019, [Retrieved September 26, 2021], Internet, <URL: https: / / www.tdcommons.org / cgi / viewcontent.cgi?article=3261&context=dpubs_series> Nian Zhang et al., "Analysis of Multi-Phase Trans-Inductor Voltage Regulator with Fast Transient Response for Large Load Current Applications," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Conference Proceedings, pp.1-5, published on April 27, 2021

[0005] However, the output current of the TLVR contains ripple components of the order of the phase number of the switching frequency. Therefore, a large noise filter is required to suppress noise propagating to the CPU or GPU. This may hinder the miniaturization of the power supply circuit.

[0006] TLVRs are expected to be used as POL (Point of Load) power supplies, which place power supply circuits in close proximity to devices such as CPUs or GPUs. As noise filters that filter the output current become larger, the wiring length to the load increases, raising concerns about increased voltage drop or power loss due to the resistance of the wiring. Therefore, POL power supplies are required to suppress output current ripple without using large noise filters.

[0007] An object of the present disclosure is to provide a voltage regulator, such as a TLVR, that can suppress ripple in output current while maintaining responsiveness to load fluctuations without using a large noise filter, and a power conversion device that includes the voltage regulator.

[0008] A voltage regulator according to one aspect of the present disclosure comprises: a plurality of chopper circuits connected in parallel between an input terminal and an output terminal, each of which switches an input voltage input to the input terminal and then outputs the voltage from the output terminal via a first inductor of a primary winding of a transformer whose primary winding and secondary winding are magnetically coupled; a first series circuit formed by connecting in series second inductors of secondary windings of each of the transformers of the plurality of chopper circuits; and a second series circuit in which a third inductor is connected in series, the second series circuit being connected to first and second connection points that are connected to each other at both ends of the second series circuit; a first capacitor connected so as to be inserted between the first connection point and the output terminal; and a fourth inductor, wherein: (1) the fourth inductor is connected so as to be inserted between the first connection point and one end of a second inductor connected in close proximity to the first connection point; (2) the fourth inductor is connected so as to be inserted between the second connection point and one end of a second inductor connected in close proximity to the second connection point; (3) The fourth inductor is connected so as to be inserted between any pair of adjacent inductors among the plurality of second inductors.

[0009] Therefore, the voltage regulator according to one aspect of the present disclosure can significantly suppress ripple in the output current, which reduces the number of noise filters and enables the device to be made smaller, lighter, and less expensive than conventional power conversion devices.

[0010] 1 is a circuit diagram showing an example configuration of a DCDC converter 1 including a voltage regulator according to a first embodiment. FIG. 2 is a circuit diagram showing a configuration of a DCDC converter 1A including an interleaved step-down chopper circuit according to a first conventional example. FIG. 3 is a timing chart of gate control signals and currents showing the operation of the DCDC converter 1A of FIG. 2. FIG. 4 is a circuit diagram showing a configuration of a DCDC converter 1B including a TLVR according to a second conventional example. FIG. 5 is a timing chart of gate control signals and currents showing the operation of the DCDC converter 1B of FIG. 4. FIG. 6 is a timing chart of gate control signals and currents showing the operation of the DCDC converter 1 of FIG. 1. FIG. 7 is a waveform diagram of a total current I1 showing a simulation result of the DCDC converter 1B of FIG. 4. FIG. 8 is a waveform diagram of an output current I2 showing a simulation result of the DCDC converter 1 of FIG. 1. FIG. 9 is a circuit diagram showing an example configuration of a DCDC converter 1C including a voltage regulator according to a first modified example. FIG. 10 is a circuit diagram showing an example configuration of a DCDC converter 1D including a voltage regulator according to a second modified example. FIG. 11 is a circuit diagram showing an example configuration of a DCDC converter 1F including a voltage regulator according to a third modified example. 13 is a circuit diagram showing a configuration example of a DCDC converter 1E including a voltage regulator according to embodiment 2. It is a diagram showing a setting example table of a capacitor C3 of the DCDC converter 1E of Fig. 12. It is a waveform diagram of an output current I2 showing a simulation result of the DCDC converter 1E of Fig. 12. It is a block diagram showing a configuration example of a power conversion device 100 according to embodiment 3.

[0011] Hereinafter, embodiments and modifications of the present disclosure will be described with reference to the drawings, in which the same or similar components are denoted by the same reference numerals.

[0012] 1 is a circuit diagram showing a configuration example of a DC-DC converter 1 including a voltage regulator according to embodiment 1. Here, the DC-DC converter 1 is an example of a power converter.

[0013] 1, the DCDC converter 1 includes a smoothing capacitor C1, multiple n step-down chopper circuits B1 to Bn connected in parallel with each other, and a smoothing capacitor C2 connected in series between an input terminal T1 and an output terminal T2. The smoothing capacitor C1 smoothes an input voltage Vin, which is a DC voltage applied to the input terminal T1, and outputs the smoothed voltage to each of the step-down chopper circuits B1 to Bn. The step-down chopper operation (or step-down switching operation) of each of the step-down chopper circuits B1 to Bn is controlled based on gate control signals Sg11, Sg12; Sg21, Sg22; ...; Sgn1, Sgn2 from a control circuit 10. That is, each of the step-down chopper circuits B1 to Bn includes a switching circuit 11-1 to 11-n, which switches the input voltage Vin according to gate control signals Sg11, Sg12; Sg21, Sg22; ...; Sgn1, Sgn2, thereby converting it into an AC voltage and outputting it to the inductors Lp1 to Lpn of the primary windings of the transformers TR1 to TRn. The output currents I11, I12, ..., I1n from each of the step-down chopper circuits B1 to Bn are combined at the output terminal T2, and a portion of the total current I1, current I3, flows through capacitor C3. The remaining current I2 (= I1 - I3), is output to load 20 via smoothing capacitor C2. Here, the voltage at output terminal T2 is defined as output voltage Vout.

[0014] Next, the detailed configuration of each of the step-down chopper circuits B1 to Bn will be described below.

[0015] The step-down chopper circuit B1 includes a pair of switch elements St1 and Sb1 connected in series to form a switching circuit 11-1, and a transformer TR1. Here, switch element St1 is a high-side switch element, and switch element Sb1 is a low-side switch element. The connection point between the source of switch element St1 and the drain of switch element Sb1 is connected to one end (winding start point; indicated by a black circle) of a primary winding inductor Lp1 of the transformer TR1. The transformer TR1 is composed of a primary winding inductor Lp1 and a secondary winding inductor Ls1 that are magnetically coupled in opposite directions. The other end (winding end point) of the primary winding inductor Lp1 is connected to the output terminal T2.

[0016] Similar to the step-down chopper circuit B1, the step-down chopper circuit B2 includes a pair of switch elements St2 and Sb2 connected in series to form the switching circuit 11-2, and a transformer TR2. The transformer TR2 includes a primary winding inductor Lp2 and a secondary winding inductor Ls2 that are magnetically coupled in opposite directions. The other end (winding end point) of the primary winding inductor Lp2 is connected to the output terminal T2.

[0017] The step-down chopper circuits B3 to Bn are configured similarly to the step-down chopper circuits B1 and B2. Like the step-down chopper circuits B1 and B2, the step-down chopper circuit Bn is configured with a pair of switch elements Stn and Sbn connected in series to form a switching circuit 11-n, and a transformer TRn. The transformer TRn is configured with a primary winding inductor Lpn and a secondary winding inductor Lsn that are magnetically coupled in opposite directions. The other end (winding end point) of the primary winding inductor Lpn is connected to the output terminal T2.

[0018] The output terminal T2 is grounded via capacitor C3, node N1, and inductor L1, and node N1 is grounded via inductor L2, one end (winding end point) and the other end (winding start point) of inductor Ls1, one end (winding end point) and the other end (winding start point) of inductor Ls2, ..., and one end (winding end point) and the other end (winding start point) of inductor Lsn. That is, node N1 is a first connection point connecting one end of inductor L1, one end of inductor L2, and one end of capacitor C3. The first connection point is also connected to one end of inductor Ls1 via inductor L2 and a second connection point. Here, the current flowing through capacitor C3 is I3, the current flowing through inductor L2 is I5, and the current flowing through inductor L1 is I4.

[0019] 1, in the continuous current mode, when the duty ratio of the gate control signal Sg11 of the switch element St1 is D, the duty ratio of the gate control signal Sg12 of the switch element Sb1 is (1-D), and the switch elements St1 and Sb1 are controlled to be alternately turned on / off. However, strictly speaking, a certain dead time Td (see FIG. 5, etc.) is provided from the time one switch element is turned off until the other switch element is turned on so that the switch elements St1 and Sb1 are not turned on at the same time.

[0020] The DC-DC converter 1 including the voltage regulator configured as described above is an interleaved circuit with n phases, in which n step-down chopper circuits B1 to Bn are connected in parallel to the input terminal T1. Gate control signals Sg11 to Sgn2 are provided from the control circuit 10 so that the step-down chopper circuits B1 to Bn of each phase operate with an operating phase shift of 2π / n. A voltage Vout is output to the output terminal T2, and its relationship to the input voltage Vin is expressed by the following equation:

[0021] Vout = D x Vin

[0022] FIG. 2 is a circuit diagram showing the configuration of a DCDC converter 1A including an interleaved step-down chopper circuit according to Conventional Example 1.

[0023] 2, the DCDC converter 1A differs from the DCDC converter 1 of FIG. 1 in the following respects: (1) The inductor Ls1 of the secondary winding of TR1 is eliminated, and a step-down chopper circuit B1a is configured with a switching circuit 11-1 consisting of a pair of switch elements St1 and Sb1 and an inductor Lp1. (2) The inductor Ls2 of the secondary winding of TR2 is eliminated, and a step-down chopper circuit B2a is configured with a switching circuit 11-2 consisting of a pair of switch elements St2 and Sb2 and an inductor Lp2. (3) Similarly, the inductor Lsn of the secondary winding of TRn is eliminated, and a step-down chopper circuit Bna is configured with a switching circuit 11-n consisting of a pair of switch elements Stn and Sbn and an inductor Lp2n. (4) The inductors L1 and L2 and the capacitor C3 are eliminated. (5) The output voltage Vout at the output terminal T2 is output to the load 20 as the output voltage Vout3 via the noise filter 12 and the output terminal T3.

[0024] In the DC-DC converter 1A according to Conventional Example 1 configured as described above, for example, focusing on the step-down chopper circuit B1a, the current in the inductor Lp1 increases when the high-side switch element St1 is on and decreases when it is off.

[0025] FIG. 3 is a timing chart of gate control signals and currents illustrating the operation of the DCDC converter 1A of FIG. 2. The DCDC converter 1A of FIG. 2 repeats the same operation with a period Tp. Here, FIG. 3 shows the currents of the inductors Lp1 to Lp4 of each phase and their total current I1, assuming, for example, a four-phase configuration. The total current I1 includes a ripple component that is multiple of the switching frequency (four times in FIG. 3 ). Ripple components that cannot be completely absorbed by capacitor C2 propagate to the load 20 (CPU or GPU), and therefore must be suppressed by providing a separate noise filter 12 between the output terminal T2 and the load.

[0026] FIG. 4 is a circuit diagram showing the configuration of a DCDC converter 1B including a TLVR according to Conventional Example 2.

[0027] 4, the DCDC converter 1B differs from the DCDC converter 1 in FIG. 1 in the following respects: (1) the inductor L2 and the capacitor C3 are eliminated, and (2) the output voltage Vout at the output terminal T2 is output to the load 20 as the output voltage Vout3 via the noise filter 12 and the output terminal T3.

[0028] In the DCDC converter 1B configured as described above, compared to the DCDC converter 1A including the interleaved step-down chopper circuit of FIG. 2, the currents I11 to I1n of the inductors Lp1 to Lpn are also affected by other phases through the loop circuit of inductors L1 and Ls1 to Lsn.

[0029] Fig. 5 is a timing chart of each gate control signal and each current, illustrating the operation of the DCDC converter 1B of Fig. 4. Here, Fig. 5 shows the currents of the inductors Lp1 to Lp4 of each phase and their total current I1, for example, when the number of phases is four. As with the DCDC converter 1A of Fig. 3, the total current I1 contains a ripple component that is multiple of the switching frequency by the number of phases (four times in Fig. 5), and therefore, a noise filter 12 (Fig. 4) is required.

[0030] Although it depends on the set circuit constants, the ripple component contained in the output current of the DCDC converter 1B including the TLVR according to Conventional Example 2 is likely to be larger than that of the interleaved step-down chopper circuit according to Conventional Example 1. This is because, as can be seen from a comparison of Figures 3 and 5, the current of the inductors Lp1 to Lp4 of each phase of the TLVR according to Conventional Example 2 contains a ripple component whose frequency is equal to the number of phases of the switching frequency. Therefore, in order to utilize the TLVR according to Conventional Example 2 as a POL power supply, a technique for suppressing the ripple component of the total current I1 is important.

[0031] Finally, the operation of the DCDC converter 1 according to embodiment 1 will be described using the current path diagram shown in Fig. 1. Compared to the DCDC converter 1B including the TLVR according to conventional example 2, a current component I3 of the total current I1 of the inductors Lp1 to Lpn flows to the capacitor C3, causing a current I2 (= I1 - I3) to flow to the output terminal T2.

[0032] Fig. 6 is a timing chart of each gate control signal and each current, showing the operation of the DCDC converter 1 of Fig. 1. As will be described in detail later, when the capacitance value of capacitor C3 is set correctly, the ripple component of output current I2 can be suppressed as shown in Fig. 8. On the other hand, when the capacitance value of capacitor C3 is not specified or is set incorrectly, the ripple component of output current I2 may be amplified.

[0033] Furthermore, in the DCDC converter 1 according to the first embodiment shown in FIG. 1 , there is a loop circuit consisting only of inductors L1, L2, and Ls1 to Lsn. Furthermore, in the DCDC converter 1B according to the second conventional example shown in FIG. 4 , there is a loop circuit consisting only of inductors L1 and Ls1 to Lsn. This loop circuit consisting only of inductors can achieve high-speed load response performance. For example, when increasing the output current due to a sudden change in load, in the case of the DCDC converter 1A according to the first conventional example shown in FIG. 2 , which includes the interleaved step-down chopper circuit, increasing the current in the inductors Lp1 to Lpn of each phase requires time to store magnetic energy in the magnetic cores of the inductors Lp1 to Lpn, and therefore, instantaneous response is not possible.

[0034] On the other hand, in the DCDC converter 1B including the TLVR according to Conventional Example 2 or the DCDC converter 1 according to Embodiment 1, the current in the inductors Lp1 to Lpn of each phase can be increased without storing magnetic energy in the magnetic core by inducing a current in the above-described loop circuit. That is, the DCDC converter 1 according to Embodiment 1 can suppress noise current at the output terminal T2 while maintaining a load response equivalent to that of the DCDC converter 1B including the TLVR according to Conventional Example 2. Note that even in a circuit similar to the DCDC converter 1, a high-speed load response cannot be achieved in a circuit that does not have a loop of only inductors, for example, by inserting a capacitor in series with the inductors Ls1 to Lsn.

[0035] Next, with reference to FIG. 1, the setting conditions of the capacitor C3 for suppressing noise in the output current I2 will be described.

[0036] Here, the switching frequency of the switching circuits 11-1 to 11-n for each phase is set to fs (switching angular frequency ωs = 2πfs), and the number of interleaved phases is set to n. As described above, when the operating phases of the switching circuits 11-1 to 11-n for each phase are shifted by 2π / n, the interleaving effect cancels out the 1st to (n-1st) order current components, and they do not appear in the output current I2. Therefore, it is important to suppress the multiple nth order current components. In the following equation expansion, frequency components other than the nth order are ignored. Furthermore, the inductance of inductors Lp1 to Lpn is set to Lp, and the inductance of inductors Ls1 to Lsn is set to Ls. Assume that inductors Lp1 to Lpn and inductors Ls1 to Lsn are tightly coupled, and the coupling coefficient can be approximated to 1.

[0037] A plurality of n-th order ripple components ip contained in the current flowing through the inductors Lp1 to Lpn of each phase are defined by the following equation (1).

[0038] (1)

[0039] Here, A is a predetermined constant.

[0040] In FIG. 1, in the total current I1, the n-th order ripple components contained in the currents flowing through the inductors Lp1 to Lpn of each phase are in phase and reinforce each other. Therefore, the instantaneous current i １ The n-th order ripple component contained in is expressed by the following equation (2).

[0041] (2)

[0042] When all of the n-th order ripple components contained in the total current I1 flow through the capacitor C3 (I1=I3), the voltage v3 between the terminals of the capacitor C3 is expressed by the following equation (3).

[0043] (3)

[0044] At this time, the potential of the node N1 oscillates in the opposite phase to the terminal voltage v3 of the capacitor C3, so the instantaneous current i of the current I4 flowing through the inductor L1 ４ and the instantaneous current i of the current I5 flowing through the inductor L2. ５ are expressed by the following equations (4) and (5), respectively.

[0045] (4)

[0046] (5)

[0047] According to Kirchhoff's current law, the current I3=I4+I5, and the conditional expression for the capacitor C3 that satisfies this is expressed by the following expression (6).

[0048] (6)

[0049] When the capacitor C3 satisfies the above equation (6), the current I1 = I3, and therefore, according to Kirchhoff's current law, the output current I2 = 0, and the output current I2 does not contain any n-th order current components. In other words, the n-th order noise current components can be completely canceled out.

[0050] Although the above conditions are optimal, if the capacitance value of the capacitor C3 is set as shown in the following equation (7), a noise reduction effect of 6 dB or more can be obtained. In other words, the amplitude of the noise current can be reduced by half or more.

[0051] (7)

[0052] In this case as well, by reducing the number of components in the noise filter 12, it is possible to achieve a smaller size and lower costs.

[0053] As shown in Fig. 1, the magnetic coupling between the inductors Lp1 to Lpn and the inductors Ls1 to Lsn is such that the magnetic fluxes reinforce each other when current flows from the terminals at the winding start points marked with black circles, thereby achieving the above-mentioned noise suppression effect.

[0054] Next, the inventors performed a circuit simulation on a DC-DC converter 1 including four-phase interleaved (n=4) step-down chopper circuits B1 to B4 that operate in four different phases, as an example. The effect of reducing ripple current will be shown below with reference to the results of the circuit simulation.

[0055] First, the simulation results of the DCDC converter 1B including the TLVR according to Conventional Example 2 shown in FIG. 4 will be described below.

[0056] 7 is a waveform diagram of the total current I1, showing the results of a simulation of the DCDC converter 1B of FIG. 4. Here, the inductances Lp and Ls are set to 1 μH, the inductor L1 is set to 0.2 μH, and the switching frequency fs is set to 200 kHz. The input voltage Vin is set to 12 V, and the output voltage Vout is set to 1.8 V.

[0057] As is clear from FIG. 7, the total current I1 contains a triangular wave ripple component four times the switching frequency, as also shown in FIG. 5, and its amplitude is as large as 75 Ap-p.

[0058] Next, a description will be given of the simulation results of the DCDC converter 1 according to the first embodiment shown in Fig. 1. Here, it is assumed that the inductances Lp and Ls are 1 µH, the inductor L1 is 20 nH, the inductor L2 is 0.2 µH, and the switching frequency fs is 200 kHz. In this case, the optimum capacitance value of the capacitor C3 is calculated to be 2.61 µF according to equation (6).

[0059] 8 is a waveform diagram of the output current I2 showing the simulation results of the DCDC converter 1 of FIG. 1. Here, it is assumed that the input voltage Vin=12V and the output voltage Vout=1.8V.

[0060] As is clear from FIG. 8 and also shown in FIG. 6, the ripple component of four times the switching frequency contained in the total current I1 was removed, and the amplitude of the output current I2 was significantly suppressed to 13 App.

[0061] The response speed to a sudden change in load capacitance is determined by the total inductance of the inductor loop circuit. In the above simulation, the value of Ls is set to be the same for Conventional Example 2 and Embodiment 1. Therefore, when comparing other inductances, Conventional Example 2 has L1 = 0.2 μH, while Embodiment 1 has L1 + L2 = 0.22 μH, resulting in approximately the same response speed.

[0062] In the above embodiment, the case of a four-phase interleaved DCDC converter 1 has been described, but the number of phases is not limited, and the present invention may be applied to an interleaved DCDC converter with any number of n phases, such as 16 phases. This makes it possible to suppress noise in the output current I2 in an interleaved DCDC converter with any number of phases.

[0063] As described above, according to the present embodiment, it is possible to provide a voltage regulator such as a TLVR that can suppress ripples in output current while maintaining responsiveness to load fluctuations without using a large noise filter, and a power conversion device that includes the voltage regulator.

[0064] (Modification 1) In the above embodiment, one pair, multiple pairs, or a combination of three or more inductors among the inductors Lp1 to Lpn may be magnetically coupled to each other. An example of this will be described below.

[0065] Fig. 9 is a circuit diagram showing a configuration example of a DCDC converter 1C including a voltage regulator according to Modification 1. The DCDC converter 1C of Fig. 9 is an example of a power converter. For example, as shown in Fig. 9, in the case of a four-phase interleaved DCDC converter, inductors Lp1 and Lp2 may be magnetically coupled by MC1, and inductors Lp3 and Lp4 may be magnetically coupled by MC2. Note that the magnetic coupling of Modification 1 may be applied to other modifications and other embodiments.

[0066] Similarly, in the case of an 8-phase or 16-phase interleaved DCDC converter, for example, inductors of four phases may be magnetically coupled together, which can further increase the response speed to load fluctuations compared to a case where no magnetic coupling is used.

[0067] The switch elements St1 to Stn and Sb1 to Sbn may be transistors such as MOS field effect transistors (MOSFETs) or GaN-HEMTs (High Mobility Electron Transistors). Alternatively, diodes may be used for the switch elements Sb1 to Sbn.

[0068] 1, inductor L2 and inductors Ls1 to Lsn are connected in series, so the order of their connection may be reversed. That is, inductor L2 may be connected so as to be inserted between node N1 and inductor Ls1 as shown in FIG. 1, or may be connected as follows: (1) inductor L2 may be connected so as to be inserted between one end of inductor Lsn connected to ground and ground. (2) inductor L2 may be connected so as to be inserted between any pair of adjacent inductors among the plurality n of inductors Ls1 to Lsn. This makes it possible to optimize the component layout on the circuit board and further reduce the mounting area.

[0069] (Modification 2) Fig. 10 is a circuit diagram showing a configuration example of a DCDC converter 1D including a voltage regulator according to Modification 2. In Fig. 10, the DCDC converter 1D according to Modification 2 differs from the DCDC converter 1 according to Embodiment 1 shown in Fig. 1 in the following respects: (1) An inductor L3 is further provided between the node N1 and the capacitor C3. Note that the insertion of the inductor L3 according to Modification 2 may be applied to other modifications and other embodiments.

[0070] In the DC-DC converter 1D configured as described above, even when the inductance of the inductor L1 is relatively small, it is possible to prevent a large current such as an inrush current from flowing through the capacitor C3 and causing damage to other components. Here, since the inductor L3 and the capacitor C3 are connected in series, the order of their connection may be reversed.

[0071] (Modification 3) Fig. 11 is a circuit diagram showing a configuration example of a DCDC converter 1F including a voltage regulator according to Modification 3. In Fig. 11, the DCDC converter 1F according to Modification 3 differs from the DCDC converter 1 according to Embodiment 1 shown in Fig. 1 in the following respects: (1) A switch SW1 is further provided between the node N1 and the capacitor C3. (2) The switch SW1 switches on and off in response to a command from the control circuit 10. Note that the insertion of the switch SW1 according to Modification 3 may be applied to other modifications and other embodiments.

[0072] The switch SW1 may be configured with a transistor such as a MOSFET or a GaN-HEMT. Alternatively, the switch SW1 may be configured with a mechanical switch such as a relay. When a transistor is used as the switch SW1, the terminal closer to the node N1 may be used as the source terminal.

[0073] In the DC-DC converter 1F configured as described above, by keeping the switch SW1 on during normal operation, both ripple suppression and fast response are achieved. On the other hand, when the switch SW1 is off, only the ripple suppression function can be disabled. For example, if an abnormal overcurrent flows through the capacitor C3, the breakdown of the capacitor C3 can be prevented by temporarily turning off the switch SW1. Furthermore, by turning off the switch SW1 in the event of breakdown of the capacitor C3, power conversion can be continued without impairing transient response performance. In other words, the power supply function can be maintained until the load is safely stopped (shutdown). Here, since the switch SW1 and the capacitor C3 are connected in series, their connection order may be reversed.

[0074] 12 is a circuit diagram showing a configuration example of a DCDC converter 1E including a voltage regulator according to a second embodiment. In FIG. 12, the DCDC converter 1E according to the second embodiment differs from the DCDC converter 1 according to the first embodiment shown in FIG. 1 in the following respects: (1) A magnetic coupling MC11 is provided between the inductor L1 and the inductor L2. Note that the magnetic coupling according to the second embodiment may be applied to other modifications and other embodiments.

[0075] The basic operation and effects of the DCDC conversion device 1E configured as above are similar to those of the first embodiment shown in Fig. 6. However, the setting conditions for the capacitor C3 are different due to the magnetic coupling MC11 between the inductors L1 and L2.

[0076] Fig. 13 is a diagram showing a setting example table of the capacitor C3 of the DCDC conversion device 1E of Fig. 12. Hereinafter, setting conditions of the capacitor C3 for suppressing noise in the output current I2 will be described with reference to Fig. 13.

[0077] The switching frequency of the switching circuits 11-1 to 11-n for each phase is fs (switching angular frequency ωs = 2πfs), and the number of interleaved phases is n. As described above, when the switching circuits 11-1 to 11-n for each phase are operated with the phase shifts of 2π / n, the interleaving effect cancels out the 1st to (n-1st) order current components and they do not appear in the output current I2. Therefore, it is important to suppress the multiple nth order current components. In the following equation expansion, frequency components other than the multiple nth order are ignored. Also, let Lp be the inductance of inductors Lp1 to Lpn, and Ls be the inductance of inductors Ls1 to Lsn. Inductors Lp1 to Lpn and inductors Ls1 to Lsn are tightly coupled, and the coupling coefficient can be approximated to 1. Meanwhile, let k12 be the coupling coefficient between inductors L1 and L2.

[0078] An n-th order ripple component ip contained in currents I11 to I1n flowing through inductors Lp1 to Lpn of switching circuits 11-1 to 11-n of the respective phases is defined by the following equation (1) (listed again):

[0079] (1)

[0080] 12, in the total current I1, the n-th order ripple components contained in the currents flowing through the inductors Lp1 to Lpn of the switching circuits 11-1 to 11-n of the respective phases are in phase and reinforce each other. Therefore, the n-th order ripple component contained in the total current I1 is expressed by the following equation (2) (listed again):

[0081] (2)

[0082] Here, when all of the n-th order ripple components contained in the total current I1 flow through the capacitor C3 (I1=I3), the voltage v3 between the terminals of the capacitor C3 is expressed by the following equation (3) (listed again):

[0083] (3)

[0084] At this time, the potential of node N1 oscillates in antiphase with the inter-terminal voltage v3 of capacitor C3, so the current I4 flowing through inductor L1 and the current I5 flowing through inductor L2 are expressed by the following equations (8) and (9), respectively.

[0085] (8)

[0086] (9)

[0087] Here, according to Kirchhoff's current law, I3=I4+I5, and the conditional expression for the capacitor C3 that satisfies this is given by the following expression (10).

[0088] (10)

[0089] When the capacitor C3 satisfies the above equation (10), the current I1 = I3, and therefore, according to Kirchhoff's current law, the output current I2 = 0, and the output current I2 does not contain any n-th order current components. In other words, the n-th order noise current components can be completely canceled out.

[0090] The above formula (10) is the optimum condition.

[0091] Next, referring to Figure 13, a guideline (approximate values) for the setting range to obtain an effective noise reduction effect is shown. Here, the inductances Lp = Ls = 1 μH, inductor L1 = 20 nH, inductor L2 = 0.2 μH, switching frequency fs = 200 kHz, and number of phases n = 4. The vertical axis of Figure 13 represents the coupling coefficient k12 between inductors L1 and L2. The horizontal axis of Figure 13 represents the ratio of current I3 to total current I1 shown in Figure 12.

[0092] As is clear from Figure 13, when I3 / I1 = 0.5, Kirchhoff's current law dictates that I2 = I1 - I3 = 0.5 x I1, so the ripple contained in the output current I2 is halved. When I3 / I1 = 1, Kirchhoff's current law dictates that the output current I2 = I1 - I3 = 0, so the ripple contained in the output current I2 is 0. When I3 / I1 = 1.5, Kirchhoff's current law dictates that I2 = I1 - I3 = -0.5 x I1, so the ripple contained in the output current I2 is halved. In other words, the parentheses in Figure 13 indicate the value of capacitor C3 to achieve a noise reduction effect of more than half. The values ​​shown are the capacitance multipliers for each of these values ​​relative to the capacitance value of capacitor C3 under optimal conditions (I3 / I1 = 1).

[0093] For example, when the coupling coefficient k12 is 0.4, the range of capacitance C3 that achieves more than half the noise reduction effect is 1.76 μF to 1.90 μF, which is 0.94 to 1.02 times the optimal value of 1.86 μF. In FIG. 13, the minimum multiplier is 0.74 and the maximum multiplier is 1.45. In other words, as a guideline for the setting range, noise reduction can be achieved by setting the capacitance value of capacitor C3 between 0.75 and 1.5 times the capacitance value calculated using equation (10). In this case, too, reducing the number of components in the noise filter 12 allows for size and cost reduction.

[0094] As shown in Fig. 12, the magnetic coupling between the inductors Lp1 to Lpn and the inductors Ls1 to Lsn is such that the magnetic fluxes reinforce each other when current flows from the terminals at the winding start points marked with black circles, thereby achieving the above-mentioned noise suppression effect.

[0095] The present inventors performed a circuit simulation on the four-phase interleaved (n=4) DCDC converter 1E.

[0096] Fig. 14 is a waveform diagram of the output current I2 showing the simulation results of the DCDC converter 1E of Fig. 12. Referring to Fig. 14, the effect of reducing ripple current is shown by circuit simulation using an example of four-phase interleaving (n = 4). Fig. 14 shows the simulation results of the output current I2 when the input voltage Vin = 12 V and the output voltage Vout = 1.8 V.

[0097] 12 , inductance Lp=Ls=1 μH, inductor L1=20 nH, inductor L2=0.2 μH, and switching frequency fs=200 kHz. Furthermore, coupling coefficient k12=0.1. In this case, the optimal capacitance value of capacitor C3 is calculated to be 2.37 μF using equation (6).

[0098] As is clear from FIG. 14, the ripple component of four times the switching frequency contained in the total current I1 was removed, and the amplitude of the output current I2 was significantly reduced to 14 Ap-p (75 Ap-p in Conventional Example 2).

[0099] The response speed to a sudden change in load is determined by the total inductance of the inductor loop circuit. In the above simulation, the value of inductor Ls is the same in Conventional Example 2 and Embodiment 2 (Ls1 = Ls2 = ... = Lsn). Therefore, when comparing other inductances, Conventional Example 2 has L1 = 0.2 μH, while Embodiment 1 has L1 + L2 - 2 × k12 × √(L1 × L2) = 0.214 μH, resulting in approximately the same response speed.

[0100] Although the four-phase interleaved DC-DC converter 1E has been described here, the number of phases is not limited, and the present invention may be applied to an interleaved DC-DC converter with any n phases. This makes it possible to suppress noise in the output current in an interleaved DC-DC converter with any number of phases.

[0101] Furthermore, any pair or combination of three inductors among the inductors Lp1 to Lpn may be magnetically coupled to each other. For example, in the case of a four-phase interleaved DC-DC converter, inductor Lp1 and inductor Lp2 may be coupled, and inductor Lp3 and inductor Lp4 may be coupled. This allows for a faster response to load fluctuations than when the inductors are not coupled.

[0102] The switch elements St1 to Stn and Sb1 to Sbn may be transistors such as MOSFETs or GaN-HEMTs, etc. The switch elements Sb1 to Sbn may be diodes.

[0103] 12, inductor L2 and inductors Ls1 to Lsn are connected in series, so the order of their connections may be reversed. This allows for optimization of component placement on the circuit board, further reducing the mounting area. When inductors L1 and L2 are both connected to node N1 as shown in FIG. 12, the coupled inductor consisting of inductors L1 and L2 can be a three-terminal component, making mounting easier.

[0104] As described above, according to the present embodiment, it is possible to provide a voltage regulator such as a TLVR that can suppress ripples in output current while maintaining responsiveness to load fluctuations without using a large noise filter, and a power conversion device that includes the voltage regulator.

[0105] 15 is a block diagram showing a configuration example of a power conversion device 100 according to embodiment 3. In Fig. 15, the power conversion device 100 is configured by providing an ACDC conversion device 3 in a stage preceding the DCDC conversion device 1 (or 1C, 1D, 1E, or 1F) of embodiment 1 or 2 or modified example 1 or 2.

[0106] 15 , an AC voltage Vinac from an AC power supply 2 is input to an ACDC converter 3, which includes a predetermined rectifying and smoothing circuit, rectifies and smoothes the input Vinac, and outputs the output voltage as an input voltage Vin to a DCDC converter 1 (or 1C, 1D, 1E, or 1F). Next, the DCDC converter 1 smoothes the input voltage Vin, which is an input DC voltage, and switches and smooths it to generate, for example, a stepped-down or stepped-up DC output voltage Vout, which is output to a load 20.

[0107] According to the power conversion device 100 configured as described above, since it is equipped with the DCDC conversion device 1 (or 1C, 1D, 1E), it is possible to suppress ripple in the output current while maintaining responsiveness to load fluctuations without using a large noise filter.

[0108] (Modifications) In the above embodiment and modifications 1 to 3, step-down chopper circuits B1 to Bn are used, but the present disclosure is not limited to this, and step-up chopper circuits may also be used.

[0109] In the above-described embodiment and modified examples 1 to 3, for example, four-phase interleaved chopper circuits B1 to Bn are described, but the present disclosure is not limited to this, and a multi-phase interleaved chopper circuit, for example, 16-phase, may also be used.

[0110] A voltage regulator according to the present disclosure or a power conversion device including the voltage regulator is useful for realizing a power conversion circuit device for use in automotive equipment, industrial equipment, etc., which has low ripple, low noise, is small in size, and is low cost.

[0111] 1, 1A to 1E DCDC converter 2 AC power supply 3 DCDC converter 10 Control circuit 11-1 to 11-n Switching circuit 12 Noise filter 20 Load 100 Power conversion device B1 to Bn, B1a to Bna Step-down chopper circuit C1, C2 Smoothing capacitor C3 Capacitor L1 to L3 Inductors Lp1 to Lpn Primary winding inductors Ls1 to Lsn Secondary winding inductors MC1, MC2, MC11 Magnetic coupling N1 Node Sb1 to Sbn, St1 to Stn Switch element SW1 Switch T1 Input terminal T2, T3 Output terminal TR1 to TRn Transformer

Claims

1. A voltage regulator comprising: a plurality of chopper circuits connected in parallel between an input terminal and an output terminal, each of which switches an input voltage input to the input terminal and then outputs from an output terminal via a first inductor of a primary winding of a transformer whose primary winding and secondary winding are magnetically coupled; a first series circuit formed by connecting in series second inductors of secondary windings of each transformer of the plurality of chopper circuits; and a second series circuit in which a third inductor is connected in series, the second series circuit being connected to first and second connection points at both ends of the second series circuit, the second series circuit comprising: a first capacitor connected so as to be inserted between the first connection point and the output terminal; and a fourth inductor; (1) the fourth inductor is connected so as to be inserted between the first connection point and one end of a second inductor connected in close proximity to the first connection point; (2) the fourth inductor is connected so as to be inserted between the second connection point and one end of a second inductor connected in close proximity to the second connection point; (3) The voltage regulator, wherein the fourth inductor is connected so as to be inserted between any pair of inductors adjacent to each other among the plurality of second inductors.

2. The voltage regulator according to claim 1, further comprising: a second capacitor connected to the input terminal for smoothing the input voltage; and a third capacitor connected to the output terminal for smoothing an output voltage output from the output terminal, wherein the input voltage and the output voltage are both DC voltages, and the voltage regulator is a DCDC conversion device.

3. The plurality of n chopper circuits are operated in a plurality of n phases different from each other, and the switching angular frequency of the plurality of chopper circuits is set to ω ｓ The inductance of each of the first inductors is L ｐ The inductance of each of the second inductors is L ｓ The inductance of the third inductor is L １ The inductance of the fourth inductor is L ２ Then, the capacitance value C of the first capacitor is ３ is configured to satisfy the following equation:

3. A voltage regulator according to claim 1 or 2.

4. The plurality of n chopper circuits are operated in a plurality of n phases different from each other, and the switching angular frequency of the plurality of chopper circuits is set to ω ｓ The inductance of each of the first inductors is L ｐ The inductance of each of the second inductors is L ｓ The inductance of the third inductor is L １ The inductance of the fourth inductor is L ２ Then, the capacitance value C of the first capacitor is ３ is configured to satisfy the following equation:

3. A voltage regulator according to claim 1 or 2.

5. The voltage regulator according to claim 1 or 2, wherein the third inductor and the fourth inductor are magnetically coupled to each other.

6. The plurality of n chopper circuits are operated in a plurality of n phases different from each other, and the switching angular frequency of the plurality of chopper circuits is set to ω ｓ The inductance of each of the first inductors is L ｐ The inductance of each of the second inductors is L ｓ The inductance of the third inductor is L １ The inductance of the fourth inductor is L ２ The coupling coefficient between the third inductor and the fourth inductor is k １２ Then, the capacitance value C of the first capacitor is ３ is configured to satisfy the following equation:

6. The voltage regulator of claim 5.

7. The capacitance value C of the first capacitor ３ is a value within a range of 0.75 to 1.5 times the capacitance value calculated by the formula according to claim 6.

8. The voltage regulator according to claim 1, wherein a pair, a plurality of pairs, or a combination of three or more of the plurality of first inductors are magnetically coupled to each other.

9. The voltage regulator according to claim 1, further comprising a fifth inductor connected in series with the first capacitor between the first connection point and the output terminal.

10. The voltage regulator according to claim 1, further comprising a switch connected in series with the first capacitor between the first connection point and the output terminal.

11. A power conversion device comprising: a DCDC conversion device which is the voltage regulator according to claim 2, or the voltage regulator according to any one of claims 3 to 10 which cite claim 2; and an ACDC conversion device provided in a stage preceding the DCDC conversion device, which converts AC voltage into DC voltage and outputs the DC voltage to the DCDC conversion device.