Memory circuit

Abstract

This memory circuit (11) comprises: first switches (SW) which are provided for each group of a first bit line (BL1) and a second bit line (BL2) and are connected to a first memory cell (MC1) and a second memory cell (MC2); an all first bit line selection circuit (8) which can turn all first switches on regardless of bit data of an input switch control signal (YG) when an input test signal (Test) indicates a test; and a detection unit (7) which is configured to be able to detect the magnitude relation between the total sum of currents flowing through the first bit line and a reference current, and the magnitude relation between the total sum of currents flowing through the second bit line and the reference current, wherein a DC voltage (VDD) can be applied to a gate of the first memory transistor (MT1) and a gate of the second memory transistor (MT2).

Description

memory circuit

[0001] The present disclosure relates to memory circuits.

[0002] Conventionally, semiconductor memory devices having memory cells are known. The memory cells include memory transistors. For example, some memory transistors have a control gate and a floating gate, and erase and program data by applying a high voltage to an oxide film adjacent to the floating gate to inject and extract electrons from the floating gate (see, for example, Patent Document 1).

[0003] JP 2017-174485 A

[0004] In some semiconductor memory devices, in order to improve reliability, a complementary cell is formed from two (pair) memory cells, and one complementary cell stores one bit of data. When data in a complementary cell is erased, both memory cells that make up the complementary cell are in the erased state, and the data becomes indefinite. There is a demand for a function to confirm the erased state of such a complementary cell.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a memory circuit that can effectively realize a function for checking the erased state of a complementary cell.

[0006] For example, a memory circuit according to the present disclosure includes: a plurality of first bit lines connected in common; a plurality of second bit lines connected in common; a plurality of complementary cells each having a first memory cell connected to the first bit lines and a second memory cell connected to the second bit lines; a first switch provided for each pair of the first bit lines and the second bit lines and connected to the first memory cell and the second memory cell; a first bit line full selection circuit that is capable of turning on all of the first switches regardless of the bit data of an input switch control signal when an input test signal indicates a test; and a detection unit configured to be able to detect the magnitude relationship between the sum of currents flowing through the first bit lines and a reference current, and the magnitude relationship between the sum of currents flowing through the second bit lines and the reference current, and is configured such that a DC voltage can be applied to the gate of the first memory transistor included in the first memory cell and the gate of the second memory transistor included in the second memory cell.

[0007] The memory circuit according to the present disclosure can effectively realize the function of checking the erased state of the complementary cell.

[0008] FIG. 1 is a diagram showing the configuration of a memory cell. FIG. 2 is a diagram showing the vertical structure of a memory transistor. FIG. 3A is a diagram showing a memory cell including a memory transistor in a programmed state (written state). FIG. 3B is a diagram showing a memory cell including a memory transistor in an erased state (erased state). FIG. 4 is a diagram showing the relationship between the gate voltage and the drain current in the programmed state and the erased state. FIG. 5 is a diagram showing a complementary cell. FIG. 6 is a diagram showing the data states (storage states) of a complementary cell and the gate voltage Vcg-drain current Id characteristics corresponding to each data state. FIG. 7 is a schematic diagram showing the configuration of an IC chip including a memory circuit according to a comparative example. FIG. 8 is a diagram showing the gate voltage Vcg-drain current Id characteristics of a memory transistor. FIG. 9 is a schematic diagram showing an IC chip including a memory circuit according to a first embodiment of the present disclosure. FIG. 10 is a diagram showing the relationship between the threshold voltage and frequency in the erased state of a memory transistor. FIG. 11 is a diagram showing the gate voltage Vcg-drain current Id characteristics of a memory transistor. FIG. 12 is a schematic diagram showing an IC chip including a memory circuit according to a second embodiment of the present disclosure.

[0009] Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0010] 1. Complementary Cell FIG. 1 shows the configuration of a memory cell MC. The memory cell MC has a memory transistor MT and a select transistor ST. The memory transistor MT is configured as an NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) and is an element for storing data. The memory transistor MT has a control gate Cg and a floating gate Fg.

[0011] The select transistor ST is composed of an NMOS transistor and is an element for selecting the memory transistor MT. The source of the memory transistor MT is connected to a terminal to which a ground potential is applied. The drain of the memory transistor MT is connected to the source of the select transistor ST. The drain of the select transistor ST is connected to a bit line BL. The select transistor ST has a read gate Rg. The select transistor ST is switched on and off depending on the voltage applied to the read gate Rg.

[0012] 2 is a diagram showing the vertical structure of the memory transistor MT. As shown in FIG. 2, a P-well region PW is formed in a semiconductor substrate. Two N-type wells are formed on the surface of the P-well region PW. ＋ The region is formed. Two N ＋ An oxide film Ox is formed directly above a channel region sandwiched between the regions. A floating gate Fg is formed directly above the oxide film Ox. A control gate Cg (not shown) is disposed directly above the floating gate Fg.

[0013] 3A is a diagram showing a memory cell MC including a memory transistor MT in a programmed state (write state). Applying a positive potential to a program gate (not shown) attracts electrons to the back gate and repels holes to the floating gate. Applying a negative gate voltage Vcg to the control gate Cg attracts holes to the floating gate Fg, as shown in FIG. 3A, making the floating gate Fg hole-rich. This state is the programmed state.

[0014] On the other hand, Figure 3B shows a memory cell MC including a memory transistor MT in an erased state. Applying a negative potential to the erase gate (not shown) attracts holes toward the back gate and repels electrons toward the floating gate. At this time, applying a positive gate voltage Vcg to the control gate Cg injects electrons into the floating gate Fg, as shown in Figure 3B, making the floating gate Fg electron-rich. This state is the erased state.

[0015] 4 is a diagram showing the relationship between the gate voltage Vcg applied to the control gate Cg of the memory transistor MT in the programmed state PG and the erased state ER, with the select transistor ST turned on by the gate voltage Vrg applied to the read gate Rg. As shown in FIG. 4, in the programmed state PG, the threshold voltage Vt is negative, and in the erased state ER, the threshold voltage Vt is positive.

[0016] Due to these characteristics of the programmed and erased states, when a read gate voltage Vcg is applied to the control gate Cg, the magnitude of the drain current Id varies between the programmed and erased states. Therefore, by turning on the select transistor ST and applying a read gate voltage Vcg to the control gate Cg, the drain Id flows through the bit line BL, and data can be read based on the magnitude of the drain current Id.

[0017] In an embodiment of the present disclosure, as shown in FIG. 5 , two memory cells are arranged side by side to form a so-called complementary memory cell (complementary cell). The complementary cell CL has a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 has a first select transistor ST1 and a first memory transistor MT1. The second memory cell MC2 has a second select transistor ST2 and a second memory transistor MT2. A first bit line BL1 is connected to the first select transistor ST1. A second bit line BL2 is connected to the second select transistor ST2. The bit lines BL1 and BL2 are connected to a sense amplifier SA. The sense amplifier SA reads one bit of data DT by detecting the magnitude relationship between the first drain current Id1 flowing through the first memory cell MC1 and the second drain current Id2 flowing through the second memory cell MC2 with the select transistors ST1 and ST2 turned on by the gate voltage Vrg applied to the read gate and with a read gate voltage Vcg applied to the control gates of the memory transistors MT1 and MT2. By setting the gate voltage Vcg applied to the control gate within the range indicated by the solid arrow in Figure 4, a current difference indicated by the dashed arrow in Figure 4 occurs between the erased state and the programmed state, making it possible to determine the data.

[0018] 6 shows the data states (memory states) of the complementary cell CL and the gate voltage Vcg-drain current Id characteristics corresponding to each data state. In FIG. 6, the solid line shows the characteristics of the first memory transistor MT1, and the dashed line shows the characteristics of the second memory transistor MT2.

[0019] As shown in FIG. 6, when both the memory transistors MT1 and MT2 are in the erased state ER, the data DT read by the sense amplifier SA becomes indefinite, and the complementary cell CL is in the erased state.

[0020] When the first memory transistor MT1 is in the programmed state and the second memory transistor MT2 is in the erased state ER, the first drain current Id1 is greater than the second drain current Id2, and therefore the sense amplifier SA reads out data DT="1". In other words, the complementary cell CL is in a state where data "1" is stored.

[0021] When the second memory transistor MT2 is in the programmed state and the first memory transistor MT1 is in the erased state ER, the first drain current Id1 is smaller than the second drain current Id2, and therefore the sense amplifier SA reads out data DT="0". In other words, data "0" is stored in the complementary cell CL.

[0022] 6, data "1" or "0" is stored in the complementary cell CL depending on which of the memory transistors MT1 and MT2 is changed from the erased state to the programmed state. In the data "1" or "0" storage state, the memory transistor in the programmed state is changed to the erased state, thereby causing the complementary cell CL to be in the erased state.

[0023] 2. Comparative Example Next, a function for checking the erased state of the complementary cell CL as described above (erase state checking function) will be described. First, a comparative example will be described for comparison with the embodiment of the present disclosure. FIG. 7 is a schematic diagram showing the configuration of an IC (integrated circuit) chip 10 having a memory circuit 1 according to the comparative example.

[0024] The memory circuit 1 corresponds to a memory function block (memory IP (intellectual property core)) in the IC chip 10. The memory circuit 1 has a complementary cell CL, a switch SW, PMOS transistors (P-channel MOSFETs) 2 and 3, a constant current source 4, a switch 5, an NMOS transistor 6, and an amplifier 7. The memory circuit 1 has terminals 1A and 1B for establishing electrical connection with the outside of the circuit. A power supply voltage VDD required for operation of the memory circuit 1 can be applied to terminal 1B. The power supply voltage VDD is a DC voltage.

[0025] 7, circuits other than the memory circuit 1 in the IC chip 10 can have any configuration. The IC chip 10 has external terminals 10A for establishing electrical connection with the outside of the chip.

[0026] Similar to the configuration described above, the complementary cell CL has a first memory cell MC1 and a second memory cell MC2. The first memory cell MC1 has a first select transistor ST1 and a first memory transistor MT1. The second memory cell MC2 has a second select transistor ST2 and a second memory transistor MT2. The complementary cell CL can store data "1" or "0".

[0027] A read gate signal RG can be applied to the read gates of the select transistors ST1 and ST2. The on / off states of the select transistors ST1 and ST2 are switched in response to the read gate signal RG. A read gate voltage Vcg can be applied to the control gates of the memory transistors MT1 and MT2 via a path not shown in FIG.

[0028] The first select transistor ST1 and the second select transistor ST2 are connected to the first bit line BL1 and the second bit line BL2, respectively, via a switch SW. The on / off of the switch SW is controlled by a switch control signal YG. A plurality of sets of first and second bit lines are provided. For example, if there are eight sets of bit lines, the bit line sets provided will be (BL1, BL2), (BL3, BL4), ... (BL15, BL16). The first bit line BL1, etc. are commonly connected at a node N1. The second bit line BL2, etc. are commonly connected at a node N2.

[0029] A complementary cell CL and a switch SW are provided for each pair of bit lines. In the example of FIG. 7, since there are eight pairs of bit lines as described above, eight complementary cells CL and switches SW are provided. Therefore, as shown in FIG. 7, the read gate signal RG is eight bits of data (RG[7:0]) to control the select transistors ST1 and ST2 in each of the eight complementary cells CL, and the switch control signal is eight bits of data (YG[7:0]) to control each of the eight switches SW.

[0030] The multiple sets of bit lines are connected to common PMOS transistors 2 and 3. The first bit line BL1, etc. is connected to the drain of the PMOS transistor 2. The second bit line BL2, etc. is connected to the drain of the PMOS transistor 3. The sources of the PMOS transistors 2 and 3 are connected to an application terminal of the power supply voltage VDD. A bias voltage Vbias can be applied to the gates of the PMOS transistors 2 and 3. The bias voltage Vbias is a predetermined DC voltage.

[0031] A read sense amplifier (not shown in Fig. 7) is connected to the bit lines BL1, BL2, etc. When reading using the sense amplifier, one of the switches SW is turned on by a switch control signal YG, and one of the select transistors ST1, ST2 is turned on by a read gate signal RG.

[0032] The constant current source 4, switch 5, NMOS transistor 6, amplifier 7, terminal 1A, and external terminal 10A are provided for the function of checking the erased state of the complementary cell CL.

[0033] The constant current source 4 is connected to the drain of a diode-connected NMOS transistor 6 via a switch 5. The drain of the NMOS transistor 6 is connected to a first input terminal of an amplifier 7. A voltage corresponding to the reference current Iref generated by the constant current source 4 appears at the drain of the NMOS transistor 6 and is applied to the first input terminal of the amplifier 7. When the erase state verification function is not in operation, unnecessary power consumption can be reduced by turning off the switch 5.

[0034] The control gates of the memory transistors MT1 and MT2 are commonly connected to a terminal 1A. The terminal 1A is connected to an external terminal 10A. A gate voltage Vcg can be applied to the control gates of the memory transistors MT1 and MT2 from the outside via the external terminal 10A. The gate voltage Vcg may be applied to each of a plurality of pairs of memory transistors MT1 and MT2. The first bit line BL1, etc. is connected to the second input terminal of the amplifier 7. The second bit line BL2, etc. is connected to the third input terminal of the amplifier 7.

[0035] By turning on the PMOS transistors 2 and 3 with the bias voltage Vbias, it is possible to precharge the bit lines BL1, BL2, etc. (charging the parasitic capacitance of the bit lines BL1, BL2, etc.) After precharging the bit lines BL1, BL2, etc., the PMOS transistors 2 and 3 are turned off with the bias voltage Vbias, one of the select transistors ST1, ST2 is turned on with the read gate signal RG, and one of the switches SW is turned on with the switch control signal YG, whereby the parasitic capacitance of the bit lines BL1, BL2 is discharged by the current flowing through the memory transistors MT1 and MT2.

[0036] The amplifier 7 can select either the bit line BL1 or BL2. The amplifier 7 outputs a logic output Vout (high level or low level) depending on the time required for the voltage at the input terminal (second input terminal or third input terminal) of the amplifier 7 corresponding to the selected bit line to decrease to the voltage at the first input terminal (the drain voltage of the NMOS transistor 6) due to the discharge. More specifically, for example, if the time is longer than a predetermined time, the logic output Vout remains high, and if the time is equal to or shorter than the predetermined time, the logic output Vout switches from high level to low level. The predetermined time is the time required for the voltage at the first input terminal of the amplifier 7 to decrease from the power supply voltage VDD, which is the voltage of the bit lines BL1, BL2, etc. after precharging, to the voltage at the first input terminal of the amplifier 7 when discharged by the reference current Iref.

[0037] As a result, the amplifier 7 detects the magnitude relationship between the current flowing through the first bit line BL1 etc. and the reference current Iref, or the magnitude relationship between the current flowing through the second bit line BL2 etc. and the reference current Iref. In the following, it is assumed that when the current flowing through the bit lines BL1, BL2 etc. is less than the reference current Iref, the logic output Vout is at a high level, and when the current flowing through the bit lines BL1, BL2 is equal to or greater than the reference current Iref, the logic output Vout is at a low level.

[0038] As shown in FIG. 7, a plurality of amplifiers 7 (32 in the example of FIG. 7) are provided. Each amplifier 7 is provided with PMOS transistors 2 and 3, first bit lines BL1, etc., second bit lines BL2, etc., a switch SW, and a complementary cell CL. The drain voltage of the NMOS transistor 6 is applied to the first input terminal of each amplifier 7. As a result, the same number of logic outputs Vout as the number of amplifiers 7 are generated (Vout[0] to Vout

[31] in the example of FIG. 7).

[0039] Next, the operation of the erased state confirmation function of the memory circuit 1 configured as described above will be described. To confirm the erased state of the complementary cell CL, it is necessary to confirm whether both memory cells MC1 and MC2 are in the erased state. In the memory circuit 1, the erased state of each of the memory cells MC1 and MC2 is confirmed one by one. When confirming the erased state, the bit lines BL1, BL2, etc. are precharged in advance.

[0040] When checking the erased state of the first memory cell MC1, the select transistors ST1 and ST2 in the complementary cell CL to be checked are turned on by the read gate signal RG, and the select transistors ST1 and ST2 in the complementary cells CL other than the one to be checked are turned off by the read gate signal RG. At this time, the switch SW corresponding to the complementary cell CL to be checked is turned on by the switch control signal YG, and the other switches SW are turned off. In this state, a gate voltage Vcg is applied from the outside to the external terminal 10A.

[0041] 8 shows the gate voltage Vcg-drain current Id characteristics of the memory transistors MT1 and MT2, in which the characteristics of the memory transistors MT1 and MT2 in the erased state ER and the characteristics of the memory transistors MT1 and MT2 in the programmed state PG are shown.

[0042] First, a gate voltage Vcg of an initial value INI is applied. The initial value INI is a value between the threshold voltage Vt in the programmed state PG and the threshold voltage Vt in the erased state ER. When the gate voltage Vcg of the initial value INI is applied and the current flowing through the first memory cell MC1 (first bit line) is less than the reference current Iref, the logic output Vout output from the amplifier 7 that selects the first bit line becomes high, and it is detected that the first memory cell MC1 is in the erased state. In this case, the gate voltage Vcg is increased stepwise in predetermined voltage increments, and the logic output Vout output from the amplifier 7 is checked. Then, the threshold voltage Vt in the erased state ER is obtained by determining the gate voltage Vcg when the logic output Vout switches from high to low, i.e., when the current flowing through the first memory cell MC1 becomes equal to or greater than the reference current Iref.

[0043] In this comparative example, by applying a gate voltage Vcg that changes stepwise, it is possible to detect whether the first memory transistor MT1 is in the erased state ER and the threshold voltage Vt in the erased state ER. This makes it possible to detect the threshold voltage Vt according to the characteristics variation of the first memory transistor MT1. Note that if the logic output Vout output from the amplifier 7 becomes low when the initial value INI of the gate voltage Vcg is applied, it is detected that the first memory transistor MT1 is in the programmed state PG.

[0044] When checking the erased state of the second memory cell MC2, similar to the case of the first memory cell MC1, the checking process is performed by detecting the magnitude relationship between the current flowing through the second memory cell MC2 and the reference current Iref using the amplifier 7. By checking the erased states of both memory cells MC1 and MC2, the erased state of the complementary cell CL is confirmed.

[0045] However, in this comparative example, only one switch SW can be selected by the switch control signal YG, and only one set of select transistors ST1, ST2 can be selected by the read gate signal RG, so when checking the erased state of the complementary cell CL, it is necessary to check each of the memory transistors MT1 or MT2 connected to one bit line, which poses the problem of time-consuming checking.

[0046] 3. First Embodiment of the Present Disclosure In order to solve the problems in the comparative example as described above, the embodiment of the present disclosure described below is implemented. Figure 9 is a schematic diagram showing an IC chip 101 having a memory circuit 11 according to a first embodiment of the present disclosure.

[0047] The memory circuit 11 differs from the memory circuit 1 (FIG. 7) according to the comparative example in that it is provided with bit line full selection circuits 8 and 9. The bit line full selection circuits 8 and 9 are provided for each amplifier 7.

[0048] The bit line full selection circuit 8 is a circuit that selects all bit lines by turning on all switches SW regardless of the bit data of the switch control signal YG when the test signal Test indicates an erase verification test. When the test signal Test does not indicate an erase verification test, the bit line full selection circuit 8 controls the on / off of the switches SW according to the bit data of the switch control signal YG.

[0049] The bit line full selection circuit 9 is a circuit that selects all bit lines by turning on all pairs of selection transistors ST1 and ST2 when the test signal Test indicates an erase verification test, regardless of the bit data of the read gate signal RG. When the test signal Test does not indicate an erase verification test, the bit line full selection circuit 9 controls the on / off of the selection transistors ST1 and ST2 according to the bit data of the read gate signal RG.

[0050] Furthermore, terminals 1A and 1B are commonly connected to an application terminal of power supply voltage VDD. As a result, IC chip 101 does not have external terminal 10A, which is provided on IC chip 10 according to the comparative example.

[0051] The operation of checking the erased state of the complementary cell CL in the memory circuit 11 of this embodiment will be described. To check the erased state of the complementary cell CL, it is necessary to check whether both memory cells MC1 and MC2 are in the erased state. In the memory circuit 1, the erased state of each of the memory cells MC1 and MC2 is checked one by one. When checking the erased state, the bit lines BL1, BL2, etc. are precharged in advance.

[0052] In this embodiment, when checking the erased state of the first memory cell MC1, the test signal Test is set to indicate an erase check test, which turns on all the switches SW, turns on all the select transistors ST1 and ST2, and applies the power supply voltage VDD as the gate voltage Vcg to the control gates of the memory transistors MT1 and MT2 in all the complementary cells CL via the terminal 1A. At this time, the amplifier 7 selects the first bit line BL1 etc.

[0053] At this time, the amplifier 7 discharges the bit line BL1 with a current Isum1, which is the sum of the currents flowing through the first bit line BL1 etc., i.e., the currents flowing through the first memory cells MC1 in all the complementary cells CL. The amplifier 7 detects the magnitude relationship between the current Isum1 and the reference current Iref, and outputs a logic output Vout according to the detection result.

[0054] FIG. 10 shows the relationship between the threshold voltage Vt of the memory transistors MT1 and MT2 in the erased state ER and the frequency. FIG. 10 is a diagram statistically representing the voltage range in which the threshold voltages Vt of the large number of memory transistors MT1 and MT2 inside the memory circuit 11 are located. Note that the frequency reaches its maximum at the point where it intersects with the threshold voltage Vt axis. As shown in FIG. 10, the power supply voltage VDD is lower than the minimum value Vt_min of the threshold voltage Vt in the erased state ER. In other words, the threshold voltage Vt in the erased state ER is ensured to be equal to or higher than the power supply voltage VDD.

[0055] FIG. 11 shows the gate voltage Vcg-drain current Id characteristics of the memory transistors MT1 and MT2. FIG. 11 also shows the characteristics of the memory transistors MT1 and MT2 in the erased state ER and the programmed state PG. As shown in FIG. 11, when the power supply voltage VDD is applied as the gate voltage Vcg, if the first memory transistor MT1 is in the erased state ER, the drain current Id becomes zero. If all the first memory transistors MT1 in all complementary cells CL are in the erased state, the current Isum1 becomes zero, so Isum1<Iref, and the output of the amplifier 7, for example, becomes high. At this time, if all the outputs of the multiple amplifiers 7 (Vout[0] to Vout

[31] in FIG. 9) are high, it is detected that all the first memory cells MC1 in the memory circuit 11 are in the erased state. Incidentally, if an AND circuit is provided to receive the outputs of the multiple amplifiers 7, it is possible to detect this as 1-bit data from the output of the AND circuit.

[0056] On the other hand, if even one of the first memory transistors MT1 in all the complementary cells CL is not in the erased state, Isum1>Iref, and the output of the amplifier 7, for example, becomes low level.

[0057] In this way, by checking the logic output Vout, it is possible to check whether all of the first memory cells MC1 are in the erased state. When checking the erased state of the second memory cell MC2, as in the case of the first memory cell MC1, the amplifier 7 that selects the second bit line BL2, etc. detects the magnitude relationship between the current Isum2 flowing in the second bit line BL2, etc. (the sum of the currents flowing in all of the second memory cells MC2 connected to the second bit line BL2, etc.) and the reference current Iref, and checks the logic output Vout as the detection result.

[0058] By confirming that all the first memory cells MC1 are in the erased state and all the second memory cells MC2 are in the erased state, the erased state of all the complementary cells CL is confirmed.

[0059] According to this embodiment, the erased state of all complementary cells CL can be confirmed by two processes for the first bit line and the second bit line, thereby significantly reducing the time required for confirmation.

[0060] In this embodiment, the power supply voltage VDD applied to terminal 1B is applied to terminal 1A, which is used to apply the gate voltage Vcg. That is, the power supply voltage VDD (applied to terminal 1B) required for the operation of the memory circuit 11 for a purpose other than the application of the gate voltage Vcg is applied to terminal 1A. Because the power supply voltage VDD is generated inside the IC chip 101, it is not necessary to provide the IC chip 101 with an external terminal 10A as in the comparative example. Although terminals 1A and 1B may be a common terminal, providing them as separate terminals allows the configuration of the comparative example to be reused. Note that an external terminal connected to terminal 1A may be provided on the IC chip 101, and a DC voltage equivalent to the power supply voltage VDD may be applied to the external terminal from the outside.

[0061] 12 is a schematic diagram showing an IC chip 102 having a memory circuit 12 according to a second embodiment of the present disclosure. This embodiment differs from the first embodiment in that a ground potential (0 V) is applied to terminal 1A.

[0062] In this embodiment, when checking the erased state of complementary cells CL, ground potential is applied as gate voltage Vcg to the control gates of memory transistors MT1 and MT2 via terminal 1A. As a result, as shown in Figure 11, if memory transistors MT1 and MT2 are in the erased state ER, the current flowing through memory cells MC1 and MC2 becomes zero. Therefore, the magnitude relationship between currents Isum1 and Isum2 and reference current Iref is detected by amplifier 7, and the erased state of all complementary cells CL can be checked by checking the logic output Vout.

[0063] In this embodiment, the ground potential is applied to the terminal 1A, so there is no need to provide the external terminal 10A as in the comparative example.

[0064] Note that, since the drain current tends to flow more easily when the power supply voltage VDD is applied as the gate voltage Vcg as in the first embodiment, it becomes easier to detect when the erased state of the memory transistors MT1 and MT2 is insufficient (when the shift amount of the threshold voltage Vt from 0 V is small). Conversely, when the ground potential is applied as the gate voltage Vcg as in the second embodiment, the conditions for determining the erased state can be relaxed.

[0065] <5. Others> In addition to the above embodiments, various modifications can be made to the various technical features of the present disclosure without departing from the spirit of the technical creation. In other words, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention should not be limited to the above embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0066] <6. Supplementary Note> As described above, for example, a memory circuit (11) according to one aspect of the present disclosure includes: a plurality of first bit lines (BL1) connected in common; a plurality of second bit lines (BL2) connected in common; a plurality of complementary cells (CL) each having a first memory cell (MC1) connected to the first bit lines and a second memory cell (MC2) connected to the second bit lines; first switches (SW) provided for each pair of the first bit lines and the second bit lines and connected to the first memory cells and the second memory cells; a first bit line full selection circuit (8) capable of turning on all of the first switches regardless of bit data of an input switch control signal (YG) when an input test signal (Test) indicates a test; and a detection unit (7) configured to be able to detect the magnitude relationship between a sum (Isum1) of currents flowing through the first bit lines and a reference current, and the magnitude relationship between a sum (Isum2) of currents flowing through the second bit lines and the reference current, A DC voltage (VDD) can be applied to the gate of the first memory transistor (MT1) included in the first memory cell and the gate of the second memory transistor (MT2) included in the second memory cell (first configuration).

[0067] In the first configuration, the detection unit (7) may be provided in plurality, and the first bit line, the second bit line, the complementary cell, the first switch, and the first bit line full selection circuit may be provided for each detection unit (second configuration).

[0068] In the above first or second configuration, the first memory cell (MC1) has a first selection transistor (ST1), the second memory cell (MC2) has a second selection transistor (ST2), and the memory circuit may be configured to include a second bit line full selection circuit (9) that can turn on all pairs of the first selection transistor and the second selection transistor when the input test signal indicates a test, regardless of the bit data of the input read gate signal (RG) (third configuration).

[0069] In any one of the first to third configurations, the DC voltage may be a first power supply voltage (VDD) (fourth configuration).

[0070] In addition, in the fourth configuration, the first power supply voltage (VDD) may be configured to be the same as a second power supply voltage (VDD) required for operation of the memory circuit (11) for a purpose other than the purpose of applying the DC voltage to the gate (fifth configuration).

[0071] In addition, in the fifth configuration, the circuit may have a first terminal (1A) for applying the first power supply voltage (VDD) and a second terminal (1B) for applying the second power supply voltage (VDD), and the first terminal and the second terminal may be separate terminals (sixth configuration).

[0072] In any one of the first to third configurations, the DC voltage may be a ground potential (seventh configuration).

[0073] Another aspect of the present disclosure is an IC chip (101, 102) including a memory circuit (11, 12) having any one of the fifth to seventh configurations (eighth configuration).

[0074] Furthermore, any of the first to seventh configurations may be configured to include a second switch (5), a reference current source (4), and a diode-connected MOS transistor (6) connected to the reference current source via the second switch (ninth configuration).

[0075] The present disclosure can be used in memory circuits for various applications.

[0076] 1 Memory circuit 1A, 1B Terminal 2, 3 PMOS transistor 4 Constant current source 5 Switch 6 NMOS transistor 7 Amplifier 8, 9 Bit line full selection circuit 10 IC chip 10A External terminal 11, 12 Memory circuit 101, 102 IC chip BL Bit line BL1, BL3 First bit line BL2, BL4 Second bit line CL Complementary cell Cg Control gate Fg Floating gate MC Memory cell MC1 First memory cell MC2 Second memory cell MT Memory transistor MT1 First memory transistor MT2 Second memory transistor Ox Oxide film PW P well region Rg Read gate SA Sense amplifier ST Selection transistor ST1 First selection transistor ST2 Second selection transistor SW Switch

Claims

1. a plurality of first bit lines connected together; a plurality of second bit lines connected together; a plurality of complementary cells, each having a first memory cell connected to the first bit line and a second memory cell connected to the second bit line; a first switch provided for each pair of the first bit line and the second bit line, the first switch being connected to the first memory cell and the second memory cell; a first bit line full selection circuit capable of turning on all of the first switches when an input test signal indicates a test, regardless of bit data of an input switch control signal; a detection unit configured to detect a magnitude relationship between a sum of currents flowing through the first bit lines and a reference current, and a magnitude relationship between a sum of currents flowing through the second bit lines and the reference current; Equipped with a gate of a first memory transistor included in the first memory cell and a gate of a second memory transistor included in the second memory cell, the memory circuit being capable of applying a DC voltage to the gate of the first memory transistor included in the second memory cell.

2. The detection unit is provided in plurality, 2. The memory circuit according to claim 1, wherein the first bit line, the second bit line, the complementary cell, the first switch, and the first bit line full select circuit are provided for each of the detection units.

3. the first memory cell has a first selection transistor; the second memory cell has a second selection transistor; 2. The memory circuit of claim 1, further comprising a second bit line full selection circuit capable of turning on all sets of the first selection transistors and the second selection transistors when an input test signal indicates a test, regardless of bit data of an input read gate signal.

4. 2. The memory circuit of claim 1, wherein the DC voltage is a first power supply voltage.

5. 5. The memory circuit according to claim 4, wherein the first power supply voltage is the same as a second power supply voltage necessary for operation of the memory circuit for a purpose other than the application of the DC voltage to the gate.

6. a first terminal for applying the first power supply voltage; a second terminal for applying the second power supply voltage; The memory circuit of claim 5 , wherein the first terminal and the second terminal are separate terminals.

7. 2. The memory circuit according to claim 1, wherein the DC voltage is a ground potential.

8. An IC chip comprising the memory circuit according to claim 5.

9. A second switch; A reference current source; 2. The memory circuit of claim 1, further comprising: a diode-connected MOS transistor connected to said reference current source via said second switch.