Memory device, and memory device power source control method

Abstract

The present invention includes a first and a second memory, and a control circuit that receives write access and read access from the outside, and performs write and read control with respect to the first memory. If a signal prompting a power source shutoff is received, the control circuit: executes a data saving process for writing, to the second memory, only the difference between data stored in a data storage region of the first memory and data stored in a data storage region of the second memory; stops the power supply to the first and the second memory following the data saving process; and when a signal prompting power on is received, starts the power supply to the first and the second memory, and then executes a data recovery process for writing the data stored in the data storage region of the second memory to the first memory.

Description

MEMORY DEVICE AND METHOD FOR CONTROLLING POWER SUPPLY FOR MEMORY DEVICE

[0001] The present invention relates to a memory device and a power supply control method for a memory device.

[0002] Known electronic devices that include a microcomputer (hereinafter referred to as an MC) are equipped with a standby mode that reduces power consumption by stopping the supply of power to the built-in memory, for example, when the CPU stops processing for a certain period of time.

[0003] Therefore, as a semiconductor memory device compatible with such a standby mode, one has been proposed that incorporates a nonvolatile memory together with an SRAM as the main memory on a single semiconductor IC chip (see, for example, Patent Document 1). In this semiconductor memory device, during standby mode, all pieces of data stored in the SRAM are read, and all of the read pieces of data are written to the nonvolatile memory, after which the power supply to the SRAM and the nonvolatile memory is cut off. Thereafter, when the standby mode is released, all pieces of data stored in the nonvolatile memory are read and written to the SRAM. This allows the contents of the SRAM to be restored to the state they were in immediately before the standby mode, even if all of the pieces of data stored in the SRAM are erased by cutting off the power supply during standby mode.

[0004] Japanese Patent Application Laid-Open No. 2006-302466

[0005] In the semiconductor memory device described in Patent Document 1, all data stored in the SRAM must be read and written to the nonvolatile memory during standby mode. The current consumed when writing data to the nonvolatile memory is greater than the current consumed when reading data from the SRAM. Therefore, power consumption cannot be significantly reduced, and the problem of increased power consumption arises, particularly when the duration of each standby mode is short.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a memory device and a power supply control method for a memory device that can significantly reduce power consumption.

[0007] The memory device of the present invention includes first and second memories, and a control circuit that performs write and read control on the first memory in response to external write access and read access, wherein the control circuit, upon receiving a signal to shut down the power supply, executes a data evacuation process in which only the difference between the data stored in the data storage area of ​​the first memory and the data stored in the data storage area of ​​the second memory is written to the second memory, and following the data evacuation process, stops the supply of power to the first and second memories, and upon receiving a signal to shut down the power supply, starts the supply of power to the first and second memories and then executes a data recovery process in which the data stored in the data storage area of ​​the second memory is written to the first memory.

[0008] The power supply control method for a memory device according to the present invention is a power supply control method executed by a control circuit in a memory device including first and second memories and a control circuit that performs write and read control on the first memory in response to external write access and read access, wherein, when a signal prompting power-off is received, only the difference between the data stored in the data storage area of ​​the first memory and the data stored in the data storage area of ​​the second memory is written to the second memory, and then the power supply to the first and second memories is stopped, and when a signal prompting power-on is received, the power supply to the first and second memories is started, and then the data stored in the data storage area of ​​the second memory is written to the first memory.

[0009] In this invention, when data stored in a data storage area of ​​an externally accessible first memory is saved to a second memory in response to a signal prompting power cutoff, only the difference between the data stored in the data storage area of ​​the first memory and the data stored in the data storage area of ​​the second memory is written to the second memory. This data saving significantly reduces the number of writes compared to when all data stored in the first memory is written to the second memory, making it possible to significantly reduce power consumption.

[0010] 1 is a block diagram showing the configuration of a memory device 100 according to a first embodiment of the present invention. FIG. 2 is a flowchart showing the procedure of a data save process executed by the memory controller 11. FIG. 3 is a flowchart showing the procedure of a data recovery process executed by the memory controller 11. FIG. 4 is a time chart showing an example of an internal operation of the memory device 100 due to the data save process executed by the memory controller 11. FIG. 5 is a time chart showing an example of an internal operation of the memory device 100 due to the data recovery process executed by the memory controller 11. FIG. 6 is a block diagram showing the configuration of a memory device 100A according to a second embodiment of the present invention. FIG. 7 is a diagram showing areas AR1 to ARr obtained by dividing the entire storage area of ​​each of the SRAM 12 and the MRAM 13 into r sections. FIG. 8 is a diagram showing write flags f1 to fr stored in a flag register in association with the areas AR1 to ARr. FIG. 9 is a flowchart showing the procedure of a write flag process executed by the memory controller 11A. FIG. 10 is a flowchart showing the procedure of a data save process executed by the memory controller 11A. FIG. 11 is a flowchart showing the procedure of a data recovery process executed by the memory controller 11A.

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0012] 1 is a block diagram showing the configuration of a memory device 100 according to a first embodiment of the present invention. The memory device 100 is formed on a semiconductor IC chip or a semiconductor IC chip on which a control device such as a microcomputer is formed.

[0013] Furthermore, memory device 100 receives data write access and data read access from an external system, such as a personal computer or smartphone that includes memory device 100. Memory device 100 is set to one of two states: a normal mode in which data is written or read in response to the write or read access, and a standby mode in which power is cut off internally in response to a standby request from the system that has made the write or read access, thereby reducing power consumption.

[0014] 1, the memory device 100 includes a power supply controller 10, a memory controller 11, a static random access memory (SRAM) 12 as a volatile memory, and a magnetoresistive random access memory (MRAM) 13 as a nonvolatile memory. The memory device 100 further includes a dedicated bus DBS for transferring data between the SRAM 12 and the MRAM 13.

[0015] The power supply controller 10 and the memory controller 11 receive a standby mode request signal STB or a standby mode release request signal REL. The standby mode request signal STB is a signal that requests the system that is the source of the write and read access to reduce power consumption by putting its main operation on hold. On the other hand, the standby mode release request signal REL is a signal that requests the system to release standby mode and transition to normal mode.

[0016] The power supply controller 10 controls the supply of the power supply voltage VDD to the SRAM 12 and the MRAM 13 or the stop of the supply of the power supply voltage VDD based on the standby mode request signal STB, the standby mode release request signal REL, or the data transfer completion signal TXc supplied from the memory controller 11. In this way, the power supply controller 10 regards the standby mode request signal STB as a signal that prompts the SRAM 12 and the MRAM 13 to cut off power, and regards the standby mode release request signal REL as a signal that resumes the power supply to the SRAM 12 and the MRAM 13.

[0017] It should be noted that before receiving the standby mode request signal STB, the power supply controller 10 supplies the power supply voltage VDD to the SRAM 12 and the MRAM 13, thereby setting the memory device 100 in an operable state, i.e., in a normal mode in which data can be written and read.

[0018] The memory controller 11 receives various control signals CMD (chip enable signal, write enable signal, output enable signal, etc.) for instructing the SRAM 12 to access the SRAM 12 for writing or reading data, the standby mode request signal STB, and the standby mode release request signal REL.

[0019] In response to the control signal CMD, the memory controller 11 supplies a write signal WR1 to the SRAM 12 to write, for example, 16-bit data DAT to an address indicated by an address AD. In response to the control signal CMD, the memory controller 11 also supplies a read signal RD1 to the SRAM 12 to read from the SRAM 12 the data stored at the address indicated by the address AD.

[0020] Furthermore, when the memory controller 11 receives a standby mode request signal STB, it executes the following data saving process in response to the standby mode request signal STB.

[0021] In the data saving process, the memory controller 11 reads out a piece of data stored in the data storage area of ​​the SRAM 12 onto the bus DBS by supplying a read signal RD1 to the SRAM 12 while supplying an address to the SRAM 12 via the bus DBS. Furthermore, the memory controller 11 supplies a read signal RD2 or a write signal WR2 to the MRAM 13 while supplying an address to the MRAM 13 via the bus DBS. This causes the memory controller 11 to read out a piece of data stored in the data storage area of ​​the MRAM 13 onto the bus DBS, or write a piece of data on the bus DBS to the data storage area of ​​the MRAM 13. The data storage areas of the SRAM 12 and the MRAM 13 may be the entire areas of the SRAM 12 and the MRAM 13, respectively, or may be predetermined portions of the areas.

[0022] The operation of the memory device 100 shown in FIG. 1 will now be described in detail.

[0023] FIG. 2 is a flowchart showing the procedure of the data saving process executed by the memory controller 11 when the standby mode request signal STB is received.

[0024] In FIG. 2, first, the memory controller 11 sets a read address Ad indicating, for example, address zero as an initial address (step S10).

[0025] Next, the memory controller 11 reads out the data piece stored at the address indicated by the read address Ad from the SRAM 12, and takes it in as read data Rs via the bus DBS (step S11).

[0026] Next, the memory controller 11 reads out the data piece stored at the address indicated by the read address Ad from the MRAM 13 and takes it in as read data Rm via the bus DBS (step S12).

[0027] Next, the memory controller 11 determines whether the contents of the read data Rs and the contents of the read data Rm do not match (step S13).

[0028] If it is determined in step S13 that the read data Rs and the read data Rm do not match, the memory controller 11 overwrites the read data Rs at the address indicated by the read address Ad in the MRAM 13 (step S14).

[0029] After executing step S14, or if it is determined in step S13 that the read data Rs and the read data Rm match, the memory controller 11 adds 1 to the address indicated by the read address Ad and sets it as the new read address Ad (step S15).

[0030] Next, the memory controller 11 determines whether the address indicated by the read address Ad indicates an address within the data storage area of ​​the SRAM 12 (step S16).

[0031] In step S16, if it is determined that the address indicated by the read address Ad indicates an address within the data storage area of ​​the SRAM 12, the memory controller 11 returns to executing step S11 and executes the processing of steps S11 to S16 described above again.

[0032] On the other hand, if it is determined in step S16 that the address indicated by the read address Ad indicates an address outside the data storage area of ​​SRAM 12, the memory controller 11 supplies a data transfer completion signal TXc to the power supply controller 10 indicating that the data transfer between SRAM 12 and MRAM 13 has been completed (step S17).

[0033] After executing step S17, the memory controller 11 ends this data saving process.

[0034] By this data saving process, all the data pieces that were stored in the storage area of ​​the SRAM 12 immediately before receiving the standby mode request signal STB are stored in the MRAM 13 .

[0035] When the power supply controller 10 receives the standby mode request signal STB described above and then receives a data transfer completion signal TXc from the memory controller 11, it stops supplying the power supply voltage VDD to the SRAM 12 and the MRAM 13. This erases all data stored in the SRAM 12, but since the MRAM 13 is a non-volatile memory, it continues to hold all pieces of data stored therein even after the power supply is stopped.

[0036] Thereafter, upon receiving the standby mode release request signal REL, the power supply controller 10 first starts supplying the power supply voltage VDD to the SRAM 12 and MRAM 13, and then the memory controller 11 executes the following data recovery process.

[0037] FIG. 3 is a flowchart showing the procedure of the data recovery process.

[0038] In FIG. 3, first, the memory controller 11 sets a read address Ad indicating, for example, address zero as an initial address (step S20).

[0039] Next, the memory controller 11 reads out the data piece stored at the address indicated by the read address Ad from the MRAM 13, and takes it in as read data Rm via the bus DBS (step S21).

[0040] Next, the memory controller 11 writes the read data Rm to the SRAM 12 (step S22).

[0041] Next, the memory controller 11 adds 1 to the address indicated by the read address Ad and sets the address as a new read address Ad (step S23).

[0042] Next, the memory controller 11 determines whether the address indicated by the read address Ad indicates an address within the data storage area of ​​the SRAM 12 (step S24).

[0043] In step S24, if it is determined that the address indicated by the read address Ad indicates an address within the data storage area of ​​the SRAM 12, the memory controller 11 returns to executing step S21 and again executes the processing of steps S21 to S24 described above.

[0044] On the other hand, if it is determined in step S24 that the address indicated by the read address Ad indicates an address outside the data storage area of ​​SRAM 12, the memory controller 11 supplies a data transfer completion signal TXc to the power supply controller 10 indicating that the data transfer between MRAM 13 and SRAM 12 has been completed (step S25).

[0045] After step S25 is executed, the memory controller 11 ends this data restoration process and returns to the main flow (not described) executed in the normal mode. In other words, by executing this data restoration process, the data storage area of ​​the SRAM 12 returns to the data storage state immediately before receiving the standby mode request signal STB.

[0046] Through the above-described series of processes, the memory device 100 transitions from the standby mode to the normal mode.

[0047] The internal operation of the memory device 100 in the data saving process shown in FIG. 2 will be described in detail below with reference to an example shown in FIG.

[0048] FIG. 4 is a time chart showing an example of an internal operation of the memory device 100 in accordance with a data saving process executed by the memory controller 11 in response to the standby mode request signal STB, in which data in all areas of the SRAM is saved.

[0049] 4, in response to the standby mode request signal STB, the memory controller 11 supplies the MRAM 13 with a read signal RD2 that reads all data pieces stored in the MRAM 13 in address order. As a result, for example, as shown in FIG. 4, data a1 stored in the first address 0 of the MRAM 13, data a2 stored in address 1, and data a3 stored in address 2 are read out from the MRAM 13 in that order.

[0050] Furthermore, the memory controller 11 supplies the SRAM 12 with a read signal RD1 for reading all data pieces stored in the SRAM 12 in address order, thereby reading data b1 stored in the first address 0 of the SRAM 12, data a2 stored in address 1, and data a3 stored in address 2 from the SRAM 12 in that order, as shown in FIG.

[0051] During this time, the memory controller 11 compares the data fragments read from the SRAM 12 and the MRAM 13 at the same address, and only if they do not match, rewrites the data fragment stored in the MRAM 13 with the data fragment read from the SRAM 12.

[0052] 4, data a1 read from address 0 of MRAM 13 matches data b1 read from address 0 of SRAM 12. Data a2 read from address 1 of MRAM 13 does not match data b2 read from address 1 of SRAM 12. Furthermore, data a3 read from address 2 of MRAM 13 matches data b3 read from address 2 of SRAM 12.

[0053] 4, the memory controller 11 supplies a write signal WR2 of logic level 1 to the MRAM 13 to write only data b2, out of data b1 to b3 read from addresses 0 to 2 of the SRAM 12, to address 1 of the MRAM 13. As a result, only data a2, out of data a1 to a3 already stored in the MRAM 13, is rewritten with data b2 stored in the SRAM 12.

[0054] 4 , when reading of the data bx stored in the last address of the storage area of ​​the SRAM 12 is completed, the memory controller 11 supplies a data transfer completion signal TXc of logic level 1, which indicates the completion of the data transfer operation from the SRAM 12 to the MRAM 13, to the power supply controller 10. Therefore, in response to the data transfer completion signal TXc of logic level 1, the power supply controller 10 stops supplying the power supply voltage VDD to the SRAM 12 and the MRAM 13.

[0055] Next, the internal operation of the memory device 100 in the data recovery process shown in FIG. 3 will be described in detail with reference to an example shown in FIG.

[0056] FIG. 5 is a time chart showing an example of an internal operation of the memory device 100 in response to a data recovery process executed in response to a standby mode release request signal REL, in which data in all areas of the SRAM is recovered.

[0057] 5, in response to the standby mode release request signal REL, the memory controller 11 supplies the MRAM 13 with a read signal RD2 that reads all data pieces stored in the MRAM 13 in address order. As a result, for example, as shown in FIG. 5, data a1 stored in the first address 0 of the MRAM 13, data b2 stored in address 1, and data a3 stored in address 2 are read out from the MRAM 13 in that order.

[0058] Furthermore, the memory controller 11 supplies a write signal WR1 to the SRAM 12 to write each piece of data read from the MRAM 13 to the SRAM 12 in the order of the addresses. As a result, for example, as shown in FIG. 5, data a1, b2, and a3 read from addresses 0 to 2 of the MRAM 13, respectively, are stored in addresses 0 to 2 of the SRAM 12.

[0059] As described above in detail, in the memory device 100, in response to a standby mode request (STB), first, data is transferred from the SRAM 12 to the MRAM 13 so that all data stored in the SRAM 12 and all data stored in the MRAM 13 are the same (data saving process). Then, after the data saving process is completed, the memory device 100 stops the supply of power to the SRAM 12 and the MRAM 13. Note that since the MRAM 13 is a non-volatile memory, it continues to hold all of the stored contents of the SRAM 12 immediately before receiving the standby mode request, even after the power is stopped.

[0060] Thereafter, upon receiving a standby mode release request (REL), the memory device 100 resumes the power supply to the SRAM 12 and MRAM 13 and transfers all data pieces stored in the MRAM 13 to the SRAM 12 (data restoration process), thereby restoring all stored contents of the SRAM 12 to the state they were in immediately before the standby mode request was received.

[0061] In the data saving process described above, when the memory contents stored in the data saving area of ​​SRAM 12 are saved to MRAM 13, the contents of the data fragment stored in SRAM 12 at the same address are compared with the contents of the data fragment stored in MRAM 13. At this time, the data fragment stored in SRAM 12 is written to MRAM 13 only if the two are different from each other.

[0062] That is, by the data saving process, only the difference between the data stored in the data saving area of ​​the SRAM 12 and the data stored in the data saving area of ​​the MRAM 13 is written to the MRAM 13 .

[0063] As a result, when data stored in the data storage area of ​​SRAM 12 is saved to MRAM 13 immediately before the power supply to SRAM 12 and MRAM 13 is stopped, the number of writes is significantly reduced compared to conventional memory devices that perform a process of writing the data stored in the data storage area of ​​SRAM 12 to MRAM 13.

[0064] Therefore, the memory device 100 can significantly reduce power consumption.

[0065] In the above embodiment, whether or not to write to MRAM 13 is determined in units of data pieces corresponding to each address, but it may also be determined whether or not to write to MRAM 13 in units of areas obtained by dividing the entire storage area of ​​each of SRAM 12 and MRAM 13 into multiple sections.

[0066] FIG. 6 is a block diagram showing the configuration of a memory device 100A according to a second embodiment of the present invention, which has been developed in consideration of the above points.

[0067] The memory device 100A has the same configuration (10, 12, 13) and operation as those shown in FIG. 1, except that it employs a memory controller 11A instead of the memory controller 11.

[0068] The memory controller 11A includes a built-in flag register (not shown) that stores write flags f1 to fr indicating whether data has been written to each of the areas AR1 to ARr, which are obtained by dividing the data storage areas of the SRAM 12 and the MRAM 13 into r areas (r is an integer of 2 or greater) as shown in Fig. 7A. In other words, in the initial state, write flags f1 to fr of, for example, logic level 0 indicating no writing have been performed are stored in the flag register, and when data is written to the SRAM 12, the write flag corresponding to the area to which the data has been written is rewritten to logic level 1 indicating that writing has been performed.

[0069] The memory controller 11A executes the write flag process shown in FIG. 8 every time an external access is made to the SRAM 12 for writing data in the normal mode.

[0070] That is, first, the memory controller 11A determines which of the areas AR1 to ARr shown in FIG. 7A is the area in the SRAM 12 to which data is to be written, and designates that area as area ARx (step S71). Next, the memory controller 11A rewrites the contents of the write flag fx stored in the flag register and corresponding to area ARx to, for example, logic level 1, indicating that writing has occurred (step S72). After executing step S72, the memory controller 11A returns to the main flow (not described) executed in normal mode.

[0071] Next, a data saving process executed by the memory controller 11A in response to the standby mode request signal STB will be described.

[0072] FIG. 9 is a flowchart showing the procedure of the data saving process executed by the memory controller 11A.

[0073] 9, first, the memory controller 11A sets the area number w indicating the number "1" of the first area AR1 as the area number (1 to r) indicating the areas AR1 to ARr shown in FIG. 7A (step S81).

[0074] Next, the memory controller 11A determines whether the write flag fw corresponding to the area ARw indicated by the area number w among the areas AR1 to ARr is at logic level 1, indicating that writing has occurred (step S82). If it is determined in step S82 that the write flag fw is at logic level 1, the memory controller 11A reads a piece of data from the area ARw of the SRAM 12 and takes it in as read data Rs via the bus DBS (step S83). Next, the memory controller 11A reads a piece of data from the area ARw of the MRAM 13 and takes it in as read data Rm via the bus DBS (step S84).

[0075] Next, the memory controller 11A determines whether the contents of the read data Rs and the contents of the read data Rm do not match (step S85).

[0076] If it is determined in step S85 that the read data Rs and the read data Rm do not match, the memory controller 11A overwrites the read data Rs in the area ARw of the MRAM 13 (step S86).

[0077] After execution of step S86, or if it is determined in step S85 that the read data Rs and the read data Rm match, or if it is determined in step S82 that the write flag fw is not at logical level 1, the memory controller 11A adds 1 to the area number w and sets it as the new area number w (step S87).

[0078] Next, the memory controller 11A determines whether the area number w is larger than the last area number r of the storage area, that is, whether the area number w is a number outside the storage area (step S88).

[0079] If it is determined in step S88 that the area number w is equal to or less than the area number r, the memory controller 11A returns to the execution of step S82 and executes the processes of steps S82 to S88 described above again.

[0080] On the other hand, if it is determined in step S88 that the area number w is greater than the area number r, the memory controller 11A supplies the power supply controller 10 with a data transfer completion signal TXc indicating that the data transfer between the SRAM 12 and the MRAM 13 has been completed (step S89).

[0081] After executing step S89, the memory controller 11A ends this data saving process and goes into a standby state to wait for a standby mode release request signal REL.

[0082] By this data saving process, all the data pieces that were stored in the storage area of ​​the SRAM 12 immediately before receiving the standby mode request signal STB are stored in the MRAM 13 .

[0083] When the power supply controller 10 receives the standby mode request signal STB and the data transfer completion signal TXc from the memory controller 11A, it stops supplying the power supply voltage VDD to the SRAM 12 and the MRAM 13. This erases all data stored in the SRAM 12, but since the MRAM 13 is a non-volatile memory, it continues to hold all pieces of data stored therein even after the power supply is stopped.

[0084] Thereafter, upon receiving the standby mode release request signal REL, the power supply controller 10 first starts supplying the power supply voltage VDD to the SRAM 12 and MRAM 13, and then the memory controller 11A executes the following data recovery process.

[0085] FIG. 10 is a flowchart showing the procedure of the data recovery process executed by the memory controller 11A.

[0086] 10, first, the memory controller 11A sets the area number w indicating the number "1" of the first area AR1 as the area number (1 to r) indicating the areas AR1 to ARr shown in FIG. 7A (step S91).

[0087] Next, the memory controller 11A reads out the data fragment from the area ARw of the MRAM 13 and takes it in as read data Rm via the bus DBS (step S92).

[0088] Next, the memory controller 11A writes the read data Rm to the area ARw of the SRAM 12 (step S93).

[0089] Next, the memory controller 11A adds 1 to the area number w and sets the result as a new area number w (step S94).

[0090] Next, the memory controller 11A determines whether or not the area number w is larger than the last area number r of the storage area, that is, whether or not the area number w is a number outside the storage area (step S95).

[0091] If it is determined in step S95 that the area number w is equal to or less than the area number r, the memory controller 11A returns to the execution of step S92 and executes the processes of steps S92 to S95 described above again.

[0092] On the other hand, if it is determined in step S95 that the area number w is greater than the area number r, the memory controller 11A initializes all of the contents of the write flags f1 to fr stored in the flag register to logic level 0, i.e., a state indicating no write (step S96).

[0093] Next, the memory controller 11A supplies the power supply controller 10 with a data transfer completion signal TXc indicating that the data transfer between the MRAM 13 and the SRAM 12 has ended (step S97).

[0094] After step S97, the memory controller 11A ends the data restoration process and returns to the main flow (not described) executed in the normal mode. By executing the data restoration process, the data storage area of ​​the SRAM 12 returns to the data storage state immediately before receiving the standby mode request signal STB.

[0095] Through the above series of processes, the memory device 100A returns from the standby mode to the normal mode.

[0096] In this way, in the data saving process (FIG. 9) of memory device 100A, data stored in SRAM 12 is written to MRAM 13 only for areas (AR1 to ARr) of the data saving area of ​​SRAM 12 that have been written to immediately before receiving a standby mode request (STB). In other words, in memory device 100A, as in memory device 100, only the difference between the data stored in the data saving area of ​​SRAM 12 and the data stored in the data saving area of ​​MRAM 13 is written to MRAM 13.

[0097] Therefore, according to memory device 100A, similar to memory device 100, the number of write operations performed to save data stored in the data storage area of ​​SRAM 12 to MRAM 13 is significantly reduced, thereby making it possible to significantly reduce power consumption.

[0098] In the above embodiment, the memory controller (100, 100A) executes the data saving process (FIGS. 2 and 9) and the data restoring process (FIGS. 3 and 10) in response to a standby mode request (STB) and a release request (REL). In short, when a signal instructing the memory device (100, 100A) to turn off power and a signal instructing the memory device (100, 100A) to turn on power are received, the data saving process and the data restoring process may be executed.

[0099] In the above embodiment, the first memory of the memory device 100 is a volatile memory, SRAM, and the second memory is a non-volatile memory, MRAM (Magnetoresistive Memory), but the types of memory are not limited. That is, as long as data can be written, other storage elements such as DRAM may be used as the first memory, and flash memory, resistive memory, ferroelectric memory, or the like may be used as the second memory.

[0100] In short, the memory device (100, 100A) according to the present invention may include the following control circuit, first and second memories.

[0101] That is, the control circuit (10, 11, 11A) receives write and read accesses from the outside and controls writing and reading of the first memory (12). When the control circuit receives a signal (STB) prompting power-off, it writes only the difference between the data stored in the data storage area of ​​the first memory and the data stored in the data storage area of ​​the second memory to the second memory (S14, S86), and then stops the supply of power to the first and second memories. When the control circuit receives a signal (REL) prompting power-on, it starts supplying power to the first and second memories and then writes the data stored in the data storage area of ​​the second memory to the first memory (S22, S93).

[0102] 10 Power supply controller 11, 11A Memory controller 12 SRAM 13 MRAM 100, 100A Memory device

Claims

1. first and second memories; a control circuit for performing write and read control on the first memory in response to write and read accesses from an external device; The control circuit includes: when receiving a signal to interrupt power supply, execute a data save process for writing only a difference between data stored in a data storage area of ​​the first memory and data stored in a data storage area of ​​the second memory to the second memory, and stop supplying power to the first and second memories following the data save process; A memory device characterized in that, when it receives a signal prompting power-on, it starts supplying power to the first and second memories, and then executes a data recovery process in which data stored in a data storage area of ​​the second memory is written to the first memory.

2. 2. The memory device of claim 1, wherein the first memory is a volatile memory and the second memory is a non-volatile memory.

3. the signal for urging power cutoff is a standby mode request signal for requesting that a source of the write access and the read access be placed in a standby state; 3. The memory device according to claim 1, wherein the signal for prompting power-on is a standby mode release request signal for requesting release of a standby state.

4. 3. The memory device according to claim 1, wherein the first memory is an SRAM and the second memory is a magnetoresistive memory.

5. 3. The memory device according to claim 1, wherein the first and second memories and the control circuit are formed on a single semiconductor chip.

6. the control circuit includes a flag register for storing a write flag corresponding to each of the areas obtained by dividing the data storage areas of each of the first and second memories into a plurality of areas, the write flag indicating that data has been written in the area when data has been written in the area, and indicating that data has not been written in the area when data has not been written; The memory device according to claim 1 or 2, characterized in that in the data evacuation process, data in the second memory is rewritten with data stored in the first memory only for areas among the multiple areas in the first memory to which the write flag indicating the presence of writing is associated.

7. 7. The memory device according to claim 6, wherein the control circuit initializes the contents of all of the plurality of write flags to the no-write state when the control circuit receives the signal prompting power-on.

8. 1. A power supply control method for a memory device including first and second memories, and a control circuit for receiving write access and read access from an external device and performing write and read control on the first memory, the method comprising: when receiving a signal to interrupt power supply, write only a difference between data stored in a data storage area of ​​the first memory and data stored in a data storage area of ​​the second memory into the second memory, and then stop supplying power to the first and second memories; A power control method for a memory device, characterized in that, when a signal prompting power-on is received, power supply to the first and second memories is started, and then data stored in a data storage area of ​​the second memory is written to the first memory.