Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

A semiconductor light-emitting element (1) comprises an active layer (30), a P-type cladding layer (40), a contact layer (50), and an insulation film (60). A ridge (R) is formed in a region including the P-type cladding layer (40) and the contact layer (50). The ridge (R) includes a lower ridge (Rd) that includes the P-type cladding layer (40) and an upper ridge (Ru) that is disposed on the top surface (Rdt) of the lower ridge (Rd) and that includes the contact layer (50). The top surface (Rdt) of the lower ridge (Rd) is positioned between the bottom surface (Rub) of the upper ridge (Ru) and a side surface (Rds) of the lower ridge (Rd), and has a flat part (Rdf). The width of the bottom surface (Rub) of the upper ridge (Ru) is less than the width of the top surface (Rdt) of the lower ridge (Rd) and the width of the lower ridge (Rd) at the center position in the lamination direction. The insulation film (60) continuously covers an area from the side surface (Rds) of the lower ridge (Rd) to part of the top surface (Rut) of the upper ridge (Ru).

Description

Semiconductor light emitting element and method for manufacturing semiconductor light emitting element

[0001] The present disclosure relates to a semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device.

[0002] Laser light has been used for processing applications, and a highly efficient and high-power laser light source is required. A semiconductor light-emitting element such as a semiconductor laser element is used as such a laser light source.

[0003] A technique for forming a ridge and confining current within the ridge is known as a technique for increasing the efficiency of a semiconductor light emitting device (see, for example, Patent Document 1).

[0004] JP 2010-67763 A

[0005] However, in a semiconductor light emitting device having a ridge formed therein, there is a problem in that current flows along the side surfaces of the ridge, which causes heat generation.

[0006] The present disclosure is intended to solve such problems, and has an object to provide a semiconductor light emitting device and the like that can suppress current flowing on the side surfaces of the ridge.

[0007] In order to solve the above-described problems, one aspect of the semiconductor light-emitting device according to the present disclosure is a semiconductor light-emitting device that emits light, comprising: a substrate; an N-type cladding layer disposed above the substrate; an active layer disposed above the N-type cladding layer; a P-type cladding layer disposed above the active layer; a contact layer disposed above the P-type cladding layer; and an insulating film disposed above the P-type cladding layer; a ridge extending in a propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer; the ridge includes a lower ridge including the P-type cladding layer; and an upper ridge disposed on a top surface of the lower ridge and including the contact layer; the top surface of the lower ridge has a flat portion located between a side surface of the lower ridge and a bottom surface of the upper ridge and extending in the propagation direction of the light; the width of the bottom surface of the upper ridge is smaller than the width of the top surface of the lower ridge and the width of the lower ridge at a center position in the stacking direction; and the insulating film continuously covers from the side surface of the lower ridge to a portion of the top surface of the upper ridge.

[0008] In order to solve the above-described problems, another aspect of the semiconductor light-emitting device according to the present disclosure is a semiconductor light-emitting device that emits light, comprising: a substrate; an N-type cladding layer disposed above the substrate; an active layer disposed above the N-type cladding layer; a P-type cladding layer disposed above the active layer; and a contact layer disposed above the P-type cladding layer, wherein a ridge extending in a propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer, the ridge including a lower ridge including the P-type cladding layer and an upper ridge disposed on a top surface of the lower ridge and including the contact layer, and the P-type cladding layer is Al Ｘ Ga １－Ｘ and X1=X2>X0, wherein an Al composition ratio X0 of the lower cladding layer, an Al composition ratio X1 of the first cladding layer, and an Al composition ratio X2 of the second cladding layer satisfy the relationships: X1=X2>0.8 and X1=X2>X0.

[0009] In order to solve the above problems, one aspect of a method for manufacturing a semiconductor light-emitting element according to the present disclosure is a method for manufacturing a semiconductor light-emitting element that emits light, the method including the steps of: forming an N-type cladding layer above a substrate; forming an active layer above the N-type cladding layer; forming a P-type cladding layer above the active layer; forming a contact layer above the P-type cladding layer; forming a ridge in a region including the P-type cladding layer and the contact layer; and forming an insulating film on the ridge, the ridge including a lower ridge including the P-type cladding layer and a top layer of the lower ridge. and an upper ridge disposed on a surface of the lower ridge and including the contact layer, the process of forming the ridge includes a process of forming the upper ridge and a process of forming the lower ridge after the process of forming the upper ridge, the top surface of the lower ridge is located between the side surface of the lower ridge and the bottom surface of the upper ridge and has a flat portion extending in the propagation direction of the light, the width of the bottom surface of the upper ridge is smaller than the width of the top surface of the lower ridge and the width of the lower ridge at a central position in the stacking direction, and the insulating film continuously covers from the side surface of the lower ridge to a portion of the top surface of the upper ridge.

[0010] According to the present disclosure, it is possible to provide a semiconductor light emitting device and the like that can suppress current flowing along the side surfaces of the ridge.

[0011] FIG. 1 is a schematic top view showing the overall configuration of a semiconductor light emitting device according to an embodiment. FIG. 2 is a schematic first cross-sectional view showing the overall configuration of a semiconductor light emitting device according to an embodiment. FIG. 3 is a schematic second cross-sectional view showing the overall configuration of a semiconductor light emitting device according to an embodiment. FIG. 4 is a schematic third cross-sectional view showing the overall configuration of a semiconductor light emitting device according to an embodiment. FIG. 5 is a schematic cross-sectional view showing the configuration of an active layer according to an embodiment. FIG. 6 is a schematic cross-sectional view showing the configuration of a second etching stop layer according to an embodiment. FIG. 7 is an enlarged view of a ridge shown in FIG. 2. FIG. 8 is an enlarged view of a wing portion shown in FIG. 2. FIG. 9 is a schematic cross-sectional view showing a first step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 10 is a schematic cross-sectional view showing a second step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 11 is a schematic first cross-sectional view showing a third step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 12 is a schematic second cross-sectional view showing the third step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 13 is a schematic first cross-sectional view showing a fourth step of a method for manufacturing a semiconductor light emitting device according to an embodiment. FIG. 14 is a second schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 15 is a first schematic cross-sectional view showing a fifth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 16 is a second schematic cross-sectional view showing the fifth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 17 is a first schematic cross-sectional view showing a sixth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 18 is a second schematic cross-sectional view showing the sixth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 19 is a seventh schematic cross-sectional view showing a seventh step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 20 is a first schematic cross-sectional view showing an eighth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 21 is a second schematic cross-sectional view showing the eighth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 22 is a ninth schematic cross-sectional view showing a ninth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment. FIG. 23 is a first schematic cross-sectional view showing a tenth step of the method for manufacturing a semiconductor light-emitting device according to the embodiment.FIG. 24 is a second schematic cross-sectional view showing a tenth step of the manufacturing method of the semiconductor light-emitting device according to the embodiment. FIG. 25 is a graph showing the relationship between the output power and the injection current of the semiconductor light-emitting device according to the embodiment. FIG. 26 is a graph showing the relationship between the remaining thickness of the semiconductor light-emitting device according to the embodiment and the horizontal divergence angle of the emitted light. FIG. 27 is a graph showing the relationship between the horizontal divergence angle of the emitted light of the semiconductor light-emitting device according to the embodiment and the effective refractive index difference. FIG. 28 is a schematic top view showing the overall configuration of the semiconductor light-emitting device according to Modification 1 of the embodiment. FIG. 29 is a first schematic cross-sectional view showing the overall configuration of the semiconductor light-emitting device according to Modification 1 of the embodiment. FIG. 30 is a second schematic cross-sectional view showing the overall configuration of the semiconductor light-emitting device according to Modification 1 of the embodiment. FIG. 31 is a third schematic cross-sectional view showing the overall configuration of the semiconductor light-emitting device according to Modification 1 of the embodiment. FIG. 32 is a fourth schematic cross-sectional view showing the overall configuration of the semiconductor light-emitting device according to Modification 1 of the embodiment. FIG. 33 is a schematic top view showing the overall configuration of the semiconductor light-emitting device according to Modification 2 of the embodiment. Fig. 34 is a schematic first cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 2 of the embodiment. Fig. 35 is a schematic second cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 2 of the embodiment. Fig. 36 is a schematic third cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 2 of the embodiment.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, and the arrangement and connection of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0013] Furthermore, each figure is a schematic diagram and is not necessarily an exact representation. Therefore, the scales and the like do not necessarily match in each figure. In each figure, the same reference numerals are used to denote substantially the same components, and redundant explanations will be omitted or simplified.

[0014] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are used not only when two components are arranged with a gap between them and another component is present between the two components, but also when two components are arranged in contact with each other.

[0015] (Embodiment) A semiconductor light emitting device according to an embodiment will be described.

[0016] [1. Overall Configuration] First, the overall configuration of a semiconductor light-emitting device according to this embodiment will be described with reference to FIGS. 1 to 4. FIG. 1 is a schematic top view showing the overall configuration of a semiconductor light-emitting device 1 according to this embodiment. FIGS. 2 to 4 are schematic cross-sectional views showing the overall configuration of the semiconductor light-emitting device 1 according to this embodiment, respectively. FIGS. 2 and 3 show cross sections of the semiconductor light-emitting device 1 taken along lines II-II and III-III in FIG. 1, respectively. FIG. 4 shows only a portion of the cross section of the semiconductor light-emitting device 1 taken along line IV-IV in FIG. 1, including an end face 1F. Note that each figure shows mutually orthogonal X-, Y-, and Z-axes. The X-, Y-, and Z-axes are in a right-handed Cartesian coordinate system. The stacking direction of the semiconductor light-emitting device 1 (i.e., the thickness direction of each layer included in the semiconductor light-emitting device 1) is parallel to the Z-axis, and the main propagation direction of light (laser light) is parallel to the Y-axis.

[0017] The semiconductor light-emitting element 1 is an element that emits light when supplied with current. In this embodiment, the semiconductor light-emitting element 1 is a semiconductor laser element that emits laser light with a wavelength in the near-infrared region (approximately 900 nm to 980 nm). More specifically, the semiconductor light-emitting element 1 emits laser light with a wavelength of approximately 976 nm. As shown in FIG. 1 , the semiconductor light-emitting element 1 has two end faces 1F and 1R that form a resonator. The end face 1F is a front end face that emits laser light, and the end face 1R is a rear end face that has a higher reflectivity than the end face 1F. The semiconductor light-emitting element 1 also has a waveguide formed between the end face 1F and the end face 1R. The resonator length of the semiconductor light-emitting element 1, i.e., the distance between the end faces 1F and 1R in the propagation direction of the laser light (the Y-axis direction in each figure, i.e., the resonance direction), is not particularly limited, but is 2 mm or more in this embodiment. The resonator length of the semiconductor light-emitting element 1 may also be 5 mm or more. The semiconductor light emitting element 1 includes reflective films 2F and 2R disposed at the end portions in the propagation direction of the laser light. The reflective films 2F and 2R are films for adjusting the reflectance of the end faces 1F and 1R, respectively. In this embodiment, the reflective films 2F and 2R are each a dielectric multilayer film. The reflective film 2F has a lower reflectance than the reflective film 2R.

[0018] 2 , the semiconductor light emitting element 1 includes a substrate 10, an N-type cladding layer 20, an active layer 30, a P-type cladding layer 40, a contact layer 50, and an insulating film 60. In this embodiment, the semiconductor light emitting element 1 further includes an N-type buffer layer (not shown), an N-type buffer boundary layer (not shown), a first P-side electrode 71, a pad electrode 73, a second P-side electrode 72, and an N-side electrode 80.

[0019] The substrate 10 is a plate-like member that serves as a base for the semiconductor light-emitting device 1. In this embodiment, the substrate 10 is an N-type GaAs substrate.

[0020] The N-type buffer layer is an N-type semiconductor layer disposed above the substrate 10. In this embodiment, the N-type buffer layer is an N-type GaAs layer with a film thickness of 0.5 μm.

[0021] The N-type buffer boundary layer is an N-type semiconductor layer disposed between the N-type buffer layer and the N-type cladding layer 20. In this embodiment, the N-type buffer boundary layer is an N-type Al 2 O 3 layer having a thickness of 0.05 μm. Ｘ２２ Ga １－Ｘ２２ The Al composition ratio X22 of the N-type buffer boundary layer is 0.15 at the interface with the N-type buffer layer, and 0.25 at the interface with the N-type cladding layer 20.

[0022] The N-type cladding layer 20 is an N-type semiconductor layer disposed above the substrate 10. The average refractive index of the N-type cladding layer 20 is lower than the average refractive index of the active layer 30. In this embodiment, the N-type cladding layer 20 is disposed on the N-type buffer boundary layer. The N-type cladding layer 20 is made of an N-type Al 2 O 3 layer having a thickness of 3.1 μm. ０．２５ Ga ０．７５ This is an As layer.

[0023] The active layer 30 is a light-emitting layer disposed above the N-type cladding layer 20. In this embodiment, the active layer 30 has a quantum well structure. The configuration of the active layer 30 will be described with reference to FIG. 5 . FIG. 5 is a schematic cross-sectional view showing the configuration of the active layer 30 according to this embodiment. FIG. 5 shows a cross section of the active layer 30 taken along line II-II in FIG. 1 . As shown in FIG. 5 , the active layer 30 includes an N-side cladding boundary layer 31, an N-side guide layer 32, an N-side barrier layer 33, a well layer 34, a P-side barrier layer 35, a P-side guide layer 36, and a P-side cladding boundary layer 37.

[0024] As shown in FIGS. 3 and 4 , the active layer 30 has a window region 30w (i.e., a non-light-emitting region) near the facet 1F of the semiconductor light-emitting device 1. The window region 30w is a region in which a portion of the quantum well structure including the N-side barrier layer 33, the well layer 34, and the P-side barrier layer 35 is disordered, and the band gap energy of the window region 30w is larger than that of the region of the active layer 30 other than the window region 30w. This suppresses light emission and light absorption near the facet 1F, thereby suppressing heat generation near the facet 1F. Therefore, it is possible to suppress catastrophic optical damage (COD) near the facet 1F of the semiconductor light-emitting device 1. In this embodiment, the active layer 30 also has a window region 30w near the facet 1R. The window region 30w is formed over a predetermined length in the light propagation direction from the end of the active layer 30 on the facet 1F side. The length of the window region 30w in the light propagation direction may be equal to the length from the end of the upper ridge Ru on the end facet 1F side to the end of the P-type cladding layer 40 on the end facet 1F side. Here, the term "these lengths are equal" does not mean that these lengths are completely equal, but also includes a state where they are substantially equal. The term "these lengths are equal" also means, for example, that the difference between these lengths is 10% or less.

[0025] 5 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4). In this embodiment, the N-side cladding boundary layer 31 is an N-type Al 0.83 μm thick semiconductor layer disposed between the N-type cladding layer 20 and the N-side guide layer 32. Ｘ３１ Ga １－Ｘ３１ The Al composition ratio X31 of the N-side cladding boundary layer 31 decreases toward the N-side guide layer 32. The Al composition ratio X31 of the N-side cladding boundary layer 31 is 0.25 at the interface with the N-type cladding layer 20 and is 0.20 at the interface with the N-side guide layer 32.

[0026] The N-side guide layer 32 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4). The average refractive index of the N-side guide layer 32 is higher than the average refractive index of the N-type cladding layer 20. In this embodiment, the N-side guide layer 32 is disposed above the N-side cladding boundary layer 31. The N-side guide layer 32 is an N-type Al 0.27 μm thick semiconductor layer. ０．２０ Ga ０．８０ This is an As layer.

[0027] The N-side barrier layer 33 is a semiconductor layer disposed above the N-type cladding layer 20 and functions as a barrier for the quantum well structure. In this embodiment, the N-side barrier layer 33 is disposed above the N-side guide layer 32. The N-side barrier layer 33 is an undoped Al layer having a thickness of 0.010 μm. ０．１６ Ga ０．８４ This is an As layer.

[0028] The well layer 34 is a semiconductor layer disposed above the N-type cladding layer 20 and functions as a well of the quantum well structure. In this embodiment, the well layer 34 is disposed above the N-side barrier layer 33. The well layer 34 is an undoped In layer having a thickness of 0.0090 μm. ０．１４ Ga ０．８６ This is an As layer.

[0029] The P-side barrier layer 35 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4) and functions as a barrier for the quantum well structure. In this embodiment, the P-side barrier layer 35 is disposed above the well layer 34. The P-side barrier layer 35 is an undoped AlN layer having a thickness of 0.010 μm. ０．１６ Ga ０．８４ This is an As layer.

[0030] The P-side guide layer 36 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4). The average refractive index of the P-side guide layer 36 is higher than the average refractive index of the P-type cladding layer 40 (see FIGS. 2 to 4). In this embodiment, the P-side guide layer 36 is disposed above the P-side barrier layer 35. The P-side guide layer 36 is a P-type Al 0.29 μm thick semiconductor layer. Ｘ３６ Ga １－Ｘ３６The Al composition ratio X36 of the P-side guide layer 36 is 0.20 in a region where the distance from the interface of the P-side guide layer 36 with the P-side barrier layer 35 is 0.010 μm or less. The Al composition ratio X36 of the P-side guide layer 36 increases toward the P-side cladding boundary layer 37 in a region where the distance from the interface of the P-side guide layer 36 with the P-side barrier layer 35 is greater than 0.010 μm. The Al composition ratio X36 of the P-side guide layer 36 at the interface with the P-side cladding boundary layer 37 is 0.21.

[0031] The P-side cladding boundary layer 37 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4). In this embodiment, the P-side cladding boundary layer 37 is a 0.1 μm-thick N-type Al layer disposed between the P-side guide layer 36 and the P-type cladding layer 40 (see FIGS. 2 to 4). Ｘ３７ Ga １－Ｘ３７ The Al composition ratio X37 of the P-side cladding boundary layer 37 increases toward the P-type cladding layer 40. The Al composition ratio X37 of the P-side cladding boundary layer 37 is 0.21 at the interface with the P-side guide layer 36 and is 0.75 at the interface with the P-type cladding layer 40.

[0032] The P-type cladding layer 40 shown in FIGS. 2 to 4 is a P-type semiconductor layer disposed above the active layer 30. The average refractive index of the P-type cladding layer 40 is lower than the average refractive index of the active layer 30. In this embodiment, the P-type cladding layer 40 is made of Al Ｘ Ga １－Ｘ The semiconductor device is made of As (0<x<1) and has a lower cladding layer 41 , a first cladding layer 42 , a first etching stop layer 43 , a second cladding layer 44 and a second etching stop layer 45 .

[0033] The lower cladding layer 41 is a P-type semiconductor layer disposed above the active layer 30. In this embodiment, the lower cladding layer 41 is a P-type AlN layer having a thickness of 0.050 μm. ０．７５ Ga ０．２５ This is an As layer.

[0034] The first cladding layer 42 is a P-type semiconductor layer disposed above the active layer 30. In this embodiment, the first cladding layer 42 is a P-type AlN layer having a thickness of 0.10 μm disposed above the lower cladding layer 41. ０．８５ Ga ０．１５ This is an As layer.

[0035] The first etching stop layer 43 is a P-type semiconductor layer disposed above the active layer 30. In this embodiment, the first etching stop layer 43 is disposed above the first cladding layer 42. The Al composition ratio of the first etching stop layer 43 is 0.7 or less. The first etching stop layer 43 is a P-type Al layer having a thickness of 0.05 μm. ０．７０ Ga ０．３０ This is an As layer.

[0036] The second cladding layer 44 is a P-type semiconductor layer disposed above the active layer 30. In this embodiment, the second cladding layer 44 is a P-type Al 2 O 3 layer having a thickness of 0.20 μm disposed above the first etching stop layer 43. ０．８５ Ga ０．１５ This is an As layer.

[0037] In this embodiment, the Al composition ratio X0 of the lower cladding layer 41, the Al composition ratio X1 of the first cladding layer 42, and the Al composition ratio X2 of the second cladding layer 44 satisfy the relationships: X1=X2>0.8 and X1=X2>X0.

[0038] The second etching stop layer 45 is a P-type semiconductor layer disposed above the active layer 30. In this embodiment, the second etching stop layer 45 is a P-type Al 2 O 3 layer having a thickness of 0.050 μm disposed above the second cladding layer 44. Ｘ４５ Ga １－Ｘ４５The second etching stop layer 45 is an As layer (0.70≧X45≧0.15). The second etching stop layer 45 has two or more gradient regions in which the Al composition ratio decreases toward the contact layer, and one or more constant regions in which the Al composition ratio is constant with respect to the position in the stacking direction. The two or more gradient regions and the one or more constant regions are alternately arranged in the stacking direction. The configuration of the second etching stop layer 45 according to this embodiment will be described below with reference to FIG. 6. FIG. 6 is a schematic cross-sectional view showing the configuration of the second etching stop layer 45 according to this embodiment. FIG. 6 shows a cross section of the second etching stop layer 45 at the ridge R along line II-II in FIG. 1. As shown in FIG. 6, the second etching stop layer 45 has two gradient regions 45b and 45d and two constant regions 45a and 45c.

[0039] The fixed region 45a is a P-type AlN layer having a thickness of 0.050 μm and disposed above the second cladding layer 44. ０．７０ Ga ０．３０ The inclined region 45b is a P-type Al layer having a thickness of 0.01 μm and disposed above the constant region 45a. Ｘ４５ Ga １－Ｘ４５ The Al composition ratio X45 of the inclined region 45b decreases toward the contact layer 50. The Al composition ratio X45 of the inclined region 45b is 0.70 at the interface with the constant region 45a and 0.60 at the interface with the constant region 45c. The constant region 45c is a P-type Al layer with a thickness of 0.030 μm, which is disposed above the inclined region 45b. ０．６０ Ga ０．４０ The inclined region 45d is a P-type Al layer having a thickness of 0.010 μm and disposed above the constant region 45c. Ｘ４５ Ga １－Ｘ４５ The Al composition ratio X45 of the inclined region 45d decreases toward the contact layer 50. The Al composition ratio X45 of the inclined region 45d is 0.60 at the interface with the constant region 45c and is 0.15 at the interface with the contact layer 50.

[0040] The contact layer 50 is a P-type semiconductor layer disposed above the P-type cladding layer 40 and in ohmic contact with the first P-side electrode 71. In this embodiment, the contact layer 50 is a P-type GaAs layer with a film thickness of 0.25 μm.

[0041] As shown in FIGS. 1 and 2 , a ridge R extending in the light propagation direction is formed in a region including the P-type cladding layer 40 and the contact layer 50. A waveguide is formed along the ridge R. Note that FIG. 1 shows the outline of the top surface of the ridge R. The configuration of the ridge R will be described below using FIG. 7 in addition to FIGS. 1 to 4 . FIG. 7 is an enlarged view of the ridge R shown in FIG. 2. As shown in FIG. 2 , the ridge R includes a lower ridge Rd including the P-type cladding layer 40, and an upper ridge Ru disposed on a top surface Rdt of the lower ridge Rd and including a contact layer 50. The top surface Rdt of the lower ridge Rd is located between a side surface Rds of the lower ridge Rd and a bottom surface Rub of the upper ridge Ru, and has a flat portion Rdf extending in the light propagation direction. The width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction. Note that the width of the ridge R here refers to the dimension of the ridge R in the stacking direction (i.e., the Z-axis direction) and in the direction perpendicular to the longitudinal direction of the ridge R (i.e., the light propagation direction or Y-axis direction) (i.e., the X-axis direction). The width Wut of the top surface Rut of the upper ridge Ru is smaller than the width Wub of the bottom surface Rub of the upper ridge Ru. In other words, the upper ridge Ru has a forward mesa shape in a cross section perpendicular to the longitudinal direction of the ridge R. The side surfaces Rus of the upper ridge Ru form inclined surfaces of the forward mesa shape.

[0042] The upper ridge Ru includes at least a part of the contact layer 50. In this embodiment, the upper ridge Ru includes at least a part of each of the second etching stop layer 45 and the contact layer 50.

[0043] As shown in FIGS. 1, 3, and 4, the upper ridge Ru is not formed near the end face 1F of the semiconductor light-emitting device 1. In other words, the upper surface of the end of the ridge R in the light propagation direction that is closer to the end face 1F from which light of the semiconductor light-emitting device 1 is emitted is located on the second etching stop layer 45. That is, the contact layer 50 is not formed on the end of the ridge R in the light propagation direction that is closer to the end face 1F from which light of the semiconductor light-emitting device 1 is emitted. This makes it possible to prevent concentrated stress from being applied to the end of the ridge R when the semiconductor light-emitting device 1 is junction-down (i.e., flip-chip) mounted on a mounting substrate or the like. Therefore, damage near the end face 1F of the semiconductor light-emitting device 1 can be suppressed. In this embodiment, the upper ridge Ru is not formed near the end face 1R of the semiconductor light-emitting device 1 either.

[0044] 4, in a cross section of the upper ridge Ru parallel to the light propagation direction (and stacking direction), the end of the upper ridge Ru closer to the end face 1F from which light of the semiconductor light emitting element 1 is emitted has an inverted mesa shape. In other words, the upper end of the upper ridge Ru is located closer to the end face 1F than the lower end.

[0045] 7 , the lower ridge Rd includes at least a portion of each of the second cladding layer 44 and the second etching stop layer 45. In the present embodiment, the lower ridge Rd includes at least a portion of each of the first etching stop layer 43, the second cladding layer 44, and the second etching stop layer 45. The top surface Rdt of the lower ridge Rd is located on the second etching stop layer 45. Therefore, a flat portion Rdf, which is part of the top surface Rdt of the lower ridge Rd, is also located on the second etching stop layer 45. The Al composition ratio of the flat portion Rdf is 0.7 or less.

[0046] The width Wdt of the top surface of the lower ridge Rd, the width Wdc of the lower ridge Rd at the central position Rdc in the stacking direction, and the width Wdb of the bottom surface Rdb of the lower ridge Rd satisfy the relationships Wdt>Wdc and Wdb>Wdc.

[0047] The width Wdt of the top surface Rdt of the lower ridge Rd may be equal to the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction. Here, the term "the widths Wdt and Wdc are equal" does not necessarily mean that the widths Wdt and Wdc are completely equal, but also includes a state in which they are substantially equal. The term "the widths Wdt and Wdc are equal" also includes, for example, a state in which the difference between the widths Wdt and Wdc is 3% or less of each width.

[0048] The upper surface of the P-type cladding layer 40 (i.e., the bottom portion Tb shown in FIG. 7 ) at a position adjacent to the bottom surface Rdb of the lower ridge Rd in the width direction of the lower ridge Rd (i.e., the X-axis direction) is located in the first etching stop layer 43. In other words, the bottom surface Rdb of the lower ridge Rd is located in the first etching stop layer 43.

[0049] In this embodiment, a wing portion G extending along the ridge R is formed in a region including the P-type cladding layer 40 and the contact layer 50. In other words, a groove T is formed between the wing portion G and the ridge R. Note that FIG. 1 shows the outline of the upper surface of the wing portion G. The wing portion G will be described below with reference to FIG. 8. FIG. 8 is an enlarged view of the wing portion G shown in FIG. 2.

[0050] 8 , the wing portion G includes a lower wing portion Gd including a P-type cladding layer 40, and an upper wing portion Gu disposed on a top surface Gdt of the lower wing portion Gd and including a contact layer 50. The top surface Gdt of the lower wing portion Gd has a wing flat portion Gdf that is a flat region extending in the light propagation direction and is located between a side surface Gds of the lower wing portion Gd and a bottom surface Gub of the upper wing portion Gu. In this embodiment, a ridge R is formed between the two wing portions G. Such a wing portion G can suppress stress applied to the ridge R when the semiconductor light emitting element 1 is mounted on a mounting substrate or the like.

[0051] A recess 3 recessed in the width direction of the semiconductor light emitting element 1 is formed at an end in the width direction (i.e., an end in the X-axis direction) of the semiconductor light emitting element 1. The recess 3 is formed on the outer side in the X-axis direction of the wing portion G. The recess 3 is part of a separation groove used when singulating the semiconductor light emitting element 1. As shown in FIG. 8 and other figures, the portion of the side surface of the semiconductor light emitting element 1 corresponding to the recess 3 is constricted inward in the X-axis direction. The side surface Gds of the lower wing portion Gd farther from the ridge R is included in the recess 3. The side surface Gds of the lower wing portion Gd farther from the ridge R has a constriction 3w located more inward in the width direction of the semiconductor light emitting element 1 than the upper end of the lower wing portion Gd (a position on the side surface Gds corresponding to the top surface Gdt).

[0052] The position of the recess 3 in the width direction of the semiconductor light emitting element 1 is located at the innermost position in the width direction (i.e., closer to the ridge R) in the P-type cladding layer 40. In other words, the recess 3 is most constricted in the P-type cladding layer 40. The position of the recess 3 in the width direction of the semiconductor light emitting element 1 moves outward in the width direction of the semiconductor light emitting element 1 (i.e., away from the ridge R) as it approaches the substrate 10 from the upper end of the lower wing portion Gd from the active layer 30.

[0053] The upper wing portion Gu has a forward mesa shape in a cross section perpendicular to the longitudinal direction of the wing portion G. The side surface Gus of the upper wing portion Gu forms an inclined surface of the forward mesa shape.

[0054] The insulating film 60 is an electrical insulating film disposed above the P-type cladding layer 40. As shown in FIG. 7 , the insulating film 60 continuously covers the area from the side surface Rds of the lower ridge Rd to a portion of the top surface Rut of the upper ridge Ru. That is, the insulating film 60 continuously covers the side surface Rds of the lower ridge Rd, the flat portion Rdf, the side surface Rus of the upper ridge Ru, and the top surface Rut. In this embodiment, an opening 60a is formed in the insulating film 60 at a position corresponding to the top surface Rut of the upper ridge Ru. Current is injected from the first P-side electrode 71 to the contact layer 50 through the opening 60a. That is, the opening 60a is a current injection window region for the contact layer 50. The insulating film 60 continuously covers the entire top surface of the semiconductor stack formed on the substrate 10, excluding the opening 60a. This prevents current from flowing to regions other than the ridge R. The material of the insulating film 60 is not particularly limited as long as it is electrically insulating. In this embodiment, the insulating film 60 is a silicon nitride film with a thickness of 100 nm.

[0055] The first P-side electrode 71 is a conductive layer disposed above the contact layer 50. As shown in FIG. 7 , the first P-side electrode 71 contacts the contact layer 50 on the upper surface of the ridge R, i.e., on the top surface Rut of the upper ridge Ru. As shown in FIGS. 7 and 8 , the first P-side electrode 71 continuously covers from the top surface of one wing portion G (i.e., the top surface Gut of the upper wing portion Gu) to the top surface of the other wing portion G, excluding the opening 60a. The material of the first P-side electrode 71 is not particularly limited as long as it is conductive. The first P-side electrode 71 includes, for example, a 50-nm-thick Ti film, a 150-nm-thick Pt film, and a 50-nm-thick Au film, which are stacked in this order from the contact layer 50 side.

[0056] 2 and 4 is a pad-shaped conductive layer disposed above the first P-side electrode 71. In this embodiment, the pad electrode 73 has an overhanging portion 73a at the end in the X-axis direction. The overhanging portion 73a is a portion that protrudes outward in the X-axis direction at the upper end of the end in the X-axis direction of the pad electrode 73. The configuration of the pad electrode 73 is not particularly limited. In this embodiment, the pad electrode 73 is an Au plated film with a film thickness of 2.5 μm.

[0057] 2 to 4 is a conductive layer disposed above the pad electrode 73. The second P-side electrode 72 may also be disposed in an area of ​​the upper surfaces of the first P-side electrode 71 and the insulating film 60 where the pad electrode 73 is not disposed. The configuration of the second P-side electrode 72 is not particularly limited. In this embodiment, the second P-side electrode 72 is a 50-nm-thick Ti film, a 150-nm-thick Pt film, and a 300-nm-thick Au film laminated in this order from the pad electrode 73 side.

[0058] 2 and 4 is a conductive layer disposed on the lower principal surface of the substrate 10 (i.e., the principal surface of the substrate 10 on the back side of the principal surface on which the semiconductor layers are stacked). The configuration of the N-side electrode 80 is not particularly limited. In this embodiment, the N-side electrode 80 includes, stacked in this order from the substrate 10 side, a 90-nm-thick AuGe film, a 20-nm-thick Ni film, a 50-nm-thick Au film, a 100-nm-thick Ti film, a 50-nm-thick Pt film, a 50-nm-thick Ti film, a 100-nm-thick Pt film, and a 500-nm-thick Au film.

[0059] [2. Manufacturing Method] A manufacturing method of the semiconductor light emitting device 1 according to this embodiment will be described with reference to FIGS. 9 to 24. FIGS. 9 to 24 are schematic cross-sectional views showing each step of the manufacturing method of the semiconductor light emitting device 1 according to this embodiment. FIGS. 9, 11, 13, 15, 17, 19, 20, 22, and 23 show a cross section corresponding to line II-II of the semiconductor light emitting device 1 shown in FIG. 1. FIGS. 10, 12, 14, 16, 18, 21, and 24 show a cross section corresponding to line III-III of the semiconductor light emitting device 1 shown in FIG. 1.

[0060] First, as shown in FIG. 9 , a substrate 10 is prepared, and each semiconductor layer is formed. The process of forming each semiconductor layer includes a step of forming an N-type cladding layer 20 above the substrate 10, a step of forming an active layer 30 above the N-type cladding layer 20, a step of forming a P-type cladding layer 40 above the active layer 30, and a step of forming a contact layer 50 above the P-type cladding layer 40. In this embodiment, the process of forming each semiconductor layer further includes a step of forming an N-type buffer layer above the substrate 10 and a step of forming an N-type buffer boundary layer above the N-type buffer layer before the step of forming the N-type cladding layer. Each semiconductor layer is formed by crystal growth using, for example, MOCVD (Metalorganic Chemical Vapor Deposition).

[0061] 10 , a window region 30w is formed in a region of the active layer 30 corresponding to the vicinity of the facet 1F. Specifically, the window region 30w can be formed by diffusing an impurity such as Zn into the active layer 30. In this embodiment, the window region 30w is also formed in a region corresponding to the vicinity of the facet 1R.

[0062] Next, a ridge R is formed in a region including the P-type cladding layer 40 and the contact layer 50. The process of forming the ridge R includes a step of forming an upper ridge Ru and a step of forming a lower ridge Rd (see FIG. 2) after the step of forming the upper ridge Ru. First, as shown in FIGS. 11 and 12, the upper ridge Ru is formed. In this embodiment, the upper wing portion Gu is also formed at the same time. Also, in this embodiment, wet etching is used in the step of forming the upper ridge Ru. This allows the side surface Ru to be inclined so that the upper ridge Ru has a forward mesa shape. Therefore, the adhesion between the side surface Ru and the insulating film 60 can be improved.

[0063] In this process, specifically, SiO ２A mask made of a material such as silicon dioxide is formed in a predetermined pattern. Then, wet etching is used to remove the portions of the contact layer 50 that are not covered by the mask. The chemical solution used for the etching and the composition of each semiconductor layer are determined so that the etching rate of the second etching stop layer 45 is slower than that of the contact layer 50 during wet etching. This makes it easier to stop etching at the second etching stop layer 45. This means that the controllability of the heights of the upper ridge Ru and the upper wing portions Gu can be improved. In this embodiment, the contact layer 50 and a portion of the second etching stop layer 45 are removed by wet etching. This means that the bottom surface Rub of the upper ridge Ru and the bottom surfaces Gub of the upper wing portions Gu are located on the second etching stop layer 45.

[0064] Furthermore, in this embodiment, the second etching stop layer 45 has constant regions 45a and 45c (see FIG. 6) in which the Al composition ratio is constant with respect to the position in the stacking direction, and therefore etching can be more reliably stopped in the second etching stop layer 45 than when the entire second etching stop layer 45 is made up of inclined regions.

[0065] The chemical solution used for etching may be, for example, a solution containing tartaric acid and hydrogen peroxide, the mixture ratio of which is, for example, 2:1.

[0066] By the above-described method, it is possible to form the upper ridge Ru and upper wing portions Gu having a forward mesa shape in a cross section perpendicular to the light propagation direction, as shown in Figures 11 and 12. Note that, as shown in Figure 12, the upper ridge Ru is not formed near the end face 1F (and end face 1R) of the semiconductor light emitting device 1. As shown in Figure 4, in a cross section parallel to the light propagation direction (and stacking direction) of the upper ridge Ru, the end of the upper ridge Ru closer to the end face 1F has an inverted mesa shape.

[0067] Next, after forming the upper ridge Ru and the upper wing portions Gu as described above, the lower ridge Rd and the lower wing portions Gd are formed as shown in Figures 13 and 14. In this embodiment, wet etching is used in the process of forming the lower ridge Rd. Specifically, SiO ２ A mask consisting of the above is formed to cover the upper ridge Ru and the upper wing portions Gu. Here, the mask is also formed in the regions corresponding to the flat portion Rdf and the wing flat portion Gdf. Then, by wet etching, the regions of the P-type cladding layer 40 not covered by the mask are etched down to the first etching stop layer 43, thereby forming a trench T. This allows the lower ridge Rd having the flat portion Rdf and the lower wing portions Gd having the wing flat portion Gdf to be formed. The chemical solution used for the wet etching and the composition of each semiconductor layer are determined so that the etching rate of the first etching stop layer 43 is slower than that of the second cladding layer 44. This makes it easier to stop etching at the first etching stop layer 43. In other words, the height of the lower ridge Rd and the lower wing portions Gd can be more easily controlled. In this embodiment, the second etching stop layer 45, the second cladding layer 44, and a portion of the first etching stop layer 43 are removed by wet etching. That is, the bottom surface Rdb of the lower ridge Rd and the bottom surface Gdb of the lower wing portion Gd are located on the first etching stop layer 43 .

[0068] The chemical solution used for etching may be, for example, a solution containing sulfuric acid, hydrogen peroxide, and water, with the mixture ratio of sulfuric acid, hydrogen peroxide, and water being, for example, 1:1:6.

[0069] 13 and 14, the lower ridge Rd and the lower wing Gd can be formed. In this embodiment, the lower ridge Rd and the lower wing Gd are formed continuously from the end of the P-type cladding layer 40 on the facet 1F side to the end on the facet 1R side.

[0070] Dry etching may be used in the process of forming the lower ridge Rd. Using dry etching improves the controllability of the film thickness removed by etching. This reduces the effective refractive index difference ΔN between the inside and outside of the ridge R of the semiconductor light-emitting element 1 and the individual differences in the divergence angle of the emitted light. Here, the effective refractive index difference refers to the difference between the effective refractive index n0 for light at the ridge R and below the ridge R and the effective refractive index n1 on the outside in the width direction of the ridge R. The outside in the width direction of the ridge R refers to the outside (in the X-axis direction) of the maximum width of the ridge R. In this embodiment, the maximum width of the ridge R is the width Wdb of the bottom surface Rdb of the lower ridge Rd. The effective refractive index is the product of the distribution of light guided through the semiconductor light-emitting element 1 (in this embodiment, the light distribution generated during laser oscillation) and the refractive index distribution of the semiconductor light-emitting element 1. Dry etching can be performed, for example, by employing (chemical) reactive etching to form the lower ridge Rd and lower wing portions Gd having the above-described shapes. Examples of dry etching gases include SiCl ４ When etching, SiCl ４ The inclination angle of the side surface Rds of the lower ridge Rd changes depending on the flow rate of SiCl ４ By setting the flow rate to, for example, 10 sccm or more, it is possible to form the side surface Rds of the lower ridge Rd having an inclination angle nearly perpendicular to the main surface of the substrate 10 .

[0071] 15 and 16, recesses 3 recessed in the width direction of the semiconductor light emitting element 1 are formed at the ends in the width direction of the semiconductor light emitting element 1. The recesses 3 are part of separation grooves used to separate the semiconductor light emitting elements 1. In other words, in a state in which multiple semiconductor stacks are connected in the X-axis direction as shown in FIGS. 13 and 14, separation grooves are formed between adjacent semiconductor stacks, and the semiconductor stacks are separated along the separation grooves. This forms the recesses 3 as shown in FIGS. 15 and 16.

[0072] 17, an insulating film 60 is formed on the ridge R. The insulating film 60 continuously covers from the side surface Rds of the lower ridge Rd to a part of the top surface Rut of the upper ridge Ru. In this embodiment, the insulating film 60 is formed on the entire upper surface of the semiconductor stack shown in FIGS. 15 and 16. In this embodiment, a silicon nitride film is formed as the insulating film 60 by using a CVD method or the like.

[0073] 19 , an opening 60a is formed in a region of the insulating film 60 that corresponds to the top surface Rut of the upper ridge Ru. Specifically, a mask is formed in a region of the insulating film 60 other than the region that corresponds to the opening 60a. The region of the insulating film 60 that corresponds to the opening 60a is, for example, etched to form the opening 60a.

[0074] 20 and 21 , a first P-side electrode 71 is formed. The first P-side electrode 71 is formed at least in the opening 60a of the insulating film 60. In the present embodiment, the first P-side electrode 71 continuously covers from the top surface Gut of one upper wing portion Gu to the top surface Gut of the other upper wing portion Gu. The first P-side electrode 71 is formed using, for example, photolithography and vapor deposition.

[0075] Next, as shown in FIG. 22 , a pad electrode 73 is formed. The pad electrode 73 is formed at least above the opening 60a of the insulating film 60. In this embodiment, the pad electrode 73 continuously covers the region on the first P-side electrode 71 from the top surface Gut of one upper wing portion Gu to the top surface Gut of the other upper wing portion Gu. The pad electrode 73 is formed using, for example, a plating method. As shown in FIG. 22 , the pad electrode 73 may have a canopy portion 73a at the end in the X-axis direction.

[0076] 23 and 24 , the second P-side electrode 72 is formed. The second P-side electrode 72 is formed in a region on the pad electrode 73, at least above the opening 60a of the insulating film 60. In this embodiment, the second P-side electrode 72 covers the entire upper surface of the pad electrode 73. The second P-side electrode 72 also covers at least a portion of the upper surface of the first P-side electrode 71 arranged on the periphery of the pad electrode 73. The second P-side electrode 72 does not need to cover the region below the overhanging portion 73a of the side surface of the pad electrode 73. The second P-side electrode 72 is formed using, for example, photolithography and vapor deposition.

[0077] 2 and 4, an N-side electrode 80 is formed on the lower surface of the substrate 10 (the main surface of the substrate 10 behind the main surface on which the semiconductor layers are stacked). The N-side electrode 80 is formed at least in a position facing the opening 60a of the insulating film 60. The N-side electrode 80 is formed using, for example, photolithography and vapor deposition.

[0078] Through the above steps, the semiconductor light emitting device 1 according to this embodiment can be formed.

[0079] 3. Effects The effects of the semiconductor light emitting device 1 according to this embodiment will be described.

[0080] As described above, the semiconductor light-emitting device 1 according to this embodiment has an upper ridge Ru and a lower ridge Rd. The top surface Rdt of the lower ridge Rd is located between the side surface Rds of the lower ridge Rd and the bottom surface Rub of the upper ridge Ru, and has a flat portion Rdf extending in the light propagation direction. The width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction.

[0081] In this way, because the width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction, the current injected from the top surface Rut of the upper ridge Ru flows into a region of the top surface Rdt of the lower ridge Rd that is more inward than the side surface Rds. Therefore, the current can be prevented from flowing to the side surface Rds of the lower ridge Rd. This makes it possible to prevent heat generation caused by the current flowing along the side surface Rds of the lower ridge Rd, thereby enabling the semiconductor light-emitting element 1 to have a higher output. Furthermore, it is possible to reduce failures caused by heat generation in the semiconductor light-emitting element 1.

[0082] Furthermore, since the lower ridge Rd has the flat portion Rdf, it is possible to improve the adhesion between the insulating film 60 and the ridge R. Therefore, it is possible to improve the insulation between the first p-side electrode 71 and the side surfaces of the ridge R (side surfaces Rds and Rus).

[0083] The P-type cladding layer 40 is Al Ｘ Ga １－Ｘ The Al composition ratio X1 of the first cladding layer 42 is composed of As (0<X<1), and the Al composition ratio X2 of the second cladding layer 44 satisfies the relationship X1 = X2 > 0.8. This allows the average refractive index of the P-type cladding layer 40 to be reduced compared to when the Al composition ratios X1 and X2 are 0.8 or less. The effect of this configuration will be described with reference to FIG. 25 . FIG. 25 is a graph showing the relationship between the output power and the injection current of the semiconductor light-emitting device 1 according to this embodiment. In FIG. 25 , the relationship when the temperature (Tc) of the measurement stage is 25° C. and the Al composition ratios X1 and X2 are 0.85 is shown by a solid line. In FIG. 25 , the relationship between the output power and the injection current of a semiconductor light-emitting device having the Al composition ratios X1 and X2 of 0.75 is also shown by a dashed line as a comparative example.

[0084] In the semiconductor light-emitting device 1 according to this embodiment, the Al composition ratios X1 and X2 are greater than 0.8, so the average refractive index of the P-type cladding layer 40 can be reduced. Therefore, the difference in average refractive index between the active layer 30 and the P-type cladding layer 40 can be increased, thereby enhancing the effect of confining light near the active layer 30. As a result, as shown in FIG. 25 , the semiconductor light-emitting device 1 according to this embodiment can increase the maximum output power by about 3.5 W compared to the semiconductor light-emitting device of the comparative example.

[0085] Furthermore, in the semiconductor light-emitting device 1 according to this embodiment, the Al composition ratio of the first etching stop layer 43 is 0.7 or less. When the Al composition ratio X1 is greater than 0.8, as in the first cladding layer 42, the layer is prone to oxidation and is easily corroded by chemicals used in etching and the like. However, by disposing the first etching stop layer 43 having an Al composition ratio of 0.7 or less on the first cladding layer 42, etching can be stopped at the first etching stop layer 43, and exposure of the first cladding layer 42 can be prevented. Therefore, oxidation and erosion of the first cladding layer 42 can be prevented.

[0086] Furthermore, in this embodiment, the Al composition ratio of the flat portion Rdf of the lower ridge Rd is 0.7 or less. That is, the flat portion Rdf is located in the second etching stop layer 45. This allows etching to be stopped at the flat portion Rdf, reducing exposure of the second cladding layer 44, which has an Al composition ratio X2 greater than 0.8. Therefore, oxidation and erosion of the second cladding layer 44 can be suppressed.

[0087] In this embodiment, the second etching stop layer 45 includes gradient regions 45b and 45d in which the Al composition ratio decreases toward the contact layer 50. This suppresses abrupt changes in composition in the stacking direction, thereby suppressing the energy barrier associated with abrupt changes in the band gap. Therefore, the electrical resistance in the second etching stop layer 45 can be suppressed, thereby suppressing the operating voltage of the semiconductor light emitting device 1.

[0088] In the present embodiment, the second etching stop layer 45 includes one or more constant regions 45 a and 45 c in which the Al composition ratio is constant with respect to the position in the stacking direction. This can improve the etching stop performance of the second etching stop layer 45. Furthermore, by alternately arranging two or more inclined regions 45 b and 45 d and one or more constant regions 45 a and 45 c in the stacking direction, the etching stop performance can be improved while suppressing the electrical resistance of the second etching stop layer 45.

[0089] In this embodiment, the width Wdt of the top surface Rdt of the lower ridge Rd, the width Wdc of the lower ridge Rd at the central position Rdc in the stacking direction, and the width Wdb of the bottom surface Rdb of the lower ridge Rd satisfy the relationships Wdt>Wdc and Wdb>Wdc, respectively, which enable current to be confined in the lower ridge Rd.

[0090] In this embodiment, the width Wut of the top surface Rut of the upper ridge Ru is smaller than the width Wub of the bottom surface Rub of the upper ridge Ru. This allows the side surface Rus of the upper ridge Ru to be inclined, thereby improving the adhesion between the side surface Rus and the insulating film 60.

[0091] Furthermore, in this embodiment, the upper surface of the end of the ridge R in the light propagation direction that is closer to the end face 1F from which light of the semiconductor light-emitting element 1 is emitted is located on the second etching stop layer 45. No upper ridge Ru is formed on the end of the ridge R that is closer to the end face 1F. In other words, no contact layer 50 is formed on the end of the ridge R in the light propagation direction that is closer to the end face 1F from which light of the semiconductor light-emitting element 1 is emitted. This makes it possible to prevent concentrated stress from being applied to the end of the ridge R when the semiconductor light-emitting element 1 is junction-down mounted on a mounting substrate or the like. Therefore, damage near the end face 1F of the semiconductor light-emitting element 1 can be suppressed.

[0092] In this embodiment, the active layer 30 includes a well layer 34, a P-side barrier layer 35 disposed above the well layer 34, a P-side guide layer 36 disposed above the P-side barrier layer 35, and a P-side cladding boundary layer 37. A remaining thickness dc, defined as the sum of the total thickness of the P-side guide layer 36 and the P-side cladding boundary layer 37, the thickness tpc0 of the lower cladding layer 41, the thickness tpc1 of the first cladding layer 42, and the thickness ts of the first etching stop layer 43, is greater than 0.5 μm. The effect of this configuration will be described with reference to FIG. 26 . FIG. 26 is a graph showing the relationship between the remaining thickness dc of the semiconductor light-emitting device 1 according to this embodiment and the horizontal divergence angle of the emitted light. Here, the horizontal divergence angle refers to the divergence angle in the X-axis direction in each diagram. As shown in FIG. 26 , by increasing the remaining thickness dc to greater than 0.5 μm, the horizontal divergence angle of the emitted light can be suppressed. Furthermore, for example, when constructing a lens-equipped light-emitting module comprising a semiconductor light-emitting element 1 and a lens arranged near the end face 1F of the semiconductor light-emitting element 1, the coupling efficiency between the emitted light and the lens can be increased by suppressing the horizontal spread angle of the emitted light.

[0093] In this embodiment, the effective refractive index difference ΔN between the effective refractive index n0 for light at the ridge R and below the ridge R and the effective refractive index n1 on the outside in the width direction of the ridge R is 4×10 －４ The effect achieved by the above-mentioned effective refractive index difference will be described with reference to FIG. 27. FIG. 27 is a graph showing the relationship between the horizontal divergence angle of the emitted light from the semiconductor light emitting element 1 according to this embodiment and the effective refractive index difference ΔN. As shown in FIG. 27, when the effective refractive index difference ΔN is 4×10 －４ By setting the horizontal divergence angle to 10.5 degrees or less, the horizontal divergence angle can be kept to 10.5 degrees or less. Therefore, when configuring a lens-equipped light-emitting module as described above, the coupling efficiency between the emitted light and the lens can be increased by suppressing the horizontal divergence angle of the emitted light.

[0094] Furthermore, in this embodiment, the relationship ts1≦tpc0<tpc1 holds among the thickness tpc0 of the lower cladding layer 41, the thickness tpc1 of the first cladding layer 42, and the thickness ts1 of the first etching stop layer 43. In this way, by increasing the thickness of the lower cladding layer 41, which has a higher refractive index than the first cladding layer 42, it is possible to suppress leakage of light from the first cladding layer 42 to the first etching stop layer 43, which has a higher refractive index than the first cladding layer 42. Furthermore, by reducing the thickness ts1 of the first etching stop layer 43, which has a relatively high electrical resistance, it is possible to suppress the operating voltage of the semiconductor light emitting device 1.

[0095] In this embodiment, the relationship tng>tpg holds between the thickness tng of the N-side guide layer 32 and the thickness tpg of the P-side guide layer 36. This allows the peak position of the light intensity distribution to be positioned closer to the N-side guide layer 32 than to the well layer 34. This allows the waveguide loss in the semiconductor light-emitting device 1 to be reduced, thereby increasing the slope efficiency.

[0096] In this embodiment, the top surface Gdt of the lower wing portion Gd has a wing flat portion Gdf, which is a flat region extending in the light propagation direction and is located between the side surface Gds of the lower wing portion Gd and the bottom surface Gub of the upper wing portion Gu, thereby improving the adhesion between the wing portion Gd and the insulating film 60.

[0097] [4. Modification 1] A semiconductor light-emitting device according to Modification 1 of the present embodiment will be described. The semiconductor light-emitting device according to this modification differs from the semiconductor light-emitting device 1 according to the embodiment in the configuration near the end in the light propagation direction, but is otherwise identical in configuration. The semiconductor light-emitting device according to this modification will be described below with reference to FIGS. 28 to 32, focusing on the differences from the semiconductor light-emitting device 1 according to the embodiment. FIG. 28 is a schematic top view showing the overall configuration of a semiconductor light-emitting device 1a according to this modification. FIGS. 29 to 32 are schematic cross-sectional views showing the overall configuration of a semiconductor light-emitting device 1a according to this modification, respectively. FIGS. 29, 30, and 31 show cross sections of the semiconductor light-emitting device 1a taken along lines XXIX-XXIX, XXX-XXX, and XXXI-XXXI in FIG. 28, respectively. FIG. 32 shows only a portion of the cross section of the semiconductor light-emitting device 1a taken along line XXXII-XXXII in FIG. 28, including the end face 1F.

[0098] 28 and 32, the semiconductor light emitting device 1a according to this modification differs from the semiconductor light emitting device 1 according to the embodiment in the configuration near the end in the light propagation direction, but is the same in other configurations as shown in Fig. 28 to 32. More specifically, the semiconductor light emitting device 1a according to this modification differs from the semiconductor light emitting device 1 according to the embodiment in the configuration between the ridge R and the end facet 1F, and the configuration between the ridge R and the end facet 1R.

[0099] 32 , in the semiconductor light emitting element 1a according to this modification, a region including the P-type cladding layer 40 and the contact layer 50 is disposed between the upper ridge Ru and an end face 1F of the semiconductor light emitting element 1a in the light propagation direction, and has a separation region De separated from the upper ridge Ru. In other words, as shown in FIG. 32 , a trench Te is formed between the upper ridge Ru and the separation region De. In this modification, the contact layer 50 and a portion of the P-type cladding layer 40 (a portion of the second etching stop layer 45) are removed in the trench Te.

[0100] 28 and 31 , in this modification, the isolation region De is disposed between the two wing portions G. The isolation region De is also connected to the two wing portions G. In other words, the upper surface of the contact layer 50 at the end portion in the light propagation direction of the semiconductor light emitting element 1a is flat and continuous over the entire length of the contact layer 50 in the width direction (i.e., the X-axis direction).

[0101] In this way, at the end in the light propagation direction of the semiconductor light emitting element 1a according to this modification, the contact layer 50 and the second etching stop layer 45 cover the second cladding layer 44 having a high Al composition ratio, etc., thereby suppressing oxidation and erosion of the second cladding layer 44, etc. By suppressing oxidation and erosion of the second cladding layer 44 having a high Al composition ratio, it is possible to improve adhesion between the semiconductor stack including these layers and the insulating film 60.

[0102] Furthermore, when the semiconductor light emitting element 1a is singulated, it is cleaved at positions corresponding to the ends in the light propagation direction, and therefore, if the adhesion between the contact layer 50 and the insulating film 60 is low, the insulating film 60 may peel off. However, in the semiconductor light emitting element 1a according to this modification, as described above, the adhesion between the insulating film 60 and the contact layer 50 can be increased at positions corresponding to the ends in the light propagation direction, and therefore peeling of the insulating film 60 can be suppressed.

[0103] 32 , the distance D1 from the end of the contact layer 50 in the light propagation direction to the end of the pad electrode 73 in the light propagation direction is smaller than the distance D2 between both ends of the isolation region De in the light propagation direction (i.e., the length of the isolation region De) and is greater than zero. For example, the distance D1 is about 10 μm, and the distance D2 is 20 μm or more and 150 μm or less. The smaller the distance D1, the better, as long as it is equal to or greater than the control accuracy of the cleavage position when singulating the semiconductor light emitting element 1a.

[0104] [6. Modification 2] A semiconductor light-emitting device according to Modification 2 of the present embodiment will be described. The semiconductor light-emitting device according to this modification differs from the semiconductor light-emitting device 1a according to Modification 1 in the configuration of the isolation region De, but is otherwise identical in configuration. The semiconductor light-emitting device according to this modification will be described below with reference to FIGS. 33 to 36, focusing on the differences from the semiconductor light-emitting device 1a according to Modification 1. FIG. 33 is a schematic top view showing the overall configuration of a semiconductor light-emitting device 1b according to this modification. FIGS. 34 to 36 are schematic cross-sectional views showing the overall configuration of the semiconductor light-emitting device 1b according to this modification. FIGS. 34, 35, and 36 show cross sections of the semiconductor light-emitting device 1b taken along lines XXXIV-XXXIV, XXXV-XXXV, and XXXVI-XXXVI in FIG. 33, respectively.

[0105] As shown in Figures 33 and 36, the semiconductor light-emitting element 1b of this modified example differs from the semiconductor light-emitting element 1a of modified example 1 in the configuration of the isolation region De, but is identical in other configurations as shown in Figures 34 to 35.

[0106] In the semiconductor light emitting device 1b according to this modification, as shown in FIGS. 33 and 36 , the isolation region De and the wing portion G (upper wing portion Gu) are not connected. That is, the contact layer 50 is not continuous between the isolation region De and the wing portion G. Also, as shown in FIG. 33 , the widthwise end of the isolation region De is located at a position corresponding to the widthwise end of the upper ridge Ru. In other words, the position in the X-axis direction of the widthwise end of the isolation region De is equal to the position in the X-axis direction of the widthwise end of the upper ridge Ru. Here, the statement that these positions are equal does not mean that these positions are completely equal, but also includes a state where they are substantially equal. The statement that these positions are equal also includes, for example, a state where the difference between these positions is 10% or less of the width of the ridge R.

[0107] In this modification, as in the first modification, the pad electrode 73 is not formed at the end of the semiconductor light emitting element 1b in the light propagation direction, and therefore at least a portion of the isolation region De is not covered with the pad electrode 73. Therefore, the position of the widthwise end of the isolation region De can be confirmed based on the external appearance of the semiconductor light emitting element 1b. Note that in this modification, the widthwise position of the isolation region De corresponds to the widthwise position of the ridge R, and therefore the position of the waveguide, i.e., the position in the X-axis direction at the end face 1F from which light is emitted, can be confirmed based on the external appearance of the semiconductor light emitting element 1b, based on the position of the widthwise end of the isolation region De.

[0108] As described above, in the semiconductor light emitting device 1b according to this modification, the contact layer 50 is separated by the isolation region De and the wing portion G, but the second etching stop layer 45 and the second cladding layer 44 of the P-type cladding layer 40 are not separated. In other words, the upper surface of the second cladding layer 44 at the end portion in the light propagation direction of the semiconductor light emitting device 1b is flat and continuous over the entire width of the second cladding layer 44, and is covered with the second etching stop layer 45.

[0109] As a result, the second etching stop layer 45 covers the second cladding layer 44 having a high Al composition ratio, etc., thereby suppressing oxidation and erosion of the second cladding layer 44, etc. By suppressing oxidation and erosion of the second cladding layer 44 having a high Al composition ratio, it is possible to improve adhesion between the semiconductor stack including these layers and the insulating film 60. Therefore, similar to the semiconductor light emitting device 1a according to Modification 1, peeling of the insulating film 60 during cleavage can be suppressed.

[0110] (Other Modifications, etc.) The semiconductor light emitting device according to the present disclosure has been described above based on the embodiments and modifications, but the present disclosure is not limited to the above-described embodiments and modifications.

[0111] For example, in the above embodiment, an example was shown in which the semiconductor light emitting element 1 was a semiconductor laser element, but the semiconductor light emitting element 1 is not limited to a semiconductor laser element. For example, the semiconductor light emitting element may be a superluminescent diode.

[0112] Furthermore, in the above embodiment, the semiconductor light emitting device 1 has two wing portions G, but the semiconductor light emitting device 1 may have only one wing portion G.

[0113] In the above embodiment, the active layer 30 of the semiconductor light emitting device 1 has a single quantum well structure, but it may have a multiple quantum well structure.

[0114] In the above embodiment, the active layer 30 of the semiconductor light emitting device 1 has the window regions 30w near the end faces 1F and 1R, but the semiconductor light emitting device 1 does not necessarily have to have the window regions 30w.

[0115] In addition, in the above embodiment, the inclined regions 45b and 45d of the second etching stop layer 45 are regions in which the Al composition ratio decreases as the region approaches the contact layer 50, but they may also be regions in which the Al composition ratio increases as the region approaches the contact layer 50.

[0116] This disclosure also includes forms obtained by applying various modifications to the above embodiments and modifications that a person skilled in the art would conceive, and forms realized by arbitrarily combining the components and functions of the above embodiments and modifications within the scope that does not deviate from the intent of this disclosure.

[0117] The semiconductor light emitting device and the like according to the present disclosure can be used, for example, as a high-output, highly efficient light source in a light source for laser processing.

[0118] REFERENCE SIGNS LIST 1, 1a, 1b Semiconductor light emitting element 1F, 1R End face 2F, 2R Reflecting film 3 Recess 3w Constricted portion 10 Substrate 20 N-type cladding layer 30 Active layer 30w Window region 31 N-side cladding boundary layer 32 N-side guide layer 33 N-side barrier layer 34 Well layer 35 P-side barrier layer 36 P-side guide layer 37 P-side cladding boundary layer 40 P-type cladding layer 41 Lower cladding layer 42 First cladding layer 43 First etching stop layer 44 Second cladding layer 45 Second etching stop layer 45a, 45c Constant region 45b, 45d Inclined region 50 Contact layer 60 Insulating film 60a Opening 71 First P-side electrode 72 Second P-side electrode 73 Pad electrode 73a Overhanging portion 80 N-side electrode De Separation region G Wing portion Gd Lower wing portion Gdb, Gub, Rdb, Rub Bottom surface Gdf Wing flat portion Gds, Gus, Rds, Rus Side surface Gdt, Gut, Rdt, Rut Top surface Gu Upper wing portion R Ridge Rd Lower ridge Rdc Center position in stacking direction Rdf Flat portion Ru Upper ridge T, Te Groove Tb Bottom portion

Claims

1. A semiconductor light emitting device that emits light, A substrate; an N-type cladding layer disposed above the substrate; an active layer disposed above the N-type cladding layer; a P-type cladding layer disposed above the active layer; a contact layer disposed above the P-type cladding layer; an insulating film disposed above the P-type cladding layer; a ridge extending in a propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer; the ridge includes a lower ridge including the P-type cladding layer, and an upper ridge disposed on a top surface of the lower ridge and including the contact layer; a top surface of the lower ridge has a flat portion located between a side surface of the lower ridge and a bottom surface of the upper ridge and extending in a propagation direction of the light, a width of a bottom surface of the upper ridge is smaller than a width of a top surface of the lower ridge and a width of the lower ridge at a center position in a stacking direction; The insulating film continuously covers from the side surface of the lower ridge to a part of the top surface of the upper ridge. Semiconductor light emitting element.

2. A semiconductor light emitting device that emits light, A substrate; an N-type cladding layer disposed above the substrate; an active layer disposed above the N-type cladding layer; a P-type cladding layer disposed above the active layer; a contact layer disposed above the P-type cladding layer; a ridge extending in a propagation direction of the light is formed in a region including the P-type cladding layer and the contact layer; the ridge includes a lower ridge including the P-type cladding layer, and an upper ridge disposed on a top surface of the lower ridge and including the contact layer; The P-type cladding layer is Al Ｘ G １－Ｘ X is a SiO 2 , and ... Regarding the Al composition ratio X0 of the lower cladding layer, the Al composition ratio X1 of the first cladding layer, and the Al composition ratio X2 of the second cladding layer, X1=X2>0.8, And, X1=X2>X0 The relationship is Semiconductor light emitting element.

3. The Al composition ratio of the first etching stop layer is 0.7 or less. The semiconductor light emitting device according to claim 2 .

4. a top surface of the lower ridge has a flat portion located between a side surface of the lower ridge and a bottom surface of the upper ridge and extending in a propagation direction of the light, the upper ridge includes at least a portion of each of the second etch stop layer and the contact layer; The Al composition ratio of the flat portion of the lower ridge is 0.7 or less. The semiconductor light-emitting device according to claim 2 .

5. The second etching stop layer includes a gradient region in which the Al composition ratio increases or decreases toward the contact layer. The semiconductor light-emitting device according to claim 2 .

6. the second etching stop layer includes two or more inclined regions and one or more constant regions in which an Al composition ratio is constant with respect to a position in a stacking direction, Each of the two or more gradient regions has an Al composition ratio that increases or decreases toward the contact layer, The two or more inclined regions and the one or more constant regions are alternately arranged in the stacking direction. The semiconductor light-emitting device according to claim 2 .

7. The gradient region is a region in which the Al composition ratio decreases toward the contact layer. The semiconductor light emitting device according to claim 5 .

8. a width of a top surface of the lower ridge is equal to a width of the lower ridge at a central position in a stacking direction, The upper surface of the P-type cladding layer at a position adjacent to the bottom surface of the lower ridge in the width direction of the lower ridge is located on the first etching stop layer. The semiconductor light-emitting device according to claim 2 .

9. With respect to a width Wdt of a top surface of the lower ridge, a width Wdc of the lower ridge at a center position in the stacking direction, and a width Wdb of a bottom surface of the lower ridge, Wdt>Wdc, And, Wdb>Wdc The relationship is established, The upper surface of the P-type cladding layer at a position adjacent to the bottom surface of the lower ridge in the width direction of the lower ridge is located on the first etching stop layer. The semiconductor light-emitting device according to claim 2 .

10. the active layer includes a well layer, a P-side barrier layer disposed above the well layer, a P-side guide layer disposed above the P-side barrier layer, and a P-side cladding boundary layer disposed above the P-side guide layer, A remaining thickness dc defined by the sum of the total thickness of the P-side guide layer and the P-side cladding boundary layer, the thickness tpc0 of the lower cladding layer, the thickness tpc1 of the first cladding layer, and the thickness ts of the first etching stop layer is greater than 0.5 μm. The semiconductor light-emitting device according to claim 2 .

11. With respect to a thickness tpc0 of the lower cladding layer, a thickness tpc1 of the first cladding layer, and a thickness ts1 of the first etching stop layer, ts1≦tpc0<tpc1 The relationship is The semiconductor light-emitting device according to claim 2 .

12. Among the ends of the ridge in the light propagation direction, the upper surface of the end closer to the end face from which the light of the semiconductor light emitting element is emitted is located on the second etching stop layer. The semiconductor light-emitting device according to claim 2 .

13. an upper surface of the second cladding layer at an end portion in the light propagation direction of the semiconductor light emitting element is flat and continuous over the entire width of the second cladding layer, and is covered with the second etching stop layer; a region including the P-type cladding layer and the contact layer is disposed between an end face of the semiconductor light emitting device in a light propagation direction and the upper ridge, and has a separation region separated from the upper ridge; The ends of the isolation region in the width direction are located at positions corresponding to the ends of the upper ridge in the width direction. The semiconductor light-emitting device according to claim 2 .

14. The width of the top surface of the upper ridge is smaller than the width of the bottom surface of the upper ridge. The semiconductor light emitting device according to any one of claims 1 to 3.

15. The difference in effective refractive index between the effective refractive index n0 for the light at and below the ridge and the effective refractive index n1 on the outside in the width direction of the ridge is 4×10 －４ is less than or equal to The semiconductor light emitting device according to any one of claims 1 to 3.

16. the active layer includes an N-side guide layer, an N-side barrier layer disposed above the N-side guide layer, a P-side barrier layer disposed above the N-side barrier layer, and a P-side guide layer disposed above the P-side barrier layer, Regarding the thickness tng of the N-side guide layer and the thickness tpg of the P-side guide layer, tng>tpg The relationship is The semiconductor light emitting device according to any one of claims 1 to 3.

17. a wing portion extending along the ridge is formed in a region including the P-type cladding layer and the contact layer; the wing portion includes a lower wing portion including the P-type cladding layer, and an upper wing portion disposed on a top surface of the lower wing portion and including the contact layer; The top surface of the lower wing portion has a wing flat portion which is a flat region located between the side surface of the lower wing portion and the bottom surface of the upper wing portion and extends in the propagation direction of the light. The semiconductor light emitting device according to any one of claims 1 to 3.

18. a recess that is recessed in a width direction of the semiconductor light emitting element is formed at an end portion in a width direction of the semiconductor light emitting element, a side surface of the lower wing portion away from the ridge is included in the recess; a side surface of the lower wing portion farther from the ridge has a constricted portion located inward in a width direction of the semiconductor light emitting device than an upper end of the lower wing portion; The position of the recess in the width direction of the semiconductor light emitting device is located at the innermost position in the width direction in the P-type cladding layer, and moves outward in the width direction of the semiconductor light emitting device as it approaches the substrate from the active layer. The semiconductor light emitting device according to claim 17 .

19. In a cross section of the upper ridge in a direction parallel to the light propagation direction, an end portion of the upper ridge closer to an end face from which the light of the semiconductor light emitting element is emitted has an inverted mesa shape. The semiconductor light emitting device according to any one of claims 1 to 3.

20. The upper surface of the contact layer at the end portion in the light propagation direction of the semiconductor light emitting element is flat and continuous over the entire width of the contact layer. The semiconductor light emitting device according to any one of claims 1 to 3.

21. A method for manufacturing a semiconductor light emitting device that emits light, comprising the steps of: forming an N-type cladding layer over a substrate; forming an active layer above the N-type cladding layer; forming a P-type cladding layer above the active layer; forming a contact layer above the P-type cladding layer; forming a ridge in a region including the P-type cladding layer and the contact layer; forming an insulating film on the ridge; the ridge includes a lower ridge including the P-type cladding layer, and an upper ridge disposed on a top surface of the lower ridge and including the contact layer; The step of forming the ridge includes: forming the upper ridge; forming the lower ridge after forming the upper ridge; a top surface of the lower ridge has a flat portion located between a side surface of the lower ridge and a bottom surface of the upper ridge and extending in a propagation direction of the light, a width of a bottom surface of the upper ridge is smaller than a width of a top surface of the lower ridge and a width of the lower ridge at a center position in a stacking direction, The insulating film continuously covers from the side surface of the lower ridge to a part of the top surface of the upper ridge. A method for manufacturing a semiconductor light emitting device.

22. In the step of forming the upper ridge, wet etching is used. The method for manufacturing the semiconductor light emitting device according to claim 21 .

23. In the step of forming the lower ridge, dry etching is used. The method for manufacturing the semiconductor light-emitting device according to claim 21 or 22.

24. In the step of forming the lower ridge, wet etching is used. The method for manufacturing the semiconductor light-emitting device according to claim 21 or 22.