Semiconductor device

Abstract

This semiconductor device comprises: an n-type semiconductor layer; an n-type first body region formed in a surface of the semiconductor layer; a p-type source region that is formed in the first body region, and that is formed separated from the outer edge of the first body region towards the inside thereof; a p-type drain region that is formed in the surface of the semiconductor layer, and that is formed separated from the first body region in the X-axis direction; a field insulation film that is formed over a section of the surface of the semiconductor layer, between the source region and the drain region in the X-axis direction; a gate insulation film formed over a section of the surface of the semiconductor layer, between the field insulation film and the drain region in the X-axis direction; a gate electrode formed on the gate insulation film; and a temperature sensor formed on the field insulation film.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] 2. Description of the Related Art Generally, semiconductor devices are known that have a temperature sensor for detecting the temperature of transistors, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), provided on the same chip (see, for example, Japanese Patent Application Laid-Open No. 2003-222198).

[0003] Japanese Patent Application Laid-Open No. 2015-166714

[0004] However, if the region where the transistor is formed and the region where the temperature sensor is formed are provided as separate regions, the semiconductor device will become larger in size.

[0005] a gate insulating film formed on a portion of the surface of the semiconductor layer between the source region and the drain region in the first direction; a gate electrode formed on the gate insulating film; and a temperature sensor formed on the field insulating film.

[0006] A semiconductor device according to one aspect of the present disclosure includes: a semiconductor layer having a surface; an n-channel first MOS region and a p-channel second MOS region formed on the surface of the semiconductor layer; an element isolation region including an insulating film formed on the surface of the semiconductor layer and isolating the first MOS region and the second MOS region; and a temperature sensor formed on the insulating film.

[0007] According to the semiconductor device of the present disclosure, it is possible to prevent the device from becoming large in size.

[0008] FIG. 1 is a schematic plan view of a semiconductor device of a first embodiment. FIG. 2 is a schematic plan view of a semiconductor layer of the semiconductor device of FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 1. FIG. 4 is an enlarged view of a portion F4 in FIG. 3. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 1. FIG. 6 is an enlarged view of a portion F6 in FIG. 1. FIG. 7 is a schematic plan view of a semiconductor device of a second embodiment. FIG. 8 is a schematic cross-sectional view of the semiconductor device taken along line F8-F8 in FIG. 7. FIG. 9 is a schematic cross-sectional view of the semiconductor device taken along line F9-F9 in FIG. 7. FIG. 10 is a schematic cross-sectional view of the semiconductor device taken along line F10-F10 in FIG. 7. FIG. 11 is a schematic plan view of a semiconductor device of a modified example. FIG. 12 is a schematic cross-sectional view of an enlarged portion of the semiconductor device of the modified example.

[0009] Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] First Embodiment Fig. 1 shows a schematic planar structure of a semiconductor device 10. For ease of understanding, Fig. 1 shows a simplified configuration of the semiconductor device 10. Furthermore, Fig. 1 omits a field insulating film 24, an interlayer insulating layer 40, a source wiring 42, and a drain wiring 44, which will be described later. Fig. 2 shows a schematic planar structure of a semiconductor layer 22, which will be described later, of the semiconductor device 10. Figs. 3 to 5 show schematic cross-sectional structures of the semiconductor device 10.

[0012] Furthermore, the term "plan view" used in the present disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Figures 3 to 5. Furthermore, for convenience, in the semiconductor device 10 shown in Figures 3 to 5, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless explicitly stated otherwise, "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis. In this embodiment, the X-axis direction corresponds to the "first direction," and the Y-axis direction corresponds to the "second direction."

[0013] As shown in Fig. 1, the semiconductor device 10 is formed in a rectangular shape in a plan view. In the example of Fig. 1, the semiconductor device 10 is formed in a rectangular shape with the X-axis direction as the short side direction and the Y-axis direction as the long side direction. Note that the shape of the semiconductor device 10 in a plan view can be changed as desired.

[0014] The semiconductor device 10 includes device side surfaces 12A to 12D. Device side surfaces 12A and 12B face each other in the X-axis direction, and device side surfaces 12C and 12D face each other in the Y-axis direction. Device side surfaces 12A and 12B extend along the Y-axis direction in a plan view, and device side surfaces 12C and 12D extend along the X-axis direction in a plan view.

[0015] The semiconductor device 10 includes a cell region 16 surrounded by an element isolation portion 14. In other words, the cell region 16 is partitioned by the element isolation portion 14. A plurality of transistors are formed in the cell region 16. In the example shown in FIG. 1, the element isolation portion 14 is formed in the shape of a rectangular frame with the X-axis direction as the short side direction and the Y-axis direction as the long side direction in a plan view. Therefore, the cell region 16 is formed in the shape of a rectangle with the X-axis direction as the short side direction and the Y-axis direction as the long side direction in a plan view. Also, in the example shown in FIG. 1, the element isolation portion 14 is configured to include the device side surfaces 12A to 12D. The shape of the cell region 16 in a plan view can be changed as desired.

[0016] As shown in FIG. 3 , the semiconductor device 10 includes a p-type semiconductor substrate 20 and an n-type semiconductor layer 22 formed on the semiconductor substrate 20. The semiconductor substrate 20 is formed of a material containing, for example, silicon (Si). In one example, the semiconductor substrate 20 is a Si substrate. Note that the semiconductor substrate 20 can be arbitrarily changed and may be, for example, a silicon carbide (SiC) substrate. The thickness of the semiconductor substrate 20 is, for example, 100 μm or more and 500 μm or less. The p-type impurity concentration of the semiconductor substrate 20 is, for example, 1×10 １３ cm －３ 1x10 or more １５ cm －３ The semiconductor substrate 20 includes a substrate front surface 20s and a substrate back surface 20r. The substrate back surface 20r constitutes the device back surface of the semiconductor device 10. The semiconductor substrate 20 includes four substrate side surfaces. The four substrate side surfaces constitute a part of each of the device side surfaces 12A to 12D.

[0017] The semiconductor layer 22 is formed on the substrate surface 20s. In this embodiment, the semiconductor layer 22 is in contact with the substrate surface 20s. The semiconductor layer 22 is formed, for example, over the entire surface of the substrate surface 20s. The semiconductor layer 22 is formed of an n-type epitaxial layer whose thickness is in the Z-axis direction. Therefore, the Z-axis direction can be said to be the thickness direction of the semiconductor layer 22. The thickness of the semiconductor layer 22 is thinner than the thickness of the semiconductor substrate 20, and is, for example, not less than 3 μm and not more than 20 μm. The n-type impurity concentration of the semiconductor layer 22 is, for example, 1×10 １４ cm －３ 1x10 or more １６ cm －３ The following is the result.

[0018] 1, the element isolation portion 14 is provided on the outer periphery of the semiconductor layer 22. As shown in Fig. 3, the element isolation portion 14 includes a first isolation region 14A and a second isolation region 14B as p-type well regions, and a p-type buried layer 14C.

[0019] The buried layer 14C is formed to straddle the boundary between the semiconductor substrate 20 and the semiconductor layer 22. The buried layer 14C has a thickness of, for example, 2 μm or more and 3 μm or less. The p-type impurity concentration of the buried layer 14C is higher than the n-type impurity concentration of the semiconductor layer 22.

[0020] The first isolation region 14A is formed on the buried layer 14C. The second isolation region 14B is formed on the first isolation region 14A. The second isolation region 14B is exposed at a surface 22s of the semiconductor layer 22. In this manner, the element isolation part 14 penetrates the semiconductor layer 22 in the Z-axis direction. The p-type impurity concentration of the second isolation region 14B is higher than the p-type impurity concentration of the first isolation region 14A.

[0021] A p-type element isolation side contact region 14D is formed in a surface layer portion of the second isolation region 14B. The p-type impurity concentration of the element isolation side contact region 14D is higher than the p-type impurity concentration of the second isolation region 14B.

[0022] As shown in FIGS. 3 and 5, the semiconductor device 10 includes n-type semiconductor devices formed in a cell region 16 partitioned by an element isolation portion 14. ＋ The semiconductor device includes an n-type buried layer 18. The buried layer 18 is formed in a rectangular shape that is slightly smaller than the element isolation portion 14 in a plan view. As shown in FIGS. 3 and 5 , the buried layer 18 is formed so as to straddle the boundary between the semiconductor substrate 20 and the semiconductor layer 22. The thickness of the buried layer 18 is, for example, 2 μm or more and 3 μm or less. The n-type impurity concentration of the buried layer 18 is higher than the n-type impurity concentration of the semiconductor layer 22.

[0023] In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc. The p-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0024] The semiconductor device 10 includes a field insulating film 24 formed on the surface 22s of the semiconductor layer 22. Similar to the element isolation portion 14, the field insulating film 24 is formed in the shape of a rectangular frame surrounding the cell region 16 in a plan view. The field insulating film 24 is also selectively formed in the cell region 16. The field insulating film 24 is, for example, a local oxidation of silicon (LOCOS) film formed by selectively oxidizing the surface 22s of the semiconductor layer 22. The field insulating film 24 is, for example, a silicon oxide (SiO ２ The field insulating film 24 may be made of other insulating materials such as silicon oxynitride (SiON).

[0025] (Transistor Configuration) Next, the configuration of the transistors in the cell region 16 will be described. The transistors in the cell region 16 include at least one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Transistor), and a JFET (Junction Field Effect Transistor). In one example, the transistors include a MOSFET. In this embodiment, the transistors include a LD (Laterally Diffused) MOSFET.

[0026] As shown in FIG. 3, the semiconductor device 10 includes an n-type first body region 26 and a p-type second body region 28 formed on the surface 22s of the semiconductor layer 22 in the cell region 16, and a p-type second body region 29 formed on the surface of the first body region 26. ＋ -type source region 30 and n ＋ a p-type body contact region 32 (see FIG. 2) and a p-type body contact region 32 formed on the surface of the second body region 28; ＋ and a drain region 34 of the same type.

[0027] 1 , a plurality of first body regions 26 and a plurality of second body regions 28 are formed. Each of the body regions 26, 28 extends in the Y-axis direction in a plan view. The plurality of first body regions 26 and the plurality of second body regions 28 are arranged alternately one by one in the X-axis direction. The first body regions 26 and the second body regions 28 are arranged spaced apart from each other in the X-axis direction.

[0028] 3 , the thickness of each of the first body region 26 and the second body region 28 is, for example, not less than 0.5 μm and not more than 4 μm. Here, the thickness of the first body region 26 can be defined by the distance in the Z-axis direction between the surface 22 s of the semiconductor layer 22 and the bottom surface of the first body region 26. The thickness of the second body region 28 can be defined by the distance in the Z-axis direction between the surface 22 s of the semiconductor layer 22 and the bottom surface of the second body region 28.

[0029] The bottom surface of each of the first body region 26 and the second body region 28 is located closer to the semiconductor substrate 20 than the bottom surface of the field insulating film 24. On the other hand, the bottom surface of each of the first body region 26 and the second body region 28 is located closer to the surface 22s of the semiconductor layer 22 than the buried layer 18. The n-type impurity concentration of the first body region 26 and the p-type impurity concentration of the second body region 28 are each, for example, 1×10 １７ cm －３ 1x10 or more １８ cm －３ The following is the result.

[0030] As shown in FIG. 2 , the source region 30 and the body contact region 32 are formed in an inner region of the first body region 26 in a plan view. Each of the source region 30 and the body contact region 32 is disposed inwardly and spaced apart from the outer edge 26A of the first body region 26. Each of the source region 30 and the body contact region 32 has an outer periphery shaped along the outer edge 26A of the first body region 26. The outer periphery of each of the source region 30 and the body contact region 32 is, for example, slightly smaller than the outer edge 26A of the first body region 26. A plurality of source regions 30 and a plurality of body contact regions 32 are formed. The plurality of source regions 30 and the plurality of body contact regions 32 are alternately disposed one by one in the Y-axis direction. Adjacent source regions 30 and body contact regions 32 in the Y-axis direction are in contact with each other. The body contact regions 32 are disposed at both ends of the first body region 26 in the Y-axis direction. The arrangement of the source region 30 and the body contact region 32 is not limited to the arrangement shown in FIG. 2, but can be changed as desired.

[0031] The p-type impurity concentration of the source region 30 is higher than the n-type impurity concentration of the first body region 26. The p-type impurity concentration of the source region 30 is, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ 3, the thickness of the source region 30 is thinner than the thickness of the first body region 26, and is, for example, not less than 0.2 μm and not more than 1 μm.

[0032] The n-type impurity concentration of the body contact region 32 is higher than the n-type impurity concentration of the first body region 26. The n-type impurity concentration of the body contact region 32 is, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ The thickness of the body contact region 32 is thinner than the thickness of the first body region 26, and is, for example, not less than 0.2 μm and not more than 1 μm.

[0033] 2 and 5, the drain region 34 is formed in an inner region of the second body region 28 in a plan view. The drain region 34 is disposed inwardly and spaced apart from the outer edge 28A of the second body region 28. The drain region 34 extends along the Y-axis direction in a plan view. The p-type impurity concentration of the drain region 34 is higher than the p-type impurity concentration of the second body region 28. The p-type impurity concentration of the drain region 34 is, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ 5, the thickness of the drain region 34 is thinner than the thickness of the second body region 28, and is, for example, not less than 0.2 μm and not more than 2 μm.

[0034] 4, the semiconductor device 10 includes a gate insulating film 36 formed on the surface 22s of the semiconductor layer 22, a gate electrode 38 formed on the gate insulating film 36, and an interlayer insulating layer 40 covering the gate electrode 38. Furthermore, as shown in FIG.

[0035] 4, the gate insulating film 36 is formed so as to cover the outer regions of the first body region 26 and the second body region 28 on the surface 22s of the semiconductor layer 22. The outer region of the first body region 26 is a region of the first body region 26 that surrounds the source region 30 and the body contact region 32 in a plan view. In other words, the gate insulating film 36 exposes both the source region 30 and the body contact region 32. The gate insulating film 36 is integrated with the field insulating film 24. The gate insulating film 36 is made of, for example, SiO ２ The gate insulating film 36 may be formed of another insulating material such as SiON. The gate insulating film 36 is formed of, for example, the same material as the field insulating film 24. The thickness of the gate insulating film 36 is thinner than the thickness of the field insulating film 24, and is, for example, not less than 2 nm and not more than 55 nm.

[0036] As shown in FIG. 1 , the gate electrode 38 is formed in the shape of a rectangular band extending in the Y-axis direction. Both ends of the gate electrode 38 in the Y-axis direction are located outward from the first body region 26. The gate electrode 38 has a gate opening 39 (not shown in FIG. 2 ) that exposes both the source region 30 and the body contact region 32. The gate electrode 38 is formed, for example, from conductive polysilicon. The gate electrode 38 is formed, for example, from polysilicon containing p-type impurities. The p-type impurity concentration of the gate electrode 38 is, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ The gate electrode 38 may be formed of a material containing at least one of cobalt (Co), hafnium (Hf), zirconium (Zr), Al, titanium (Ti), tantalum (Ta), and molybdenum (Mo), for example.

[0037] 4, the gate electrode 38 extends continuously from on the gate insulating film 36 onto the field insulating film 24. That is, the gate electrode 38 includes a main electrode portion 38A provided on the gate insulating film 36 and a field plate portion 38B covering a part of the field insulating film 24. The gate opening 39 is formed in the main electrode portion 38A. That is, in a plan view, the main electrode portion 38A is formed so as to surround both the source region 30 and the body contact region 32.

[0038] 4 and 5, a gate silicide 47 is formed on the gate electrode 38. The gate silicide 47 is formed as a Si compound containing at least one of nickel (Ni), Co, and Ti.

[0039] As shown in Fig. 4, the interlayer insulating layer 40 is formed on the surface 22s of the semiconductor layer 22 so as to cover the gate insulating film 36, the gate electrode 38, and the field insulating film 24. The interlayer insulating layer 40 covers at least the entire cell region 16. In the example shown in Fig. 3, the interlayer insulating layer 40 also covers the element isolation portion 14. The thickness of the interlayer insulating layer 40 is equal to or greater than the thickness of the field insulating film 24, and is, for example, 0.3 µm to 2 µm. The interlayer insulating layer 40 is made of, for example, SiO ２ The interlayer insulating layer 40 may be formed of other insulating materials such as silicon nitride (SiN). ２ The silicon nitride layer may have a laminated structure of silicon nitride and silicon nitride.

[0040] The source wiring 42 formed on the interlayer insulating layer 40 is electrically connected to the source region 30. More specifically, the source wiring 42 includes a source contact portion 42A that penetrates the interlayer insulating layer 40 in the Z-axis direction. The source contact portion 42A is disposed at a position that overlaps with the source region 30 in a plan view and is in contact with the source region 30. This electrically connects the source wiring 42 to the source region 30. The source wiring 42 is formed of a conductive material that includes at least one of Al, Cu, and Ti, for example. In one example, the source wiring 42 is formed of Al.

[0041] The drain wiring 44 formed on the interlayer insulating layer 40 is electrically connected to the drain region 34. More specifically, the drain wiring 44 includes a drain contact portion 44A that penetrates the interlayer insulating layer 40 in the Z-axis direction. The drain contact portion 44A is disposed at a position that overlaps with the drain region 34 in a plan view and is in contact with the drain region 34. This electrically connects the drain wiring 44 to the drain region 34. The drain wiring 44 is formed of a conductive material that includes at least one of Al, Cu, and Ti, for example. In one example, the drain wiring 44 is formed of Al.

[0042] As shown in FIG. 5 , a gate wiring 46 is formed on the interlayer insulating layer 40. The gate wiring 46 is electrically connected to the gate electrode 38 via a gate contact portion 46A, similar to the source wiring 42 and the drain wiring 44 (both see FIG. 3 ). As shown in FIG. 1 , the gate contact portion 46A is disposed at a position overlapping both ends of the gate electrode 38 in the Y-axis direction in a plan view. The gate contact portion 46A is in contact with the gate silicide 47. Therefore, the gate contact portion 46A is electrically connected to the gate electrode 38 via the gate silicide 47. The gate wiring 46 is formed of a conductive material containing at least one of Al, Cu, and Ti, for example. In one example, the gate wiring 46 is formed of Al. That is, the source wiring 42, the drain wiring 44, and the gate wiring 46 may be formed of the same material.

[0043] The source contact portion 42A, the drain contact portion 44A, and the gate contact portion 46A may each be formed of a conductive material different from that of the source wiring 42, the drain wiring 44, and the gate wiring 46. In one example, the source contact portion 42A, the drain contact portion 44A, and the gate contact portion 46A are each formed of a material containing tungsten (W).

[0044] 1 and 2 , the semiconductor device 10 includes an n-type guard ring 48 that surrounds both the first body region 26 and the second body region 28. In other words, the guard ring 48 surrounds the source region 30, the body contact region 32, and the drain region 34 in a plan view. The guard ring 48 also surrounds the gate electrode 38 in a plan view. The guard ring 48 is provided at a position that overlaps the outer periphery of the buried layer 18 in a plan view. Therefore, in a plan view, the guard ring 48 is formed in the shape of a rectangular frame with the X-axis direction as the short side direction and the Y-axis direction as the long side direction.

[0045] 1 to 3, the guard ring 48 includes a first ring region 50 formed on the buried layer 18 and a second ring region 52 formed on the first ring region 50. As shown in FIG. 3, the second ring region 52 is exposed at the surface 22s of the semiconductor layer 22. In this manner, the transistor in the cell region 16 is surrounded by the guard ring 48 and the buried layer 18 in the X-axis direction, the Y-axis direction, and the Z-axis direction. The n-type impurity concentration of the second ring region 52 is higher than the n-type impurity concentration of the first ring region 50. In addition, both the guard ring 48 and the buried layer 18 are in an electrically floating state.

[0046] An n-type ring-side contact region 54 is formed in a surface layer portion of the second ring region 52. The n-type impurity concentration of the ring-side contact region 54 is higher than the n-type impurity concentration of the second ring region 52. The ring-side contact region 54 may be omitted.

[0047] 1, the semiconductor device 10 includes a temperature sensor 60 formed on the field insulating film 24. In plan view, the temperature sensor 60 can also be said to be formed in a region surrounded by the element isolation portion 14. In this embodiment, in plan view, the temperature sensor 60 is formed in the cell region 16. In plan view, the temperature sensor 60 can also be said to be formed in a region surrounded by the guard ring 48. In plan view, the temperature sensor 60 can also be said to be formed in a region in which a transistor is formed.

[0048] 4 and 5 , the temperature sensor 60 includes a diode 61. The diode 61 is formed on the field insulating film 24. More specifically, the diode 61 is formed on a portion of the field insulating film 24 that covers the second body region 28. The diode 61 is in contact with, for example, the field insulating film 24. Note that an insulating film other than the field insulating film 24 may be interposed between the diode 61 and the field insulating film 24.

[0049] In this embodiment, the diode 61 is made of, for example, conductive polysilicon. That is, the diode 61 is made of the same material as the gate electrode 38. Note that the diode 61 may be made of a material different from that of the gate electrode 38.

[0050] The temperature sensor 60 (diode 61) is covered together with the gate electrode 38 by the interlayer insulating layer 40. The thickness TS of the interlayer insulating layer 40 is thicker than the thickness TD of the diode 61. As shown in FIG. 5 , the thickness TD of the diode 61 is equal to the thickness TG of the gate electrode 38. More specifically, the thickness TD of the diode 61 is equal to the thickness TF of the field plate portion 38B. Here, if the difference between the thickness TD of the diode 61 and the thickness TG of the gate electrode 38 is, for example, within 10% of the thickness TD of the diode 61, then the thickness TD of the diode 61 can be said to be equal to the thickness TG of the gate electrode 38. Furthermore, if the difference between the thickness TD of the diode 61 and the thickness TF of the field plate portion 38B is, for example, within 10% of the thickness TD of the diode 61, then the thickness TD of the diode 61 can be said to be equal to the thickness TF of the field plate portion 38B.

[0051] The diode 61 includes an anode region 62A, a cathode region 62C formed at a distance from the anode region 62A, and an intermediate region 62U provided between the anode region 62A and the cathode region 62C. The anode region 62A, the cathode region 62C, and the intermediate region 62U are aligned in the Y-axis direction. It can also be said that the anode region 62A and the cathode region 62C are aligned in the Y-axis direction. In the example of FIG. 5 , the anode region 62A is positioned closer to the device side surface 12C than the intermediate region 62U. The cathode region 62C is positioned closer to the device side surface 12D than the intermediate region 62U.

[0052] The anode region 62A contains p-type impurities. That is, the anode region 62A is of the second conductivity type. In other words, the anode region 62A has the same conductivity type as the gate electrode 38. The p-type impurity concentration of the anode region 62A may be equal to the p-type impurity concentration of the gate electrode 38. The cathode region 62C contains n-type impurities. That is, the cathode region 62C is of the first conductivity type. In other words, the cathode region 62C has a different conductivity type from the gate electrode 38. The n-type impurity concentration of the cathode region 62C may be equal to the p-type impurity concentration of the anode region 62A, for example.

[0053] The p-type impurity concentration of the anode region 62A and the n-type impurity concentration of the cathode region 62C can each be changed as desired. For example, the p-type impurity concentration of the anode region 62A may be higher or lower than the p-type impurity concentration of the gate electrode 38. The n-type impurity concentration of the cathode region 62C may be higher or lower than the p-type impurity concentration of the anode region 62A.

[0054] The impurity concentration of the intermediate region 62U is lower than the impurity concentrations of the anode region 62A and the cathode region 62C. More specifically, the impurity concentration at the center of the intermediate region 62U in the Y-axis direction is lower than the impurity concentrations at both ends of the intermediate region 62U in the Y-axis direction. Of both ends of the intermediate region 62U in the Y-axis direction, the end closer to the anode region 62A contains p-type impurities. Of both ends of the intermediate region 62U in the Y-axis direction, the end closer to the cathode region 62C contains n-type impurities. The center of the intermediate region 62U in the Y-axis direction may be a region that does not contain impurities. In this way, the intermediate region 62U is configured so that the p-type impurity concentration gradually increases from the center in the Y-axis direction toward the anode region 62A, and the n-type impurity concentration gradually increases from the center in the Y-axis direction toward the cathode region 62C.

[0055] The temperature sensor 60 (diode 61) further includes an anode silicide 64A formed on the anode region 62A, and a cathode silicide 64C formed on the cathode region 62C.

[0056] The anode silicide 64A and the cathode silicide 64C are arranged spaced apart from each other in the Y-axis direction. The anode silicide 64A and the cathode silicide 64C are formed as a Si compound containing at least one of Ni, Co, and Ti.

[0057] The semiconductor device 10 further includes a plurality of anode contacts 66A electrically connected to the anode region 62A, and a plurality of cathode contacts 66C electrically connected to the cathode region 62C.

[0058] The multiple anode contacts 66A are provided at positions overlapping the anode regions 62A in plan view. Each anode contact 66A extends to penetrate the interlayer insulating layer 40 in the Z-axis direction. Each anode contact 66A is in contact with an anode silicide 64A. In this manner, each anode contact 66A is electrically connected to the anode region 62A via the anode silicide 64A. In plan view, the multiple anode contacts 66A are arranged spaced apart from one another in the Y-axis direction. The multiple anode contacts 66A are aligned with one another in the X-axis direction.

[0059] The multiple cathode contacts 66C are provided at positions overlapping the cathode regions 62C in a plan view. Each cathode contact 66C extends to penetrate the interlayer insulating layer 40 in the Z-axis direction. Each cathode contact 66C is in contact with a cathode silicide 64C. In this manner, each cathode contact 66C is electrically connected to the cathode region 62C via the cathode silicide 64C. In a plan view, the multiple cathode contacts 66C are arranged spaced apart from one another in the Y-axis direction. The multiple cathode contacts 66C are aligned with one another in the X-axis direction.

[0060] The semiconductor device 10 further includes an intermediate insulating film 68 provided between the anode silicide 64A and the cathode silicide 64C in the Y-axis direction. The intermediate insulating film 68 is made of, for example, SiO ２The intermediate insulating film 68 may be formed of a material containing SiN or SiON.

[0061] The intermediate insulating film 68 is covered by the interlayer insulating layer 40. The intermediate insulating film 68 is in contact with both the anode silicide 64A and the cathode silicide 64C. In plan view, the intermediate insulating film 68 covers the intermediate region 62U. In addition, in the example of FIG. 5 , the intermediate insulating film 68 covers both the end of the anode region 62A closer to the intermediate region 62U and the end of the cathode region 62C closer to the intermediate region 62U. That is, the length of the intermediate insulating film 68 in the Y-axis direction is longer than the length of the intermediate region 62U in the Y-axis direction. In the example of FIG. 5 , the thickness of the intermediate insulating film 68 is thicker than both the anode silicide 64A and the cathode silicide 64C. Meanwhile, the thickness of the intermediate insulating film 68 is thinner than both the anode region 62A and the cathode region 62C. The thickness of the intermediate insulating film 68 can be changed as desired.

[0062] The semiconductor device 10 includes an anode wiring 70 and a cathode wiring 72 formed on the interlayer insulating layer 40. The anode wiring 70 is connected to each anode contact 66A. That is, the anode wiring 70 is electrically connected to the anode region 62A via each anode contact 66A. The cathode wiring 72 is connected to each cathode contact 66C. That is, the cathode wiring 72 is electrically connected to the cathode region 62C via each cathode contact 66C. The anode wiring 70 and the cathode wiring 72 are formed of the same material as the source wiring 42, the drain wiring 44, and the gate wiring 46, for example.

[0063] Fig. 6 shows an enlarged structure of the central portion in the X-axis direction and the Y-axis direction of the semiconductor device 10 in Fig. 1. For convenience, the anode silicide 64A, the cathode silicide 64C, and the intermediate insulating film 68 are omitted from Fig. 6.

[0064] In a plan view, the temperature sensor 60 is formed in the center of the semiconductor device 10 in the X-axis direction and the Y-axis direction. It can also be said that the temperature sensor 60 (diode 61) is formed in the center of the cell region 16 in the X-axis direction and the Y-axis direction in a plan view. In a plan view, the temperature sensor 60 (diode 61) is formed in the second body region 28. In a plan view, it can also be said that the temperature sensor 60 (diode 61) is formed in a position overlapping the second body region 28. In this embodiment, the temperature sensor 60 (diode 61) is formed on a field insulating film 24 that is provided in a position overlapping the second body region 28 in a plan view. Therefore, in a plan view, the temperature sensor 60 (diode 61) is disposed closer to the drain region 34 than to the source region 30.

[0065] The diode 61 extends in the Y-axis direction in plan view. That is, the diode 61 extends in the arrangement direction of the anode region 62A and the cathode region 62C. The length LDY of the diode 61 in the Y-axis direction is longer than the length LDX of the diode 61 in the X-axis direction.

[0066] The length LDY of the diode 61 in the Y-axis direction is shorter than the length LY of the drain region 34 in the Y-axis direction. The length LDY of the diode 61 in the Y-axis direction is longer than the length LX of the drain region 34 in the X-axis direction. The length LDY of the diode 61 in the Y-axis direction is longer than the length LBY of the body contact region 32 in the Y-axis direction. The length LDY of the diode 61 in the Y-axis direction is longer than the length LBX of the body contact region 32 in the X-axis direction. The length LDY of the diode 61 in the Y-axis direction is longer than the length LSY of the source region 30 in the Y-axis direction. The length LDY of the diode 61 in the Y-axis direction is longer than the length LSX of the source region 30 in the X-axis direction.

[0067] The length LDX of the diode 61 in the X-axis direction is shorter than the length LX of the drain region 34 in the X-axis direction. The length LDX of the diode 61 in the X-axis direction is shorter than the length LBY of the body contact region 32 in the Y-axis direction. The length LDX of the diode 61 in the X-axis direction is shorter than the length LBX of the body contact region 32 in the X-axis direction. The length LDX of the diode 61 in the X-axis direction is shorter than the length LSY of the source region 30 in the Y-axis direction. The length LDX of the diode 61 in the X-axis direction is shorter than the length LSX of the source region 30 in the X-axis direction.

[0068] 5 and 6, the length of the anode region 62A in the Y-axis direction and the length of the cathode region 62C in the Y-axis direction are each longer than the length of the intermediate region 62U in the Y-axis direction. In the example of FIGS. 5 and 6, the length of the anode region 62A in the Y-axis direction is equal to the length of the cathode region 62C in the Y-axis direction. Here, if the difference between the lengths of the anode region 62A in the Y-axis direction and the cathode region 62C in the Y-axis direction is, for example, within 10% of the length of the anode region 62A in the Y-axis direction, it can be said that the length of the anode region 62A in the Y-axis direction is equal to the length of the cathode region 62C in the Y-axis direction.

[0069] The gate electrode 38 includes an opening recess 38C formed by cutting out a portion of the field plate portion 38B in the Y-axis direction. In plan view, the opening recess 38C is formed in the center of the cell region 16 in the X-axis direction and the Y-axis direction. That is, in the example of FIG. 6 , the opening recess 38C is formed in the central gate electrode 38 in the X-axis direction among the three gate electrodes 38 arranged in the X-axis direction. The opening recess 38C is open in the X-axis direction in plan view. More specifically, in plan view, the opening recess 38C is open toward the drain region 34 adjacent to the central gate electrode 38 in the X-axis direction among the three gate electrodes 38, closer to the device side surface 12A (see FIG. 1 ). The length of the opening recess 38C in the Y-axis direction is longer than the length of the opening recess 38C in the X-axis direction.

[0070] In a plan view, at least a portion of the temperature sensor 60 is disposed within the opening recess 38C. In the example of FIG. 6 , in a plan view, the entire temperature sensor 60 is disposed within the opening recess 38C. Of both end edges of the temperature sensor 60 in the X-axis direction, the edge closer to the device side surface 12A is aligned in the X-axis direction with the edge of both end edges of the gate electrode 38 in the X-axis direction closer to the device side surface 12A. The temperature sensor 60 is disposed at a distance from the gate electrode 38. Both the temperature sensor 60 and the gate electrode 38 are covered by the interlayer insulating layer 40. Therefore, the interlayer insulating layer 40 is provided between the temperature sensor 60 and the gate electrode 38. Here, the interlayer insulating layer 40 corresponds to an "insulating layer."

[0071] (Function) For example, in the semiconductor layer 22, if a temperature sensor is formed in a region different from the cell region 16, an element isolation portion is provided between the region where the temperature sensor is formed and the cell region 16. For this reason, it is necessary to increase the area of ​​the surface 22s of the semiconductor layer 22 in a plan view by the area of ​​the region where the temperature sensor is formed and the region where the element isolation portion is formed.

[0072] In this regard, in this embodiment, the temperature sensor 60 is formed on the field insulating film 24 formed between the source region 30 and the drain region 34 in the X-axis direction on the surface 22s of the semiconductor layer 22. In other words, the temperature sensor 60 is formed within the cell region 16. This eliminates the need for both a region where the temperature sensor is formed and a region where the element isolation portion is formed, separate from the cell region 16, thereby preventing the area of ​​the surface 22s of the semiconductor layer 22 from increasing in plan view.

[0073] (Effects) The semiconductor device 10 of this embodiment has the following effects: (1-1) The semiconductor device 10 includes an n-type semiconductor layer 22 having a surface 22 s, an n-type first body region 26 formed in the surface 22 s of the semiconductor layer 22, a p-type source region 30 formed in the first body region 26 and spaced inward from an outer edge 26A of the first body region 26, a p-type drain region 34 formed in the surface 22 s of the semiconductor layer 22 and spaced apart from the first body region 26 in a first direction (X-axis direction) orthogonal to the thickness direction (Z-axis direction) of the semiconductor layer 22, a field insulating film 24 formed on a portion of the surface 22 s of the semiconductor layer 22 between the source region 30 and the drain region 34 in the X-axis direction, a gate insulating film 36 formed on a portion of the surface 22 s of the semiconductor layer 22 between the field insulating film 24 and the drain region 34 in the X-axis direction, a gate electrode 38 formed on the gate insulating film 36, and a temperature sensor 60 formed on the field insulating film 24.

[0074] With this configuration, the temperature sensor 60 is formed on the field insulating film 24, so that the temperature sensor 60 can be formed in the cell region 16, which is the region where the transistor is formed, without providing element isolation. Compared to when the temperature sensor 60 is disposed in a region separate from the cell region 16, the area of ​​the surface 22s of the semiconductor layer 22 in a plan view can be prevented from increasing. Therefore, the size of the semiconductor device 10 can be prevented from increasing.

[0075] Since the temperature sensor 60 is disposed between the source region 30 and the drain region 34 in a plan view, it is possible to directly detect the temperature of the cell region 16. Therefore, it is possible to accurately detect the temperature of the transistor. Furthermore, since the temperature sensor 60 can be disposed near the transistor, it is possible to quickly detect temperature changes of the transistor.

[0076] (1-2) The temperature sensor 60 includes a diode 61. The diode 61 is made of conductive polysilicon. The gate electrode 38 is made of conductive polysilicon.

[0077] According to this configuration, since the gate electrode 38 and the diode 61 are formed from the same material, the diode 61 can be formed in the process of forming the gate electrode 38. Therefore, the manufacturing process of the semiconductor device 10 can be simplified, and the manufacturing cost of the semiconductor device 10 can be reduced.

[0078] (1-3) The length LDY of the diode 61 in the Y-axis direction is longer than the length LDX of the diode 61 in the X-axis direction. With this configuration, it is easier to secure an area for forming the diode 61 in the Y-axis direction, which is orthogonal to the X-axis direction in plan view, than in the X-axis direction, which is the arrangement direction of the source regions 30 and the drain regions 34. Therefore, the diode 61 can be easily formed on the field insulating film 24.

[0079] (1-4) The diode 61 includes an anode region 62A and a cathode region 62C. The anode region 62A and the cathode region 62C are arranged in the Y-axis direction. With this configuration, the anode region 62A and the cathode region 62C are arranged in the Y-axis direction, so that the anode region 62A and the cathode region 62C can be easily formed in the diode 61 formed to extend in the Y-axis direction.

[0080] (1-5) The semiconductor device 10 further includes a plurality of anode contacts 66A electrically connected to the anode region 62A, and a plurality of cathode contacts 66C electrically connected to the cathode region 62C. The plurality of anode contacts 66A are arranged at intervals in the Y-axis direction, and the plurality of cathode contacts 66C are arranged at intervals in the Y-axis direction.

[0081] With this configuration, in the diode 61 formed to extend in the Y-axis direction, both the anode region 62A and the cathode region 62C can be formed long in the Y-axis direction. Therefore, each anode contact 66A can be easily positioned to overlap the anode region 62A long in the Y-axis direction in a planar view. Each cathode contact 66C can be easily positioned to overlap the cathode region 62C long in the Y-axis direction in a planar view.

[0082] (1-6) For example, unless at least one of the channel region between the source region 30 and the drain region 34 and the region in the second body region 28 where the field insulating film 24 for arranging the temperature sensor 60 is formed is made large, the temperature sensor 60 cannot be arranged closer to the source region 30 than the drain region 34. For this reason, if an attempt is made to arrange the temperature sensor 60 closer to the source region 30 than the drain region 34, the size of the semiconductor device 10 will increase.

[0083] In this regard, in the present embodiment, in plan view, the temperature sensor 60 is disposed closer to the drain region 34 than to the source region 30. This eliminates the need to enlarge at least one of the channel region between the source region 30 and the drain region 34 and the region in the second body region 28 where the field insulating film 24 for disposing the temperature sensor 60 is formed, thereby preventing the semiconductor device 10 from becoming larger.

[0084] (1-7) The gate electrode 38 includes a field plate portion 38B formed on the field insulating film 24. In a plan view, the field plate portion 38B includes an opening recess 38C that opens toward the drain region 34. In a plan view, at least a portion of the temperature sensor 60 is disposed within the opening recess 38C.

[0085] According to this configuration, the temperature sensor 60 is disposed so as to overlap the gate electrode 38 in both the X-axis direction and the Y-axis direction in a plan view. Therefore, by separating the temperature sensor 60 from the gate electrode 38 in the X-axis direction, the semiconductor layer 22 can be made smaller in size in the X-axis direction compared to a configuration in which the temperature sensor 60 is disposed at a position that does not overlap the gate electrode 38 when viewed in the Y-axis direction. Therefore, the semiconductor device 10 can be made smaller.

[0086] (1-8) An interlayer insulating layer 40 is provided between the temperature sensor 60 and the gate electrode 38. With this configuration, the interlayer insulating layer 40 can insulate the temperature sensor 60 from the gate electrode 38.

[0087] (1-9) The thickness TD of the diode 61 is equal to the thickness TG of the gate electrode 38. According to this configuration, when the diode 61 is formed in the step of forming the gate electrode 38, the thickness TD of the diode 61 does not need to be changed relative to the thickness TG of the gate electrode 38, and therefore the diode 61 can be easily formed.

[0088] (1-10) The anode wiring 70 and the cathode wiring 72 are formed from the same material as the source wiring 42, the drain wiring 44, and the gate wiring 46. With this configuration, the anode wiring 70, the cathode wiring 72, the source wiring 42, the drain wiring 44, and the gate wiring 46 formed on the interlayer insulating layer 40 can be formed, for example, by etching a common metal layer. Therefore, the anode wiring 70, the cathode wiring 72, the source wiring 42, the drain wiring 44, and the gate wiring 46 can be easily formed.

[0089] Second Embodiment A semiconductor device 100 according to a second embodiment will be described with reference to FIGS. 7 to 10 . FIGS. 7 to 10 show a portion of the semiconductor device 100 that constitutes a temperature sensor 170. The semiconductor device 100 includes a plurality of first MOS regions 120 and a plurality of second MOS regions 130. Each of the first MOS regions 120 and each of the second MOS regions 130 are formed within a region of the semiconductor device 100 in which a transistor is formed. Note that FIG. 7 shows one first MOS region 120 and one second MOS region 130 as the portion that constitutes the temperature sensor 170. The first MOS region 120 and the first gate electrode 152 constitute an n-channel MOSFET. The second MOS region 130 and the second gate electrode 154 constitute a p-channel MOSFET. The temperature sensor 170 can be constructed using the first MOS region 120, the second MOS region 130, the first gate electrode 152, and the second gate electrode 154 formed in the semiconductor device 100. The area where the temperature sensor 170 is formed will be described in detail below.

[0090] 8, the semiconductor device 100 of the second embodiment includes a p-type semiconductor substrate 110 and an n-type semiconductor layer 112 formed on the semiconductor substrate 110. The semiconductor substrate 110 and the semiconductor layer 112 have the same configuration as the semiconductor substrate 20 and the semiconductor layer 22 of the first embodiment (see FIG. 3). The semiconductor layer 112 includes a surface 112s.

[0091] 7, the semiconductor device 100 includes a complementary metal oxide semiconductor (CMOS) structure including an n-channel first MOS region 120 and a p-channel second MOS region 130. The semiconductor device 100 further includes an element isolation portion 140 that separates the first MOS region 120 from the second MOS region 130.

[0092] Each of the first MOS region 120 and the second MOS region 130 is a region in which a MOSFET is formed, and is formed on the surface 112s of the semiconductor layer 112 (see FIG. 8 for both). The first MOS region 120 and the second MOS region 130 are arranged spaced apart from each other in the X-axis direction. At least a portion of the element isolation portion 140 is formed between the first MOS region 120 and the second MOS region 130 in the X-axis direction.

[0093] 9 , the first MOS region 120 includes an n-type first well region 122, and a p-type first source region 124 and a p-type first drain region 126 formed on the surface of the first well region 122. The first source region 124 and the first drain region 126 are arranged spaced apart from each other in the Y-axis direction. That is, the first source region 124 and the first drain region 126 are arranged in a direction perpendicular to the arrangement direction of the first MOS region 120 and the second MOS region 130 in a plan view.

[0094] The n-type impurity concentration of the first well region 122 is higher than the n-type impurity concentration of the semiconductor layer 112. The p-type impurity concentrations of both the first source region 124 and the first drain region 126 are higher than the n-type impurity concentration of the first well region 122. In one example, the n-type impurity concentration of the first well region 122 is, for example, 1×10 １７ cm －３ 1x10 or more１８ cm －３ The p-type impurity concentration of the first source region 124 and the first drain region 126 is, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ The following is the result.

[0095] 10 , the second MOS region 130 includes a p-type second well region 132, and an n-type second source region 134 and an n-type second drain region 136 formed on the surface of the second well region 132. The second source region 134 and the second drain region 136 are arranged spaced apart from each other in the Y-axis direction. That is, the second source region 134 and the second drain region 136 are arranged in a direction perpendicular to the arrangement direction of the first MOS region 120 and the second MOS region 130 in a plan view.

[0096] The p-type impurity concentration of the second well region 132 is higher than the n-type impurity concentration of the semiconductor layer 112. The n-type impurity concentrations of both the second source region 134 and the second drain region 136 are higher than the p-type impurity concentration of the second well region 132. In one example, the p-type impurity concentration of the second well region 132 is, for example, 1×10 １７ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the second source region 134 and the second drain region 136 is, for example, 1×10 １９ cm －３ 5x10 or more ２１ cm －３ The following is the result.

[0097] 7, the element isolation portion 140 is formed so as to surround each of the first MOS region 120 and the second MOS region 130. As shown in FIG. 8, the element isolation portion 140 includes a field insulating film 142. The field insulating film 142 is formed of, for example, a LOCOS film. The field insulating film 142 is also formed on the periphery of the first MOS region 120 and the periphery of the second MOS region 130. The field insulating film 142 includes an intermediate insulating film 144 formed between the first MOS region 120 and the second MOS region 130 in the X-axis direction. The intermediate insulating film 144 extends along the Y-axis direction.

[0098] 7 , a gate electrode 150 is formed in the center of the first MOS region 120 and the second MOS region 130 in the Y-axis direction, extending in the X-axis direction so as to straddle both the first MOS region 120 and the second MOS region 130. The gate electrode 150 extends in the X-axis direction so as to straddle the intermediate insulating film 144.

[0099] 8, the gate electrode 150 includes a first gate electrode 152 formed on the first MOS region 120, a second gate electrode 154 formed on the second MOS region 130, and a third gate electrode 156 formed on the element isolation portion 140. The gate electrode 150 is formed of, for example, conductive polysilicon.

[0100] A gate insulating film 158 is interposed between the first MOS region 120 and the first gate electrode 152 in the Z-axis direction, and between the second MOS region 130 and the second gate electrode 154 in the Z-axis direction. The gate insulating film 158 is made of, for example, SiO ２ In other words, it can be said that both the first gate electrode 152 and the second gate electrode 154 are formed on the gate insulating film 158. The first gate electrode 152 contains p-type impurities, and the second gate electrode 154 contains n-type impurities.

[0101] The third gate electrode 156 is formed on the intermediate insulating film 144. The impurity concentration of the third gate electrode 156 is lower than the p-type impurity concentration of the first gate electrode 152 and the n-type impurity concentration of the second gate electrode 154. More specifically, the impurity concentration at the center of the third gate electrode 156 in the X-axis direction is lower than the impurity concentrations at both ends of the third gate electrode 156 in the X-axis direction. Of both ends of the third gate electrode 156 in the X-axis direction, the end closer to the first gate electrode 152 contains p-type impurities. Of both ends of the third gate electrode 156 in the X-axis direction, the end closer to the second gate electrode 154 contains n-type impurities. The center of the third gate electrode 156 in the X-axis direction may be a region that does not contain impurities. In this way, the third gate electrode 156 is configured so that the p-type impurity concentration gradually increases from the center in the X-axis direction toward the first gate electrode 152, and the n-type impurity concentration gradually increases from the center in the X-axis direction toward the second gate electrode 154.

[0102] In this way, the gate electrode 150 is formed on the gate insulating film 158 and the field insulating film 142 (intermediate insulating film 144). In other words, it can be said that the gate electrode 150 is formed on an insulating film formed on the surface 112s of the semiconductor layer 112. Here, in this embodiment, both the gate insulating film 158 and the field insulating film 142 correspond to the "insulating film."

[0103] A first silicide 152A is formed on the first gate electrode 152. A second silicide 154A is formed on the second gate electrode 154. An insulating film 160 is formed on the third gate electrode 156. The insulating film 160 is in contact with both the first silicide 152A and the second silicide 154A. The insulating film 160 insulates the first silicide 152A and the second silicide 154A from each other.

[0104] The semiconductor device 100 further includes an interlayer insulating layer 162, a first source contact 164A, a second source contact 164B, a first drain contact 166A, a second drain contact 166B, an anode contact 168A, and a cathode contact 168C.

[0105] The interlayer insulating layer 162 is formed on the surface 112s of the semiconductor layer 112 so as to cover the field insulating film 142 and the gate electrode 150. The interlayer insulating layer 162 also covers the first silicide 152A, the second silicide 154A, and the insulating film 160. The interlayer insulating layer 162 has a configuration similar to that of the interlayer insulating layer 40 of the first embodiment.

[0106] 9 , both the first source contact 164A and the first drain contact 166A are provided so as to penetrate the interlayer insulating layer 162 in the Z-axis direction. Both the first source contact 164A and the first drain contact 166A extend in the Z-axis direction. A plurality of first source contacts 164A are provided. The plurality of first source contacts 164A are provided at positions overlapping with the first source regions 124 in a plan view. The plurality of first source contacts 164A are arranged at intervals in the X-axis direction. A plurality of first drain contacts 166A are provided. The plurality of first drain contacts 166A are provided at positions overlapping with the first drain regions 126 in a plan view. The plurality of first drain contacts 166A are arranged at intervals in the X-axis direction.

[0107] 10 , both the second source contact 164B and the second drain contact 166B are provided so as to penetrate the interlayer insulating layer 162 in the Z-axis direction. Both the second source contact 164B and the second drain contact 166B extend in the Z-axis direction. A plurality of second source contacts 164B are provided. The plurality of second source contacts 164B are provided at positions overlapping with the second source region 134 in a plan view. The plurality of second source contacts 164B are arranged at intervals in the X-axis direction. A plurality of second drain contacts 166B are provided. The plurality of second drain contacts 166B are provided at positions overlapping with the second drain region 136 in a plan view. The plurality of second drain contacts 166B are arranged at intervals in the X-axis direction.

[0108] 8, both the anode contact 168A and the cathode contact 168C are provided so as to penetrate the interlayer insulating layer 162 in the Z-axis direction. Both the anode contact 168A and the cathode contact 168C extend in the Z-axis direction.

[0109] The anode contact 168A is disposed at a position overlapping one of both ends of the gate electrode 150 in the X-axis direction that is closer to the first MOS region 120 in plan view. The anode contact 168A is in contact with the first silicide 152A. As a result, the anode contact 168A is electrically connected to the first gate electrode 152 via the first silicide 152A.

[0110] The cathode contact 168C is disposed at a position overlapping one of both ends of the gate electrode 150 in the X-axis direction that is closer to the second MOS region 130 in plan view. The cathode contact 168C is in contact with the second silicide 154A. As a result, the cathode contact 168C is electrically connected to the second gate electrode 154 via the second silicide 154A.

[0111] 8 to 10, the source contacts 164A, 164B, the drain contacts 166A, 166B, the anode contact 168A, and the cathode contact 168C are formed of, for example, tungsten (W). Note that the source contacts 164A, 164B, the drain contacts 166A, 166B, the anode contact 168A, and the cathode contact 168C are not limited to tungsten (W) and can be changed as desired.

[0112] As described above, the gate electrode 150 includes a p-type first gate electrode 152, an n-type second gate electrode 154, and a third gate electrode 156. In this manner, a diode 171 is configured. An anode contact 168A and a cathode contact 168C are provided on both ends of the gate electrode 150 in the X-axis direction. This gate electrode 150 configures a temperature sensor 170.

[0113] (Effects) The semiconductor device 100 of this embodiment has the following effects: (2-1) The semiconductor device 100 includes a semiconductor layer 112 having a surface 112s, an n-channel first MOS region 120 and a p-channel second MOS region 130 formed on the surface 112s of the semiconductor layer 112, an element isolation part 140 including a field insulating film 142 formed on the surface 112s of the semiconductor layer 112 and isolating the first MOS region 120 and the second MOS region 130, and a temperature sensor 170 formed on the field insulating film 142 (intermediate insulating film 144) and the gate insulating film 158.

[0114] According to this configuration, the gate electrode 150 constitutes the temperature sensor 170, so that the temperature sensor 170 can be disposed in the region of the semiconductor device 100 where the transistors are formed, without providing separate element isolation. Therefore, compared to a case where the temperature sensor is provided in a region other than the region where the transistors are formed, the area of ​​the surface 112s of the semiconductor layer 112 in a plan view can be prevented from increasing. Therefore, the size of the semiconductor device 100 can be prevented from increasing.

[0115] (2-2) The semiconductor device 100 includes a gate electrode 150 that extends across the first MOS region 120 and the second MOS region 130. The gate electrode 150 forms a temperature sensor 170.

[0116] With this configuration, the gate electrode 150 constitutes the temperature sensor 170, and therefore the first MOS region 120, the second MOS region 130, and the gate electrode 150 in the region where the transistor is formed in the semiconductor device 100 can have a common configuration. Compared to a case where the temperature sensor 170 has a different configuration from the gate electrode 150, the configuration of the semiconductor device 100 can be simplified.

[0117] <Modifications> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0118] In the first embodiment, the number of temperature sensors 60 can be changed arbitrarily. A plurality of temperature sensors 60 may be provided. In one example, as shown in FIG. 11 , the semiconductor device 10 may include six temperature sensors 60. The six temperature sensors 60 are arranged relative to the central gate electrode 38 in the X-axis direction among the three gate electrodes 38. More specifically, three temperature sensors 60 are arranged at each end in the X-axis direction of the central gate electrode 38 in the X-axis direction. The three temperature sensors 60 are aligned with each other in the X-axis direction but spaced apart from each other in the Y-axis direction. This configuration allows accurate detection of the temperature at the center of the cell region 16 in the X-axis direction.

[0119] Alternatively, multiple temperature sensors 60 may be arranged for all three gate electrodes 38. In this case, multiple temperature sensors 60 may be arranged at intervals in the Y-axis direction for each gate electrode 38. With this configuration, temperatures at various locations in the cell region 16 can be detected.

[0120] Furthermore, each anode contact 66A and each cathode contact 66C electrically connected to the temperature sensor 60 corresponding to the location in the cell region 16 where the temperature is to be detected may be selectively connected by wiring formed on the interlayer insulating layer 40. With this configuration, the location in the cell region 16 where the temperature is to be detected can be easily set.

[0121] In the first embodiment, the thickness TD of the diode 61 may be different from the thickness TG of the gate electrode 38. In the first embodiment, the length LDX of the diode 61 in the X-axis direction may be equal to or greater than the length LDY of the diode 61 in the Y-axis direction.

[0122] In the first embodiment, the anode region 62A and the cathode region 62C may be disposed apart from each other in the X-axis direction. In the first embodiment, the intermediate insulating film 68 may be omitted. In this case, the interlayer insulating layer 40 is interposed between the anode silicide 64A and the cathode silicide 64C.

[0123] In the first embodiment, the intermediate region 62U may be omitted from the diode 61. In the first embodiment, the position of the temperature sensor 60 may be changed as desired. For example, the temperature sensor 60 may be disposed in a position that does not overlap with the drain region 34 when viewed from the X-axis direction, for example, closer to the device side surface 12C or closer to the device side surface 12D than the drain region 34.

[0124] In another example, the temperature sensor 60 may be positioned at a position that does not overlap with the second body region 28 when viewed from the X-axis direction, for example, at a position closer to the device side surface 12C or closer to the device side surface 12D than the second body region 28.

[0125] In another example, the temperature sensor 60 may be positioned at a position that does not overlap with the first body region 26 when viewed from the X-axis direction, for example, at a position closer to the device side surface 12C or closer to the device side surface 12D than the first body region 26.

[0126] In another example, the temperature sensor 60 may be disposed somewhere other than between the drain region 34 and the source region 30. For example, the temperature sensor 60 may be disposed on the field insulating film 24 provided between the guard ring 48 and the second body region 28 adjacent to the guard ring 48 in the X-axis direction.

[0127] In the first embodiment, the second body region 28 may be omitted. In the first embodiment, as shown in FIG. 12 , the length of the second body region 28 in the X-axis direction may be the same as the length of the first body region 26 in the X-axis direction. Accordingly, the length of the field insulating film 24 formed between the source region 30 and the drain region 34 in the X-axis direction becomes shorter. Therefore, in the region where the temperature sensor 60 is formed, the gate electrode 38 does not need to have a field plate portion 38B formed therein.

[0128] In the second embodiment, the semiconductor device 100 may include a temperature sensor 170 separate from the gate electrode 150. That is, the temperature sensor 170 may be disposed apart from the gate electrode 150. In this case, the temperature sensor 170 includes, for example, a diode 171. The diode 171 is disposed on the intermediate insulating film 144. The diode 171 extends, for example, in the Y-axis direction. Like the gate electrode 150, the diode 171 is formed of conductive polysilicon. This configuration also prevents the semiconductor device 100 from becoming larger. Furthermore, because the diode 171 and the gate electrode 150 are formed of the same material, the diode 171 can be formed during the process of forming the gate electrode 150. This simplifies the manufacturing process of the semiconductor device 100, thereby reducing the manufacturing cost of the semiconductor device 100.

[0129] As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." The term "on" as used in this disclosure includes the meanings "on" and "above," unless the context clearly indicates otherwise. Thus, the expression "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0130] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "forward," "rearward," "sideways," "left," "right," "front," "rear," etc., used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0131] <Supplementary Notes> The technical ideas that can be understood from the above-described embodiments and modified examples are described below. Note that, for the purpose of aiding understanding and not intending to limit the scope of the invention, the corresponding reference numerals in the embodiments are shown in parentheses for the configurations described in the Supplementary Notes. The reference numerals are shown as examples to aid understanding, and the components described with the reference numerals should not be limited to the components indicated by the reference numerals.

[0132] (Supplementary Note 1) A semiconductor layer (22) of a first conductivity type having a surface (22s), a body region (26) of the first conductivity type formed on the surface (22s) of the semiconductor layer (22), a source region (30) of a second conductivity type formed in the body region (26) and spaced apart inward from an outer edge (26A) of the body region (26), a drain region (34) of a second conductivity type formed on the surface (22s) of the semiconductor layer (22) and spaced apart from the body region (26) in a first direction (X-axis direction) perpendicular to a thickness direction (Z-axis direction) of the semiconductor layer (22), and a field insulating film (24) formed on a portion of the surface (22s) of the semiconductor layer (22) between the source region (30) and the drain region (34) in the first direction (X-axis direction), a gate insulating film (36) formed on a portion of the surface (22s) of the semiconductor layer (22) between the field insulating film (24) and the drain region (34) in the first direction (X-axis direction); a gate electrode (38) formed on the gate insulating film (36); and a temperature sensor (60) formed on the field insulating film (24).

[0133] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the temperature sensor (60) includes a diode (61).

[0134] (Supplementary Note 3) The semiconductor device according to Supplementary Note 2, wherein the diode (61) is formed of conductive polysilicon.

[0135] (Supplementary Note 4) The semiconductor device according to Supplementary Note 2 or 3, wherein a direction perpendicular to both the thickness direction (Z-axis direction) of the semiconductor layer and the first direction (X-axis direction) is defined as a second direction (Y-axis direction), and the length (LDY) of the diode (61) in the second direction (Y-axis direction) is longer than the length (LDX) of the diode (61) in the first direction (X-axis direction).

[0136] (Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 2 to 4, wherein a direction perpendicular to both the thickness direction (Z-axis direction) of the semiconductor layer and the first direction (X-axis direction) is a second direction (Y-axis direction), the diode (61) includes an anode region (62A) and a cathode region (62C), and the anode region (62A) and the cathode region (62C) are arranged in the second direction (Y-axis direction).

[0137] (Supplementary Note 6) The semiconductor device according to Supplementary Note 5, further comprising: a plurality of anode contacts (66A) electrically connected to the anode region (62A); and a plurality of cathode contacts (66C) electrically connected to the cathode region (62C), wherein the plurality of anode contacts (66A) are arranged at a distance in the second direction (Y-axis direction), and the plurality of cathode contacts (66C) are arranged at a distance in the second direction (Y-axis direction).

[0138] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the temperature sensor (60) is disposed closer to the drain region (34) than to the source region (30) when viewed in the thickness direction (Z-axis direction) of the semiconductor layer (22).

[0139] (Appendix 8) The semiconductor device according to any one of Appendices 1 to 7, wherein the gate electrode (38) includes a field plate portion (38B) formed on the field insulating film (24), and when viewed in the thickness direction (Z-axis direction) of the semiconductor layer (22), the field plate portion (38B) includes an opening recess (38C) that opens toward the drain region (34), and when viewed in the thickness direction (Z-axis direction) of the semiconductor layer (22), at least a portion of the temperature sensor (60) is disposed within the opening recess (38C).

[0140] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein an insulating layer (40) is provided between the temperature sensor (60) and the gate electrode (38).

[0141] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 2 to 6, wherein a thickness (TD) of the diode (61) is equal to a thickness (TG) of the gate electrode (38).

[0142] (Supplementary Note 11) The semiconductor device according to any one of Supplementary Notes 2 to 6, wherein the diode (61) includes an anode region (62A), a cathode region (62C) formed at a distance from the anode region (62A), and an intermediate region (62U) provided between the anode region (62A) and the cathode region (62C), and the intermediate region (62U) has an impurity concentration lower than both the anode region (62A) and the cathode region (62C).

[0143] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 2 to 6, wherein the diode (61) includes an anode region (62A) of a second conductivity type, and a cathode region (62C) of a first conductivity type.

[0144] (Supplementary Note 13) The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein a plurality of the temperature sensors (60) are provided.

[0145] (Appendix 14) A semiconductor device (100) comprising: a semiconductor layer (112) having a surface (112s); an n-channel first MOS region (120) and a p-channel second MOS region (130) formed on the surface (112s) of the semiconductor layer (112); an element isolation region (140) including an insulating film (142, 144, 158) formed on the surface (112s) of the semiconductor layer (112), isolating the first MOS region (120) and the second MOS region (130); and a temperature sensor (170) formed on the insulating film (142, 144, 158).

[0146] (Supplementary Note 15) The semiconductor device according to any one of Supplementary Notes 2 to 6, wherein the diode (61) is formed from the same material as the gate electrode (38).

[0147] (Supplementary Note 16) The semiconductor device according to Supplementary Note 14, wherein the temperature sensor (170) includes a diode (171).

[0148] (Supplementary Note 17) The semiconductor device according to Supplementary Note 16, wherein the diode (171) is formed of conductive polysilicon.

[0149] (Appendix 18) The semiconductor device according to appendix 16 or 17, further comprising: a gate insulating film (158) formed on both the first MOS region (120) and the second MOS region (130) of the surface (112s) of the semiconductor layer (112); a first gate electrode (152) and a second gate electrode (154) formed on the gate insulating film (158), respectively; and a third gate electrode (156) formed on an insulating film (144) between the first MOS region (120) and the second MOS region (130), wherein the first gate electrode (152), the second gate electrode (154), and the third gate electrode (156) constitute the diode (171).

[0150] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0151] 10...Semiconductor device 12A to 12D...Device side surface 14...Element isolation portion 14A...First isolation region 14B...Second isolation region 14C...Buried layer 14D...Element isolation side contact region 16...Cell region 18...Buried layer 20...Semiconductor substrate 20s...Substrate surface 20r...Substrate back surface 22...Semiconductor layer 22s...Surface 24...Field insulating film 26...First body region 26A...Outer edge 28...Second body region 28A...Outer edge 30...Source region 32...Body contact region 34...Drain region 36...Gate insulating film 38...Gate electrode 38A...Main electrode portion 38B...Field plate portion 38C...Opening recess 39...Gate opening 40...Interlayer insulating layer 42...Source wiring 42A...Source contact portion 44...Drain wiring 44A...Drain contact portion 46...Gate wiring 46A...Gate contact portion 47...Gate silicide 48...Guard ring 50...First ring region 52...Second ring region 54...Ring side contact region 60...Temperature sensor 61...Diode 62A...Anode region 62C...Cathode region 62U...Intermediate region 64A...Anode silicide 64C...Cathode silicide 66A...Anode contact 66C...Cathode contact 68...Intermediate insulating film 70...Anode wiring 72...Cathode wiring 100...Semiconductor device 110...Semiconductor substrate 112...Semiconductor layer 112s...Surface 120...First MOS region 122...First well region 124...First source region 126...First drain region 130...Second MOS region 132...Second well region 134...Second source region 136...Second drain region 140: element isolation portion 142: field insulating film 144: intermediate insulating film 150: gate electrode 152: first gate electrode 152A: first silicide 154: second gate electrode 154A: second silicide 156: third gate electrode 158: gate insulating film 160: insulating film 162: interlayer insulating layer 164A: first source contact 164B: second source contact 166A: first drain contact 166B: second drain contact 168A: anode contact168C...Cathode contact 170...Temperature sensor 171...Diode TD...Thickness of diode TG...Thickness of gate electrode TF...Thickness of field plate portion TS...Thickness of interlayer insulating layer LX...Length of drain region LY...Length of drain region LDX...Length of diode LDY...Length of diode LBX...Length of body contact region LBY...Length of body contact region LSX...Length of source region LSY...Length of source region

Claims

1. a semiconductor layer of a first conductivity type having a surface; a body region of a first conductivity type formed on the surface of the semiconductor layer; a source region of a second conductivity type formed in the body region and spaced apart from an outer edge of the body region; a drain region of a second conductivity type formed on the surface of the semiconductor layer and spaced apart from the body region in a first direction perpendicular to a thickness direction of the semiconductor layer; a field insulating film formed on a portion of the surface of the semiconductor layer between the source region and the drain region in the first direction; a gate insulating film formed on a portion of the surface of the semiconductor layer between the field insulating film and the drain region in the first direction; a gate electrode formed on the gate insulating film; a temperature sensor formed on the field insulating film; A semiconductor device comprising:

2. The temperature sensor includes a diode. The semiconductor device according to claim 1 .

3. The diode is formed from conductive polysilicon. The semiconductor device according to claim 2 .

4. A direction perpendicular to both the thickness direction of the semiconductor layer and the first direction is defined as a second direction, The length of the diode in the second direction is longer than the length of the diode in the first direction. The semiconductor device according to claim 2 .

5. A direction perpendicular to both the thickness direction of the semiconductor layer and the first direction is defined as a second direction, the diode includes an anode region and a cathode region; The anode regions and the cathode regions are aligned in the second direction. The semiconductor device according to claim 4.

6. a plurality of anode contacts electrically connected to the anode region; a plurality of cathode contacts electrically connected to the cathode region; Further equipped with The plurality of anode contacts are arranged at intervals in the second direction, The plurality of cathode contacts are arranged at intervals in the second direction. The semiconductor device according to claim 5 .

7. When viewed in a thickness direction of the semiconductor layer, the temperature sensor is disposed closer to the drain region than to the source region. The semiconductor device according to claim 1 .

8. the gate electrode includes a field plate portion formed on the field insulating film, When viewed in a thickness direction of the semiconductor layer, the field plate portion includes an opening recess that opens toward the drain region, When viewed from a thickness direction of the semiconductor layer, at least a portion of the temperature sensor is disposed within the open recess. The semiconductor device according to claim 1 .

9. An insulating layer is provided between the temperature sensor and the gate electrode. The semiconductor device according to claim 1 .

10. The thickness of the diode is equal to the thickness of the gate electrode. The semiconductor device according to claim 2 .

11. The diode is an anode region; a cathode region formed spaced apart from the anode region; an intermediate region provided between the anode region and the cathode region; Including, The impurity concentration of the intermediate region is lower than both the anode region and the cathode region. The semiconductor device according to claim 2 .

12. The diode is an anode region of a second conductivity type; a cathode region of a first conductivity type; Includes The semiconductor device according to claim 2 .

13. The temperature sensor is provided in plurality. The semiconductor device according to claim 1 .

14. a semiconductor layer having a surface; a first MOS region of an n-channel type and a second MOS region of a p-channel type formed on the surface of the semiconductor layer; an isolation region including an insulating film formed on the surface of the semiconductor layer, the isolation region isolating the first MOS region and the second MOS region; a temperature sensor formed on the insulating film; Equipped Semiconductor device.