Semiconductor device

Abstract

This semiconductor device comprises: a first semiconductor element having a first electrode and a second electrode; first wiring conductively connected to the first electrode; and second wiring conductively connected to the second electrode. The direction of the current that flows through the second wiring is the opposite of the direction of the current that flows through the first wiring. Viewed from a first direction, the first wiring overlaps with the second wiring. The distance between the first wiring and the second wiring in the first direction is shorter than a first dimension of the first wiring in a direction orthogonal to both the first direction and the direction in which the current flows in the first wiring.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses an example of a semiconductor device including a lateral-structure semiconductor element (HEMT). The semiconductor element has a first electrode and a second electrode. In this semiconductor device, the semiconductor element is bonded to a die pad. The first electrode and the second electrode are electrically connected to a plurality of terminal leads located around the die pad via wires.

[0003] In the semiconductor device disclosed in Patent Document 1, transmission of high-frequency electrical signals is sometimes required to achieve more efficient power conversion, and to achieve this, it is necessary to reduce parasitic inductance in the wiring that serves as the transmission path for the electrical signals.

[0004] Japanese Patent Application Laid-Open No. 2020-188085

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce parasitic inductance in wiring.

[0006] A semiconductor device according to one aspect of the present disclosure includes a first semiconductor element having a first electrode and a second electrode, a first wiring electrically connected to the first electrode, and a second wiring electrically connected to the second electrode. A direction of current flowing through the second wiring is opposite to a direction of current flowing through the first wiring, and the first wiring overlaps the second wiring as viewed in a first direction. A distance between the first wiring and the second wiring in the first direction is shorter than a first dimension of the first wiring in a direction perpendicular to the first direction and the direction of current flow in the first wiring.

[0007] According to the above configuration, it is possible to reduce the parasitic inductance in the wiring.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view corresponding to FIG. 1, omitting the fourth insulating layer, the plurality of first vias, the plurality of second vias, and the plurality of heat dissipation layers. FIG. 3 is a plan view corresponding to FIG. 2, omitting the third insulating layer and the plurality of intermediate layers. FIG. 4 is a plan view corresponding to FIG. 3, omitting the second insulating layer and showing the first semiconductor element, the second semiconductor element, and the IC. FIG. 5 is a bottom view of the semiconductor device shown in FIG. 1, showing the coating layer. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 4. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 4. FIG. 11 is a partially enlarged view of FIG. 4. 12 is a cross-sectional view taken along line XII-XII in FIG. 11 . FIG. 13 is a cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 14 is a cross-sectional view of the semiconductor device shown in FIG. 13 , but the cross-sectional position is different from that of FIG. 13 . FIG. 15 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 13 . FIG. 16 is a plan view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 16 . FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 16 . FIG. 20 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20 . FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20 . FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 20 .

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] 1 to 12 , a semiconductor device A10 according to a first embodiment of the present disclosure will be described. The semiconductor device A10 includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a first wiring 21, a second wiring 22, a third wiring 23, a fourth wiring 24, a plurality of power wirings 25, a plurality of control wirings 26, a plurality of interconnect wirings 29, a first semiconductor element 31, a second semiconductor element 32, an IC 33, and a plurality of connection wirings 39. The semiconductor device A10 further includes a plurality of first vias 41, a plurality of second vias 42, a plurality of third vias 43, a plurality of fourth vias 44, a plurality of fifth vias 45, a plurality of terminals 51, a coating layer 52, a plurality of heat dissipation layers 61, and a plurality of intermediate layers 62. The semiconductor device A10 is a resin package that is surface-mounted on a wiring substrate.

[0012] For ease of understanding, FIG. 2 omits the fourth insulating layer 14, the plurality of first vias 41, the plurality of second vias 42, and the plurality of heat dissipation layers 61. For ease of understanding, FIG. 3 omits the third insulating layer 13 and the plurality of intermediate layers 62 compared to FIG. 2. For ease of understanding, FIG. 4 omits the second insulating layer 12 compared to FIG. 3 and shows the first semiconductor element 31, the second semiconductor element 32, and the IC 33 in a transparent manner. In FIG. 4, the transparent first semiconductor element 31, the second semiconductor element 32, and the IC 33 are shown with imaginary lines (two-dot chain lines). For ease of understanding, FIG. 5 shows the collapsed covering layer 52. In FIG. 5, the transparent covering layer 52 is shown with imaginary lines.

[0013] In describing the semiconductor device A10, for convenience, an example of a normal direction to a top surface 141 of a fourth insulating layer 14 (described later) will be referred to as the "first direction z." An example of a direction perpendicular to the first direction z will be referred to as the "second direction x." An example of a direction perpendicular to the first direction z and the second direction x will be referred to as the "third direction y." As shown in FIG. 1 , the semiconductor device A10 has a rectangular shape when viewed in the first direction z.

[0014] The semiconductor device A10 converts DC power supplied to the semiconductor device A10 from an external source into AC power using a first semiconductor element 31 and a second semiconductor element 32. The semiconductor device A10 is used, for example, in an inverter for driving a motor. The semiconductor device A10 can be formed, for example, by the laser direct structuring (LDS) method disclosed in U.S. Patent Application Publication No. 2010 / 0019370.

[0015] 9 and 12 , the first insulating layer 11 is located between the first wiring 21 and the second wiring 22 in the first direction z. The first insulating layer 11 contains resin. The first insulating layer 11 has a bottom surface 111 facing the first direction z. When the semiconductor device A10 is mounted on a wiring substrate, the bottom surface 111 faces the wiring substrate.

[0016] 6 to 8 , the second insulating layer 12 is located between the first semiconductor element 31, the second semiconductor element 32, and the IC 33 and the first insulating layer 11 in the first direction z. The second insulating layer 12 is in contact with the first insulating layer 11. The composition of the second insulating layer 12 is the same as the composition of the first insulating layer 11.

[0017] 6 to 10 , the third insulating layer 13 is located on the opposite side of the second insulating layer 12 from the first insulating layer 11 in the first direction z. The third insulating layer 13 is in contact with the second insulating layer 12. The composition of the third insulating layer 13 is the same as the composition of the first insulating layer 11.

[0018] 6 to 10 , the fourth insulating layer 14 is located on the opposite side of the second insulating layer 12 with respect to the third insulating layer 13 in the first direction z. The fourth insulating layer 14 is in contact with the third insulating layer 13. The composition of the fourth insulating layer 14 is the same as the composition of the first insulating layer 11. The fourth insulating layer 14 has a top surface 141 facing the opposite side to the bottom surface 111 in the first direction z.

[0019] As shown in FIGS. 6, 7, and 9, the first semiconductor element 31 faces the second insulating layer 12. At least a portion of the second semiconductor element 32 is covered with the third insulating layer 13. The first semiconductor element 31 is a transistor (switching element) used mainly for power conversion. The first semiconductor element 31 is made of a material containing, for example, a nitride semiconductor. In the semiconductor device A10, the first semiconductor element 31 is a HEMT (High Electron Mobility Transistor) made of a material containing gallium nitride (GaN).

[0020] 3 and 9 , each of the first semiconductor elements 31 has a first main surface 31A, two first electrodes 311, a plurality of second electrodes 312, and a plurality of third electrodes 313. The first main surface 31A faces the same side as the top surface 141 of the fourth insulating layer 14 in the first direction z. The two first electrodes 311, the plurality of second electrodes 312, and the plurality of third electrodes 313 are located on the opposite side of the first main surface 31A in the first direction z. Therefore, the two first electrodes 311, the plurality of second electrodes 312, and the plurality of third electrodes 313 face the second insulating layer 12.

[0021] 3 , each of the plurality of second electrodes 312 and the plurality of third electrodes 313 extends in the third direction y. Two of the plurality of third electrodes 313 are located on either side of the plurality of second electrodes 312 in the third direction y. A current corresponding to the power before being converted by the first semiconductor element 31 flows through the plurality of third electrodes 313. Therefore, the plurality of third electrodes 313 correspond to drains of the first semiconductor element 31. A current corresponding to the power after being converted by the first semiconductor element 31 flows through the plurality of second electrodes 312. Therefore, the plurality of second electrodes 312 correspond to sources of the first semiconductor element 31.

[0022] 3 , the two first electrodes 311 are located on both sides of the first semiconductor element 31 in the third direction y. A gate voltage for driving the first semiconductor element 31 is applied to one of the two first electrodes 311. When viewed in the first direction z, the area of ​​each of the two first electrodes 311 is smaller than the area of ​​each of the multiple second electrodes 312 and the multiple third electrodes 313. The shapes and arrangements of the two first electrodes 311, the multiple second electrodes 312, and the multiple third electrodes 313 in the first semiconductor element 31 are examples.

[0023] As shown in Figures 6, 7, and 10, the second semiconductor element 32 faces the second insulating layer 12. At least a portion of the second semiconductor element 32 is covered with the third insulating layer 13. The second semiconductor element 32 is spaced apart from the first semiconductor element 31 in the second direction x. The first semiconductor element 31 has the same structure and function as the second semiconductor element 32. Therefore, in the description of the first semiconductor element 31, content that overlaps with the description of the second semiconductor element 32 will be omitted.

[0024] 3 and 10 , the second semiconductor element 32 has a second main surface 32A, two fourth electrodes 321, a plurality of fifth electrodes 322, and a plurality of sixth electrodes 323. The second main surface 32A faces the same side as the top surface 141 of the fourth insulating layer 14 in the first direction z. The two fourth electrodes 321, the plurality of fifth electrodes 322, and the plurality of sixth electrodes 323 are located on the opposite side of the second main surface 32A in the first direction z. Therefore, the two fourth electrodes 321, the plurality of fifth electrodes 322, and the plurality of sixth electrodes 323 face the second insulating layer 12.

[0025] The structure and function of the two fourth electrodes 321 correspond to the structure and function of the two first electrodes 311 of the first semiconductor element 31. The structure and function of the plurality of fifth electrodes 322 correspond to the structure and function of the plurality of second electrodes 312 of the first semiconductor element 31. The structure and function of the plurality of sixth electrodes 323 correspond to the structure and function of the plurality of third electrodes 313 of the second semiconductor element 32. As in the case of the first semiconductor element 31, the shapes and arrangements of the two fourth electrodes 321, the plurality of fifth electrodes 322, and the plurality of sixth electrodes 323 of the second semiconductor element 32 are merely examples.

[0026] As shown in FIGS. 2 , 5 , and 6 , the IC 33 faces the second insulating layer 12. The IC 33 is covered by the third insulating layer 13. The IC 33 is located on one side of the first semiconductor element 31 and the second semiconductor element 32 in the third direction y. The IC 33 is electrically connected to the first semiconductor element 31 and the second semiconductor element 32. The IC 33 is a gate driver that applies a gate voltage to either of the two fourth electrodes 321 of the second semiconductor element 32 and either of the two first electrodes 311 of the multiple first semiconductor elements 31. The IC 33 has multiple pads 331. The multiple pads 331 face the second insulating layer 12.

[0027] 6 to 10 , the plurality of connection wirings 39 are housed in the second insulating layer 12. As shown in Fig. 3 , when viewed in the first direction z, each of the plurality of connection wirings 39 overlaps with any of the first semiconductor element 31, the second semiconductor element 32, and the IC 33. Each of the plurality of connection wirings 39 is connected to any of the first wiring 21, the third wiring 23, the plurality of power wirings 25, and the plurality of control wirings 26. The composition of the plurality of connection wirings 39 is the same as the composition of the first wiring 21.

[0028] As shown in FIGS. 3 and 4, the plurality of connection wirings 39 includes a plurality of first connection wirings 39A, a plurality of second connection wirings 39B, and a plurality of third connection wirings 39C.

[0029] Each of the plurality of first connection wirings 39A is connected to any of the two first electrodes 311, the plurality of second electrodes 312, and the plurality of third electrodes 313 of the first semiconductor element 31. Each of the plurality of second connection wirings 39B is connected to any of the two fourth electrodes 321, the plurality of fifth electrodes 322, and the plurality of sixth electrodes 323 of the second semiconductor element 32. The plurality of third connection wirings 39C are individually connected to the plurality of pads 331 of the IC 33.

[0030] 6, 7, 9, and 10, the plurality of power wirings 25 are located between the first insulating layer 11 and the second insulating layer 12. At least a portion of each of the plurality of power wirings 25 is housed in the second insulating layer 12. The composition of the plurality of power wirings 25 is the same as the composition of the first wirings 21.

[0031] 4 , the multiple power wirings 25 include first power wiring 25A, second power wiring 25B, and third power wiring 25C. The multiple second electrodes 312 of the first semiconductor element 31 are electrically connected to the first power wiring 25A via some of the multiple first connection wirings 39A. The multiple third electrodes 313 of the first semiconductor element 31 are electrically connected to the second power wiring 25B via some of the multiple first connection wirings 39A. The multiple fifth electrodes 322 of the second semiconductor element 32 are electrically connected to the second power wiring 25B via some of the multiple second connection wirings 39B. The multiple sixth electrodes 323 of the second semiconductor element 32 are electrically connected to the third power wiring 25C via some of the multiple second connection wirings 39B.

[0032] 8 and 10 , the plurality of control wirings 26 are located between the first insulating layer 11 and the second insulating layer 12. At least a portion of each of the plurality of control wirings 26 is housed in the second insulating layer 12. The composition of the plurality of control wirings 26 is the same as the composition of the first wirings 21. Each of the plurality of control wirings 26 is electrically connected to one of the plurality of pads 331 of the IC 33 via one of the plurality of third connection wirings 39C.

[0033] As shown in FIG. 12 , the first wiring 21 is located between the first insulating layer 11 and the second insulating layer 12. At least a portion of the first wiring 21 is housed in the second insulating layer 12. The composition of the first wiring 21 includes at least copper (Cu). The first wiring 21 is electrically connected to one of the two first electrodes 311 of the first semiconductor element 31 via one of the plurality of first connection wirings 39A. Furthermore, the first wiring 21 is electrically connected to one of the plurality of pads 331 of the IC 33 via one of the plurality of third connection wirings 39C. In the first wiring 21, a current I1 flows from one of the plurality of pads 331 of the IC 33 to one of the two first electrodes 311 of the first semiconductor element 31.

[0034] As shown in FIG. 12 , the second wiring 22 is located on the opposite side of the second insulating layer 12 with respect to the first insulating layer 11. At least a portion of the second wiring 22 is housed in the first insulating layer 11. The composition of the second wiring 22 is the same as the composition of the first wiring 21. The second wiring 22 is electrically connected to a plurality of second electrodes 312 of the first semiconductor element 31 via a first terminal 51A (described later) and a first power wiring 25A. The second wiring 22 is also electrically connected to one of a plurality of pads 331 of the IC 33 via one of a plurality of control wirings 26. In the second wiring 22, a current I2 flows from the plurality of second electrodes 312 of the first semiconductor element 31 to one of the plurality of pads 331 of the IC 33. Therefore, the direction of the current I2 is opposite to the direction of the current I1 flowing in the first wiring 21.

[0035] 11 , when viewed in the first direction z, the first wiring 21 overlaps the second wiring 22. As shown in Fig. 11 and Fig. 12 , the distance D between the first wiring 21 and the second wiring 22 in the first direction z is shorter than a first dimension B1 of the first wiring 21 in a direction perpendicular to the first direction z and the direction in which the current I1 flows in the first wiring 21. Furthermore, as shown in Fig. 11 , the first dimension B1 is smaller than a second dimension B2 of the second wiring 22 in a direction perpendicular to the first direction z and the direction in which the current I2 flows in the second wiring 22.

[0036] As shown in FIG. 12 , the third wiring 23 is located between the first insulating layer 11 and the second insulating layer 12. At least a portion of the third wiring 23 is housed in the second insulating layer 12. The composition of the third wiring 23 is the same as the composition of the first wiring 21. The third wiring 23 is electrically connected to one of the two fourth electrodes 321 of the second semiconductor element 32 via one of the plurality of second connection wirings 39B. Furthermore, the third wiring 23 is electrically connected to one of the plurality of pads 331 of the IC 33 via one of the plurality of third connection wirings 39C. In the third wiring 23, a current flows from one of the plurality of pads 331 of the IC 33 to one of the two fourth electrodes 321 of the second semiconductor element 32.

[0037] As shown in FIG. 12 , the fourth wiring 24 is located on the opposite side of the second insulating layer 12 with respect to the first insulating layer 11. At least a portion of the fourth wiring 24 is housed in the first insulating layer 11. The composition of the fourth wiring 24 is the same as the composition of the first wiring 21. The fourth wiring 24 is electrically connected to the plurality of fifth electrodes 322 of the second semiconductor element 32 via a second terminal 51B (described later) and a second power wiring 25B. The fourth wiring 24 is also electrically connected to one of the plurality of pads 331 of the IC 33 via one of the plurality of control wirings 26. In the fourth wiring 24, a current flows from the plurality of fifth electrodes 322 of the second semiconductor element 32 to one of the plurality of pads 331 of the IC 33. Therefore, the direction of the current flowing in the fourth wiring 24 is opposite to the direction of the current flowing in the third wiring 23. When viewed in the first direction z, the third wiring 23 overlaps the fourth wiring 24.

[0038] 11 , the conduction path length L1 of the first wiring 21 is longer than the conduction path length L2 of the third wiring 23. The conduction path length L1 is the length of the shortest path in the first wiring 21 among the conduction paths from one of the multiple pads 331 of the IC 33 to one of the two first electrodes 311 of the first semiconductor element 31. The conduction path length L2 is the length of the shortest path in the second wiring 22 among the conduction paths from one of the multiple pads 331 of the IC 33 to one of the two second electrodes 312 of the second semiconductor element 32.

[0039] 6 to 10 , the plurality of interconnection wires 29 are housed in the first insulating layer 11. Each of the plurality of interconnection wires 29 is connected to any of the first wiring 21, the second wiring 22, the plurality of power wirings 25, and the plurality of control wirings 26, and to any of the second wiring 22, the fourth wiring 24, and the plurality of terminals 51. As shown in FIG. 5 , when viewed in the first direction z, the plurality of interconnection wires 29 are surrounded by the periphery of the bottom surface 111 of the first insulating layer 11. The composition of the plurality of interconnection wires 29 is the same as the composition of the first wiring 21.

[0040] As shown in FIGS. 4 and 5, the plurality of interconnecting wires 29 includes a plurality of first interconnecting wires 29A, a plurality of second interconnecting wires 29B, a plurality of third interconnecting wires 29C, and a plurality of fourth interconnecting wires 29D.

[0041] As shown in Figures 6 and 7, the multiple first connecting wires 29A are connected to the first power wires 25A and a first terminal 51A (described later). The multiple second connecting wires 29B are connected to the second power wires 25B and a second terminal 51B (described later). The multiple third connecting wires 29C are connected to the third power wires 25C and a third terminal 51C (described later). As shown in Figures 8 to 10, each of the multiple fourth connecting wires 29D is connected to one of the first wires 21, the third wires 23, and the multiple control wires 26, and to one of the second wires 22, the fourth wires 24, and the multiple control terminals 51D (described later).

[0042] As shown in Figures 6 to 10, the multiple terminals 51 are located on the opposite side of the first insulating layer 11 from the second insulating layer 12. As shown in Figure 5, each of the multiple terminals 51 is connected to one of the multiple interconnections 29. As a result, each of the multiple terminals 51 is electrically connected to at least one of the first semiconductor element 31, the second semiconductor element 32, and the IC 33. The multiple terminals 51 are in contact with the first insulating layer 11. In the semiconductor device A10, at least a portion of each of the multiple terminals 51 is housed in the first insulating layer 11. The composition of the multiple terminals 51 is the same as the composition of the first interconnections 21.

[0043] As shown in FIG. 5, the plurality of terminals 51 include a third terminal 51C, a second terminal 51B, a third terminal 51C, and a plurality of control terminals 51D.

[0044] As shown in Figures 4 and 5, the first terminal 51A is electrically connected to the first power wiring 25A via a plurality of first interconnecting wirings 29A. The second wiring 22 is connected to the first terminal 51A. The third terminal 51C is electrically connected to the second power wiring 25B via a plurality of third interconnecting wirings 29C. DC power, which is the target for conversion by the first semiconductor element 31 and the second semiconductor element 32, is input to the first terminal 51A and the third terminal 51C. The first terminal 51A is a negative electrode (N terminal). The third terminal 51C is a positive electrode (P terminal).

[0045] 4 and 5, the second terminal 51B is electrically connected to the second power wiring 25B via a plurality of second interconnection wirings 29B. The second terminal 51B outputs AC power converted by the first semiconductor element 31 and the second semiconductor element 32. The fourth wiring 24 is connected to the second terminal 51B.

[0046] Each of the plurality of control terminals 51D is electrically connected to one of the first wiring 21, the third wiring 23, and the plurality of control wirings 26 via one of the plurality of fourth connection wirings 29D. Therefore, each of the plurality of control terminals 51D is electrically connected to the IC 33. Power for driving the IC 33 is input to one of the plurality of control terminals 51D. An electrical signal to the IC 33 is input to one of the plurality of control terminals 51D. Furthermore, an electrical signal from the IC 33 is output from one of the plurality of control terminals 51D.

[0047] As shown in FIGS. 6 to 10 , the covering layer 52 is located on the opposite side of the second insulating layer 12 with respect to the first insulating layer 11. The covering layer 52 covers the bottom surface 111 as part of the first insulating layer 11. The covering layer 52 is an insulator. The covering layer 52 is, for example, a solder resist. The second wiring 22 and the fourth wiring 24 are covered by the covering layer 52. The covering layer 52 has a plurality of openings 521. The plurality of openings 521 penetrate the covering layer 52 in the first direction z. One of the plurality of terminals 51 is exposed to the outside through each of the plurality of openings 521. As a result, when the semiconductor device A10 is mounted on a wiring board, each of the plurality of terminals 51 can be conductively joined to the wiring board via solder.

[0048] 6 , 7 , 9 , and 10 , the plurality of heat dissipation layers 61 are located on the opposite side of the third insulating layer 13 from the second insulating layer 12. In the semiconductor device A10, at least a portion of each of the plurality of heat dissipation layers 61 is housed in the fourth insulating layer 14. The plurality of heat dissipation layers 61 are in contact with the fourth insulating layer 14. The plurality of heat dissipation layers 61 are exposed to the outside from a top surface 141 of the fourth insulating layer 14. The composition of the plurality of heat dissipation layers 61 is the same as the composition of the first wiring 21.

[0049] 1 , the plurality of heat dissipation layers 61 include a first heat dissipation layer 61A and a second heat dissipation layer 61B. The first heat dissipation layer 61A and the second heat dissipation layer 61B are spaced apart from each other in the second direction x. As viewed in the first direction z, the first heat dissipation layer 61A overlaps the first semiconductor element 31. As viewed in the first direction z, the second heat dissipation layer 61B overlaps the second semiconductor element 32.

[0050] 6 to 10 , the multiple intermediate layers 62 are located on the opposite side of the third insulating layer 13 from the second insulating layer 12, and are located between the third insulating layer 13 and the multiple heat dissipation layers 61. At least a portion of each of the multiple intermediate layers 62 is contained in the third insulating layer 13. The multiple intermediate layers 62 are in contact with the fourth insulating layer 14. Therefore, the fourth insulating layer 14 is located between the multiple intermediate layers 62 and the multiple heat dissipation layers 61. The composition of the multiple intermediate layers 62 is the same as the composition of the first wiring 21.

[0051] As shown in FIG. 2 , the multiple intermediate layers 62 include a first intermediate layer 62A, a second intermediate layer 62B, and a third intermediate layer 62C. The first intermediate layer 62A and the second intermediate layer 62B are spaced apart from each other in the second direction x. As viewed in the first direction z, the first intermediate layer 62A overlaps the first semiconductor element 31 and the first heat dissipation layer 61A. The first intermediate layer 62A is spaced apart from the first semiconductor element 31. As viewed in the first direction z, the second intermediate layer 62B overlaps the second semiconductor element 32 and the second heat dissipation layer 61B. The second intermediate layer 62B is spaced apart from the second semiconductor element 32. The third intermediate layer 62C is located between the first intermediate layer 62A and the second intermediate layer 62B in the second direction x. As viewed in the first direction z, the third intermediate layer 62C overlaps the IC 33. The third intermediate layer 62C is spaced apart from the IC 33.

[0052] 6 , the plurality of first vias 41 are housed in the fourth insulating layer 14. The plurality of first vias 41 are connected to the first heat dissipation layer 61A and the first intermediate layer 62A. As a result, the first intermediate layer 62A is electrically connected to the first heat dissipation layer 61A. The composition of the plurality of first vias 41 is the same as the composition of the first wiring 21.

[0053] 6 and 10 , the plurality of second vias 42 are housed in the fourth insulating layer 14. The plurality of second vias 42 are connected to the second heat dissipation layer 61B and the second intermediate layer 62B. As a result, the second intermediate layer 62B is electrically connected to the second heat dissipation layer 61B. The composition of the plurality of second vias 42 is the same as the composition of the first wiring 21.

[0054] 6 and 7 , the third vias 43 are housed in the second insulating layer 12 and the third insulating layer 13. The third vias 43 are connected to the first intermediate layer 62A and the first power wiring 25A. This provides electrical continuity between the first intermediate layer 62A and the first power wiring 25A. The composition of the third vias 43 is the same as the composition of the first wiring 21.

[0055] 6 and 7 , the plurality of fourth vias 44 are housed in the second insulating layer 12 and the third insulating layer 13. The plurality of fourth vias 44 are connected to the second intermediate layer 62B and the second power wiring 25B. This provides electrical continuity between the second intermediate layer 62B and the second power wiring 25B. The composition of the plurality of fourth vias 44 is the same as the composition of the first wiring 21.

[0056] 8 , the plurality of fifth vias 45 are housed in the second insulating layer 12 and the third insulating layer 13. The plurality of fifth vias 45 are electrically connected to the second intermediate layer 62B and any of the plurality of control wirings 26.

[0057] Next, the effects of the semiconductor device A10 will be described.

[0058] The semiconductor device A10 includes a first wiring 21 electrically connected to a first electrode 311 of a first semiconductor element 31 and a second wiring 22 electrically connected to a second electrode 312 of the first semiconductor element 31. The direction of current I2 flowing through the second wiring 22 is opposite to the direction of current I1 flowing through the first wiring 21. As viewed in the first direction z, the first wiring 21 overlaps the second wiring 22. The distance D between the first wiring 21 and the second wiring 22 in the first direction z is shorter than the first dimension B1 of the first wiring 21 (the dimension in the direction perpendicular to the first direction z and the direction in which current I1 flows in the first wiring 21). With this configuration, a counter electromotive force is generated in the first wiring 21 when the second wiring 22 is electrically connected. That is, in the semiconductor device A10, mutual inductance is likely to act between the first wiring 21 and the second wiring 22. This reduces the parasitic inductance in the first wiring 21, thereby making the current flow more smoothly in the first wiring 21. Therefore, with this configuration, it is possible to reduce the parasitic inductance in the wiring of the semiconductor device A10.

[0059] In the semiconductor device A10, a gate voltage for driving the first semiconductor element 31 is applied to the first electrode 311 of the first semiconductor element 31. Therefore, by reducing the parasitic inductance in the first wiring 21, the switching loss of the first semiconductor element 31 can be suppressed.

[0060] The first dimension B1 of the first wiring 21 is shorter than the second dimension B2 of the second wiring 22 (the dimension in the direction perpendicular to the first direction z and the direction in which the current I2 flows in the second wiring 22). By adopting this configuration, the area of ​​the first wiring 21 that overlaps with the second wiring 22 as viewed in the first direction z is further increased. This increases the counter electromotive force generated in the first wiring 21 due to the mutual inductance acting on the first wiring 21 and the second wiring 22. Therefore, the parasitic inductance in the first wiring 21 can be more effectively reduced.

[0061] The semiconductor device A10 further includes a first insulating layer 11 located between the first wiring 21 and the second wiring 22 in the first direction z. The first insulating layer 11 contains resin. At least a portion of the second wiring 22 is housed in the first insulating layer 11. This configuration makes it possible to further shorten the distance D between the first wiring 21 and the second wiring 22 in the first direction z while ensuring electrical insulation between the first wiring 21 and the second wiring 22. This increases the mutual inductance acting on the first wiring 21 and the second wiring 22, thereby making it possible to further reduce the parasitic inductance in the first wiring 21.

[0062] The semiconductor device A10 further includes a second insulating layer 12 located between the first semiconductor element 31 and the first insulating layer 11 in the first direction z, and a third insulating layer 13 located on the opposite side of the second insulating layer 12 from the first insulating layer 11. At least a portion of the first semiconductor element 31 is covered by the third insulating layer 13. The first wiring 21 is located between the first insulating layer 11 and the second insulating layer 12. This configuration makes it possible to suppress a decrease in the dielectric strength voltage of the first semiconductor element 31 while arranging the first wiring 21 between the first semiconductor element 31 and the first insulating layer 11.

[0063] The semiconductor device A10 further includes a heat dissipation layer 61 located on the opposite side of the third insulating layer 13 from the second insulating layer 12. The heat dissipation layer 61 is exposed to the outside. As viewed in the first direction z, the heat dissipation layer 61 overlaps the first semiconductor element 31. This configuration allows heat generated from the first semiconductor element 31 to be efficiently dissipated to the outside.

[0064] The semiconductor device A10 further includes an intermediate layer 62 located on the opposite side of the third insulating layer 13 from the second insulating layer 12 and between the third insulating layer 13 and the heat dissipation layer 61. The intermediate layer 62 is in contact with the third insulating layer 13 and spaced apart from the first semiconductor element 31. The intermediate layer 62 is electrically connected to the heat dissipation layer 61 and one of the power wirings 25 connected to the first semiconductor element 31. This configuration allows heat generated by the first semiconductor element 31 to be conducted to the intermediate layer 62 via one of the power wirings 25. In this case, the intermediate layer 62 overlaps the first semiconductor element 31 and the heat dissipation layer 61 when viewed in the first direction z. This allows heat generated by the first semiconductor element 31 to be more smoothly conducted to the heat dissipation layer 61. Furthermore, the intermediate layer 62 has the effect of reducing noise generated by the first semiconductor element 31 and noise entering the semiconductor device A10 from the outside.

[0065] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to FIGS. 13 to 15. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, the cross-sectional position in FIG. 13 is the same (or approximately the same) as the cross-sectional position in FIG. 6, which shows the semiconductor device A10. The cross-sectional position in FIG. 14 is the same (or approximately the same) as the cross-sectional position in FIG. 9, which shows the semiconductor device A10. The cross-sectional position in FIG. 15 is the same (or approximately the same) as the cross-sectional position in FIG. 12, which shows the semiconductor device A10.

[0066] In the semiconductor device A20, the configuration of the first insulating layer 11 is different from that of the semiconductor device A10.

[0067] 13 to 15, the second wiring 22, the fourth wiring 24, and the multiple terminals 51 are located on the opposite side of the multiple interconnection wirings 29 from the bottom surface 111 of the first insulating layer 11. Therefore, the second wiring 22, the fourth wiring 24, and the multiple terminals 51 are not contained in the first insulating layer 11 and are in contact with the bottom surface 111. In the semiconductor device A20, the first insulating layer 11 contains a silicon compound. The silicon compound is either silicon dioxide (SiO2) or silicon nitride (Si3N4). The first insulating layer 11 is formed by plasma CVD (chemical vapor deposition) under relatively low temperature conditions.

[0068] 15, the dimension of the first insulating layer 11 in the first direction z is smaller than that in the semiconductor device A10. Therefore, the distance D between the first wiring 21 and the second wiring 22 in the first direction z is even shorter than the distance D in the semiconductor device A10.

[0069] Next, the effects of the semiconductor device A20 will be described.

[0070] The semiconductor device A20 includes a first wiring 21 electrically connected to a first electrode 311 of a first semiconductor element 31 and a second wiring 22 electrically connected to a second electrode 312 of the first semiconductor element 31. The direction of current I2 flowing through the second wiring 22 is opposite to the direction of current I1 flowing through the first wiring 21. As viewed in the first direction z, the first wiring 21 overlaps the second wiring 22. The distance D between the first wiring 21 and the second wiring 22 in the first direction z is shorter than the first dimension B1 of the first wiring 21 (the dimension in the direction perpendicular to the first direction z and the direction of current I1 flow in the first wiring 21). Therefore, this configuration enables the semiconductor device A20 to reduce parasitic inductance in the wiring of the semiconductor device A20. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0071] In the semiconductor device A20, the first insulating layer 11 contains a silicon compound. This configuration allows the distance D between the first wiring 21 and the second wiring 22 in the first direction z to be set shorter. This increases the mutual inductance acting on the first wiring 21 and the second wiring 22, making it possible to further reduce the parasitic inductance in the first wiring 21.

[0072] 16 to 19, a semiconductor device A30 according to a third embodiment of the present disclosure will be described. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted.

[0073] The semiconductor device A30 differs from the semiconductor device A10 in the configuration of the intermediate layer 62 and in the absence of the fourth insulating layer 14, multiple intermediate layers 62, multiple first vias 41, multiple second vias 42, multiple third vias 43, multiple fourth vias 44, and multiple fifth vias 45.

[0074] 16 to 19 , the third insulating layer 13 has a top surface 131 facing the opposite side to the bottom surface 111 of the first insulating layer 11 in the first direction z. At least a portion of each of the plurality of heat dissipation layers 61 is housed in the third insulating layer 13. The plurality of heat dissipation layers 61 are exposed to the outside from the top surface 131. Each of the plurality of heat dissipation layers 61 is electrically insulated from both the plurality of power wirings 25 and the plurality of control wirings 26.

[0075] Next, the effects of the semiconductor device A30 will be described.

[0076] The semiconductor device A30 includes a first wiring 21 electrically connected to a first electrode 311 of a first semiconductor element 31 and a second wiring 22 electrically connected to a second electrode 312 of the first semiconductor element 31. The direction of current I2 flowing through the second wiring 22 is opposite to the direction of current I1 flowing through the first wiring 21. As viewed in the first direction z, the first wiring 21 overlaps the second wiring 22. The distance D between the first wiring 21 and the second wiring 22 in the first direction z is shorter than the first dimension B1 of the first wiring 21 (the dimension in the direction perpendicular to the first direction z and the direction in which current I1 flows in the first wiring 21). Therefore, with this configuration, the semiconductor device A30 can also reduce parasitic inductance in the wiring of the semiconductor device A30. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0077] Unlike the semiconductor device A10, the semiconductor device A30 does not include the fourth insulating layer 14 and the intermediate layer 62. At least a portion of the heat dissipation layer 61 is housed in the third insulating layer 13. The heat dissipation layer 61 is in contact with the third insulating layer 13 and is exposed to the outside from the third insulating layer 13. By adopting this configuration, it is possible to reduce the dimension of the semiconductor device A30 in the first direction z while suppressing a deterioration in the heat dissipation performance of the semiconductor device A30.

[0078] 20 to 23, a semiconductor device A40 according to a fourth embodiment of the present disclosure will be described. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted.

[0079] The semiconductor device A40 differs from the semiconductor device A30 described above in the configuration of the third insulating layer 13 and in that it does not include a plurality of heat dissipation layers 61.

[0080] 20 to 23 , the first main surface 31A of the first semiconductor element 31 and the second main surface 32A of the second semiconductor element 32 are exposed to the outside from the top surface 131 of the third insulating layer 13. The first main surface 31A and the second main surface 32A are each flush with the top surface 131. Therefore, the dimension of the third insulating layer 13 in the first direction z is smaller than the corresponding dimension of the semiconductor device A30.

[0081] Next, the effects of the semiconductor device A40 will be described.

[0082] The semiconductor device A40 includes a first wiring 21 electrically connected to a first electrode 311 of a first semiconductor element 31 and a second wiring 22 electrically connected to a second electrode 312 of the first semiconductor element 31. The direction of current I2 flowing through the second wiring 22 is opposite to the direction of current I1 flowing through the first wiring 21. As viewed in the first direction z, the first wiring 21 overlaps the second wiring 22. The distance D between the first wiring 21 and the second wiring 22 in the first direction z is shorter than the first dimension B1 of the first wiring 21 (the dimension in the direction perpendicular to the first direction z and the direction of current I1 flow in the first wiring 21). Therefore, with this configuration, the semiconductor device A40 can also reduce parasitic inductance in the wiring of the semiconductor device A40. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0083] Unlike the semiconductor device A30, the semiconductor device A40 does not include the heat dissipation layer 61. The first main surface 31A of the first semiconductor element 31 is exposed to the outside from the third insulating layer 13. Furthermore, the first main surface 31A is flush with the third insulating layer 13. By adopting this configuration, it is possible to further reduce the dimension of the semiconductor device A40 in the first direction z while suppressing a decrease in the heat dissipation performance of the semiconductor device A40.

[0084] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0085] The present disclosure includes embodiments described in the following appendices. Appendix 1: A semiconductor device comprising: a first semiconductor element having a first electrode and a second electrode; a first wiring electrically connected to the first electrode; and a second wiring electrically connected to the second electrode, wherein a direction of current flowing in the second wiring is opposite to a direction of current flowing in the first wiring, the first wiring overlaps the second wiring as viewed in a first direction, and a distance between the first wiring and the second wiring in the first direction is shorter than a first dimension of the first wiring in a direction orthogonal to the first direction and the direction of current flow in the first wiring. Appendix 2: The semiconductor device according to Appendix 1, wherein the first dimension is smaller than a second dimension of the second wiring in a direction orthogonal to the first direction and the direction of current flow in the second wiring. Appendix 3: The semiconductor device according to Appendix 2, further comprising a first insulating layer located between the first wiring and the second wiring in the first direction. Appendix 4: The semiconductor device according to Appendix 3, wherein the first insulating layer contains a resin, and at least a portion of the second wiring is housed in the first insulating layer. Appendix 5: The semiconductor device according to Appendix 3, wherein the first insulating layer contains a silicon compound. Appendix 6: The semiconductor device according to Appendix 4 or 5, further comprising a second insulating layer located between the first semiconductor element and the first insulating layer in the first direction, the first wiring is located between the first insulating layer and the second insulating layer, and the first electrode and the second electrode face the second insulating layer. Appendix 7: The semiconductor device according to Appendix 6, wherein the second insulating layer contains a resin, and at least a portion of the first wiring is housed in the second insulating layer. Appendix 8: The semiconductor device described in Appendix 6 or 7, further comprising a plurality of power wirings located between the first insulating layer and the second insulating layer, the first semiconductor element having a third electrode facing the second insulating layer, and each of the second electrode and the third electrode being electrically connected to one of the plurality of power wirings.Supplementary Note 9: The semiconductor device according to Supplementary Note 8, further comprising: a second semiconductor element having a fourth electrode and a fifth electrode facing the second insulating layer; and a third wiring located between the first insulating layer and the second insulating layer and conducting to the fourth electrode, the fifth electrode conducting to one of the plurality of power wirings, and a conduction path length of the first wiring being longer than a conduction path length of the third wiring. Supplementary Note 10: The semiconductor device according to Supplementary Note 9, wherein the second wiring is conducted to the second electrode via one of the plurality of power wirings. Supplementary Note 11: The semiconductor device according to Supplementary Note 10, further comprising: an IC located on the opposite side of the second insulating layer from the first insulating layer, and the first wiring, the second wiring, and the third wiring are conducted to the IC. Supplementary Note 12: The semiconductor device according to Supplementary Note 11, further comprising a plurality of terminals located on the opposite side of the first insulating layer from the second insulating layer, each of the plurality of terminals being electrically connected to at least one of the first semiconductor element, the second semiconductor element, and the IC, and the plurality of terminals being in contact with the first insulating layer. Supplementary Note 13: The semiconductor device according to Supplementary Note 12, further comprising a covering layer located on the opposite side of the first insulating layer from the second insulating layer and covering a portion of the first insulating layer, the covering layer being an insulator, and the second wiring being covered by the covering layer. Supplementary Note 14: The semiconductor device according to any of Supplements 8 to 13, further comprising a third insulating layer located on the opposite side of the second insulating layer from the first insulating layer, and at least a portion of the first semiconductor element being covered by the third insulating layer. Supplementary Note 15: The semiconductor device according to Supplementary Note 14, wherein the first semiconductor element has a main surface facing the opposite side to a side on which the first electrode and the second electrode are located in the first direction, and the main surface is exposed from the third insulating layer. Supplementary Note 16: The semiconductor device according to Supplementary Note 14, further comprising a heat dissipation layer located on the opposite side of the third insulating layer to the second insulating layer, and the heat dissipation layer overlaps the first semiconductor element when viewed in the first direction.Appendix 17: The semiconductor device according to Appendix 16, further comprising an intermediate layer located on the opposite side of the third insulating layer to the second insulating layer and between the third insulating layer and the heat dissipation layer, the intermediate layer being in contact with the third insulating layer and spaced apart from the first semiconductor element, the intermediate layer overlapping the first semiconductor element and the heat dissipation layer as viewed in the first direction, and the intermediate layer being electrically connected to any of the plurality of power wirings and the heat dissipation layer. Appendix 18: The semiconductor device according to Appendix 17, further comprising a fourth insulating layer located between the intermediate layer and the heat dissipation layer, the intermediate layer and the heat dissipation layer being in contact with the fourth insulating layer.

[0086] A10, A20, A30, A40: semiconductor device 11: first insulating layer 111: bottom surface 12: second insulating layer 13: third insulating layer 14: fourth insulating layer 141: top surface 21: first wiring 22: second wiring 23: third wiring 24: fourth wiring 25: power wiring 25A: first power wiring 25B: second power wiring 25C: third power wiring 26: control wiring 29: interconnection wiring 29A: first interconnection wiring 29B: second interconnection wiring 29C: third interconnection wiring 29D: fourth interconnection wiring 31: first semiconductor element 31A: first main surface 311: first electrode 312: second electrode 313: third electrode 32: second semiconductor element 32A: second main surface 321: fourth electrode 322: Fifth electrode 323: Sixth electrode 33: IC 331: Pad 39: Connection wiring 39A: First connection wiring 39B: Second connection wiring 39C: Third connection wiring 41: First via 42: Second via 43: Third via 44: Fourth via 45: Fifth via 51: Terminal 51A: First terminal 51B: Second terminal 51C: Third terminal 51D: Control terminal 52: Covering layer 521: Opening 61: Heat dissipation layer 61A: First heat dissipation layer 61B: Second heat dissipation layer 62: Intermediate layer 62A: First intermediate layer 62B: Second intermediate layer 62C: Third intermediate layer B1: First dimension B2: Second dimension D: Distance z: First direction x: Second direction y: Third direction

Claims

1. a first semiconductor element having a first electrode and a second electrode; A first wiring that is electrically connected to the first electrode; a second wiring electrically connected to the second electrode, a direction of a current flowing through the second wiring is opposite to a direction of a current flowing through the first wiring, When viewed in a first direction, the first wiring overlaps the second wiring, A semiconductor device, wherein the distance between the first wiring and the second wiring in the first direction is shorter than a first dimension of the first wiring in a direction perpendicular to the first direction and a direction in which current flows in the first wiring.

2. 2 . The semiconductor device according to claim 1 , wherein the first dimension is smaller than a second dimension of the second wiring in a direction perpendicular to the first direction and a direction in which a current flows in the second wiring.

3. The semiconductor device according to claim 2 , further comprising a first insulating layer located between said first wiring and said second wiring in said first direction.

4. the first insulating layer includes a resin; The semiconductor device according to claim 3 , wherein at least a portion of said second wiring is accommodated in said first insulating layer.

5. The semiconductor device according to claim 3 , wherein the first insulating layer includes a silicon compound.

6. a second insulating layer located between the first semiconductor element and the first insulating layer in the first direction; the first wiring is located between the first insulating layer and the second insulating layer, The semiconductor device according to claim 4 , wherein the first electrode and the second electrode face the second insulating layer.

7. the second insulating layer includes a resin, The semiconductor device according to claim 6 , wherein at least a portion of the first wiring is accommodated in the second insulating layer.

8. further comprising a plurality of power wirings located between the first insulating layer and the second insulating layer; the first semiconductor element has a third electrode facing the second insulating layer; The semiconductor device according to claim 6 , wherein each of said second electrode and said third electrode is electrically connected to any one of said plurality of power wirings.

9. a second semiconductor element having a fourth electrode and a fifth electrode facing the second insulating layer; a third wiring located between the first insulating layer and the second insulating layer and electrically connected to the fourth electrode; the fifth electrode is electrically connected to any one of the plurality of power wirings, The semiconductor device according to claim 8 , wherein a conduction path length of said first wiring is longer than a conduction path length of said third wiring.

10. 10. The semiconductor device according to claim 9, wherein the second wiring is electrically connected to the second electrode via any one of the plurality of power wirings.

11. an IC located on the opposite side of the first insulating layer with respect to the second insulating layer; The semiconductor device according to claim 10 , wherein the first wiring, the second wiring, and the third wiring are electrically connected to the IC.

12. Further comprising a plurality of terminals located on an opposite side of the first insulating layer from the second insulating layer, each of the plurality of terminals is electrically connected to at least one of the first semiconductor element, the second semiconductor element, and the IC; The semiconductor device according to claim 11 , wherein the plurality of terminals are in contact with the first insulating layer.

13. a coating layer located on the opposite side of the first insulating layer from the second insulating layer and covering a part of the first insulating layer; The coating layer is an insulator, The semiconductor device according to claim 12 , wherein the second wiring is covered with the covering layer.

14. Further, a third insulating layer is provided on the opposite side of the first insulating layer with respect to the second insulating layer, 14. The semiconductor device according to claim 8, wherein at least a portion of the first semiconductor element is covered with the third insulating layer.

15. the first semiconductor element has a main surface facing a side opposite to a side on which the first electrode and the second electrode are located in the first direction; The semiconductor device according to claim 14 , wherein the main surface is exposed from the third insulating layer.

16. a heat dissipation layer located on the opposite side of the second insulating layer with respect to the third insulating layer, The semiconductor device according to claim 14 , wherein the heat dissipation layer overlaps the first semiconductor element when viewed in the first direction.

17. an intermediate layer is further provided, the intermediate layer being located on the opposite side of the third insulating layer to the second insulating layer and between the third insulating layer and the heat dissipation layer; the intermediate layer is in contact with the third insulating layer and is spaced apart from the first semiconductor element; When viewed in the first direction, the intermediate layer overlaps the first semiconductor element and the heat dissipation layer, The semiconductor device according to claim 16 , wherein the intermediate layer is electrically connected to any one of the plurality of power wirings and to the heat dissipation layer.

18. a fourth insulating layer located between the intermediate layer and the heat dissipation layer; The semiconductor device according to claim 17 , wherein the intermediate layer and the heat dissipation layer are in contact with the fourth insulating layer.