Semiconductor device

Abstract

A semiconductor device (10) according to the present invention is provided with: a first semiconductor chip (103) which is mounted on a die pad (101); and a second semiconductor chip (107) which is mounted on the first semiconductor chip (103) with the face down, while comprising a band gap element (110). The first semiconductor chip (103) and the second semiconductor chip (107) are electrically connected to each other by means of a bonding material (106); a filler (109) is arranged between the first semiconductor chip (103) and the second semiconductor chip (107); and if r1 is the distance between the band gap element (110) and the bonding material (106) and r2 is the distance between the band gap element (110) and the outline of the first semiconductor chip (103), r1 and r2 satisfy the relational expression r1 / r2 ≥ (-0.148 × r1 + 0.021) × r2 + (0.500 × r1 + 0.020).

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device, and in particular to a technology suitable for a semiconductor device structure that can suppress initial stress, mitigate the effects of aging, and reduce the fluctuation range of a reference voltage generated by an internal reference voltage generation circuit.

[0002] A conventional semiconductor device structure that suppresses the effects of stress fluctuations is disclosed in, for example, Patent Document 1, a full-mold type semiconductor package in which semiconductor chips are stacked face-up in three layers to reduce compressive stress that occurs in the circuit part provided in the middle chip due to shrinkage of the sealing resin. Note that the stress that occurs in the semiconductor chip includes not only the initial stress that occurs due to shrinkage of the sealing resin when the semiconductor chip is sealed with high-temperature sealing resin during manufacturing of the semiconductor device and then cooled to room temperature, but also stress fluctuations that occur over time.

[0003] Patent No. 6131875

[0004] However, in conventional semiconductor devices, it is said that stress is reduced when the resin shrinks because the components behave in a way that cancels out each other, but it is extremely difficult to control the behavior of each component, and it is not possible to keep up with stress fluctuations that occur over time, and the accuracy of the reference voltage generated by the reference voltage generation circuit formed on the semiconductor chip deteriorates as a result of the stress fluctuations.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor device having a highly accurate and stable reference voltage generating circuit.

[0006] In view of the above, a semiconductor device according to one embodiment of the present disclosure includes a flat lead frame, a first semiconductor chip mounted on the lead frame in a face-up state, a second semiconductor chip mounted on the first semiconductor chip in a face-down state and smaller in chip size than the first semiconductor chip, the second semiconductor chip including a bandgap element having a PN junction that constitutes a bandgap reference circuit as a reference voltage generation circuit, a bonding material that electrically bonds the first semiconductor chip and the second semiconductor chip, and a filler material disposed between the first semiconductor chip and the second semiconductor chip, wherein, in a plan view of the lead frame, when a distance between a first position where the bandgap element is disposed and a second position of the bonding material closest to the bandgap element is r1 and a distance between the first position and an outer edge of the first semiconductor chip closest to the first position is r2, a relationship of r1 / r2≧(−0.148×r1+0.021)×r2+(0.550×r1+0.020) holds.

[0007] According to the semiconductor device according to the present disclosure, a semiconductor device having a highly accurate and stable reference voltage generating circuit is provided.

[0008] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. FIG. 1 is a plan view and a cross-sectional view of the semiconductor device shown in FIG. 1. FIG. 2 is a plot showing the results of a simulation of the relationship between the r1 / r2 ratio and stress when the linear expansion coefficient of the filler material is smaller than that of the bonding material in the semiconductor device shown in FIG. 1. FIG. 3 is a plot showing the results of a simulation of the relationship between the r1 / r2 ratio and r2 for each second semiconductor chip size in the semiconductor device shown in FIG. 1. FIG. 4 is a plot showing the results of a simulation of the relationship between the ratio of r1 to the height of the bonding material and stress in the semiconductor device shown in FIG. 1. FIG. 5 is an enlarged cross-sectional view showing the structure of the semiconductor device shown in FIG. 1. FIG. 6 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0009] Hereinafter, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings. Each of the embodiments described below represents a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement and connection configurations, processes, process order, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each drawing is not necessarily an exact illustration. In each drawing, substantially identical components are assigned the same reference numerals, and duplicate explanations are omitted or simplified.

[0010] First Embodiment Fig. 1 is a cross-sectional view showing the structure of a semiconductor device 10 according to a first embodiment. In Fig. 1, the semiconductor device 10 of the present disclosure includes a die pad 101, a paste material 102, a first semiconductor chip 103, bonding wires 104, pin terminals 105, a bonding material 106, a second semiconductor chip 107, a sealing resin 108, and a filler material 109. The die pad 101 and the pin terminals 105 form a flat lead frame. Here, "flat" includes not only a flat plate but also a flat plate having stepped portions.

[0011] The first semiconductor chip 103 is mounted face-up on the die pad 101 by the paste material 102, and inputs and outputs signals to and from the outside via bonding wires 104 and pin terminals 105. The second semiconductor chip 107 is smaller in chip size than the first semiconductor chip 103, and is flip-chip mounted (i.e., mounted face-down) on the first semiconductor chip 103 by the bonding material 106, and is electrically joined to the first semiconductor chip 103 via the bonding material 106 to input and output signals. Note that "the second semiconductor chip 107 is smaller in chip size than the first semiconductor chip 103" refers to a state in which part of the first semiconductor chip 103 located below is visible in a plan view of the lead frame.

[0012] A filler 109 is disposed between the first semiconductor chip 103 and the second semiconductor chip 107. Furthermore, the die pad 101, the paste material 102, the first semiconductor chip 103, the bonding wires 104, the pin terminals 105, the bonding material 106, the second semiconductor chip 107, and the filler 109 are integrally molded with a sealing resin 108 to form a package.

[0013] In addition, the bandgap element 110 has a PN junction that constitutes a bandgap reference circuit as a reference voltage generating circuit, and is formed on the placement surface of the bonding material 106 of the second semiconductor chip 107. Since the bandgap element 110 does not come into direct contact with the sealing resin 108, the bandgap element 110 is less susceptible to the effects of molding shrinkage of the sealing resin 108 or relaxation of the shrinkage force due to changes over time.

[0014] Next, the relationship between the sizes of the second semiconductor chip 107 and the first semiconductor chip 103 will be described with reference to FIGS.

[0015] First, to explain the relationship, the definitions of distance r1 and distance r2 will be explained using FIG. 2 . FIG. 2 shows a plan view and a cross-sectional view of the semiconductor device 10 shown in FIG. 1 . As shown in FIG. 2 , in a plan view relative to the lead frame, the distance between a first position P1 where the bandgap element 110 is disposed and a second position P2 of the bonding material 106 closest to the bandgap element 110 is defined as r1, and the distance between the first position P1 and the outer edge of the first semiconductor chip 103 closest to the first position P1 is defined as r2. FIG. 2 also shows the size X1 (mm square) of the second semiconductor chip 107 and the height Bh of the bonding material 106. Note that the position of an object in a plan view relative to the lead frame refers to the center position of the object in a plan view. In addition, in the simulation described below, the outer shapes of the first semiconductor chip 103 and the second semiconductor chip 107 in a plan view are assumed to be square.

[0016] Fig. 3 is a plot showing the results of a simulation of the relationship between the r1 / r2 ratio (horizontal axis) and the stress (vertical axis) generated in the band gap element 110 when the linear expansion coefficient of the filler 109 is smaller than that of the bonding material 106 in the semiconductor device 10 shown in Fig. 1. Fig. 4 is a plot showing the results of a simulation of the relationship between the r1 / r2 ratio (horizontal axis) and the stress (vertical axis) generated in the band gap element 110 when the linear expansion coefficient of the filler 109 is larger than that of the bonding material 106 in the semiconductor device 10 shown in Fig. 1.

[0017] 3 and 4, the stress shown on the vertical axis is positive when the stress generated in the bandgap element 110 is tensile stress, and negative when the stress is compressive stress. Therefore, compressive stress (negative stress) is plotted in FIG. 3, and the downward movement of the vertical axis indicates a larger compressive stress. On the other hand, tensile stress (positive stress) is plotted in FIG. 4, and the upward movement of the vertical axis indicates a larger tensile stress.

[0018] 3 and 4 plot the results of simulations performed while changing the size X1 of the first semiconductor chip 103 and the size X1 of the second semiconductor chip 107. Plots for representative sizes of the second semiconductor chip 107, X1=1.0 (1.0 mm square) and X1=1.5 (1.5 mm square), are surrounded by lines.

[0019] From these results, it can be seen that in Figure 3 the plot generally slopes upward to the right, and in Figure 4 the plot generally slopes downward to the right, and in either case the r1 / r2 ratio increases, that is, the stress tends to decrease as the distance between the bandgap element 110 and the bonding material 106 increases relative to the distance between the bandgap element 110 and the outer edge of the first semiconductor chip 103.

[0020] Furthermore, as can be seen from the positions of the plot group where X1=1.0 and the plot group where X1=1.5 in FIGS. 3 and 4, increasing the size of the first semiconductor chip 103 tends to reduce stress.

[0021] 5 is a graph showing the results of simulation calculations of the relationship between the minimum value of the r1 / r2 ratio (vertical axis) and r2 (horizontal axis) for each size X1 of the second semiconductor chip 107 of the semiconductor device 10 shown in Fig. 1, and a diagram showing the functional formula of the graph. Here, for each of the sizes X1 = 1.0, 1.5, 1.2, and 2.0 of the second semiconductor chip 107, a plot curve (solid line) is shown in which the minimum value on the vertical axis (r1 / r2 ratio) is y and the value on the horizontal axis (r2) is x, and a straight line (dotted line) of the linear approximation formula (y = ax + b) is shown.

[0022] Based on this result, the r1 dependency of each of the coefficient a and intercept b of the four linear approximation equations (y=ax+b) is calculated, resulting in the following linear approximation equations (Equation 1, Equation 2).

[0023] a=-0.148×r1+0.021 (Formula 1) b=0.550×r1+0.020 (Formula 2)

[0024] From this, the chip size dependency of the r1 / r2 ratio can be expressed by the following function formula (Formula 3).

[0025] r1 / r2≧(-0.148×r1+0.021)×r2+(0.550×r1+0.020) (Formula 3)

[0026] In other words, by designing r1 and r2 to satisfy the above formula 3, the stress generated in the bandgap element 110 can be brought close to the minimum value.

[0027] In addition, in the above formula 3, the significant digits of the coefficient a and the intercept b may be reduced by one, and the formula may be expressed as the following formula 3-1.

[0028] r1 / r2≧(-0.15×r1+0.02)×r2+(0.55×r1+0.02) (Formula 3-1)

[0029] In the semiconductor device 10, the bonding material 106 serves as the fulcrum and the band gap element 110 serves as the point of application. When the entire package warps due to heat, the end of the first semiconductor chip 103 serves as the fulcrum and the bonding material 106 serves as the point of application. Furthermore, the behavior of the filler 109 between the first semiconductor chip 103 and the second semiconductor chip 107 also affects the stress value, and therefore, by increasing the distance between each fulcrum and point of application, it becomes more difficult to propagate the stress caused by the warping of the entire package and it becomes easier to follow the behavior of the filler 109.

[0030] As described above, according to the semiconductor device 10 of this embodiment, the second semiconductor chip 107, which has a bandgap reference circuit mounted thereon as a reference voltage generation circuit, is mounted face-down on the first semiconductor chip 103. Therefore, the bandgap element 110 having a PN junction that constitutes the bandgap reference circuit mounted on the second semiconductor chip 107 does not come into direct contact with the sealing resin 108. This makes it less susceptible to the effects of shrinkage of the sealing resin 108, suppresses initial stress, and also alleviates stress fluctuations that occur due to changes over time.

[0031] Therefore, according to the semiconductor device 10 of this embodiment, a reference voltage generation circuit that requires high accuracy and high stability is formed on the second semiconductor chip 107, and is mounted face down on the first semiconductor chip 103. This structure suppresses initial stress caused by temperature changes and alleviates stress fluctuations caused by changes over time, making it possible to reduce the fluctuation range of the accuracy of the reference voltage generated by the reference voltage generation circuit.

[0032] Here, when the size X1 of the second semiconductor chip 107 is set to 1.0 mm to 1.5 mm, the coefficient a and intercept b of the linear approximation equation (y=ax+b) in FIG. 5 can be approximated by the following values.

[0033] a=-0.127 (Formula 4) b=0.458 (Formula 5)

[0034] As a result, the above formula 3 can be expressed as the following formula 6.

[0035] r1 / r2≧-0.127×r2+0.458 (Formula 6)

[0036] Therefore, when the size X1 of the second semiconductor chip 107 is between 1.0 mm and 1.5 mm, by setting r1 and r2 so that the above formula 6 holds, the stress value applied to the bandgap element 110 can be minimized.

[0037] In addition, in the above formula 6, the significant digits of the coefficient a and the intercept b may be reduced by one, and the formula may be expressed as the following formula 6-1.

[0038] r1 / r2≧-0.13×r2+0.46 (Formula 6-1)

[0039] Furthermore, when the size X1 of the second semiconductor chip 107 is made larger than 1.5 mm, the coefficient a and intercept b of the linear approximation equation (y=ax+b) in FIG. 5 can be approximated by the following values.

[0040] a=-0.201 (Formula 7) b=0.740 (Formula 8)

[0041] As a result, the above equation 3 can be expressed as the following equation 9.

[0042] r1 / r2≧-0.201×r2+0.740 (Formula 9)

[0043] Therefore, when the size X1 of the second semiconductor chip 107 is larger than 1.5 mm, by setting r1 and r2 so that the above formula 9 holds, the stress value applied to the bandgap element 110 can be minimized.

[0044] In addition, in the above formula 9, the significant digits of the coefficient a and the intercept b may be reduced by one, and the formula may be expressed as the following formula 9-1.

[0045] r1 / r2≧-0.20×r2+0.74 (Formula 9-1)

[0046] 6 is a diagram plotting the results of a simulation of the relationship between the ratio (r1 / Bh; horizontal axis) of r1 to the height Bh of the bonding material 106 and stress (vertical axis) in the semiconductor device 10 shown in FIG. Similar to FIGS. 3 and 4 , this diagram also plots the results of a simulation in which the size of the first semiconductor chip 103 and the size X1 of the second semiconductor chip 107 are varied. The plots for representative sizes of the second semiconductor chip 107, X1=1.0 (1.0 mm square) and X1=1.5 (1.5 mm square), are surrounded by lines.

[0047] From this result, when the size X1 of the second semiconductor chip 107 is set to 1.0 mm to 1.5 mm in the semiconductor device 10 according to this embodiment, as can be seen from FIG. 6 that the relationship r1 / Bh≧4.30 holds, the stress value applied to the band gap element 110 can be minimized by setting the height Bh of the bonding material 106 so that the ratio (r1 / Bh) is 4.30 or more.

[0048] Furthermore, in FIG. 6, when the size X1 of the second semiconductor chip 107 is made larger than 1.5 mm, as can be seen from FIG. 6 that the relationship r1 / Bh≧6.80 holds, the stress value applied to the bandgap element 110 can be minimized by setting the height of the bonding material 106 so that the ratio (r1 / Bh) is 6.80 or greater.

[0049] 7 is a diagram illustrating stress in the bandgap element 110 caused by the difference in the linear expansion coefficients of the filler 109 and the bonding material 106 in the semiconductor device 10 shown in Fig. 1. Arrow 112 indicates the direction of an external force that generates a compressive stress in the bandgap element 110, and arrow 113 indicates the direction of an external force that generates a tensile stress in the bandgap element 110.

[0050] 8 is an enlarged cross-sectional view showing the structure of the semiconductor device 10 shown in Fig. 1. The sealing resin 108 laminated on the second semiconductor chip 107 is called the upper resin layer 108a, and the sealing resin 108 bonded below the die pad 101 is called the lower resin layer 108b. The inner leads 117 constitute a lead frame and are terminals connected to the first semiconductor chip 103 by bonding wires 104. The height of the lower surface position of the inner leads 117 relative to the lower surface position of the die pad 101 is called the depression 116.

[0051] In the semiconductor device 10 according to this embodiment, if the linear expansion coefficient of the filler 109 is smaller than that of the bonding material 106 (first case), when the sealing resin 108 is cooled from a high temperature, the bonding material 106 contracts more than the filler 109, and as a result, as shown by arrow 112 in Fig. 7 , the contraction of the bonding material 106 and the deformation of the first semiconductor chip 103 act to generate a force that generates a compressive stress in the bandgap element 110. For example, in the first case, the filler 109 is an epoxy resin and the bonding material 106 is a SnAg-based solder.

[0052] Therefore, it has been found that the compressive stress generated in the band gap element 110 can be alleviated by setting the thicknesses of the first semiconductor chip 103 and the second semiconductor chip 107, the lower surface position of the die pad 101 (the so-called depression amount), the thickness of the lead frame, the thickness 115 of the lower resin layer 108b, and the thickness 114 of the upper resin layer 108a to predetermined values ​​so that the structure above the filler 109 can be made flexible so that stress from above can be dispersed, and the structure below the filler 109 can be made rigid so that stress from below is not propagated.

[0053] One of the settings is to make the thickness of the second semiconductor chip 107 thinner than the thickness of the first semiconductor chip 103, for example, by making the thickness of the first semiconductor chip 103 0.25 mm and the thickness of the second semiconductor chip 107 0.25 mm or less, the compressive stress generated in the bandgap element 110 can be alleviated.

[0054] As another setting, the compressive stress occurring in the bandgap element 110 can be alleviated by processing the lead frame so that the amount of depression is, for example, 0.10 mm or less.

[0055] As another setting, the thickness of the lead frame is set to 0.6 times the thickness of the first semiconductor chip 103, for example, 0.15 mm or less, thereby making it possible to alleviate the compressive stress occurring in the bandgap element 110.

[0056] Furthermore, as another setting, the thickness 115 of the lower resin layer 108b can be set to twice the thickness of the first semiconductor chip 103, for example, 0.525 mm or more, thereby alleviating the compressive stress generated in the bandgap element 110.

[0057] As another setting, the thickness 114 of the upper resin layer 108a is made thinner than the thickness of the second semiconductor chip 107, for example, 0.105 mm or less, thereby making it possible to alleviate the compressive stress generated in the bandgap element 110.

[0058] Conversely to the first case described above, if the filler 109 has a larger linear expansion coefficient than the bonding material 106 (second case), when the sealing resin 108 cools from a high temperature, the filler 109 contracts more than the bonding material 106, and as shown by arrow 113 in Fig. 7 , the contraction of the filler 109 exerts a force that generates tensile stress on the bandgap element 110. For example, the second case is one in which the bonding material 106 is SnAg-based solder and the filler 109 is an underfill agent.

[0059] Therefore, contrary to the first case described above, it has been found that the tensile stress generated in the band gap element 110 can be alleviated by making the structure below the filler 109 flexible so that stress from below can be dispersed, and by setting the thicknesses of the first semiconductor chip 103 and the second semiconductor chip 107, the lower surface position of the die pad 101 (the so-called depression amount), the thickness of the lead frame, the thickness 115 of the lower resin layer 108b, and the thickness 114 of the upper resin layer 108a to predetermined numerical values ​​so that the structure above the filler 109 can also be flexible to stress from above.

[0060] One setting is to make the thickness of the first semiconductor chip 103 thinner than the thickness of the second semiconductor chip 107, for example, by making the thickness of the first semiconductor chip 103 0.15 mm and the thickness of the second semiconductor chip 107 0.25 mm, the tensile stress generated in the bandgap element 110 can be alleviated.

[0061] As another setting, the amount of depression may be processed to be, for example, 0.10 mm or more, thereby alleviating the tensile stress occurring in the bandgap element 110 .

[0062] As another setting, the thickness of the lead frame is set to the thickness of the first semiconductor chip 103, for example, 0.15 mm or more, so that the tensile stress generated in the bandgap element 110 can be alleviated.

[0063] As another setting, the thickness 115 of the lower resin layer 108b is set to three times the thickness of the first semiconductor chip 103, for example, 0.425 mm or less, thereby reducing the tensile stress generated in the bandgap element 110.

[0064] As another setting, the thickness 114 of the upper resin layer 108a is set to be thicker than the thickness of the second semiconductor chip 107, for example, 0.255 mm or more, thereby making it possible to alleviate the tensile stress generated in the bandgap element 110.

[0065] As another setting, the height of the bonding material 106 is set low, for example, to 0.10 mm or less, thereby reducing the volume of the filler material 109 and making it possible to reduce the tensile stress generated in the bandgap element 110 .

[0066] As another setting, by using a material with a low linear expansion coefficient, such as solder, as the bonding material 106, the bonding material 106 can follow the tensile stress generated by the contraction of the filler material 109, thereby alleviating the tensile stress generated in the bandgap element 110.

[0067] In the semiconductor device 10 according to this embodiment, a gap not filled with the filler 109 may exist at the first position P1 where the bandgap element 110 is disposed in a plan view of the lead frame. For example, the basic structure of the semiconductor device 10 described in the first embodiment may be the same as that of the semiconductor device 10 described in the first embodiment, except that the filler 109 is not present between the surface of the second semiconductor chip 107, particularly the surface where the bandgap element 110 is present, and the filler 109, i.e., a gap exists. The existence of the gap prevents the bandgap element 110 from coming into contact with other materials, and the structure is less susceptible to package warpage caused by temperature changes in the resin sealing the first semiconductor chip 103 and the second semiconductor chip 107, and shrinkage of the bonding material 106 and the filler 109, thereby maintaining the bandgap element 110 in a stress-free state.

[0068] In the semiconductor device 10 according to this embodiment, in a plan view of the lead frame, the first position P1 at which the bandgap element 110 is disposed is equidistant from both ends of one side that constitutes the outer shape of the second semiconductor chip 107. If the outer shape of the second semiconductor chip 107 is rectangular in a plan view, the first position P1 is equidistant from both ends of the short side that constitutes the outer shape of the second semiconductor chip 107.

[0069] As a result, in the second semiconductor chip 107, the center of the chip has the smallest value in terms of stress surface distribution, so by placing the bandgap element 110 in the center, fluctuations in the reference voltage generated by the reference voltage generation circuit due to initial stress and changes over time can also be suppressed.

[0070] Furthermore, in a plan view of the lead frame, the center point of second semiconductor chip 107 overlaps with the center point of the lead frame, so that second semiconductor chip 107 is placed in the center where stress is smallest in the entire package, thereby reducing deformation of bandgap element 110 and suppressing fluctuations in measurement accuracy due to initial stress and changes over time.

[0071] Second Embodiment FIG. 9 is a cross-sectional view showing the structure of a semiconductor device 10a according to a second embodiment.

[0072] The semiconductor device 10a according to this embodiment is the same as the semiconductor device 10 according to the first embodiment in terms of the materials used and the fact that the second semiconductor chip 107 is mounted face-down on the first semiconductor chip 103, but in terms of the cross-sectional structure, the lower surface of the die pad 101 is positioned at the same level as or higher than the lower surfaces of the inner leads 117. In this embodiment, the linear expansion coefficient of the filler 109 is smaller than the linear expansion coefficient of the bonding material 106.

[0073] By having such a configuration, in the semiconductor device 10a according to this embodiment, the resin volumes at the top and bottom are asymmetric, so that the stress generated in the upper chip due to resin shrinkage is offset by the shrinkage of the lower chip and below, thereby minimizing the stress value applied to the bandgap element 110.

[0074] Although the semiconductor device according to the present disclosure has been described above based on the first and second embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can make to these embodiments and other embodiments constructed by combining some of the components of these embodiments are also included within the scope of the present disclosure.

[0075] For example, in the above embodiment, the case where the linear expansion coefficients of the filler 109 and the bonding material 106 are different has been described, but it is not essential that the linear expansion coefficients of the filler 109 and the bonding material 106 are different, and the linear expansion coefficients of the filler 109 and the bonding material 106 may be approximately the same.

[0076] In addition, in the above embodiment, it has been explained that at a first position in a planar view relative to the lead frame, there may be a gap between the surface of the second semiconductor chip 107 and the filler 109 where the filler 109 is not present, but the filler 109 does not have to be positioned between the first semiconductor chip 103 and the second semiconductor chip 107.

[0077] In addition, in the simulations in the above embodiments, the outer shapes of the first semiconductor chip 103 and the second semiconductor chip 107 in a planar view are assumed to be square, but this is to simplify the calculations, and in the semiconductor device disclosed herein, the outer shapes of the first semiconductor chip 103 and the second semiconductor chip 107 in a planar view may also be rectangular.

[0078] 10, 10a Semiconductor device 101 Die pad 102 Paste material 103 First semiconductor chip 104 Bonding wire 105 Pin terminal 106 Bonding material 107 Second semiconductor chip 108 Sealing resin 108a Upper resin layer 108b Lower resin layer 109 Filler material 110 Band gap element P1 First position where band gap element is arranged P2 Second position of bonding material r1 Distance between the first position where band gap element is arranged and the second position of the bonding material closest to the band gap element r2 Distance between the first position and the outer edge of the first semiconductor chip closest to the first position Bh Height of bonding material 112 Direction of compressive stress 113 Direction of tensile stress 114 Thickness of upper resin layer 115 Thickness of lower resin layer 116 Depression 117 Inner lead

Claims

1. A flat lead frame; a first semiconductor chip mounted face-up on the lead frame; a second semiconductor chip mounted face-down on the first semiconductor chip and having a smaller chip size than the first semiconductor chip, the second semiconductor chip including a bandgap element having a PN junction constituting a bandgap reference circuit as a reference voltage generating circuit; a bonding material that electrically bonds the first semiconductor chip and the second semiconductor chip; a filler disposed between the first semiconductor chip and the second semiconductor chip; In a plan view of the lead frame, a distance between a first position where the bandgap element is arranged and a second position of the bonding material closest to the bandgap element is defined as r1, and a distance between the first position and an outer edge of the first semiconductor chip closest to the first position is defined as r2. A semiconductor device in which the relationship r1 / r2≧(−0.148×r1+0.021)×r2+(0.550×r1+0.020) is satisfied.

2. 2. The semiconductor device according to claim 1, wherein a relationship of r1 / r2≧−0.127×r2+0.458 is satisfied.

3. 3. The semiconductor device according to claim 2, wherein the relationship r1 / r2≧−0.201×r2+0.740 holds.

4. 4. The semiconductor device according to claim 1, wherein when the height of the bonding material is Bh, a relationship of r1 / Bh≧4.30 is satisfied.

5. 5. The semiconductor device according to claim 4, wherein a relationship of r1 / Bh≧6.80 is satisfied.

6. The linear expansion coefficient of the filler is smaller than the linear expansion coefficient of the bonding material, 4. The semiconductor device according to claim 1, wherein the thickness of said first semiconductor chip is greater than the thickness of said second semiconductor chip.

7. the lead frame has a die pad for mounting the first semiconductor chip thereon, and inner leads connected to the first semiconductor chip by wires; 7. The semiconductor device according to claim 6, wherein a height of the lower surface of said inner lead with respect to a lower surface of said die pad is 0.10 mm or less.

8. 7. The semiconductor device according to claim 6, wherein the thickness of said lead frame is smaller than 0.6 times the thickness of said first semiconductor chip.

9. Further, a lower resin layer is bonded under the lead frame, 7. The semiconductor device according to claim 6, wherein the thickness of said lower resin layer is greater than twice the thickness of said first semiconductor chip.

10. Further, an upper resin layer is laminated on the second semiconductor chip, 7. The semiconductor device according to claim 6, wherein the thickness of said upper resin layer is smaller than the thickness of said second semiconductor chip.

11. The linear expansion coefficient of the filler is greater than the linear expansion coefficient of the bonding material, 4. The semiconductor device according to claim 1, wherein the thickness of said first semiconductor chip is smaller than the thickness of said second semiconductor chip.

12. the lead frame has a die pad for mounting the first semiconductor chip thereon, and inner leads connected to the first semiconductor chip by wires; 12. The semiconductor device according to claim 11, wherein a height of the lower surface of the inner lead with respect to a lower surface of the die pad is 0.10 mm or more.

13. 12. The semiconductor device according to claim 11, wherein the thickness of the lead frame is greater than the thickness of the first semiconductor chip.

14. Further, a lower resin layer is bonded under the lead frame, 12. The semiconductor device according to claim 11, wherein the thickness of said lower resin layer is less than three times the thickness of said first semiconductor chip.

15. Further, an upper resin layer is laminated on the second semiconductor chip, The semiconductor device according to claim 11 , wherein the thickness of the upper resin layer is greater than the thickness of the second semiconductor chip.

16. The semiconductor device according to claim 11, wherein the height of the bonding material is 0.10 mm or less.

17. The semiconductor device according to claim 11, wherein the bonding material is made of solder.

18. 4. The semiconductor device according to claim 1, wherein at the first position in the plan view, there is a gap between the surface of the second semiconductor chip and the filler where the filler is not present.

19. 4. The semiconductor device according to claim 1, wherein the first position is at a position equidistant from both ends of one side constituting an outer shape of the second semiconductor chip in the plan view.

20. 4. The semiconductor device according to claim 1, wherein a center point of the second semiconductor chip overlaps a center point of the lead frame in the plan view.

21. A flat lead frame; a first semiconductor chip mounted face-up on the lead frame; a second semiconductor chip mounted face-down on the first semiconductor chip and having a smaller chip size than the first semiconductor chip, the second semiconductor chip including a bandgap element having a PN junction that constitutes a bandgap reference circuit; a bonding material that electrically bonds the first semiconductor chip and the second semiconductor chip; a filler disposed between the first semiconductor chip and the second semiconductor chip; the lead frame has a die pad for mounting the second semiconductor chip thereon, and inner leads connected to the first semiconductor chip by wires; The linear expansion coefficient of the filler is smaller than the linear expansion coefficient of the bonding material, A semiconductor device, wherein a lower surface of the die pad is positioned at a height position equal to or higher than a lower surface of the inner lead.