Method for manufacturing semiconductor device, and semiconductor device

Abstract

A semiconductor device obtained by a manufacturing method according to the present disclosure has a multilayer wiring in which wiring layers and insulating layers are alternately stacked, the wiring layers adjacent to each other in the stacking direction, with the insulating layer interposed therebetween, being electrically connected to each other by a conductor present in a through hole provided in the insulating layer. The multilayer wiring is formed by providing the insulating layer having a metal protective film on the surface and including an inorganic filler having an average maximum particle length B of 1-100 μm on a substrate, forming the through hole in the insulating layer, and dry desmearing the insulating layer in which the through hole has been formed.

Description

Semiconductor device manufacturing method and semiconductor device

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] To achieve higher density and performance in semiconductor packages, a packaging method has been proposed in which chips with different performance are mixed in a single package. In this case, cost-effective high-density interconnect technology between chips is becoming important (see, for example, Patent Document 1).

[0003] Non-Patent Documents 1 and 2 describe a package-on-package (PoP) configuration in which different packages are connected by stacking them on top of one another using flip-chip mounting. This PoP configuration is widely adopted in smartphones, tablet terminals, and the like.

[0004] As other forms for mounting multiple chips at high density, packaging technology using an organic substrate with high-density wiring, fan-out type packaging technology (FO-WLP: FanOut-Wafer Level Package) with through-mold vias (TMV: Through Mold Via), packaging technology using a silicon or glass interposer, packaging technology using through-silicon electrodes (TSV: Through Silicon Via), packaging technology using chips embedded in a substrate for inter-chip transmission, and the like have been proposed.

[0005] In particular, when semiconductor chips are mounted on one another in a semiconductor wiring layer and FO-WLP, a fine wiring layer is required to electrically connect the semiconductor chips with each other at high density (see, for example, Patent Document 2).

[0006] Patent Document 1: JP 2012-529770 A, US Patent Application Publication No. 2011 / 0221071

[0007] Jinseong Kim et al.,“Application of Through Mold Via (TMV) as PoP Base Package”,Electronic Components and Technology Conference (ECTC), p.1089-1092 (2008)S.W. Yoon et al., “AdvancedLow Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP)Technology”, ECTC, p.1250-1254 (2012)

[0008] Wiring layers (semiconductor wiring layers) for mounting multiple semiconductor chips are sometimes used in build-up substrates, wafer-level packages (WLPs), fan-out PoP bottom packages, and the like. The wiring layer is configured as multilayer wiring in which wiring layers and insulating layers are alternately stacked. For example, copper, which has high conductivity, is sometimes used as the metal constituting the wiring layer in order to reduce costs and suppress increases in wiring resistance. Furthermore, a cured product of an epoxy resin composition, which has an excellent balance of electrical properties, moisture resistance, heat resistance, mechanical properties, and the like, is sometimes used as a component constituting the insulating layer. An inorganic filler is contained in the epoxy resin composition for the purposes of improving the strength of the cured product and adjusting the thermal expansion properties of the cured product. Since a higher content of inorganic filler tends to improve the strength of the cured product and suppress thermal expansion, a high content of inorganic filler in the epoxy resin composition may be desirable. On the other hand, a higher content of inorganic filler tends to increase the possibility of the presence of large-sized inorganic filler particles. In order to ensure conduction between wiring layers, via holes (through holes) may be provided in an insulating layer composed of a cured product of an epoxy resin composition containing an inorganic filler. Examples of methods for forming the through holes include laser processing. The inorganic filler contained in the epoxy resin composition may be exposed on the side of the through hole. The exposed inorganic filler causes unevenness on the side of the through hole. The unevenness on the side of the through hole may cause a deterioration in the shape of the through hole. The deterioration in the shape of the through hole tends to worsen as the possibility of the presence of large-diameter inorganic filler particles increases.

[0009] The present disclosure has been made in consideration of the above-described conventional circumstances, and aims to provide a method for manufacturing a semiconductor device that can suppress the occurrence of unevenness on the side surface of a through hole, and also aims to provide a semiconductor device having highly reliable multilayer wiring.

[0010] Specific means for achieving the above object are as follows: <1> A method for manufacturing a semiconductor device having multilayer wiring in which wiring layers and insulating layers are alternately stacked, wherein adjacent wiring layers sandwiching an insulating layer in the stacking direction are electrically connected via conductors present in through holes provided in the insulating layer, and the multilayer wiring is formed by the following steps: providing, on a base, an insulating layer having a metal protective film on a surface thereof and containing an inorganic filler having an average maximum particle length B of 1 μm to 100 μm; forming through holes in the insulating layer; and performing a dry desmear treatment on the insulating layer with the through holes formed therein. <2> The method for manufacturing a semiconductor device according to <1>, wherein the dry desmear treatment is performed until the average height C of protrusions on the side surfaces of the through holes resulting from the inorganic filler and the average maximum particle length B of the inorganic filler satisfy the following relationship (I): B>2C (I) <3> The method for manufacturing a semiconductor device according to <1> or <2>, wherein the following relationship (II) is satisfied when the average diameter of the through holes is A: A>3B (II) <4> The method for manufacturing a semiconductor device according to any one of <1> to <3>, wherein the through hole is formed by at least one method selected from the group consisting of laser processing and photolithography. <5> The method for manufacturing a semiconductor device according to <4>, wherein the through hole is formed by removing a region of the metal protective film corresponding to the location where the through hole is to be provided by photolithography, and then performing the laser processing on the removed portion of the metal protective film. <6> The method for manufacturing a semiconductor device according to <4>, wherein the through hole is formed by performing the laser processing with the metal protective film present on the surface of the insulating layer. <7> The method for manufacturing a semiconductor device according to any one of <1> to <6>, wherein the insulating layer having the metal protective film on its surface is provided on the base by providing the insulating layer on the base, roughening the surface of the insulating layer, and disposing the metal protective film on the roughened surface of the insulating layer. <8> The method for manufacturing a semiconductor device according to <7>, wherein the surface of the insulating layer is roughened by at least one method selected from the group consisting of grinding, chemical treatment, and plasma etching.<9> The method for manufacturing a semiconductor device according to <7> or <8>, wherein the metal protective film is formed by at least one method selected from the group consisting of metal vapor deposition, electroless plating, and electrolytic plating. <10> The method for manufacturing a semiconductor device according to any one of <7> to <9>, wherein the roughened insulating layer has a surface roughness Ra of 0.1 μm to 2.0 μm. <11> The method for manufacturing a semiconductor device according to any one of <1> to <10>, wherein the insulating layer is a cured product of an epoxy resin composition. <12> The method for manufacturing a semiconductor device according to any one of <1> to <6>, wherein the insulating layer having the metal protective film on its surface is formed on the base by contacting the epoxy resin composition layer of a metal foil-attached adhesive film having an epoxy resin composition layer and a metal foil in that order with the base and then curing the epoxy resin composition layer. <13> The method for manufacturing a semiconductor device according to any one of <1> to <12>, further comprising forming a wiring layer on the insulating layer that has been subjected to the dry desmear treatment. <14> The method for manufacturing a semiconductor device according to <13>, wherein the wiring layer is formed after removing the metal protective film from the surface of the insulating layer. <15> The method for manufacturing a semiconductor device according to <13>, wherein the wiring layer is formed on the metal protective film. <16> The method for manufacturing a semiconductor device according to any one of <1> to <15>, wherein at least one of a wet desmearing treatment and a plasma ashing treatment is further performed before the dry desmearing treatment. <17> A semiconductor device comprising: a semiconductor element; and multilayer wiring in which wiring layers and insulating layers electrically connected to the semiconductor element are alternately stacked, the wiring layers adjacent in the stacking direction via the insulating layer being electrically connected via conductors present in through holes provided in the insulating layer, the insulating layer containing an inorganic filler having an average maximum particle length B of 1 μm to 100 μm, wherein the semiconductor element satisfies the following relationship (I) and (II), where C is the average height of protrusions on the side surfaces of the through holes resulting from the inorganic filler and A is the average diameter of the through holes: B>2C (I) and A>3B (II).

[0011] According to the present disclosure, it is possible to provide a method for manufacturing a semiconductor device that can suppress the occurrence of unevenness on the side surface of a through hole, and a semiconductor device having highly reliable multilayer wiring.

[0012] 1 is a cross-sectional view showing a state in which an insulating layer 14 containing inorganic fillers 12 having an average maximum particle length B of 1 μm to 100 μm is provided on a semiconductor substrate 10. FIG. 1 is a cross-sectional view showing a state in which the surface of the insulating layer 14 has been roughened. FIG. 1 is a cross-sectional view showing a state in which a metal protective film 16 has been provided on the roughened surface of the insulating layer 14. FIG. 2 is a view showing a state in which a region Q corresponding to a location where a through hole will be provided in the metal protective film 16 provided on the surface of the insulating layer 14 has been partially removed. FIG. 2 is a cross-sectional view showing a state in which a through hole 18 has been provided in the surface of the insulating layer 14. FIG. 3 is a cross-sectional view showing a state after a dry desmear treatment has been performed on the insulating layer 14 in which the through hole 18 has been formed.

[0013] Hereinafter, embodiments of the present disclosure will be described in detail. However, the present disclosure is not limited to the following embodiments. In the following embodiments, components (including element steps, etc.) are not essential unless otherwise specified. The same applies to numerical values ​​and their ranges, and do not limit the present disclosure.

[0014] In the present disclosure, numerical ranges indicated using "to" include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In numerical ranges described in stages in the present disclosure, the upper or lower limit value described in one numerical range may be replaced with the upper or lower limit value of another staged numerical range. Furthermore, in numerical ranges described in the present disclosure, the upper or lower limit value of that numerical range may be replaced with a value shown in the examples. In the present disclosure, each component may contain multiple corresponding substances. When multiple substances corresponding to each component are present in the composition, the content or amount of each component means the total content or amount of the multiple substances present in the composition, unless otherwise specified. In the present disclosure, particles corresponding to each component may include multiple types of particles. When multiple types of particles corresponding to each component are present in the composition, the particle size of each component means the value for a mixture of the multiple types of particles present in the composition, unless otherwise specified. In the present disclosure, the terms "layer" or "film" include cases where the layer or film is formed over the entire area when the area where the layer or film is present is observed, as well as cases where the layer or film is formed only over a portion of the area. In the present disclosure, the term "laminate" refers to stacking layers, and two or more layers may be bonded together, or two or more layers may be detachable. In the present disclosure, the average thickness of a layer or film is determined by measuring the thickness at five points on the target layer or film and calculating the arithmetic mean value. The thickness of a layer or film can be measured using a micrometer or the like. In the present disclosure, if the thickness of a layer or film can be measured directly, it is measured using a micrometer. On the other hand, when measuring the thickness of a single layer or the total thickness of multiple layers, it may be measured by observing the cross section of the target using an electron microscope.

[0015] <Method for Manufacturing a Semiconductor Device> The method for manufacturing a semiconductor device disclosed herein relates to a method for manufacturing a semiconductor device having multilayer wiring in which wiring layers and insulating layers are alternately stacked, and adjacent wiring layers sandwiching an insulating layer in the stacking direction are electrically connected via conductors present in through holes provided in the insulating layer. In the method for manufacturing a semiconductor device disclosed herein, the multilayer wiring is formed by providing, on a substrate, an insulating layer having a metal protective film on its surface and containing an inorganic filler having an average maximum particle length B of 1 μm to 100 μm, forming through holes in the insulating layer, and performing a dry desmear treatment on the insulating layer with the through holes formed therein. The method for manufacturing a semiconductor device disclosed herein makes it possible to suppress the occurrence of unevenness on the side surfaces of the through holes. The reason for this is not clear, but is presumed to be as follows.

[0016] When through holes are formed in an insulating layer using a method such as laser processing, the inorganic filler may be exposed on the side surfaces of the through holes. In particular, when through holes are formed in an insulating layer using laser processing, the resin components constituting the insulating layer are removed by laser irradiation, but the inorganic filler is difficult to remove, and the inorganic filler is easily exposed on the side surfaces of the through holes. Dry desmearing is an effective way to remove the inorganic filler exposed on the side surfaces of the through holes. However, since the dry desmearing removes not only the inorganic filler but also the resin components constituting the insulating layer, the surface of the insulating layer may be roughened by the dry desmearing, which may deteriorate the insulating properties of the insulating layer. In the present disclosure, the dry desmearing is performed on an insulating layer with a metal protective film on its surface. The metal protective film is resistant to erosion by the dry desmearing and therefore functions as a protective film for the insulating layer against the dry desmearing. Therefore, it is possible to remove the inorganic filler exposed on the side surfaces of the through holes while suppressing the occurrence of roughness on the surface of the insulating layer. As a result, it is presumed that the occurrence of unevenness on the side surfaces of the through holes can be suppressed. In the present disclosure, the maximum particle length B of the inorganic filler contained in the insulating layer is 1 μm to 100 μm. When the maximum particle length B of the inorganic filler contained in the insulating layer is 1 μm to 100 μm, the strength of the insulating layer tends to be improved and thermal expansion tends to be suppressed, but the irregularities caused by the inorganic filler on the side surfaces of the through holes tend to be large, and the shape of the through holes tends to be deteriorated. The method for manufacturing a semiconductor device of the present disclosure is also effective when forming through holes in an insulating layer containing an inorganic filler with a large particle diameter.

[0017] The manufacturing method of the semiconductor device of the present disclosure will be described in detail below. In the following manufacturing method, an insulating layer having a metal protective film on its surface is provided on a substrate by providing the insulating layer on a substrate, roughening the surface of the insulating layer, and disposing the metal protective film on the roughened surface of the insulating layer. However, the method for providing the insulating layer having a metal protective film on its surface on a substrate is not limited to the above-described method. In the following manufacturing method, a through hole is formed by photolithographically removing a region of the metal protective film corresponding to the location where the through hole will be provided, and then performing laser processing on the removed portion of the metal protective film. However, the method for forming the through hole is not limited to the above-described method. The sizes of the components in each figure are conceptual, and the relative size relationships between the components are not limited thereto. Furthermore, components having substantially the same function are assigned the same reference numerals throughout the drawings, and redundant explanations may be omitted.

[0018] 1 is a cross-sectional view showing an insulating layer 14 containing an inorganic filler 12 having an average maximum particle length B of 1 μm to 100 μm provided on a semiconductor substrate 10, which is an example of a base. The insulating layer 14 is, for example, a cured product of an epoxy resin composition. Examples of the base include semiconductor substrates such as silicon substrates, as well as FO-WLP, WLCSP (Wafer Level Chip Scale Package), FI-WLP (Fan In Wafer Level Package), glass substrates, glass epoxy substrates such as FR-4 substrates, polyester substrates, polyimide substrates, BT resin substrates, and polyphenylene ether substrates.

[0019] From the viewpoint of ensuring insulation, the average thickness of the insulating layer 14 is preferably 5 μm or more, more preferably 10 μm or more, and even more preferably 20 μm or more. From the viewpoint of thinning the semiconductor device, the average thickness of the insulating layer 14 is preferably 200 μm or less, more preferably 100 μm or less, and even more preferably 50 μm or less. The average thickness of the insulating layer 14 is preferably 5 μm to 200 μm, more preferably 10 μm to 100 μm, and even more preferably 20 μm to 50 μm.

[0020] The composition of the epoxy resin composition constituting the insulating layer 14 is not particularly limited, but an epoxy resin composition that is solid at 25° C. is preferred. The epoxy resin composition contains, for example, an epoxy resin, a curing agent, and an inorganic filler, and may contain other components as necessary.

[0021] The epoxy resin composition of the present disclosure contains an epoxy resin. The type of epoxy resin is not particularly limited as long as it has two or more epoxy groups in one molecule. Specifically, novolac epoxy resins (phenol novolac epoxy resins, orthocresol novolac epoxy resins, etc.) are obtained by epoxidizing novolac resins obtained by condensing or co-condensing, under an acid catalyst, at least one phenolic compound selected from the group consisting of phenolic compounds such as phenol, cresol, xylenol, resorcinol, catechol, bisphenol A, bisphenol F, etc., and naphthol compounds such as α-naphthol, β-naphthol, dihydroxynaphthalene, etc., with an aliphatic aldehyde compound such as formaldehyde, acetaldehyde, propionaldehyde, etc.; triphenylmethane epoxy resins are obtained by epoxidizing triphenylmethane phenolic resins obtained by condensing or co-condensing, under an acid catalyst, the above-mentioned phenolic compounds with aromatic aldehyde compounds such as benzaldehyde, salicylaldehyde, etc.; and novolac resins obtained by co-condensing, under an acid catalyst, the above-mentioned phenolic compounds and naphthol compounds with an aldehyde compound, etc., are epoxidized. diphenylmethane-type epoxy resins which are diglycidyl ethers of bisphenol A, bisphenol F, or the like; biphenyl-type epoxy resins which are diglycidyl ethers of alkyl-substituted or unsubstituted biphenols; stilbene-type epoxy resins which are diglycidyl ethers of stilbene-based phenolic compounds; sulfur-containing epoxy resins which are diglycidyl ethers of bisphenol S, or the like; epoxy resins which are glycidyl ethers of alcohols such as butanediol, polyethylene glycol, and polypropylene glycol; glycidyl ester-type epoxy resins which are glycidyl esters of polycarboxylic acids such as phthalic acid, isophthalic acid, and tetrahydrophthalic acid; glycidylamine-type epoxy resins in which active hydrogen bonded to nitrogen atoms of aniline, diaminodiphenylmethane, isocyanuric acid, or the like is substituted with a glycidyl group; and dicyclopentadiene-type epoxy resins obtained by epoxidizing a co-condensation resin of dicyclopentadiene and a phenolic compound.Alicyclic epoxy resins such as vinylcyclohexene diepoxide, 3,4-epoxycyclohexylmethyl-3,4-epoxycyclohexanecarboxylate, and 2-(3,4-epoxy)cyclohexyl-5,5-spiro(3,4-epoxy)cyclohexane-m-dioxane, which are produced by epoxidizing an intramolecular olefin bond; paraxylylene-modified epoxy resins, which are glycidyl ethers of paraxylylene-modified phenolic resins; metaxylylene-modified epoxy resins, which are glycidyl ethers of metaxylylene-modified phenolic resins; terpene-modified epoxy resins, which are glycidyl ethers of terpene-modified phenolic resins; and dicyclopentadiene-modified phenolic resins, which are glycidyl ethers of dicyclopentadiene-modified phenolic resins. Examples of suitable epoxy resins include pentadiene-modified epoxy resins, cyclopentadiene-modified epoxy resins which are glycidyl ethers of cyclopentadiene-modified phenolic resins, polycyclic aromatic ring-modified epoxy resins which are glycidyl ethers of polycyclic aromatic ring-modified phenolic resins, naphthalene-type epoxy resins which are glycidyl ethers of naphthalene ring-containing phenolic resins, halogenated phenol novolac-type epoxy resins, hydroquinone-type epoxy resins, trimethylolpropane-type epoxy resins, linear aliphatic epoxy resins obtained by oxidizing olefin bonds with peracids such as peracetic acid, and aralkyl-type epoxy resins obtained by epoxidizing aralkyl-type phenolic resins such as phenol aralkyl resins and naphthol aralkyl resins. Further examples of suitable epoxy resins include epoxidized silicone resins and aminophenol-type epoxy resins which are glycidyl ethers of aminophenols. These epoxy resins may be used alone or in combination of two or more.

[0022] The epoxy resin composition of the present disclosure contains a curing agent. The type of curing agent is not particularly limited, as long as it is a compound that undergoes a curing reaction with the epoxy resin used in combination. For example, curing agents used in combination with the epoxy resin include phenolic curing agents, amine curing agents, acid anhydride curing agents, polymercaptan curing agents, polyaminoamide curing agents, isocyanate curing agents, and blocked isocyanate curing agents. One type of curing agent may be used alone, or two or more types may be used in combination. The curing agent may be solid or liquid at room temperature and normal pressure (e.g., 25°C, atmospheric pressure), and is preferably solid. From the viewpoint of heat resistance, the curing agent is preferably a phenolic curing agent or an amine curing agent. Examples of phenolic curing agents include phenolic resins and polyhydric phenol compounds having two or more phenolic hydroxyl groups per molecule.Specifically, the novolak type phenolic resins include polyhydric phenolic compounds such as resorcinol, catechol, bisphenol A, bisphenol F, and substituted or unsubstituted biphenols; novolak type phenolic resins obtained by condensing or co-condensing at least one phenolic compound selected from the group consisting of phenolic compounds such as phenol, cresol, xylenol, resorcinol, catechol, bisphenol A, bisphenol F, phenylphenol, and aminophenol, and naphthol compounds such as α-naphthol, β-naphthol, and dihydroxynaphthalene, with an aldehyde compound such as formaldehyde, acetaldehyde, or propionaldehyde, under an acidic catalyst; and phenolic compounds synthesized from the above phenolic compounds and dimethoxyparaxylene, bis(methoxymethyl)biphenyl, or the like. Examples of suitable phenolic curing agents include aralkyl-type phenolic resins such as aryl aralkyl resins and naphthol aralkyl resins; paraxylylene-modified phenolic resins; metaxylylene-modified phenolic resins; melamine-modified phenolic resins; terpene-modified phenolic resins; dicyclopentadiene-type phenolic resins and dicyclopentadiene-type naphthol resins synthesized by copolymerization of the above-mentioned phenolic compounds with dicyclopentadiene; cyclopentadiene-modified phenolic resins; polycyclic aromatic ring-modified phenolic resins; biphenyl-type phenolic resins; triphenylmethane-type phenolic resins obtained by condensing or co-condensing the above-mentioned phenolic compounds with aromatic aldehyde compounds such as benzaldehyde and salicylaldehyde under an acidic catalyst; and phenolic resins obtained by copolymerizing two or more of these. Furthermore, examples of phenolic curing agents include monohydric phenolic compounds having one phenolic hydroxyl group per molecule. These phenolic curing agents may be used alone or in combination of two or more.

[0023] Specific examples of the amine curing agent include aliphatic amine compounds such as diethylenetriamine, triethylenetetramine, n-propylamine, 2-hydroxyethylaminopropylamine, cyclohexylamine, and 4,4'-diamino-dicyclohexylmethane, aromatic amine compounds such as diethyltoluenediamine, 3,3'-diethyl-4,4'-diaminodiphenylmethane, dimethylthiotoluenediamine, and 2-methylaniline, and imidazoline compounds such as imidazoline, 2-methylimidazoline, and 2-ethylimidazoline. Among these, aromatic amine compounds are preferred from the viewpoint of storage stability, and diethyltoluenediamine, 3,3'-diethyl-4,4'-diaminodiphenylmethane, and dimethylthiotoluenediamine are more preferred.

[0024] The functional group equivalent of the curing agent (hydroxyl group equivalent in the case of a phenolic curing agent, and active hydrogen equivalent in the case of an amine-based curing agent) is not particularly limited. From the viewpoint of the balance of various properties such as moldability, heat resistance, and electrical reliability, it is preferably 10 g / eq to 1000 g / eq, and more preferably 30 g / eq to 500 g / eq. In the case of a phenolic curing agent, the hydroxyl group equivalent refers to a value calculated based on the hydroxyl value measured in accordance with JIS K0070:1992. In the case of an amine-based curing agent, the active hydrogen equivalent refers to a value calculated based on the amine value measured in accordance with JIS K7237:1995.

[0025] In an epoxy resin composition, when the curing agent includes a phenolic curing agent, the epoxy resin composition may or may not include a curing accelerator. The type of curing accelerator is not particularly limited and can be selected depending on the type of epoxy resin, the desired properties of the epoxy resin composition, and the like. The curing accelerator is not particularly limited. For example, the curing accelerator may be at least one selected from the group consisting of an amine-based curing accelerator, an imidazole-based curing accelerator, a urea-based curing accelerator, and a phosphorus-based curing accelerator. Examples of amine-based curing accelerators include 1,8-diazabicyclo[5.4.0]-7-undecene and 1,5-diazabicyclo[4.3.0]-5-nonene. Examples of imidazole-based curing accelerators include 2-phenyl-4-methylimidazole, 2-ethyl-4-methylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, 2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2-phenyl-4-methyl-5-hydroxymethylimidazole, etc. Examples of urea-based curing accelerators include 3-phenyl-1,1-dimethylurea, etc. Examples of the phosphorus-based curing accelerator include triphenylphosphine and its addition reaction products, diphenyl(p-tolyl)phosphine, tris(alkylphenyl)phosphine, tris(alkoxyphenyl)phosphine, tris(alkylalkoxyphenyl)phosphine, tris(dialkylphenyl)phosphine, tris(trialkylphenyl)phosphine, tris(tetraalkylphenyl)phosphine, tris(dialkoxyphenyl)phosphine, tris(trialkoxyphenyl)phosphine, tris(tetraalkoxyphenyl)phosphine, trialkylphosphine, dialkylarylphosphine, alkyldiarylphosphine, (4-hydroxyphenyl)diphenylphosphine, bis(4-hydroxyphenyl)phenylphosphine, and tris(4-hydroxyphenyl)phosphine.

[0026] When the epoxy resin composition contains a curing accelerator, the content of the curing accelerator is preferably 0.1% by mass to 8% by mass, more preferably 0.3% by mass to 6% by mass, and even more preferably 0.5% by mass to 5% by mass, based on the total amount of the epoxy resin and the curing agent.

[0027] The epoxy resin composition of the present disclosure contains an inorganic filler. The type of inorganic filler is not particularly limited. Specific examples include inorganic materials such as silica (e.g., spherical silica, crystalline silica), glass, alumina, calcium carbonate, zirconium silicate, calcium silicate, silicon nitride, aluminum nitride, boron nitride, aluminum nitride, boehmite, beryllia, magnesium oxide, zirconia, zircon, fosterite, steatite, spinel, mullite, titania, talc, clay, mica, and titanates. An inorganic filler having a flame-retardant effect may also be used. Examples of inorganic fillers having a flame-retardant effect include aluminum hydroxide, magnesium hydroxide, composite metal hydroxides (e.g., magnesium-zinc composite hydroxide), and zinc borate. Among these, spherical silica is preferred from the viewpoint of reducing the linear expansion coefficient, and alumina is preferred from the viewpoint of high thermal conductivity. The inorganic filler may be used alone or in combination of two or more types. The inorganic filler may be in the form of a powder, beads formed by spheroidizing powder, or fibers.

[0028] The average particle diameter of the inorganic filler is not particularly limited. For example, the volume average particle diameter is preferably 30 μm or less, more preferably 0.1 μm to 30 μm, even more preferably 0.2 μm to 25 μm, and particularly preferably 0.5 μm to 20 μm. When the volume average particle diameter is 30 μm or less, the filling property tends to be improved. Furthermore, when the volume average particle diameter is 0.1 μm or more, the increase in viscosity of the epoxy resin composition tends to be further suppressed. The volume average particle diameter of the inorganic filler can be measured as the volume average particle diameter (D50) using a laser diffraction scattering particle size distribution analyzer.

[0029] From the viewpoint of the flowability of the epoxy resin composition, the particle shape of the inorganic filler is preferably spherical rather than angular, and the particle size distribution of the inorganic filler is preferably wide.

[0030] The content of the inorganic filler in the epoxy resin composition is not particularly limited. From the viewpoint of fluidity and strength, it is preferably 60% by volume or more of the total solid content of the epoxy resin composition, more preferably 60 to 90% by volume, and even more preferably 62 to 88% by volume. When the content of the inorganic filler is 60% by volume or more of the total solid content of the epoxy resin composition, the properties of the cured product, such as the thermal expansion coefficient, thermal conductivity, and elastic modulus, tend to be further improved. When the content of the inorganic filler is 90% by volume or less of the total solid content of the epoxy resin composition, an increase in the viscosity of the epoxy resin composition is suppressed, and the fluidity is further improved, tending to result in better moldability.

[0031] (Colorant) The epoxy resin composition of the present disclosure may contain a colorant. Examples of colorants include known colorants such as carbon black, black titanium oxide, organic dyes, organic pigments, red lead, and red iron oxide. The content of the colorant can be appropriately selected depending on the purpose, etc. One type of colorant may be used alone, or two or more types may be used in combination.

[0032] When the epoxy resin composition contains a colorant, the content thereof is preferably 0.01% by mass to 5% by mass, and more preferably 0.05% by mass to 3% by mass.

[0033] (Ion Exchanger) The epoxy resin composition of the present disclosure may contain an ion exchanger. In particular, it is preferable to contain an ion exchanger from the viewpoint of improving the moisture resistance and high-temperature storage characteristics of the semiconductor device. The ion exchanger is not particularly limited, and conventionally known ion exchangers can be used. Specific examples include hydrotalcite compounds and hydrous oxides of at least one element selected from the group consisting of magnesium, aluminum, titanium, zirconium, and bismuth. The ion exchanger may be used alone or in combination of two or more types. Among these, hydrotalcites represented by the following general formula (A) are preferred.

[0034] Mg （１－Ｘ） Al Ｘ (OH) ２ (CO ３ ) Ｘ／２ ・mH ２ O ……(A) (0<X≦0.5, m is a positive number)

[0035] When the epoxy resin composition contains an ion exchanger, the content thereof is not particularly limited as long as it is an amount sufficient to capture ions such as halogen ions, etc. For example, the content is preferably 0.1 to 30 parts by mass, and more preferably 1 to 5 parts by mass, per 100 parts by mass of the epoxy resin.

[0036] (Mold Release Agent) The epoxy resin composition of the present disclosure may contain a mold release agent from the viewpoint of obtaining good mold releasability. There are no particular limitations on the mold release agent, and conventionally known mold release agents can be used. Specific examples include carnauba wax, higher fatty acids such as montanic acid and stearic acid, higher fatty acid metal salts, ester waxes such as montanic acid esters, and polyolefin waxes such as oxidized polyethylene and non-oxidized polyethylene. One type of mold release agent may be used alone, or two or more types may be used in combination.

[0037] When the epoxy resin composition contains a release agent, the content thereof is preferably 0.01 to 15 parts by mass, more preferably 0.1 to 10 parts by mass, per 100 parts by mass of the epoxy resin. When the amount of the release agent is 0.01 part by mass or more per 100 parts by mass of the epoxy resin, sufficient release properties tend to be obtained. When the amount of the release agent is 15 parts by mass or less per 100 parts by mass of the epoxy resin, better adhesion tends to be obtained.

[0038] (Flame Retardant) The epoxy resin composition of the present disclosure may contain a flame retardant. There are no particular limitations on the flame retardant, and conventionally known flame retardants can be used. Specific examples include organic or inorganic compounds containing halogen atoms, antimony atoms, nitrogen atoms, or phosphorus atoms, and metal hydroxides. One type of flame retardant may be used alone, or two or more types may be used in combination.

[0039] When the epoxy resin composition contains a flame retardant, the content thereof is not particularly limited as long as it is an amount sufficient to obtain the desired flame retardant effect. For example, the content is preferably 1 to 30 parts by mass, and more preferably 2 to 20 parts by mass, per 100 parts by mass of the epoxy resin.

[0040] (Stress Relaxant) The epoxy resin composition of the present disclosure may contain a stress relaxation agent such as silicone rubber particles. By including a stress relaxation agent in the epoxy resin composition, warpage deformation of the insulating layer and the occurrence of cracks in the insulating layer can be further reduced. Examples of stress relaxation agents include commonly used known stress relaxation agents (flexibilizers). Specific examples include thermoplastic elastomers such as silicone, styrene, olefin, urethane, polyester, polyether, polyamide, and polybutadiene, which may be epoxy-modified; rubber particles such as NR (natural rubber), NBR (acrylonitrile-butadiene rubber), acrylic rubber, urethane rubber, and silicone powder; rubber particles having a core-shell structure such as methyl methacrylate-styrene-butadiene copolymer (MBS), methyl methacrylate-silicone copolymer, and methyl methacrylate-butyl acrylate copolymer; and indene-containing copolymers, which are copolymer resins of indenes such as indene and alkylindene with styrenes such as styrene and alkylstyrene, and other monomers used as needed. The stress relaxation agents may be used alone or in combination of two or more.

[0041] When the epoxy resin composition contains a stress relaxation agent, the content thereof is preferably 0.1 to 30 parts by mass, and more preferably 1 to 25 parts by mass, per 100 parts by mass of the epoxy resin.

[0042] (Coupling Agent) The epoxy resin composition of the present disclosure may contain a coupling agent. The type of coupling agent is not particularly limited, and known coupling agents can be used. Examples of the coupling agent include silane coupling agents and titanium coupling agents. One type of coupling agent may be used alone, or two or more types may be used in combination.

[0043] When the epoxy resin composition contains a coupling agent, the content of the coupling agent is preferably 0.001 to 10 parts by mass, more preferably 0.01 to 8 parts by mass, and even more preferably 0.05 to 5 parts by mass, relative to 100 parts by mass of the inorganic filler, from the viewpoint of adhesion at the interface between the epoxy resin and the inorganic filler.

[0044] There are no particular limitations on the method for applying the epoxy resin composition onto the semiconductor substrate 10. For example, a solvent may be added to an epoxy resin composition to prepare a liquid epoxy resin composition, and the liquid epoxy resin composition may be applied to the semiconductor substrate 10 by bar coating, spin coating, or the like, and then dried. Alternatively, an adhesive film including a support and an epoxy resin composition layer provided on the support may be laminated on the semiconductor substrate 10 so that the epoxy resin composition layer is in contact with the semiconductor substrate 10.

[0045] The support is not particularly limited in shape or material as long as it allows for the formation of an epoxy resin composition layer thereon, and metal foil or resin film is preferred. Examples of metal foil include copper foil, aluminum foil, and nickel foil. Examples of resin films that can be used include plastic films such as polyethylene terephthalate film, polyimide film, polyethylene film, polypropylene film, polytetrafluoroethylene film, polymethylpentene film, polyamideimide film, polyetherimide film, polyethersulfone film, wholly aromatic polyester film, polytetrafluoroethylene film, ethylene-tetrafluoroethylene copolymer film, tetrafluoroethylene-hexafluoropropylene copolymer film, and tetrafluoroethylene-perfluoroalkylvinyl ether copolymer film. These plastic films can also be used after their surfaces have been subjected to a release treatment.

[0046] Alternatively, an epoxy resin composition may be applied to a support and dried to form an epoxy resin composition layer, and then a protective film may be laminated on the epoxy resin composition layer. By providing a protective film on the epoxy resin composition layer, the handleability of the adhesive film is improved. The same protective film as the support can be used. Among these, when the adhesive film is wound up by a highly productive roll coating method or the like, polyolefin films such as polyethylene films and polypropylene films are preferred as protective films because they are more flexible than polyethylene terephthalate films.

[0047] The epoxy resin composition can be applied to a support by any known method, such as dip coating, flow coating, spin coating, curtain coating, knife coating, roll coating, wire bar coating, doctor blade coating, comma blade coating, spray coating, ultrasonic coating, inkjet coating, die coating, gravure coating, screen printing, trowel coating, brush coating, sponge coating, etc. Among these, the comma blade method or kiss-touch roll coating is preferred, as it is highly productive and enables precise coating to a uniform thickness.

[0048] There are no particular restrictions on the temperature at which the epoxy resin composition applied to the support is dried. When the components are dissolved or dispersed in an organic solvent to form a varnish-like epoxy resin composition, drying at a temperature 10°C to 50°C lower than the boiling point of the organic solvent used is preferred from the viewpoint of suppressing the generation of bubbles in the adhesive film due to foaming of the organic solvent during drying. In this sense, the drying temperature is preferably 15°C to 45°C lower, more preferably 20°C to 40°C lower, than the boiling point of the organic solvent.

[0049] The semiconductor substrate 10 and the adhesive film may be laminated by a vacuum lamination method. In the vacuum lamination method, the thermocompression temperature is preferably 60°C to 160°C, more preferably 80°C to 140°C. The compression pressure is preferably 0.1 MPa to 2 MPa, more preferably 0.3 MPa to 1.5 MPa. The compression time is preferably 10 seconds to 500 seconds, more preferably 20 seconds to 400 seconds. The lamination is preferably performed under reduced pressure conditions of 30 hPa or less.

[0050] The curing conditions for the epoxy resin composition layer are not particularly limited. The heat treatment temperature is preferably 120°C to 200°C, more preferably 130°C to 180°C, and even more preferably 140°C to 170°C. The heat treatment time is preferably 5 minutes to 3 hours, and more preferably 10 minutes to 2 hours. By curing the epoxy resin composition layer, an insulating layer 14 is formed on the semiconductor substrate 10. Other methods for forming the insulating layer 14 on the semiconductor substrate 10 include transfer molding, injection molding, compression molding, and the like, which are methods for encapsulating electronic component devices using an epoxy resin composition.

[0051] 2 is a cross-sectional view showing a state in which the surface of the insulating layer 14 has been roughened. The method for roughening the insulating layer 14 is not particularly limited, and may be a dry method or a wet method. Dry roughening methods include mechanical polishing using buffing or sandblasting, grinding using a grindstone, and CF ４ Gas, SF ６ Examples of the wet roughening method include a plasma etching treatment using a gas or the like. Examples of the wet roughening method include a chemical treatment using an oxidizing agent such as permanganate, dichromate, ozone, hydrogen peroxide / sulfuric acid, or nitric acid, a strong base, or a resin swelling solvent. The wet roughening method may be a wet desmear treatment described later. The surface of the insulating layer 14 is preferably roughened by at least one treatment selected from the group consisting of grinding, a chemical treatment, and a plasma etching treatment.

[0052] The surface roughness Ra of the roughened insulating layer 14 is preferably 0.1 μm to 2.0 μm, more preferably 0.2 μm to 0.5 μm, even more preferably 0.2 μm to 0.4 μm, and particularly preferably 0.2 μm to 0.3 μm. In the present disclosure, the surface roughness Ra refers to a value measured in accordance with JIS B0601:2013.

[0053] FIG. 3 is a cross-sectional view showing a state in which a metal protective film 16 is provided on the roughened surface of the insulating layer 14. The method for forming the metal protective film 16 on the surface of the insulating layer 14 is not particularly limited and may be a dry or wet method, appropriately selected depending on the type of metal constituting the metal protective film 16. Examples of metals constituting the metal protective film 16 include copper, copper alloys, and titanium. Dry metal deposition methods include physical methods such as vacuum deposition and sputtering, and chemical methods such as chemical vapor deposition (CVD). Vacuum deposition is a method in which a film-forming material is heated and evaporated by resistance heating or electron gun irradiation to form a thin film on a target object. Sputtering is a method in which a voltage is applied between an anode and a cathode to ionize an inert gas such as Ar, colliding the inert gas ions with a target material placed on the cathode side to scatter the target material, and then depositing the scattered target material on the target placed on the anode side. Wet methods include electroless plating and electrolytic plating. Electroless plating and electrolytic plating may be combined. The protective metal film is preferably formed by at least one method selected from the group consisting of metal vapor deposition, electroless plating, and electrolytic plating. The protective metal film may be one layer or two or more layers. When the protective metal film is composed of two or more layers, the types of metals contained in each layer may be the same or different.

[0054] The average thickness of the metallic protective film 16 is preferably 0.1 μm to 2.0 μm, more preferably 0.1 μm to 1.0 μm, and even more preferably 0.1 μm to 0.5 μm. When the metallic protective film 16 is composed of two or more layers, the average thickness of the metallic protective film 16 refers to the average thickness of the entire metallic protective film 16 composed of two or more layers.

[0055] 4 is a diagram showing a state in which the metal protective film 16 provided on the surface of the insulating layer 14 has been partially removed from a region (region Q) corresponding to the location where the through hole will be provided. The method for partially removing the metal protective film 16 is not particularly limited, and the metal protective film 16 can be partially removed by photolithography, which is a well-known technique (laminating a dry film resist (DFR), curing with ultraviolet light, developing the DFR, etching the metal protective film 16, and peeling off the DFR).

[0056] The shape of the region Q when observed from the thickness direction of the insulating layer 14 may be matched to the shape of the through holes to be formed in the insulating layer 14, and the shapes of the through holes and the region Q are generally circular. The ratio (Q / A) of the average diameter Q of the region Q when observed from the thickness direction of the insulating layer 14 to the average diameter A of the through holes to be formed in the insulating layer 14 is preferably 1.0 to 1.5, more preferably 1.0 to 1.2, and even more preferably 1.0 to 1.1. In the present disclosure, the diameter of a through hole refers to the circle-equivalent diameter of the narrowest point of the through hole when observed from the thickness direction of the insulating layer 14. In addition, in the present disclosure, the average diameter A of the through holes refers to the arithmetic average of the circle-equivalent diameters of five through holes. Furthermore, the average diameter Q of the region Q refers to the arithmetic average of the circle-equivalent diameters for the five regions Q. For example, when the cross-sectional shape of the through holes is tapered as shown in FIG. 6 described later, the average diameter A of the through holes refers to the arithmetic mean of the diameters of the bottoms of the through holes, as shown in FIG. 6 described later.

[0057] FIG. 5 is a cross-sectional view showing a state in which through holes 18 are provided in the surface of the insulating layer 14. The through holes 18 can be formed in the insulating layer 14 by laser processing or the like. Among these, laser processing is preferred from the viewpoint of suppressing damage to the wiring. When the through holes 18 are formed by laser processing, examples of the laser that can be used include a carbon dioxide laser (CO ２ Examples of lasers include UV lasers, YAG lasers, and excimer lasers. The wavelength, number of pulses, pulse width, output, and the like of the laser are selected in accordance with the diameter of the through-hole 18.

[0058] In the method for manufacturing a semiconductor device according to the present disclosure, when the average diameter of the through holes 18 is A, it is preferable that A and B satisfy the following relational expression (II). When A and B satisfy the following relational expression (II), the through holes 18 are less likely to be blocked by the inorganic filler 12 exposed on the side surfaces, the bonding strength of the conductor formed in the through holes to the insulating layer is ensured, and the reliability of the multilayer wiring tends to be improved. The ratio (A / B) of the average diameter A to the average maximum particle length B is preferably 3.1 to 10.0, more preferably 3.5 to 8.0, and even more preferably 4.0 to 6.0. A>3B (II)

[0059] 6 is a cross-sectional view showing a state after a dry desmear treatment has been performed on the insulating layer 14 having the through holes 18 formed therein. As shown in FIG. 5, the inorganic filler 12 may be exposed on the side surfaces of the through holes 18 formed in the insulating layer 14 by laser processing or the like. In areas of the insulating layer 14 other than the areas where the through holes 18 are formed, the metal protective film 16 remains provided on the surface of the insulating layer 14. Because the metal protective film 16 is resistant to the dry desmear treatment, when the insulating layer 14 is subjected to the dry desmear treatment, the side surfaces of the through holes 18 are treated intensively, and the unevenness on the side surfaces of the through holes 18 caused by the inorganic filler 12 is reduced.

[0060] The dry desmear treatment may be, for example, a desmear treatment using plasma. Alternatively, the dry desmear treatment may be a dry sandblasting treatment in which an abrasive is sprayed from a nozzle to polish the treatment target. Among these, a desmear treatment using plasma is preferred because it has excellent removability of the inorganic filler 12. The gas species used in the desmear treatment using plasma include O ２ , C.F. ４ , C ２ F ４ , C ３ F ８ , N.F. ３ , H ２ , Ar, N ２and mixed gases thereof. The atmospheric pressure when performing the desmear treatment using plasma is preferably 200 Pa or less, more preferably 150 Pa or less, and even more preferably 100 Pa or less. The treatment time when performing the desmear treatment using plasma is preferably 0.5 to 30.0 minutes, and more preferably 1.0 to 10.0 minutes.

[0061] The dry desmear treatment is preferably carried out until the average height C of the convex portions originating from the inorganic filler 12 on the surface of the through-hole 18 and the average maximum particle length B of the inorganic filler 12 satisfy the following relational expression (I). By carrying out the dry desmear treatment until B and C satisfy the following relational expression (I), the occurrence of irregularities on the side surface of the through-hole 18 is further suppressed. The ratio (B / C) of the average maximum particle length B to the average height C of the convex portions is preferably 2.1 to 4.0, more preferably 2.3 to 3.5, and even more preferably 2.5 to 3.0. B>2C (I)

[0062] At least one of a wet desmear treatment and a plasma ashing treatment may be further performed before the dry desmear treatment. By performing at least one of a wet desmear treatment and a plasma ashing treatment before the dry desmear treatment, it is possible to efficiently remove smears derived from resin components generated during the formation of the through holes 18, and it is possible to improve the bonding strength of the wiring layer formed in the through holes 18 to the insulating layer 14. An example of the wet desmear treatment is a method in which a swelling treatment is performed on the insulating layer 14, and the smear is oxidatively decomposed with an alkaline permanganate solution or a chromate solution, followed by a neutralization treatment and a water washing treatment. An example of the plasma ashing treatment is the desmear treatment using plasma described above.

[0063] After the dry desmear treatment, a wiring layer is formed on the insulating layer 14. The wiring layer can be formed by a method for forming a metal pattern known in the field of printed wiring boards, such as a subtractive method or a semi-additive method.

[0064] When forming a wiring layer on the insulating layer 14, the wiring layer may be formed after removing the metal protective film 16, or the wiring layer may be formed on the metal protective film 16 by the above-mentioned method. When the wiring layer is formed on the metal protective film 16, the metal protective film 16 constitutes part of the wiring layer. By forming the wiring layer on the insulating layer 14, a wiring layer is also formed on the side surface of the through hole 18. The wiring layer on the side surface of the through hole 18 functions as a conductor present inside the through hole 18. Examples of metals that constitute the wiring layer include copper, titanium, silver, gold, and alloys thereof. By repeatedly forming the insulating layer 14 and the wiring layer, a multilayer wiring is formed in which adjacent wiring layers are electrically connected via the insulating layer 14 via the conductor in the through hole 18.

[0065] In Figure 3, the insulating layer 14 having a metal protective film 16 on its surface may be provided on the semiconductor substrate 10 using a metal foil-attached adhesive film having an epoxy resin composition layer and a metal foil in that order. The epoxy resin composition layer in the metal foil-attached adhesive film is brought into contact with the semiconductor substrate 10, and then the epoxy resin composition layer is cured, thereby providing the insulating layer 14 having a metal protective film 16 on its surface on the semiconductor substrate 10. As the metal foil-attached adhesive film, one in which an epoxy resin composition layer is formed on a metal foil as a support can be used. Details of the metal foil and epoxy resin composition that constitute the metal foil-attached adhesive film, and the method for forming the epoxy resin composition layer, are as described above.

[0066] In Figure 4, in region Q, the metal protective film 16 has been partially removed in advance, but if a laser processing method that can form the through hole 18 in the insulating layer 14 while the metal protective film 16 is present is selected as the method for forming the through hole 18, it is not necessarily necessary to form region Q.

[0067] As shown in FIG. 6, the height C of the protrusions derived from the inorganic filler 12 refers to the height from the side of the through hole 18 of the inorganic filler 12 protruding from the side of the through hole 18 in the cross section of the through hole 18. The average height C of the protrusions derived from the inorganic filler 12 is determined by determining the height C of the protrusions derived from the inorganic filler 12 in each of five cross-sectional photographs of the through hole 18, and the arithmetic average of the heights C at the top three locations (a total of 15 heights C) is defined as the average height C of the protrusions derived from the inorganic filler 12. Furthermore, the average maximum particle length B of the inorganic filler is determined by determining the particle length B of the inorganic filler 12 in each of five cross-sectional photographs of the through hole 18, and the arithmetic average of the particle lengths B of the inorganic filler 12 at the top three locations (a total of 15 particle lengths B) is defined as the average maximum particle length B of the inorganic filler. The average maximum particle length B of the inorganic filler is preferably 1 μm to 50 μm, more preferably 1 μm to 30 μm, and even more preferably 5 μm to 10 μm.

[0068] <Method for Manufacturing a Printed Wiring Board> The semiconductor device manufacturing method of the present disclosure can also be applied to the manufacture of printed wiring boards. That is, the method for manufacturing a printed wiring board of the present disclosure is a method for manufacturing a printed wiring board having multilayer wiring in which wiring layers and insulating layers are alternately stacked, in which adjacent wiring layers separated by an insulating layer in the stacking direction are electrically connected via conductors present in through holes provided in the insulating layer. The multilayer wiring is formed by providing, on a substrate, an insulating layer having a metal protective film on its surface and containing an inorganic filler having an average maximum particle length B of 1 μm to 100 μm, forming through holes in the insulating layer, and subjecting the insulating layer with the through holes to a dry desmear treatment. In the method for manufacturing a printed wiring board of the present disclosure, for example, a multilayer wiring can be formed in the same manner as in FIG. 1 , except that the semiconductor substrate 10 is replaced with a core substrate, thereby obtaining a printed wiring board as a multilayer wiring board. Examples of core substrates include glass epoxy substrates such as FR-4 substrates, polyester substrates, polyimide substrates, BT resin substrates, and polyphenylene ether substrates.

[0069] <Semiconductor Device> The semiconductor device disclosed herein has a semiconductor element and multilayer wiring in which wiring layers and insulating layers electrically connected to the semiconductor element are alternately stacked, and adjacent wiring layers sandwiching an insulating layer in the stacking direction are electrically connected via conductors present in through holes provided in the insulating layer, and the insulating layer contains an inorganic filler having an average maximum particle length B of 1 μm to 100 μm, and satisfies the following relationship formulas (I) and (II) where C is the average height of protrusions originating from the inorganic filler on the side surface of the through holes and A is the average diameter of the through holes: B>2C (I) A>3B (II)

[0070] Since the semiconductor device of the present disclosure satisfies the relational expressions (I) and (II), the occurrence of unevenness on the side surface of the through hole is suppressed. As a result, the bonding strength of the conductor present in the through hole to the insulating layer is ensured, and the reliability of the multilayer wiring tends to be improved. The method for forming the multilayer wiring of the semiconductor device is not particularly limited, and the multilayer wiring may be formed by the manufacturing method of the semiconductor device of the present disclosure.

[0071] The present disclosure will be specifically described below using examples, but the scope of the present disclosure is not limited to these examples.

[0072] Example 1 Formation of an Insulating Layer A substrate was prepared from a copper-clad laminate (Showa Denko Materials K.K., MCL-E-679FG) having a base material thickness of 0.81 mm and a copper thickness of 18 μm, on the surface of the substrate on which copper wiring was formed. An insulating layer was formed as a cured product of an epoxy resin composition (containing 76% by volume of silica particles having a volume average particle size of 5.7 μm as an inorganic filler) using a compression molding machine (TOWA Corporation, CMP-1000) under conditions of a load of 3 MPa, a pressure time of 600 seconds, a temperature of 150°C, and an average molding thickness of 0.1 mm. The average maximum particle length B of the inorganic filler in the insulating layer was 23 μm.

[0073] [Formation of Metal Protective Film] The surface of the insulating layer obtained above was roughened by wet desmearing. The surface roughness Ra of the roughened insulating layer was measured using a contact profilometer (Bruker DektakXT) in accordance with JIS B0601:2013, and was found to be 0.32 μm. Titanium and copper were deposited in this order on the roughened insulating layer using a sputtering apparatus (ULVAC, SIC-500) under conditions of a titanium thickness of 25 nm and a copper thickness of 150 nm, forming a metal protective film.

[0074] [Partial Removal of Metal Protective Film] A dry film resist (Showa Denko Materials Co., Ltd., RD-1215) was laminated onto the surface of the metal protective film provided on the insulating layer using a vacuum laminator (Nikko Materials Co., Ltd., CV-300) under conditions of a load of 0.5 MPa and a temperature of 60°C. The resist was then exposed using a photomask and a UV exposure machine (Mikasa Co., Ltd., ML-320) and developed with a 1% by mass aqueous solution of sodium carbonate to form a φ0.15 mm pattern corresponding to the region (region Q) where the through-holes would be provided. Thereafter, a seed etching solution (Mitsubishi Gas Chemical Company, Inc., WLC-C2) was used to remove the portion of the metal protective film corresponding to region Q. The dry film resist was then stripped using a stripper (Mitsubishi Gas Chemical Company, Inc., R-100S, R-100) to obtain an insulating layer having a metal protective film with a φ0.15 mm region Q formed on its surface.

[0075] [Formation of Through Holes] CO ２ Through holes having a diameter of 0.15 mm were formed by laser processing using a laser processing machine under the conditions that the laser penetrated the insulating layer but did not penetrate the copper wiring on the copper-clad laminate. The average diameter A of the through holes was 132 μm.

[0076] [Dry desmearing] The insulating layer having through holes formed therein was subjected to dry desmearing under conditions such that the surface of the inorganic filler contained in the insulating layer was scraped to satisfy the following relational expression (I), where B is the average maximum particle length of the inorganic filler and C is the average height of the protrusions on the side surfaces of the through holes resulting from the inorganic filler. ４The desmear treatment using plasma was adopted. B>2C (I)

[0077] [Formation of wiring layer] After dry desmearing, wiring was formed on the insulating layer having through holes by a semi-additive (SAP) method, and the wiring on the insulating layer and the copper wiring on the substrate were connected. In the obtained multilayer wiring, the average height C of the protrusions originating from the inorganic filler on the side surfaces of the through holes was 8 μm.

[0078] Comparative Example 1: Wiring on an insulating layer and copper wiring on a substrate were connected in the same manner as in Example 1, except that the formation of a metal protective film and the partial removal of the metal protective film were not performed. In the resulting multilayer wiring, the average height C of the protrusions originating from the inorganic filler on the side surfaces of the through holes was 17 μm.

[0079] All publications, patent applications, and technical standards mentioned in this specification are incorporated by reference into this specification to the same extent as if each individual publication, patent application, or technical standard was specifically and individually indicated to be incorporated by reference.

[0080] REFERENCE SIGNS LIST 10 semiconductor substrate 12 inorganic filler 14 insulating layer 16 metal protective film 18 through hole Q region corresponding to the location where the through hole is provided

Claims

1. A method for manufacturing a semiconductor device having multi-layer wiring in which wiring layers and insulating layers are alternately stacked, comprising the steps of: the wiring layers adjacent to each other in the stacking direction with the insulating layer interposed therebetween are electrically connected to each other via a conductor present in a through hole provided in the insulating layer, The multilayer wiring includes an insulating layer having a metal protective film on a surface thereof and containing an inorganic filler having an average maximum particle length B of 1 μm to 100 μm, the insulating layer being provided on a substrate; forming a through hole in the insulating layer; and performing a dry desmear treatment on the insulating layer in which the through hole is formed.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the dry desmear treatment is performed until an average height C of a convex portion on a side surface of the through hole originating from the inorganic filler and an average maximum particle length B of the inorganic filler satisfy the following relationship (I): B>2C (I)

3. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the following relational expression (II) is satisfied, where A is an average diameter of the through holes: A>3B (II)

4. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the through hole is formed by at least one method selected from the group consisting of laser processing and photolithography.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the through hole is formed by removing an area of ​​the metal protective film corresponding to a location where the through hole is to be provided by the photolithography, and then performing the laser processing on the removed area of ​​the metal protective film.

6. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the through hole is formed by performing the laser processing in a state where the metal protective film is present on the surface of the insulating layer.

7. The insulating layer having the metal protective film on a surface thereof is provided on the substrate; roughening a surface of the insulating layer; 3. The method for manufacturing a semiconductor device according to claim 1, wherein the metal protective film is provided on the substrate through a step of disposing the metal protective film on a roughened surface of the insulating layer.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the surface of the insulating layer is roughened by at least one treatment selected from the group consisting of grinding, chemical treatment, and plasma etching.

9. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the metal protective film is formed by at least one method selected from the group consisting of metal vapor deposition, electroless plating, and electrolytic plating.

10. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the roughened surface of the insulating layer has a surface roughness Ra of 0.1 μm to 2.0 μm.

11. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is a cured product of an epoxy resin composition.

12. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer having the metal protective film on its surface is provided on the substrate by contacting the epoxy resin composition layer of a metal foil-attached adhesive film having an epoxy resin composition layer and a metal foil in that order with the substrate, and then curing the epoxy resin composition layer.

13. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising forming a wiring layer on the insulating layer that has been subjected to the dry desmear treatment.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the wiring layer is formed after removing the metal protective film from the surface of the insulating layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein the wiring layer is formed on the metal protective film.

16. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: performing at least one of a wet desmear process and a plasma ashing process before the dry desmear process.

17. A semiconductor element; a multilayer wiring in which wiring layers and insulating layers electrically connected to the semiconductor element are alternately laminated, the wiring layers adjacent to each other in the stacking direction with the insulating layer interposed therebetween are electrically connected to each other via a conductor present in a through hole provided in the insulating layer, the insulating layer contains an inorganic filler having an average maximum particle length B of 1 μm to 100 μm; A semiconductor device that satisfies the following relational expressions (I) and (II), where C is the average height of the protrusions on the side surfaces of the through holes originating from the inorganic filler, and A is the average diameter of the through holes. B>2C (I) A>3B (II)