Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a first semiconductor element; a second semiconductor element; an insulation element which includes a first coil; a second coil which is magnetically coupled to the first coil; and a supporting substrate on which the first semiconductor element and the second semiconductor element are mounted. The supporting substrate includes an insulating base material and substrate wiring which is formed on the base material. The substrate wiring includes a first wiring part which is electrically interposed between the first semiconductor element and the first coil, and a second wiring part which is electrically interposed between the second semiconductor element and the second coil. The second coil is disposed between the first coil and the base material. The insulation element is supported by the supporting substrate.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] There are semiconductor devices for driving switching elements such as IGBTs (insulated gate bipolar transistors) or MOSFETs (metal oxide semiconductor field effect transistors). Patent Document 1 (Patent Document 1) discloses an example of such a semiconductor device (switch control device). The switch control device described in Patent Document 1 includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a first island, and a second island. The first semiconductor chip is a controller chip and integrates a controller that generates a switch control signal based on an input signal. The second semiconductor chip is a driver chip and integrates a driver that controls the drive of a switch based on a switch control signal input from the first semiconductor chip via the third semiconductor chip. A power supply voltage higher than that of the first semiconductor chip is applied to the second semiconductor chip. The third semiconductor chip is, for example, a transformer chip and integrates a transformer that transfers switch control signals and the like while providing DC insulation between the first and second semiconductor chips. The first island is equipped with the first semiconductor chip and the third semiconductor chip, and the second island is equipped with the second semiconductor chip. The switch control device described in Patent Document 1 separates the power supply systems from each other by separating the first island and the second island from each other, with the first island being a low-voltage side island and the second island being a high-voltage side island.

[0003] JP 2012-257421 A

[0004] In recent years, there has been an increasing demand for miniaturization of semiconductor devices for applications such as electric vehicles. However, in the switch control device described in Patent Document 1, when the device is miniaturized, the distance between the first island and the second island may become small. In this case, it becomes difficult to ensure a sufficient distance between the first island and the second island. Therefore, when the switch control device described in Patent Document 1 is miniaturized, there is a concern that the withstand voltage of the device may decrease.

[0005] The present disclosure has been devised in view of the above circumstances, and one object of the present disclosure is to provide a semiconductor device that can suppress a decrease in dielectric strength voltage even when miniaturization is attempted.

[0006] The semiconductor device of the present disclosure comprises a first semiconductor element, a second semiconductor element, an insulating element including a first coil, a second coil magnetically coupled to the first coil, and a support substrate on which the first semiconductor element and the second semiconductor element are mounted, the support substrate including an insulating base material and substrate wiring formed on the base material, the substrate wiring including a first wiring portion electrically interposed between the first semiconductor element and the first coil, and a second wiring portion electrically interposed between the second semiconductor element and the second coil, the second coil being disposed between the first coil and the base material, and the insulating element being supported by the support substrate.

[0007] According to the semiconductor device of the present disclosure, even when miniaturization is attempted, a decrease in dielectric strength voltage can be suppressed.

[0008] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a view in which the sealing resin is omitted from the plan view of FIG. 1. FIG. 3 is a view in which the first semiconductor element, the second semiconductor element, and the insulating element are shown in imaginary lines in the plan view of FIG. 2. FIG. 4 is a front view showing a semiconductor device according to the first embodiment. FIG. 5 is a left side view showing a semiconductor device according to the first embodiment. FIG. 6 is a right side view showing a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a partially enlarged cross-sectional view of a portion of FIG. 7 (near the first semiconductor element). FIG. 9 is a partially enlarged cross-sectional view of a portion of FIG. 7 (near the second semiconductor element). FIG. 10 is a partially enlarged cross-sectional view of a portion of FIG. 7 (near the insulating element). FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 2. FIG. 12 is an exploded perspective view showing an example configuration of the insulating element. FIG. 13 is a plan view showing a semiconductor device according to a second embodiment, in which the sealing resin is omitted. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13 . FIG. 15 is a plan view showing a semiconductor device according to the third embodiment, with the sealing resin omitted. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15 . FIG. 17 is a plan view showing a semiconductor device according to a modification of the third embodiment, with the sealing resin omitted. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17 . FIG. 19 is a cross-sectional view showing a semiconductor device according to the fourth embodiment, corresponding to the cross section of FIG. 7 . FIG. 20 is a partially enlarged cross-sectional view of a portion (near the insulating element) of FIG. 19 . FIG. 21 is a cross-sectional view showing a semiconductor device according to the fourth embodiment, corresponding to the cross section of FIG. 11 . FIG. 22 is an enlarged cross-sectional view of a main portion of a semiconductor device according to a modification of the fourth embodiment. FIG. 23 is a cross-sectional view showing a semiconductor device according to a modification, corresponding to the cross section of FIG. 7 . FIG. 24 is a cross-sectional view showing a semiconductor device according to a modification, corresponding to the cross section of FIG. 7 . Fig. 25 is a cross-sectional view of a main part showing an insulating element according to a modified example, and corresponds to the cross section of Fig. 10. Fig. 26 is a cross-sectional view showing a semiconductor device according to a modified example, and corresponds to the cross section of Fig. 7. Fig. 27 is a cross-sectional view showing a semiconductor device according to a modified example, and corresponds to the cross section of Fig. 7. Fig. 28 is a plan view showing a configuration example of an insulating element (first coil and second coil) according to a modified example.29 and 30 are plan views showing configuration examples of insulating elements (first and second coils) according to modified examples.

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant descriptions will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B."

[0011] 1 to 12 show a semiconductor device A1 according to a first embodiment. The semiconductor device A1 is surface-mounted on a circuit board of an inverter device, for example, in an electric vehicle or a hybrid vehicle. The semiconductor device A1 includes a first semiconductor element 1, a second semiconductor element 2, an insulating element 3, a support substrate 4, a plurality of first external terminals 51, a plurality of second external terminals 52, and a sealing resin 6. In the semiconductor device A1, the insulating element 3 includes a first coil L1 and a second coil L2 that are magnetically coupled to each other.

[0012] For convenience of explanation, the thickness direction of the semiconductor device A1 is referred to as the "thickness direction z." In this disclosure, "plan view" refers to the view in the thickness direction z. As an example, a direction perpendicular to the thickness direction z is referred to as the "first direction x." Furthermore, a direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y."

[0013] The first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are elements that are central to the function of the semiconductor device A1. As shown in Figures 1 to 4 and 7 to 11, the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are all composed of individual elements. As shown in Figures 1 to 3, the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 each have a rectangular shape in plan view with the long sides extending in the second direction y, but their planar shapes are not limited to the examples shown.

[0014] The first semiconductor element 1 is a driving element (e.g., a gate driver) for driving a switching element such as an IGBT or a MOSFET. The first semiconductor element 1 has a first functional circuit. The first functional circuit includes, for example, a receiving circuit for receiving a PWM control signal, a circuit for controlling the driving of the switching element based on the PWM signal, and a transmitting circuit for transmitting an electrical signal to the second semiconductor element 2 via the insulating element 3. The electrical signal may be, for example, an output signal from a temperature sensor disposed near the motor. As shown in FIGS. 1 to 4, 7, 8, and 11, the first semiconductor element 1 is mounted on a support substrate 4.

[0015] The first semiconductor element 1 has a first element main surface 10a and a first element back surface 10b. The first element main surface 10a and the first element back surface 10b are spaced apart in the thickness direction z. As shown in FIG. 8 , the first element main surface 10a faces downward in the thickness direction z and faces the support substrate 4. The first element back surface 10b faces upward in the thickness direction z. The first element main surface 10a and the first element back surface 10b are both flat.

[0016] As shown in FIGS. 7, 8 and 11, the first semiconductor element 1 includes a first substrate 11, a first wiring layer 12, a first insulating layer 13 and a plurality of first pads 14.

[0017] 8 , the first substrate 11 has a first functional surface 11a on which the first functional circuit is formed. The first functional surface 11a faces downward in the thickness direction z. The constituent material of the first substrate 11 includes, for example, a semiconductor material, such as Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), GaN (gallium nitride), or InP (indium phosphide).

[0018] As shown in Fig. 8, the first wiring layer 12 is laminated on the first functional surface 11a. The first wiring layer 12 is electrically connected to the first functional circuit. In the examples shown in Figs. 7, 8, and 11, the first wiring layer 12 has a two-layer structure, but it may have three or more layers, or may have only one layer. The constituent material of the first wiring layer 12 is, for example, Cu (copper) or a Cu alloy.

[0019] The first insulating layer 13 is laminated on the first functional surface 11a as shown in Fig. 8. The first insulating layer 13 covers the first wiring layer 12 as shown in Fig. 7, Fig. 8, and Fig. 11. The constituent material of the first insulating layer 13 includes, for example, glass, and the glass includes, for example, SiO2 (silicon dioxide).

[0020] As shown in FIG. 8 , the multiple first pads 14 are provided on the first element main surface 10a. Each of the multiple first pads 14 is electrically connected to the first functional circuit via the first wiring layer 12. The constituent material of each of the multiple first pads 14 is, for example, Cu or a Cu alloy. The constituent material may be aluminum (Al) or an Al alloy, instead of Cu or a Cu alloy. As shown in FIGS. 2 , 7 , 8 , and 11 , the multiple first pads 14 include multiple electrodes 141 and multiple electrodes 142. As will be understood from the configuration described in detail later, the multiple electrodes 141 are electrically connected to the first coil L1 of the insulating element 3, and the multiple electrodes 142 are electrically connected to the multiple first external terminals 51. As shown in FIGS. 2 , 7 , and 11 , the multiple electrodes 141 are disposed closer to the insulating element 3 in the first direction x than the multiple electrodes 142.

[0021] As shown in FIG. 8 , the first semiconductor element 1 has the first insulating layer 13 and the plurality of first pads 14 (the plurality of electrodes 141, 142) exposed on the first element main surface 10a. In the semiconductor device A1, the first element main surface 10a faces downward in the thickness direction z, so the first insulating layer 13 and the plurality of first pads 14 are exposed on the underside (the surface facing downward in the thickness direction z) of the first semiconductor element 1. The surface of the first insulating layer 13 facing downward in the thickness direction z and the surface of each of the plurality of first pads 14 facing downward in the thickness direction z are flush with each other. For example, these surfaces can be made flush by mirror-finishing the first element main surface 10a. The first element main surface 10a is composed of the surface of the first insulating layer 13 facing downward in the thickness direction z and the surfaces of each of the plurality of first pads 14 facing downward in the thickness direction z. The first element back surface 10b is composed of the surface of the first substrate 11 facing upward in the thickness direction z.

[0022] The second semiconductor element 2 is a control element (e.g., a gate driver controller) for controlling the driving of the switching elements. The second semiconductor element 2 has a second function circuit. The second function circuit includes, for example, a circuit for converting a control signal input from an ECU or the like into a PWM signal, a transmission circuit for transmitting the PWM signal to the isolation element 3, and a reception circuit for receiving an electrical signal from the first semiconductor element 1 via the isolation element 3. As shown in FIGS. 1 to 4, 7, 9, and 11, the second semiconductor element 2 is mounted on a support substrate 4.

[0023] The second semiconductor element 2 has a second element main surface 20a and a second element back surface 20b. The second element main surface 20a and the second element back surface 20b are spaced apart in the thickness direction z. As shown in Figure 9, the second element main surface 20a faces downward in the thickness direction z and faces the support substrate 4. The second element back surface 20b faces upward in the thickness direction z. The second element main surface 20a and the second element back surface 20b are each flat.

[0024] As shown in FIGS. 7, 9 and 11, the second semiconductor element 2 includes a second substrate 21, a second wiring layer 22, a second insulating layer 23 and a plurality of second pads 24.

[0025] 9, the second substrate 21 has a second functional surface 21a on which the second function circuit is formed. The second functional surface 21a faces downward in the thickness direction z. The constituent material of the second substrate 21 includes, for example, a semiconductor material, and the semiconductor material is, for example, any one of Si, SiC, GaAs, GaN, and InP.

[0026] As shown in Fig. 9, the second wiring layer 22 is laminated on the second functional surface 21a. The second wiring layer 22 is electrically connected to the second functional circuit. In the examples shown in Figs. 7, 9, and 11, the second wiring layer 22 has a two-layer structure, but it may have three or more layers, or may have only one layer. The constituent material of the second wiring layer 22 is, for example, Cu or a Cu alloy.

[0027] The second insulating layer 23 is laminated on the second functional surface 21a as shown in Fig. 9. The second insulating layer 23 covers the second wiring layer 22 as shown in Fig. 7, 9, and 11. The constituent material of the second insulating layer 23 includes, for example, glass, and the glass includes, for example, SiO2.

[0028] As shown in FIG. 9 , the second pads 24 are provided on the second element main surface 20 a. Each of the second pads 24 is electrically connected to the second function circuit via the second wiring layer 22. The material of each of the second pads 24 is, for example, Cu or a Cu alloy. The material may be Al or an Al alloy, rather than Cu or a Cu alloy. As shown in FIGS. 2 , 7 , 9 , and 11 , the second pads 24 include a plurality of electrodes 241 and a plurality of electrodes 242. As will be understood from the configuration described in detail later, the electrodes 241 are electrically connected to the second coil L2 of the insulating element 3, and the electrodes 242 are electrically connected to the plurality of second external terminals 52. As shown in FIGS. 2 , 7 , and 11 , the electrodes 241 are disposed closer to the insulating element 3 in the first direction x than the electrodes 242.

[0029] As shown in FIG. 9 , the second semiconductor element 2 has the second insulating layer 23 and the plurality of second pads 24 (the plurality of electrodes 241, 242) exposed on the second element main surface 20a. In the semiconductor device A1, the second element main surface 20a faces downward in the thickness direction z, so the second insulating layer 23 and the plurality of second pads 24 are exposed on the underside (the surface facing downward in the thickness direction z) of the second semiconductor element 2. The surface of the second insulating layer 23 facing downward in the thickness direction z and the surface of each of the plurality of second pads 24 facing downward in the thickness direction z are flush with each other. For example, these surfaces can be flush with each other by mirror-finishing the second element main surface 20a. The second element main surface 20a is composed of the surface of the second insulating layer 23 facing downward in the thickness direction z and the surfaces of each of the plurality of second pads 24 facing downward in the thickness direction z. The second element back surface 20b is composed of the surface of the second substrate 21 facing upward in the thickness direction z.

[0030] The isolation element 3 is an element for transmitting PWM control signals and other electrical signals in an insulated state. The isolation element 3 is, for example, an inductor-coupled type. One example of an inductor-coupled isolation element is an isolation transformer. In the semiconductor device A1, the isolation element 3 transmits electrical signals in an insulated state by inductively coupling two inductors (a first coil L1 and a second coil L2). As shown in FIGS. 1 to 4 , 7 , 10 , and 11 , the isolation element 3 is mounted on a support substrate 4. This supports the isolation element 3 on the support substrate 4. As shown in FIGS. 1 to 4 , 7 , and 11 , the isolation element 3 is located between the first semiconductor element 1 and the second semiconductor element 2 in the first direction x.

[0031] In semiconductor device A1, second semiconductor element 2 requires a higher voltage than first semiconductor element 1. For example, in an inverter device for an electric vehicle or hybrid vehicle, second semiconductor element 2 requires a power supply voltage of approximately 0 to 5 V, while first semiconductor element 1 requires a power supply voltage of 600 V or higher. In this example, a significant potential difference occurs between first semiconductor element 1 and second semiconductor element 2, so a first circuit including first semiconductor element 1 and a second circuit including second semiconductor element 2 are insulated by isolation element 3. In other words, isolation element 3 insulates between the first circuit including first semiconductor element 1, which operates at a relatively high voltage, and the second circuit including second semiconductor element 2, which operates at a relatively low voltage.

[0032] As shown in Figures 7, 10, and 11, the insulating element 3 has a third element main surface 30a and a third element back surface 30b. The third element main surface 30a and the third element back surface 30b are spaced apart in the thickness direction z. As shown in Figures 7, 10, and 11, the third element main surface 30a faces upward in the thickness direction z. The third element back surface 30b faces downward in the thickness direction z and faces the support substrate 4. The third element main surface 30a and the third element back surface 30b are each flat.

[0033] As shown in FIGS. 7 and 10 to 12, the insulating element 3 includes a third insulating layer 31, an upper wiring layer 32, a lower wiring layer 33, a plurality of third pads , a plurality of fourth pads , and a plurality of connecting wires .

[0034] The third insulating layer 31 includes, for example, glass as a constituent material, and the glass includes, for example, SiO2. As shown in Figures 10 and 12, the third insulating layer 31 includes an intermediate portion 311, an upper covering portion 312, and a lower covering portion 313. As shown in Figure 10, the intermediate portion 311 is interposed between the upper wiring layer 32 and the lower wiring layer 33 in the thickness direction z. The upper covering portion 312 is located above the intermediate portion 311 in the thickness direction z and covers the upper wiring layer 32. The lower covering portion 313 is located below the intermediate portion 311 in the thickness direction z and covers the lower wiring layer 33.

[0035] 10, the upper wiring layer 32 is formed above the intermediate portion 311 in the thickness direction z. The upper wiring layer 32 includes a first coil L1 and a plurality of lead wires 321.

[0036] As shown in FIGS. 10 and 12 , the first coil L1 is provided on the third element main surface 30a. As shown in FIGS. 10 and 12 , the first coil L1 includes multiple winding portions L11. In the illustrated example, the first coil L1 includes four winding portions L11. The number of winding portions L11 is not limited to four and may be changed as appropriate depending on the specifications of the semiconductor device A1. Each of the multiple winding portions L11 is wound along a plane (x-y plane) perpendicular to the thickness direction z. Each of the multiple winding portions L11 is wound in a spiral shape. In the example shown in FIG. 2 , each of the multiple winding portions L11 is wound in an elliptical shape in a planar view. However, unlike this example, the multiple winding portions L11 may be wound in a circular or rectangular shape. The multiple winding portions L11 are arranged along the second direction y.

[0037] As shown in FIGS. 7 and 10 to 12, each of the multiple winding portions L11 has an inner end L12 and an outer end L13. The inner end L12 is the inner end of each winding portion L11, and the outer end L13 is the outer end of each winding portion L11. The inner end L12 is located at the center of each winding portion L11 in a planar view. In the illustrated example, the inner end L12 overlaps the winding axis of each winding portion L11 in a planar view. In each winding portion L11, proceeding from the inner end L12 along the winding portion L11 leads to the outer end L13. One of the inner end L12 and the outer end L13 is a current input terminal for each winding portion L11, and the other is a current output terminal for each winding portion L11.

[0038] In the upper wiring layer 32, the plurality of lead-out wirings 321 electrically connect the plurality of winding portions L11 to one another and electrically connect the plurality of winding portions L11 to the plurality of connection wirings 36. As shown in Figures 7 and 10 to 12, the plurality of lead-out wirings 321 include those connected to the outer ends L13 of the two winding portions L11 arranged on one side in the second direction y and connected to any of the plurality of connection wirings 36, those connected to the outer ends L13 of the two winding portions L11 arranged on the other side in the second direction y and connected to any of the plurality of connection wirings 36, and those connected to the inner ends L12 of the plurality of winding portions L11 and each of the connection wirings 36. 12 , some of the lead-out wirings 321 are located below the first coil L1 (each winding portion L11) in the thickness direction z and between the first coil L1 (each winding portion L11) and the intermediate portion 311, but instead of this configuration, they may be located above each winding portion L11 in the thickness direction z. In this case, the first coil L1 is not exposed on the third element main surface 30 a and is covered by the upper covering portion 312.

[0039] 10, the lower wiring layer 33 is formed below the intermediate portion 311 in the thickness direction z. The lower wiring layer 33 includes the second coil L2 and a plurality of lead wires 331.

[0040] As shown in FIGS. 10 and 12 , the second coil L2 is provided on the third element rear surface 30b. The second coil L2 is disposed between the first coil L1 and the support substrate 4 (substrate 41, described below) in the thickness direction z. As shown in FIGS. 10 and 12 , the second coil L2 includes multiple winding portions L21. In the illustrated example, the number of winding portions L21 is the same as the number of winding portions L11, i.e., four. The number of winding portions L21 is not limited to four and may be changed as appropriate depending on the specifications of the semiconductor device A1. Each of the multiple winding portions L21 is wound along a plane (x-y plane) perpendicular to the thickness direction z. Each of the multiple winding portions L21 is wound in a spiral shape. Although each of the multiple winding portions L21 is wound in an elliptical shape in a plan view, it may also be wound in a circular or rectangular shape, unlike this example. 2, 7, and 10, the winding portions L21 overlap the winding portions L11 in a plan view. Each of the winding portions L21 is magnetically coupled to each of the winding portions L11. This magnetically couples the first coil L1 and the second coil L2.

[0041] As shown in FIGS. 7 and 10 to 12 , each of the multiple winding portions L21 has an inner end L22 and an outer end L23. The inner end L22 is the inner end of each winding portion L21, and the outer end L23 is the outer end of each winding portion L21. The inner end L22 is located at the center of each winding portion L21 in a planar view. In the illustrated example, the inner end L22 overlaps the winding axis of each winding portion L21 in a planar view. In each winding portion L21, proceeding from the inner end L22 along the winding portion L21 leads to the outer end L23. One of the inner end L22 and the outer end L23 is a current input terminal for each winding portion L21, and the other is a current output terminal for each winding portion L21.

[0042] In the lower wiring layer 33, the plurality of lead-out wirings 331 electrically connect the plurality of winding portions L21 to each other and electrically connect the plurality of winding portions L21 to the plurality of fourth pads 35. As shown in Figures 7 and 10 to 12, the plurality of lead-out wirings 331 include those connected to the outer ends L23 of the two winding portions L21 arranged on one side in the second direction y and connected to any of the plurality of fourth pads 35, those connected to the outer ends L23 of the two winding portions L21 arranged on the other side in the second direction y and connected to any of the plurality of fourth pads 35, and those connected to the inner ends L22 of the plurality of winding portions L21 and each of the fourth pads 35. 12 , some of the lead-out wiring 331 are located above the second coil L2 (each winding portion L21) in the thickness direction z and between the second coil L2 (each winding portion L21) and the intermediate portion 311, but instead of this configuration, the lead-out wiring 331 may be located below each winding portion L21 in the thickness direction z. In this case, the second coil L2 is not exposed on the third element back surface 30b and is covered by the lower cover 313.

[0043] As shown in FIGS. 7 and 10 to 12, the multiple third pads 34 are provided on the third element rear surface 30b. The constituent material of each of the multiple third pads 34 is, for example, Cu or a Cu alloy. The constituent material may be Al or an Al alloy instead of Cu or a Cu alloy. The multiple third pads 34 are each electrically connected to the upper wiring layer 32 via each connection wiring 36. As shown in FIG. 2, the multiple third pads 34 are located on the side where the first semiconductor element 1 is disposed relative to the first coil L1 and the second coil L2 in the first direction x.

[0044] As shown in FIGS. 7 and 10 to 12, the multiple fourth pads 35 are provided on the third element rear surface 30b. The constituent material of each of the multiple fourth pads 35 is, for example, Cu or a Cu alloy. The constituent material may be Al or an Al alloy instead of Cu or a Cu alloy. Each of the multiple fourth pads 35 is electrically connected to the lower wiring layer 33. As shown in FIG. 2, the multiple fourth pads 35 are located on the side where the second semiconductor element 2 is arranged relative to the first coil L1 and the second coil L2 in the first direction x.

[0045] Each of the plurality of connection wires 36 connects each of the plurality of lead wires 321 of the upper wiring layer 32 to each of the plurality of third pads 34. Each of the plurality of connection wires 36 is covered with the third insulating layer 31. Each of the plurality of connection wires 36 extends in the thickness direction z and penetrates the intermediate portion 311 and the lower covering portion 313.

[0046] As shown in FIG. 10 , the insulating element 3 has a third insulating layer 31 (lower covering portion 313), a plurality of third pads 34, and a plurality of fourth pads 35 exposed on the third element rear surface 30b. In the semiconductor device A1, the third element rear surface 30b faces downward in the thickness direction z, so the third insulating layer 31, the third pads 34, and the fourth pads 35 are exposed on the lower surface (the surface facing downward in the thickness direction z) of the insulating element 3. The surface of the third insulating layer 31 facing downward in the thickness direction z, the surfaces of the plurality of third pads 34 facing downward in the thickness direction z, and the surfaces of the plurality of fourth pads 35 facing downward in the thickness direction z are flush with each other. For example, by mirror-finishing the third element rear surface 30b, these surfaces can be flush with each other. In the example shown in FIG. 10 , a portion of the upper wiring layer 32 (e.g., the first coil L1) is exposed on the third element main surface 30a, and a portion of the lower wiring layer 33 (e.g., the second coil L2) is exposed on the third element rear surface 30b. The lower surface of a part of the lower wiring layer 33 (for example, the second coil L2) in the thickness direction z is flush with the lower surface of the third insulating layer 31 in the thickness direction z.

[0047] The support substrate 4 mounts and supports the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3. A portion of the support substrate 4 (substrate wiring 42, described later) forms a conductive path between the first semiconductor element 1, the second semiconductor element 2, the insulating element 3, the plurality of first external terminals 51, and the plurality of second external terminals 52.

[0048] As shown in FIGS. 4 to 11 , the support substrate 4 has a mounting surface 40a and a terminal surface 40b. The mounting surface 40a and the terminal surface 40b are spaced apart in the thickness direction z. The mounting surface 40a faces upward in the thickness direction z, and the terminal surface 40b faces downward in the thickness direction z. The mounting surface 40a and the terminal surface 40b are flat. The mounting surface 40a is, for example, mirror-finished. As shown in FIGS. 4 to 11 , the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are mounted on the mounting surface 40a. The first semiconductor element 1 (first element main surface 10a), the second semiconductor element 2 (second element main surface 20a), and the insulating element 3 (third element main surface 30a) are in close contact with and directly bonded to the mounting surface 40a. In this disclosure, "A and B are in close contact" means that A and B are in close contact with each other. Under ideal conditions, there are no inclusions (for example, foreign matter such as dust or dirt) or voids at the boundary between A and B, but some inclusions or voids may exist at this boundary. Furthermore, "A and B are directly bonded" refers to a mode in which A and B are bonded without the use of an adhesive or the like. Under ideal conditions, when A and B are directly bonded, A and B are in close contact. As shown in FIGS. 4 to 7 and 11, a plurality of first external terminals 51 and a plurality of second external terminals 52 are arranged on the terminal surface 40b.

[0049] As shown in FIGS. 1 to 11, the support substrate 4 includes a base material 41, substrate wiring 42, and a plurality of through wirings 43.

[0050] The substrate 41 is made of an insulating material. This insulating material is, for example, amorphous glass such as SiO2. This insulating material may be a ceramic such as AlN instead of SiO2. As shown in FIGS. 1 to 3, the substrate 41 is, for example, rectangular in plan view. The substrate 41 has a trench region formed by trench processing. The trench region is formed in part of the upper surface (the surface facing upward in the thickness direction z) of the substrate 41, and is a portion recessed from the upper surface (thickness direction z) of the substrate 41. Substrate wiring 42 is formed in this trench region.

[0051] The substrate wiring 42 is formed on the upper surface (surface facing upward in the thickness direction z) of the base material 41. The constituent material of the substrate wiring 42 is, for example, Cu or a Cu alloy.

[0052] As shown in FIGS. 2, 3, and 7 to 11, the substrate wiring 42 includes a plurality of first wiring portions 421 and a plurality of second wiring portions 422.

[0053] Each of the multiple first wiring portions 421 is electrically interposed between the first semiconductor element 1 and the first coil L1 of the insulating element 3. The electrodes 141 of the first semiconductor element 1 and the third pads 34 of the insulating element 3 are directly bonded to each first wiring portion 421. Each of the multiple first wiring portions 421 extends from a region overlapping the first semiconductor element 1 to a region overlapping the insulating element 3 in a planar view. In the example shown in FIGS. 2 and 3 , each of the multiple first wiring portions 421 has a strip shape extending in the first direction x in a planar view and is arranged parallel (or approximately parallel) to the second direction y in a planar view. The shape and arrangement of each first wiring portion 421 are not limited to the example shown in FIGS. 2 and 3 , and may be changed as appropriate depending on the positions of the electrodes 141 of the first semiconductor element 1 and the third pads 34 of the insulating element 3. Each first wiring portion 421 is part of the first circuit.

[0054] Each of the multiple second wiring portions 422 is electrically interposed between the second semiconductor element 2 and the second coil L2 of the insulating element 3. The electrodes 241 of the second semiconductor element 2 and the fourth pads 35 of the insulating element 3 are directly bonded to each second wiring portion 422. Each of the multiple second wiring portions 422 extends from a region overlapping the second semiconductor element 2 to a region overlapping the insulating element 3 in a planar view. In the example shown in FIGS. 2 and 3 , each of the multiple second wiring portions 422 has a strip shape extending in the first direction x in a planar view and is arranged parallel (or approximately parallel) to the second direction y in a planar view. The shape and arrangement of each second wiring portion 422 are not limited to the example shown in FIGS. 2 and 3 and may be changed as appropriate depending on the positions of the electrodes 241 of the second semiconductor element 2 and the positions of the fourth pads 35 of the insulating element 3. Each second wiring portion 422 is part of the second circuit.

[0055] In the support substrate 4, the base material 41 and the board wiring 42 (the plurality of first wiring portions 421 and the plurality of second wiring portions 422) are partially exposed on the mounting surface 40a. The upper surface of the base material 41 in the thickness direction z and the upper surface of the board wiring 42 in the thickness direction z are flush with each other. For example, these surfaces are made flush by mirror-finishing the mounting surface 40a. The mounting surface 40a is composed of the upper surface of the base material 41 in the thickness direction z and the upper surface of the board wiring 42 in the thickness direction z.

[0056] In the semiconductor device A1, the first semiconductor element 1 and the support substrate 4 are bonded together such that some of the first pads 14 (each of the multiple electrodes 141) are directly bonded to each of the multiple first wiring portions 421, and the first insulating layer 13 is directly bonded to the base material 41. This ensures that the first semiconductor element 1 is in close contact with the support substrate 4. The second semiconductor element 2 and the support substrate 4 are bonded together such that some of the second pads 24 (each of the multiple electrodes 241) are directly bonded to each of the multiple second wiring portions 422, and the second insulating layer 23 is directly bonded to the base material 41. This ensures that the second semiconductor element 2 is in close contact with the support substrate 4. The insulating element 3 and the support substrate 4 are bonded together such that each of the multiple third pads 34 is directly bonded to each of the multiple first wiring portions 421, each of the multiple fourth pads 35 is directly bonded to each of the multiple second wiring portions 422, and the third insulating layer 31 is directly bonded to the base material 41. This allows the insulating element 3 to be in close contact with the support substrate 4 .

[0057] Each of the plurality of through wires 43 penetrates the substrate 41 in the thickness direction z. The constituent material of each of the plurality of through wires 43 is, for example, Cu or a Cu alloy. The plurality of through wires 43 includes a plurality of first through portions 431 and a plurality of second through portions 432.

[0058] Each of the multiple first through portions 431 contacts a corresponding electrode 142 of the first semiconductor element 1 and a corresponding first external terminal 51, thereby electrically connecting them. Each electrode 142 is directly bonded to the upper surface (the surface facing upward in the thickness direction z) of each first through portion 431. As shown in FIG. 3 , in the semiconductor device A1, the multiple first through portions 431 overlap the first semiconductor element 1 in a plan view. Each first through portion 431 is part of the first circuit.

[0059] Each of the second through portions 432 contacts a corresponding electrode 242 of the second semiconductor element 2 and a corresponding second external terminal 52, thereby electrically connecting them. Each electrode 242 is directly bonded to the upper surface (the surface facing upward in the thickness direction z) of each second through portion 432. As shown in FIG. 3 , in the semiconductor device A1, the second through portions 432 overlap the second semiconductor element 2 in a plan view. Each second through portion 432 is part of the second circuit.

[0060] In the semiconductor device A1, the plurality of through-wirings 43 are formed, for example, by the following method. By irradiating the substrate 41 with laser light, through-holes (or grooves) are formed in the substrate 41 in the thickness direction z. Thereafter, Cu or a Cu alloy is formed in the through-holes (or grooves) formed in the substrate 41, thereby forming the plurality of through-wirings 43. Note that, when grooves are formed in the substrate 41, the Cu or Cu alloy is formed in the grooves of the substrate 41, and then the surface of the substrate 41 opposite to the surface where the grooves are formed is ground to form the plurality of through-wirings 43.

[0061] Each of the first external terminals 51 is electrically connected to the first semiconductor element 1. The first external terminals 51 serve as terminals when the semiconductor device A1 is mounted on a circuit board. As shown in FIGS. 4, 6, 7, and 11, the first external terminals 51 are formed on the terminal surface 40b of the support substrate 4. As shown in FIG. 3, each of the first external terminals 51 overlaps a corresponding one of the first through-holes 431 in a plan view, and also overlaps the first semiconductor element 1 in a plan view. As shown in FIGS. 7 and 11, each of the first external terminals 51 contacts the lower surface (the surface facing downward in the thickness direction z) of each of the first through-holes 431. Each of the first external terminals 51 is electrically connected to a corresponding one of the electrodes 142 via a corresponding one of the first through-holes 431. In the example shown in FIGS. 2 and 3, the first external terminals 51 are arranged along the second direction y in correspondence with the arrangement of the electrodes 142. The arrangement of the multiple first external terminals 51 is not limited to the example shown in the figure and can be changed as appropriate depending on the positions of the multiple electrodes 142. Each first external terminal 51 is formed, for example, by electroless plating. Each first external terminal 51 is composed, for example, of a Ni (nickel) layer in contact with each first through portion 431, a Pd (palladium) layer covering the Ni layer, and an Au (gold) layer covering the Pd layer. The configuration of each first external terminal 51 is not limited to the example described above and may be a laminate of Ni and Au layers, or may be composed of only an Au layer. Alternatively, the first external terminals 51 may be ball-shaped solder.

[0062] Each of the second external terminals 52 is electrically connected to the second semiconductor element 2. The second external terminals 52 serve as terminals when the semiconductor device A1 is mounted on a circuit board. As shown in FIGS. 4 , 5 , 7 , and 11 , the second external terminals 52 are formed on the terminal surface 40b of the support substrate 4. As shown in FIG. 3 , each of the second external terminals 52 overlaps a corresponding one of the second through-holes 432 in a plan view. As shown in FIGS. 7 and 11 , each of the second external terminals 52 contacts the lower surface (the surface facing downward in the thickness direction z) of each of the second through-holes 432. Each of the second external terminals 52 is electrically connected to a corresponding one of the electrodes 242 via a corresponding one of the second through-holes 432. In the example shown in FIGS. 2 and 3 , the second external terminals 52 are arranged along the second direction y in accordance with the arrangement of the electrodes 242. The arrangement of the second external terminals 52 is not limited to the example shown in the figure and may be changed as appropriate depending on the positions of the electrodes 242. Each second external terminal 52 is formed, for example, by electroless plating. Each second external terminal 52 is composed, for example, of a Ni layer in contact with each second through-hole 432, a Pd layer covering the Ni layer, and an Au layer covering the Pd layer. The configuration of each second external terminal 52 is not limited to the example described above and may be a laminate of Ni and Au layers, or may be composed of only an Au layer. Alternatively, the second external terminals 52 may be ball-shaped solder.

[0063] The sealing resin 6 is formed above the support substrate 4 (on the mounting surface 40a) and covers the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3. The sealing resin 6 contacts the mounting surface 40a of the support substrate 4. As shown in FIG. 1 , the sealing resin 6 has, for example, a rectangular shape in a plan view.

[0064] The sealing resin 6 has a top surface 61, a pair of first side surfaces 63, and a pair of second side surfaces 64. As shown in FIGS. 4 to 11 , the top surface 61 faces upward in the thickness direction z. The top surface 61 is flat (or substantially flat). Each of the pair of first side surfaces 63 is connected to the top surface 61. Each of the pair of first side surfaces 63 is flat (or substantially flat). As shown in FIG. 1 , the pair of first side surfaces 63 are spaced apart in the first direction x and face opposite directions from each other in the first direction x. In the examples shown in FIGS. 4 , 7 , and 11 , each of the pair of first side surfaces 63 is perpendicular to the top surface 61. Each of the pair of second side surfaces 64 is connected to the top surface 61. Each of the pair of second side surfaces 64 is flat (or substantially flat). As shown in FIG. 1 , the pair of second side surfaces 64 are spaced apart in the second direction y and face opposite directions from each other in the second direction y. In the example shown in FIGS. 5 and 6 , each of the pair of second side surfaces 64 is perpendicular to the top surface 61 .

[0065] The semiconductor device A1 has the following functions and effects.

[0066] The semiconductor device A1 includes a support substrate 4 on which a first semiconductor element 1 and a second semiconductor element 2 are mounted. The support substrate 4 includes an insulating base material 41 and substrate wiring 42 formed on the base material 41. The substrate wiring 42 includes a first wiring portion 421 and a second wiring portion 422. The first wiring portion 421 is electrically interposed between the first semiconductor element 1 and the first coil L1. The second wiring portion 422 is electrically interposed between the second semiconductor element 2 and the second coil L2. With this configuration, the first circuit (e.g., the first wiring portion 421) including the first semiconductor element 1 and the second circuit (e.g., the second wiring portion 422) including the second semiconductor element 2 are insulated by the base material 41. Therefore, the withstand voltage of the base material 41 affects the withstand voltage between the first circuit and the second circuit, i.e., the withstand voltage of the semiconductor device A1, and does not depend on the distance between the first island and the second island as in the conventional semiconductor device (Patent Document 1). This makes it possible to prevent the semiconductor device A1 from decreasing in dielectric strength even when the semiconductor device A1 is made smaller.

[0067] In the semiconductor device A1, the first pads 14 are exposed on the first element main surface 10a, which faces the mounting surface 40a. The electrodes 141 of the first pads 14 are bonded to the first wiring portions 421. With this configuration, the first semiconductor element 1 is flip-chip bonded to the support substrate 4, eliminating the need for bonding wire mounting. Therefore, the semiconductor device A1 is preferable in terms of miniaturizing the device (particularly in the dimension in the thickness direction z).

[0068] In the semiconductor device A1, the first semiconductor element 1 and the supporting substrate 4 are directly bonded to each other via the electrodes 141 of the first pads 14 and the first wiring portions 421 of the substrate wiring 42, and also via the first insulating layer 13 and the base material 41. In the semiconductor device A1, the first element main surface 10a and the mounting surface 40a are each mirror-finished, for example, to allow the first semiconductor element 1 and the supporting substrate 4 to be closely attached to each other. With this configuration, the semiconductor device A1 can bond the first semiconductor element 1 to the supporting substrate 4 without using an adhesive. Furthermore, in the semiconductor device A1, the first semiconductor element 1 and the supporting substrate 4 are closely attached to each other, thereby reducing the gap between the first semiconductor element 1 and the supporting substrate 4. Unlike the semiconductor device A1, if the first semiconductor element 1 is bonded to the supporting substrate 4 using, for example, a conductive bonding material, a gap corresponding to the thickness of the conductive bonding material may be formed between the first semiconductor element 1 and the supporting substrate 4. Foreign matter such as dust and dirt, and sealing resin 6 may get into this gap, but the occurrence of the gap, the inclusion of foreign matter, and the interposition of sealing resin 6 are factors that cause a decrease in the dielectric strength and a decrease in the bonding strength between the first semiconductor element 1 and the support substrate 4. On the other hand, in the semiconductor device A1, the first semiconductor element 1 and the support substrate 4 are closely attached to each other, so that the occurrence of the gap, the inclusion of foreign matter, and the interposition of sealing resin 6 between the first semiconductor element 1 and the support substrate 4 can be suppressed. In other words, the semiconductor device A1 can suppress a decrease in the dielectric strength and a decrease in the bonding strength between the first semiconductor element 1 and the support substrate 4.

[0069] In the semiconductor device A1, the first insulating layer 13 and the base material 41 are each made of glass (e.g., SiO2). That is, the first insulating layer 13 and the base material 41 are made of the same material. This configuration can increase the adhesive strength between the first insulating layer 13 and the base material 41 compared to when the first insulating layer 13 and the base material 41 are made of different materials. Therefore, the semiconductor device A1 can prevent the first semiconductor element 1 from peeling off from the support substrate 4. This also applies to the relationship between some of the first pads 14 (each electrode 141) and each first wiring portion 421.

[0070] In the semiconductor device A1, the second pads 24 are exposed on the second element main surface 20a, which faces the mounting surface 40a. The electrodes 241 of the second pads 24 are bonded to the second wiring portions 422. With this configuration, the second semiconductor element 2 is flip-chip bonded to the support substrate 4, eliminating the need for bonding wire mounting. Therefore, the semiconductor device A1 is preferable in terms of miniaturizing the device (particularly the dimension in the thickness direction z).

[0071] In the semiconductor device A1, the second semiconductor element 2 and the supporting substrate 4 are directly bonded to each other at the electrodes 241 of the second pads 24 and the second wiring portions 422 of the substrate wiring 42, and also at the second insulating layer 23 and the base material 41. In the semiconductor device A1, the second element main surface 20a and the mounting surface 40a are each mirror-finished, for example, to bring the second semiconductor element 2 and the supporting substrate 4 into close contact with each other. With this configuration, the semiconductor device A1 can bond the second semiconductor element 2 to the supporting substrate 4 without using an adhesive. Furthermore, since the second semiconductor element 2 and the supporting substrate 4 are closely contacted with each other, gaps between the second semiconductor element 2 and the supporting substrate 4 are reduced. Therefore, the semiconductor device A1 can prevent gaps, foreign matter from entering, and the sealing resin 6 from interfering with the dielectric strength between the second semiconductor element 2 and the supporting substrate 4, thereby reducing a decrease in dielectric strength and a decrease in the bonding strength between the second semiconductor element 2 and the supporting substrate 4.

[0072] In the semiconductor device A1, the second insulating layer 23 and the base material 41 are each made of glass (e.g., SiO2). That is, the second insulating layer 23 and the base material 41 are made of the same material. This configuration can increase the adhesive strength between the second insulating layer 23 and the base material 41 compared to when the second insulating layer 23 and the base material 41 are made of different materials. Therefore, the semiconductor device A1 can prevent the second semiconductor element 2 from peeling off from the support substrate 4. The same applies to the relationship between some of the second pads 24 (each electrode 241) and each second wiring portion 422.

[0073] In the semiconductor device A1, the third pad 34 and the fourth pad 35 are exposed on the third element back surface 30b, which faces the terminal surface 40b. The third pad 34 is bonded to the first wiring portion 421, and the fourth pad 35 is bonded to the second wiring portion 422. With this configuration, it is not necessary to use bonding wires to establish electrical connection between the third pad 34 and the first wiring portion 421, and between the fourth pad 35 and the second wiring portion 422. Therefore, the semiconductor device A1 is preferable in terms of miniaturizing the device (particularly in the dimension in the thickness direction z).

[0074] In the semiconductor device A1, the insulating element 3 and the supporting substrate 4 are directly bonded to each other at the third pad 34 and the first wiring portion 421, at the fourth pad 35 and the second wiring portion 422, and at the third insulating layer 31 and the base material 41. In the semiconductor device A1, the insulating element 3 and the supporting substrate 4 are closely attached to each other by, for example, mirror-finishing the third element back surface 30b and the mounting surface 40a. This configuration allows the insulating element 3 and the supporting substrate 4 to be bonded to each other without using adhesive. Furthermore, in the semiconductor device A1, the insulating element 3 and the supporting substrate 4 are closely attached to each other, thereby reducing gaps between the insulating element 3 and the supporting substrate 4. Therefore, the semiconductor device A1 can prevent gaps, foreign matter from entering, and the sealing resin 6 from interfering with the insulating element 3 and the supporting substrate 4, thereby reducing a decrease in dielectric strength and a decrease in the bonding strength between the insulating element 3 and the supporting substrate 4.

[0075] In the semiconductor device A1, the third insulating layer 31 and the base material 41 are each made of glass (e.g., SiO2). That is, the third insulating layer 31 and the base material 41 are made of the same material. This configuration can increase the adhesion between the third insulating layer 31 and the base material 41 compared to when the third insulating layer 31 and the base material 41 are made of different materials. Therefore, the semiconductor device A1 can prevent the insulating element 3 from peeling off from the support substrate 4. The same applies to the relationship between each third pad 34 and each first wiring portion 421, and the relationship between each fourth pad 35 and each second wiring portion 422.

[0076] In the semiconductor device A1, the first coil L1 and the second coil L2 are located between the first semiconductor element 1 and the second semiconductor element 2 in a planar view. That is, the first semiconductor element 1 and the second semiconductor element 2 are arranged on opposite sides of the insulating element 3 in a planar view. With this configuration, an appropriate distance is ensured between the first wiring portion 421 and the second wiring portion 422. That is, a sufficient distance is ensured between the first circuit including the first semiconductor element 1 and the second circuit including the second semiconductor element 2. Therefore, the semiconductor device A1 is preferable in terms of improving the dielectric strength voltage.

[0077] 13 and 14 show a semiconductor device A2 according to the second embodiment. As shown in the figures, the semiconductor device A2 differs from the semiconductor device A1 mainly in the following respects. First, in the semiconductor device A2, the substrate wiring 42 further includes a plurality of third wiring portions 423 and a plurality of fourth wiring portions 424. Second, in the semiconductor device A2, the plurality of first external terminals 51 are each located outward from the first semiconductor element 1 in a planar view. Third, in the semiconductor device A2, the plurality of second external terminals 52 are each located outward from the second semiconductor element 2 in a planar view.

[0078] Each of the multiple third wiring portions 423 is electrically interposed between the first semiconductor element 1 and each of the multiple first external terminals 51. Each of the multiple third wiring portions 423 is directly bonded to each of the electrodes 142 of the first semiconductor element 1. Each of the multiple third wiring portions 423 extends, in a planar view, from a region overlapping the first semiconductor element 1 to a region overlapping each of the first external terminals 51. As described above, each of the first external terminals 51 is disposed outside the first semiconductor element 1 in a planar view. The shape and arrangement of each of the third wiring portions 423 are not limited to the example shown in FIG. 13 and may be changed as appropriate depending on the positions of each electrode 142 of the first semiconductor element 1 and each of the first external terminals 51.

[0079] Each of the multiple fourth wiring portions 424 is electrically interposed between the second semiconductor element 2 and each of the multiple second external terminals 52. Each of the multiple fourth wiring portions 424 is directly bonded to each of the electrodes 242 of the second semiconductor element 2. Each of the multiple fourth wiring portions 424 extends, in a plan view, from a region overlapping the second semiconductor element 2 to a region overlapping each of the second external terminals 52. As described above, each of the second external terminals 52 is disposed outward from the second semiconductor element 2 in a plan view. The shape and arrangement of each fourth wiring portion 424 are not limited to the example shown in FIG. 13 and may be changed as appropriate depending on the positions of each electrode 242 of the second semiconductor element 2 and each of the second external terminals 52.

[0080] In the semiconductor device A2, as in the semiconductor device A1, a first circuit including a first semiconductor element 1 and a second circuit including a second semiconductor element 2 are insulated by a substrate 41. In other words, like the semiconductor device A1, the semiconductor device A2 can suppress a decrease in dielectric strength voltage even when miniaturized. In addition, the semiconductor device A2 can achieve the effects obtained by the configuration common to the semiconductor device A1.

[0081] In the semiconductor device A2, the substrate wiring 42 includes a plurality of third wiring portions 423, each of which is interposed between the first semiconductor element 1 and a plurality of first external terminals 51. With this configuration, by extending each third wiring portion 423 outward from the first semiconductor element 1 in a planar view, each of the first external terminals 51 can be positioned outward from the first semiconductor element 1 in a planar view. In other words, the semiconductor device A2 provides increased flexibility in the placement of each of the first external terminals 51. Similarly, in the semiconductor device A2, the substrate wiring 42 includes a plurality of fourth wiring portions 424, each of which is interposed between the second semiconductor element 2 and a plurality of second external terminals 52. With this configuration, by extending each fourth wiring portion 424 outward from the first semiconductor element 1 in a planar view, each of the second external terminals 52 can be positioned outward from the first semiconductor element 1 in a planar view. That is, the semiconductor device A2 has improved flexibility in arranging the second external terminals 52.

[0082] 15 and 16 show a semiconductor device A3 according to the third embodiment. As shown in the figures, the semiconductor device A3 differs from the semiconductor device A1 mainly in the following points. First, in the semiconductor device A3, the thickness direction z of the first semiconductor element 1 is opposite. Second, in the semiconductor device A3, the thickness direction z of the second semiconductor element 2 is opposite. Third, the semiconductor device A3 further includes a plurality of connecting members 7.

[0083] In the semiconductor device A3, the first semiconductor element 1 is disposed with the first element back surface 10b facing the support substrate 4. Therefore, the plurality of first pads 14 (the plurality of electrodes 141, 142) are exposed on the top surface of the first semiconductor element 1 (the surface facing upward in the thickness direction z).

[0084] Similarly, in the semiconductor device A3, the second semiconductor element 2 is disposed with the second element back surface 20b facing the support substrate 4. Therefore, the plurality of second pads 24 (the plurality of electrodes 241, 242) are exposed on the upper surface of the second semiconductor element 2.

[0085] In the semiconductor device A3, the insulating element 3 has a plurality of third pads 34 exposed on the third element main surface 30a. Therefore, the insulating element 3 does not include a plurality of connection wirings 36.

[0086] In the semiconductor device A3, the plurality of first external terminals 51 and the plurality of first through portions 431 (some of the through wirings 43) are arranged outward from the first semiconductor element 1 in a planar view, similar to the semiconductor device A2. Also, the plurality of second external terminals 52 and the plurality of second through portions 432 (some of the through wirings 43) are arranged outward from the second semiconductor element 2 in a planar view, similar to the semiconductor device A2.

[0087] The plurality of connection members 7 electrically connect two separated portions. The plurality of connection members 7 are, for example, bonding wires. Each of the plurality of connection members 7 is made of a material including Au, Cu, or Al. The plurality of connection members 7 include a plurality of first wires 71, a plurality of second wires 72, a plurality of third wires 73, and a plurality of fourth wires 74.

[0088] The plurality of first wires 71 are respectively bonded to the electrodes 141 (some of the first pads 14) of the first semiconductor element 1 and the third pads 34 of the insulating element 3, thereby providing electrical continuity therebetween. In the semiconductor device A3, the first wires 71 provide electrical continuity between the electrodes 141 and the third pads 34, and therefore the board wiring 42 does not include the first wiring portions 421, as shown in FIGS. 15 and 16 .

[0089] The plurality of second wires 72 are respectively bonded to the electrodes 241 (some of the second pads 24) of the second semiconductor element 2 and the second wiring portions 422 of the board wiring 42, thereby providing electrical continuity therebetween. Similar to the semiconductor device A1, the second wiring portions 422 of the semiconductor device A3 are bonded to the fourth pads 35, but do not extend to the second semiconductor element 2 in plan view, and the electrodes 241 are not bonded thereto. In the semiconductor device A3, the second wires 72 provide electrical continuity between the electrodes 241 and the second wiring portions 422, so that the second wiring portions 422 do not overlap the second semiconductor element 2 in plan view, as shown in FIGS. 15 and 16 .

[0090] The plurality of third wires 73 are respectively joined to the electrodes 142 (some of the first pads 14) of the first semiconductor element 1 and the first through portions 431 of the plurality of through wirings 43, thereby providing electrical continuity therebetween. In the semiconductor device A3, the third wires 73 provide electrical continuity between the electrodes 142 and the first through portions 431, and therefore the board wiring 42 does not include the third wiring portions 423, as shown in FIGS.

[0091] The plurality of fourth wires 74 are respectively joined to the electrodes 242 (some of the second pads 24) of the second semiconductor element 2 and the second through portions 432 of the plurality of through wirings 43, thereby providing electrical continuity therebetween. In the semiconductor device A3, the fourth wires 74 provide electrical continuity between the electrodes 242 and the second through portions 432, and therefore the board wiring 42 does not include the fourth wiring portions 424, as shown in FIGS.

[0092] In the semiconductor device A3, as in the semiconductor devices A1 and A2, a first circuit including a first semiconductor element 1 and a second circuit including a second semiconductor element 2 are insulated by a substrate 41. In other words, like the semiconductor devices A1 and A2, the semiconductor device A3 can suppress a decrease in dielectric strength voltage even when miniaturized. In addition, the semiconductor device A3 can achieve the effects obtained by the configuration common to the semiconductor devices A1 and A2.

[0093] In the semiconductor device A3, the fourth pads 35 are disposed on the third element rear surface 30b, and therefore the substrate wiring 42 includes the second wiring portions 422 to electrically connect the second wires 72 to the fourth pads 35. Alternatively, if the fourth pads 35 are exposed on the third element main surface 30a, the second wires 72 may be bonded to the fourth pads 35 instead of the second wiring portions 422, as shown in FIGS. 17 and 18 . In the example shown in FIGS. 17 and 18 , the second wiring portions 422 are unnecessary, and therefore the substrate wiring 42 does not include the second wiring portions 422. Furthermore, the fourth pads 35 are electrically connected to the lower wiring layer 33 via the connection wirings 36.

[0094] 19 to 21 show a semiconductor device A4 according to the fourth embodiment. As shown in the figures, the semiconductor device A4 differs from the semiconductor device A1 mainly in the following respects: In the semiconductor device A4, the second coil L2 is formed on the support substrate 4.

[0095] In the semiconductor device A4, the substrate wiring 42 further includes a fifth wiring portion 425, as shown in FIGS. 19 to 21. The fifth wiring portion 425 includes a second coil L2 and an outgoing wiring 426. The second coil L2 has multiple winding portions L21, as in each of the semiconductor devices A1 to A3. As shown in FIG. 21, the outgoing wiring 426 connects, for example, each outer end L23 to one of the multiple second wiring portions 422. In this case, the second wiring portion 422 and the outgoing wiring 426 may be integrally formed.

[0096] 20 , the insulating element 3 further includes sixth pads 37. The sixth pads 37 are bonded to the inner ends L22 of the second coil L2, respectively. Each sixth pad 37 is electrically connected to each fourth pad 35 by the leading wiring 331 of the lower wiring layer 33.

[0097] In the semiconductor device A4, as in each of the semiconductor devices A1 to A3, a first circuit including a first semiconductor element 1 and a second circuit including a second semiconductor element 2 are insulated by a base material 41. In other words, like each of the semiconductor devices A1 to A3, the semiconductor device A4 can suppress a decrease in dielectric strength voltage even when miniaturized. In addition, the semiconductor device A4 can achieve the effects obtained by the configuration common to each of the semiconductor devices A1 to A3.

[0098] In the semiconductor device A4 shown in Figures 19 to 21, each inner end L22 of the second coil L2 is electrically connected to one of the multiple second wiring portions 422 by the lower wiring layer 33 (each lead-out wiring 331) of the insulating element 3. However, instead of this configuration, each inner end L22 may be connected to one of the multiple second wiring portions 422 by a fifth wiring portion 425 (lead-out wiring 426), as shown in Figure 22.

[0099] In each of the semiconductor devices A1 to A4 according to the first to fourth embodiments, the support substrate 4 may further include a heat dissipation portion 44. Fig. 23 shows an example in which the heat dissipation portion 44 is added to the semiconductor device A1.

[0100] 23 , the heat dissipation portion 44 penetrates the base material 41 in the thickness direction z. The heat dissipation portion 44 is formed, for example, below the first semiconductor element 1 in the thickness direction z. That is, the heat dissipation portion 44 is formed, for example, in a region that overlaps the first semiconductor element 1 in a plan view. The formation region of the heat dissipation portion 44 is not particularly limited. However, the heat dissipation portion 44 is formed so as to avoid at least the first wiring portions 421 (and the third wiring portions 423, if present). The heat dissipation portion 44 is made of, for example, Cu or a Cu alloy, similar to the through-wires 43.

[0101] In the semiconductor device shown in FIG. 23, the heat dissipation portion 44 can dissipate heat from the first semiconductor element 1, and therefore the heat dissipation performance of the heat from the first semiconductor element 1 can be improved.

[0102] 23 , the heat dissipation portion 44 is disposed in a region overlapping the first semiconductor element 1 in a plan view. However, unlike this configuration, the heat dissipation portion 44 may be formed below the second semiconductor element 2 in the thickness direction z. That is, the heat dissipation portion 44 may be formed in a region overlapping the second semiconductor element 2 in a plan view. In this case, the heat dissipation portion 44 can dissipate heat from the second semiconductor element 2, thereby improving the heat dissipation performance from the second semiconductor element 2. However, in an example in which the power supply voltage applied to the first semiconductor element 1 is higher than the power supply voltage applied to the second semiconductor element 2, the amount of heat generated by the first semiconductor element 1 becomes higher than the amount of heat generated by the second semiconductor element 2. Therefore, it is preferable to dispose the heat dissipation portion 44 below the first semiconductor element 1. Alternatively, a plurality of heat dissipation portions 44 may be provided on the support substrate 4, and the plurality of heat dissipation portions 44 may be formed below the first semiconductor element 1 and the second semiconductor element 2 in the thickness direction z.

[0103] Each of the semiconductor devices A1 to A4 according to the first to fourth embodiments may further include a resin material 67. Fig. 24 shows a modification in which a resin material 67 is added to the semiconductor device A1.

[0104] 24 , the resin material 67 is formed on the terminal surface 40b of the support substrate 4. The resin material 67 is disposed, for example, in the first direction x, between the plurality of first external terminals 51 and the plurality of second external terminals 52. The resin material 67 is made of an insulating resin material, and examples of the resin material include epoxy resin, polyimide resin, and phenol resin.

[0105] 24, the resin material 67 protects the terminal surface 40b of the substrate 41. This makes it possible to prevent scratches on the substrate 41. Furthermore, in the semiconductor device, the resin material 67 functions as a reinforcing material for the substrate 41, making it possible to prevent cracks in the substrate 41.

[0106] Each of the semiconductor devices A1 to A4 according to the first to fourth embodiments may further include a passivation film 38 that covers a portion of the insulating element 3. Fig. 25 shows an example in which the passivation film 38 is added to the insulating element 3 in the semiconductor device A1.

[0107] As shown in Figure 25, the passivation film 38 covers, for example, the upper surface (third element main surface 30a) of the insulating element 3. Note that when multiple third pads 34 or multiple fourth pads 35 are provided on the third element main surface 30a (for example, in the configuration examples shown in Figure 16 or Figure 18), the passivation film 38 is formed so as to expose each of the third pads 34 and each of the fourth pads 35. Unlike the configuration shown in Figure 25, the passivation film 38 may cover not only the third element main surface 30a but also the side surfaces of the insulating element 3 (the surfaces facing in the first direction x and the second direction y). The passivation film 38 is made of, for example, polyimide.

[0108] In the semiconductor device shown in FIG. 25, the passivation film 38 can protect the first coil L1 exposed on the third element main surface 30a.

[0109] In each of the semiconductor devices A1 to A4 according to the first to fourth embodiments, the plurality of first external terminals 51 and the plurality of second external terminals 52 may be formed not only on the back surface of the semiconductor device A1 but also on the side surfaces. Fig. 26 shows an example in which the plurality of first external terminals 51 and the plurality of second external terminals 52 are also formed on the side surfaces (side surfaces facing the first direction x) of the substrate 41 in the semiconductor device A1.

[0110] In the semiconductor device shown in Fig. 26, each through wiring 43 is formed up to the side surface of the substrate 41 and is exposed at the side surface. As a result, each first external terminal 51 or each second external terminal 52 is formed on the surface of each through wiring 43 that is exposed from the side surface of the substrate 41. Furthermore, in such a modified example, each through wiring 43 may have a recessed corner on the outward side in the first direction x and on the downward side in the thickness direction z, as shown in Fig. 27. Such a semiconductor device shown in Fig. 27 facilitates inspection of the mounting state when the semiconductor device is mounted on a circuit board.

[0111] In the first to fourth embodiments, the first semiconductor element 1, the second semiconductor element 2, and the insulating element 3 are each shown as being directly bonded to the support substrate 4, but this is not limited to this, and they may be bonded using a conductive bonding material such as solder, metal paste, or sintered metal.

[0112] In the first to fourth embodiments, examples are shown in which the first semiconductor element 1 is a driving element and the second semiconductor element 2 is a control element, but conversely, the first semiconductor element 1 may be a control element and the second semiconductor element 2 may be a driving element.

[0113] In each of the semiconductor devices A1 to A4 according to the first to fourth embodiments, the first coil L1 and the second coil L2 may have the configurations shown in Figures 28 to 30, for example. Figures 28 to 30 show the first coil L1 and the second coil L2 according to modified examples. Although Figures 28 to 30 mainly show the configuration of the first coil L1 according to the modified examples, the same applies to the second coil L2.

[0114] In each of the semiconductor devices A1 to A4, the first coil L1 has the outer ends L13 of the two winding portions L11 electrically connected by the lead-out wiring 321. In contrast, in the examples shown in FIGS. 28 and 29 , the first coil L1 has the inner ends L12 of the two winding portions L11 electrically connected by the lead-out wiring 321. Note that the wiring shapes of the lead-out wiring 321 are different between the examples shown in FIGS. 28 and 29 , but the electrical connection relationships are the same. Furthermore, in the example shown in FIG. 30 , the first coil L1 has four winding portions L11 that are electrically independent from each other, and the inner ends L12 and the outer ends L13 between any two winding portions L11 are not electrically connected by the lead-out wiring 321. Similarly, in each of the semiconductor devices A1 to A4, the outer ends L23 of the two winding portions L21 of the second coil L2 are electrically connected by the lead-out wiring 331. However, in the examples shown in FIGS. 28 and 29, the inner ends L22 of the two winding portions L21 of the second coil L2 are electrically connected by the lead-out wiring 331. Note that the wiring shapes of the lead-out wiring 331 are different between the examples shown in FIGS. 28 and 29, but the electrical connection relationships are the same. Furthermore, in the example shown in FIG. 30, the four winding portions L21 of the second coil L2 are each electrically independent, and neither the inner ends L22 nor the outer ends L23 of any two winding portions L21 are electrically connected by the lead-out wiring 331.

[0115] The semiconductor device according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. For example, the present disclosure includes the embodiments described in the following appendices. Appendix 1. A semiconductor device comprising: a first semiconductor element; a second semiconductor element; an insulating element including a first coil; a second coil magnetically coupled to the first coil; and a support substrate on which the first semiconductor element and the second semiconductor element are mounted, wherein the support substrate includes an insulating base material and substrate wiring formed on the base material, the substrate wiring including a first wiring portion electrically interposed between the first semiconductor element and the first coil and a second wiring portion electrically interposed between the second semiconductor element and the second coil, the second coil being disposed between the first coil and the base material, and the insulating element being supported by the support substrate. Appendix 2. The semiconductor device according to Supplementary Note 1, wherein the first semiconductor element is a drive element for driving a switching element, and the second semiconductor element is a control element for controlling the drive of the switching element, and the drive element requires a higher voltage than the control element. Supplementary Note 3. The semiconductor device according to Supplementary Note 1 or Supplementary Note 2, wherein the support substrate has a mounting surface on which the first semiconductor element, the second semiconductor element, and the insulating element are mounted, the mounting surface facing one side in the thickness direction of the support substrate, and a portion of each of the base material and the board wiring is exposed at the mounting surface. Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein the base material is made of glass. Supplementary Note 5. the first semiconductor element has a first element main surface and a first element back surface facing opposite each other in the thickness direction, and includes a first substrate, a first wiring layer, a first insulating layer, and a first pad; the first substrate has a first functional surface on which a first functional circuit is formed; the first wiring layer is conductive to the first functional circuit and is formed on the first functional surface; the first insulating layer covers the first wiring layer and is formed on the first functional surface; the first pad is conductive to the first wiring layer; and the first insulating layer and the first pad are exposed at the first element main surface.Appendix 6. The semiconductor device according to Appendix 5, wherein the first element main surface faces the mounting surface in the thickness direction, and the first semiconductor element and the support substrate are directly bonded to each other at the first pad and the first wiring portion, and also at the first insulating layer and the base material. Appendix 7. The semiconductor device according to Appendix 5 or Appendix 6, wherein the first insulating layer is made of glass. Appendix 8. The semiconductor device according to any one of Supplementary Notes 3 to 7, wherein the second semiconductor element has a second element main surface and a second element back surface facing opposite each other in the thickness direction, and includes a second substrate, a second wiring layer, a second insulating layer, and a second pad, the second substrate has a second functional surface on which a second functional circuit is formed, the second wiring layer is conductive to the second functional circuit and is formed on the second functional surface, the second insulating layer covers the second wiring layer and is formed on the second functional surface, the second pad is conductive to the second wiring layer, and the second insulating layer and the second pad are exposed at the second element main surface.Supplementary Note 9. The semiconductor device according to Supplementary Note 8, wherein the second element main surface faces the mounting surface in the thickness direction, and the second semiconductor element and the supporting substrate are directly bonded at the second pad and the second wiring portion, and at the second insulating layer and the base material.Supplementary Note 10. The semiconductor device according to Supplementary Note 8 or Supplementary Note 9, wherein the second insulating layer is made of glass. Supplementary Note 11. The semiconductor device according to any of Supplementary Note 3 to Supplementary Note 10, wherein the insulating element includes the second coil and a third insulating layer, and at least a portion of the third insulating layer is interposed between the first coil and the second coil in the thickness direction. Supplementary Note 12. The semiconductor device according to Supplementary Note 11, wherein the insulating element has a third element main surface and a third element back surface facing opposite each other in the thickness direction, the third element back surface facing the mounting surface in the thickness direction, the first coil is disposed on the third element main surface, and the second coil is disposed on the third element back surface.Appendix 13. The semiconductor device according to Appendix 12, wherein the insulating element includes a third pad connected to the first coil and a fourth pad connected to the second coil, the third pad, the fourth pad, and the third insulating layer are exposed on a back surface of the third element, and the insulating element and the support substrate are configured such that the third pad and the first wiring portion are directly bonded, the fourth pad and the second wiring portion are directly bonded, and the third insulating layer and the base material are directly bonded. Appendix 14. The semiconductor device according to any of Appendix 11 to Appendix 13, wherein the third insulating layer is made of glass. Appendix 15. The semiconductor device according to any of Appendix 3 to Appendix 14, wherein the support substrate is arranged in a region overlapping the first semiconductor element when viewed in the thickness direction, and includes a heat dissipation portion penetrating the base material in the thickness direction. Appendix 16. The semiconductor device according to any one of Supplementary Notes 3 to 15, further comprising a first external terminal electrically connected to the first semiconductor element and a second external terminal electrically connected to the second semiconductor element, wherein the support substrate has a terminal surface facing opposite the mounting surface in the thickness direction and on which the first external terminal and the second external terminal are arranged.Supplementary Note 17. The semiconductor device according to Supplementary Note 16, wherein the substrate wiring includes a third wiring portion electrically interposed between the first semiconductor element and the first external terminal and a fourth wiring portion electrically interposed between the second semiconductor element and the second external terminal, wherein the first external terminal is arranged outward from the first semiconductor element as viewed in the thickness direction, and the second external terminal is arranged outward from the second semiconductor element as viewed in the thickness direction.Supplementary Note 18. The semiconductor device according to Supplementary Note 17, further comprising an insulating resin material formed on the terminal surface and located between the first external terminal and the second external terminal as viewed in the thickness direction.Supplementary Note 19. 19. The semiconductor device according to claim 3, wherein the first coil and the second coil are located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction.Supplementary Note 20: The semiconductor device according to any one of Supplementary Note 3 to Supplementary Note 19, wherein each of the first coil and the second coil has two winding portions wound on a plane orthogonal to the thickness direction, and in each of the first coil and the second coil, the two winding portions each have a current input terminal and a current output terminal, and the current input terminals or the current output terminals are connected to each other.

[0116] A1 to A4: semiconductor device L1: first coil L11: winding portion L12: inner end L13: outer end L2: second coil L21: winding portion L22: inner end L23: outer end 1: first semiconductor element 10a: first element main surface 10b: first element back surface 11: first substrate 11a: first functional surface 12: first wiring layer 13: first insulating layer 14: first pad 141, 142: electrode 2: second semiconductor element 20a: second element main surface 20b: second element back surface 21: second substrate 21a: second functional surface 22: second wiring layer 23: second insulating layer 24: second pad 241, 242: electrode 3: insulating element 30a: third element main surface 30b: third element back surface 31: Third insulating layer 311: Intermediate portion 312: Upper covering portion 313: Lower covering portion 32: Upper wiring layer 321: Lead-out wiring 33: Lower wiring layer 331: Lead-out wiring 34: Third pad 35: Fourth pad 36: Connection wiring 37: Sixth pad 38: Passivation film 4: Support substrate 40a: Mounting surface 40b: Terminal surface 41: Base material 42: Substrate wiring 421: First wiring portion 422: Second wiring portion 423: Third wiring portion 424: Fourth wiring portion 425: Fifth wiring portion 426: Lead-out wiring 43: Through wiring 431: First through portion 432: Second through portion 44: Heat dissipation portion 51: First external terminal 52: Second external terminal 6: Sealing resin 61: Top surface 63: First side surface 64: Second side surface 67: Resin material 7: Connection member 71: First wire 72: Second wire 73: Third wire 74: Fourth wire

Claims

1. A first semiconductor element, A second semiconductor element, An insulating element including a first coil, A second coil magnetically coupled to the first coil, A support substrate on which the first semiconductor element and the second semiconductor element are mounted, and comprising: The support substrate includes an insulating base material and substrate wiring formed on the base material, The substrate wiring includes a first wiring portion electrically intervening between the first semiconductor element and the first coil, and a second wiring portion electrically intervening between the second semiconductor element and the second coil, The second coil is disposed between the first coil and the base material, The insulating element is supported by the support substrate, a semiconductor device.

2. The first semiconductor element is a driving element for driving a switching element, The second semiconductor element is a control element for controlling the driving of the switching element, The driving element requires a higher voltage than the control element, the semiconductor device according to claim 1.

3. The support substrate has a mounting surface on which the first semiconductor element, the second semiconductor element, and the insulating element are mounted, The mounting surface faces one direction in the thickness direction of the support substrate, A part of each of the base material and the substrate wiring is exposed on the mounting surface, the semiconductor device according to claim 1.

4. The base material is made of glass, the semiconductor device according to claim 3.

5. The first semiconductor element has a first element main surface and a first element back surface facing opposite sides in the thickness direction, and includes a first substrate, a first wiring layer, a first insulating layer, and a first pad, The first substrate has a first functional surface on which a first functional circuit is formed. The first wiring layer is electrically connected to the first functional circuit and is formed on the first functional surface. The first insulating layer covers the first wiring layer and is formed on the first functional surface. The first pad is electrically connected to the first wiring layer. The semiconductor device according to claim 3, wherein the first insulating layer and the first pad are exposed on the first main surface of the element.

6. The first main surface of the element faces the mounting surface in the thickness direction. The semiconductor device according to claim 5, wherein the first semiconductor element and the support substrate are directly bonded to each other such that the first pad and the first wiring portion are directly bonded, and the first insulating layer and the base material are directly bonded.

7. The semiconductor device according to claim 5, wherein the first insulating layer is made of glass.

8. The second semiconductor element has a second main surface and a second back surface facing opposite sides in the thickness direction, and includes a second substrate, a second wiring layer, a second insulating layer, and a second pad. The second substrate has a second functional surface on which a second functional circuit is formed. The second wiring layer is electrically connected to the second functional circuit and is formed on the second functional surface. The second insulating layer covers the second wiring layer and is formed on the second functional surface. The second pad is electrically connected to the second wiring layer. The semiconductor device according to any one of claims 3 to 7, wherein the second insulating layer and the second pad are exposed on the second main surface of the element.

9. The second main surface of the element faces the mounting surface in the thickness direction. The semiconductor device according to claim 8, wherein the second semiconductor element and the support substrate are directly joined with the second pad and the second wiring portion, and the second insulating layer and the base material are directly joined.

10. The semiconductor device according to claim 8, wherein the second insulating layer is made of glass.

11. The insulating element includes the second coil and a third insulating layer. The semiconductor device according to any one of claims 3 to 7, wherein at least a part of the third insulating layer is interposed between the first coil and the second coil in the thickness direction.

12. The insulating element has a third element main surface and a third element back surface facing opposite sides in the thickness direction. The third element back surface faces the mounting surface in the thickness direction. The first coil is disposed on the third element main surface. The semiconductor device according to claim 11, wherein the second coil is disposed on the third element back surface.

13. The insulating element includes a third pad connected to the first coil and a fourth pad connected to the second coil. The third pad, the fourth pad, and the third insulating layer are exposed on the third element back surface. The semiconductor device according to claim 12, wherein the insulating element and the support substrate are directly joined with the third pad and the first wiring portion, the fourth pad and the second wiring portion, and the third insulating layer and the base material.

14. The semiconductor device according to claim 11, wherein the third insulating layer is made of glass.

15. The semiconductor device according to any one of claims 3 to 7, wherein the support substrate is disposed in a region overlapping the first semiconductor element when viewed in the thickness direction, and includes a heat dissipation portion penetrating the base material in the thickness direction.

16. further comprising a first external terminal electrically connected to the first semiconductor element and a second external terminal electrically connected to the second semiconductor element, The semiconductor device according to any one of claims 3 to 7, wherein the support substrate faces the side opposite to the mounting surface in the thickness direction and has a terminal surface on which the first external terminal and the second external terminal are disposed.

17. The substrate wiring includes a third wiring portion electrically interposed between the first semiconductor element and the first external terminal, and a fourth wiring portion electrically interposed between the second semiconductor element and the second external terminal, The first external terminal is disposed outside the first semiconductor element when viewed in the thickness direction, The semiconductor device according to claim 16, wherein the second external terminal is disposed outside the second semiconductor element when viewed in the thickness direction.

18. The semiconductor device according to claim 17, further comprising an insulating resin material formed on the terminal surface and located between the first external terminal and the second external terminal when viewed in the thickness direction.

19. The semiconductor device according to any one of claims 3 to 7, wherein the first coil and the second coil are located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction.

20. Each of the first coil and the second coil has two winding portions wound on a plane orthogonal to the thickness direction, In each of the first coil and the second coil, each of the two winding portions has a current input end and a current output end, and the current input ends or the current output ends are connected to each other. The semiconductor device according to any one of claims 3 to 7.