Electric power conversion device

Abstract

This electric power conversion device having an arm pair (3) in which a first semiconductor switching element (M1) and a second semiconductor switching element (M2) are connected in series between a DC plus terminal and a DC minus terminal is configured to comprise: a third resistance group (6) that is connected in parallel with the first semiconductor switching element (M1); a second resistance group (5) that is connected in parallel with the second semiconductor switching element (M2); a reference-voltage-generating circuit (4) that generates a first reference voltage and a second reference voltage in which a voltage between the plus terminal and the minus terminal is divided; and an abnormality determination unit (11) that, after both semiconductor switching elements (M1, M2) have stopped operating, compares a detection voltage that is divided by the second resistance group (5) and the first and second reference voltages, and determines whether either of the semiconductor switching elements has undergone main breakdown voltage deterioration.

Description

Power Conversion Device

[0001] The present application relates to a power conversion device.

[0002] In a power conversion device, the power conversion function is realized by turning on / off a plurality of semiconductor switching elements that constitute the power converter. Examples of the semiconductor switching elements include voltage-driven semiconductor switching elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate-Bipolar-Transistors).

[0003] A fundamental characteristic of semiconductor switching elements is that they must maintain high insulating properties when their gates are turned off. However, these insulating properties can be lost due to moisture absorption from the insulating material used to seal them, potential defects in the semiconductor manufacturing process, and even undesigned overvoltage surges during operation. Therefore, understanding the degradation state of the semiconductor switching element's main breakdown voltage is expected to eliminate downtime for power conversion equipment by replacing the semiconductor switching element before it breaks down. In particular, since the larger the leakage current, the shorter the time it takes to break down, so there is a demand for technology that can accurately detect leakage current at a very low level.

[0004] Techniques for detecting an abnormality in the main withstand voltage of semiconductor switching elements in a power conversion device include the methods disclosed in, for example, Patent Document 1 or Patent Document 2. The abnormality detection device shown in Patent Document 1 includes one or more parallel power conversion units, and for each parallel power conversion unit, one high select terminal voltage detection unit with a corresponding detection resistor and one abnormality detection unit are provided, and in each parallel power conversion unit, the abnormality detection unit detects an abnormality in each power converter included in that parallel power conversion unit based on the voltage at the junction point.

[0005] The power supply device shown in Patent Document 2 has a configuration including an inverter circuit made up of two switch elements connected in series, and is equipped with an abnormality detection circuit that sends out an abnormality signal if the voltage at the connection point between the two switch elements exceeds a first reference voltage or falls below a second reference voltage when the inverter circuit is stopped.

[0006] JP 2019-110720 A JP 2013-243871 A

[0007] However, the technology proposed in Patent Document 1 determines a fault (detects an abnormality) when the detected voltage value changes compared to a predetermined threshold, but does not detect minute leakage currents due to deterioration of the main voltage resistance of semiconductor switching elements. Alternatively, the technology proposed in Patent Document 2 determines the junction voltage of an inverter circuit configured with semiconductor switching elements connected in series solely by the balance between the voltage-detecting resistors connected to the junction and the leakage currents of the semiconductor switching elements. Given the realistic conditions in which the leakage current of normal semiconductor switching elements is negligibly small, the junction voltage under normal conditions may converge to near zero due to the leakage current of the voltage-dividing resistors, making it impossible to accurately distinguish between normal and abnormal conditions. Furthermore, given the fact that the leakage current of semiconductor switching elements varies nonlinearly with the applied voltage, it is difficult to ensure a design margin for the reference voltage required to distinguish between normal and abnormal conditions in products with large fluctuations in the main circuit voltage, which results in an issue in which highly accurate leakage current detection is not possible.

[0008] The present application has been made to solve the above-mentioned problems, and has an object to provide a power conversion device that can accurately determine the main withstand voltage degradation of a semiconductor switching element.

[0009] The power conversion device disclosed in the present application is a power conversion device having an arm pair in which one of a DC positive terminal and a DC negative terminal is a first pole terminal and the other is a second pole terminal, a first semiconductor switching element is connected between the first pole terminal and an arm midpoint, and a second semiconductor switching element is connected between the arm midpoint and the second pole terminal, the power conversion device having an abnormality detection unit and a gate control unit, and a semiconductor drive control unit that controls the drive of the first semiconductor switching element and the second semiconductor switching element, the abnormality detection unit being connected in parallel to the first semiconductor switching element and a third resistor group having at least one resistor, and dividing a voltage applied to the second semiconductor switching element. a reference voltage generating circuit that generates a first reference voltage obtained by dividing the voltage between the first pole terminal and the second pole terminal and a second reference voltage that is different from the first reference voltage obtained by dividing the voltage between the first pole terminal and the second pole terminal; and an abnormality determining unit that, after the power conversion device stops its power conversion operation, compares a detection voltage that is the voltage divided by the second resistor group with the first reference voltage and the second reference voltage to determine whether the first semiconductor switching element or the second semiconductor switching element has deteriorated in main withstand voltage.

[0010] According to the present invention, it is possible to provide a power conversion device that can determine the main withstand voltage degradation of a semiconductor switching element with high accuracy.

[0011] FIG. 1 is a diagram showing a configuration of a power conversion device according to embodiment 1. FIG. 2 is a first timing chart for explaining the operation of the power conversion device according to embodiment 1. FIG. 3 is a third timing chart for explaining the operation of the power conversion device according to embodiment 1. FIG. 4 is a diagram showing another configuration of a power conversion device according to embodiment 1. FIG. 5 is a diagram showing a configuration of a power conversion device according to embodiment 2. FIG. 6 is a timing chart for explaining the operation of the power conversion device according to embodiment 2. FIG. 7 is a diagram showing a configuration of a power conversion device according to embodiment 3. FIG. 8 is a diagram showing a configuration of a power conversion device according to embodiment 4. FIG. 9 is a diagram showing a configuration of a power conversion device according to embodiment 5. FIG. 10 is a diagram showing a configuration of a power conversion device according to embodiment 6. FIG. 11 is a block diagram showing an example of the actual configuration of a gate signal generation unit, or a gate signal generation unit and an abnormality determination unit in each embodiment.

[0012] Embodiment 1. Hereinafter, an embodiment will be described with reference to the drawings. In the following description, similar or corresponding components will be designated by the same reference numerals. In the following description, a "failure" refers to a state of an element that causes the device to stop working, and a "degradation" refers to an element that operates but has deteriorated and no longer satisfies the required specifications. In the case of "degradation," if the element has undergone testing (screening) before being shipped, the "degradation" refers to an element that has been confirmed to satisfy the required specifications, quality, and reliability targets of various tests.

[0013] 1 is a diagram showing the configuration of a power conversion device according to a first embodiment. The power conversion device includes an arm pair (leg circuit) 3 in which a first semiconductor switching element M1 constituting an upper arm and a second semiconductor switching element M2 constituting a lower arm are connected in series between a positive-side potential PA and a negative-side potential GA of a DC power supply (not shown). For simplicity, an example of a single-phase inverter composed of one arm pair is shown here. The arm pair 3 has a positive-side terminal P and a negative-side terminal N, and an arm midpoint C as a connection point between the first semiconductor switching element M1 and the second semiconductor switching element M2.

[0014] The on / off operations of the first semiconductor switching element M1 and the second semiconductor switching element M2 are controlled by gate drivers 2H and 2L applying voltages between their respective gate sources based on on / off command signals SGH and SGL generated by gate signal generator 2. Here, the section consisting of gate signal generator 2, gate driver 2H, and gate driver 2L will be referred to as gate control unit 1. Gate driver 2H and gate driver 2L are generally configured to include a photocoupler that isolates the on / off command signals SGH and SGL, an insulating communication unit such as a level shifter or pulse transformer, a buffer that amplifies the insulating signal, a drive adjustment unit such as a gate resistor that adjusts the switching characteristics, and a short-circuit protection unit that detects a short circuit in the first semiconductor switching element M1 and the second semiconductor switching element M2 and safely shuts them off.

[0015] A first resistor group 4 (also referred to as a reference voltage generating circuit 4) consisting of at least three resistors connected in series is provided between the positive potential PA and negative potential GA of the DC power supply, and here an example is shown in which three resistors R20, R21, and R22 are connected in series.

[0016] A second resistor group 5 consisting of two or more resistors connected in series is provided in parallel to the second semiconductor switching element M2 of the lower arm, and here an example is shown in which two resistors, resistor R1 and resistor R2, are connected in series as the second resistor group 5. Similarly, a third resistor group 6 including one or more resistors is provided in parallel to the first semiconductor switching element M1 of the upper arm, and here an example is shown in which two resistors, R10 and R11, are connected in series as the third resistor group 6. The present application is not limited to the configuration of these resistor groups shown in the drawings, and the number of resistors connected in series may be increased.

[0017] It is preferable to provide a filter capacitor between the junction of the resistors in the first resistor group 4 and the negative potential GA to stabilize the reference potentials VrefH and VrefL generated by voltage division, and in this example, a filter capacitor C20 is provided between the junction of R20 and R21 and the negative potential GA. Furthermore, if necessary, a filter capacitor can be provided between the junction of the resistors in the second resistor group 5 and the negative potential GA to remove high-frequency noise superimposed on the detection voltage VdM generated by voltage division, and in this example, a filter capacitor C1 is provided between the junction of resistors R1 and R2 and the negative potential GA.

[0018] The reference voltage of the voltage range comparator 7 is a voltage generated by voltage division using resistors in the first resistor group 4. In this example, comparator CP1 uses a first reference voltage VrefH, and comparator CP2 uses a second reference voltage VrefL, which is different from the first reference voltage VrefH, as its reference voltage. The voltage range comparator 7 generates a signal to determine whether the detection voltage VdM generated by voltage division using resistors in the second resistor group 5 is within the range of the two different reference voltages (VrefL<VdM<VrefH). In this embodiment, the output SDH of comparator CP1 is a high output when VdM<VrefH, and the output SDL of comparator CP2 is a high output when VrefL<VdM. Therefore, when VdM≧VrefH, SDH outputs low, and when VrefL≧VdM, SDL outputs low.

[0019] After the semiconductor switching elements stop their on / off operations, the abnormality determination unit 11 compares the detection voltage VdM with the first reference voltage VrefH and the second reference voltage VrefL based on the output result of the voltage range comparator 7, and if VrefL≧VdM or VdM≧VrefH, determines that the main withstand voltage of the first semiconductor switching element M1 or the second semiconductor switching element M2 has deteriorated, and outputs a main withstand voltage abnormality signal FDL to the gate signal generation unit 2 and issues a warning.

[0020] As described above, the abnormality detection unit 10 includes the first resistor group (reference voltage generation circuit) 4, the second resistor group 5, the third resistor group 6, the voltage range comparator 7, and the abnormality determination unit 11. Here, the part consisting of the gate control unit 1 and the abnormality detection unit 10 is referred to as the semiconductor drive control unit 100.

[0021] 1 shows only an arm pair 3 in which a first semiconductor switching element M1 and a second semiconductor switching element M2 are connected in series for simplicity, but the present invention can also be applied to a power conversion device having multiple arm pairs. For example, it may be an H-bridge circuit in which two arm pairs are connected in parallel, or a three-phase inverter in which three arm pairs are connected in parallel.

[0022] (Method for Detecting Deterioration of Main Withstand Voltage) A method for detecting deterioration of main withstand voltage will be specifically described below with reference to signal timing charts. Deterioration of main withstand voltage refers to a state in which, when a voltage is applied across the main terminals of a semiconductor switching element and the semiconductor switching element is turned off, the leakage current, which flows between the main terminals, increases due to deterioration of the semiconductor switching element, and the semiconductor switching element no longer satisfies the required specifications. Even a semiconductor switching element with a deteriorated main withstand voltage can still perform normal on / off operations for a while, but in the near future, the leakage current will further increase, preventing normal on / off operations. FIG. 2 is a timing chart of signals during switching operations when the semiconductor switching elements are in a healthy state. Based on the upper-arm on command SGH and the lower-arm on command SGL generated by the gate signal generating unit 2, gate voltages VGH and VGL are applied to the gates of the first semiconductor switching element M1 of the upper arm and the second semiconductor switching element M2 of the lower arm, respectively. As a result, the first semiconductor switching element M1 and the second semiconductor switching element M2 perform on / off operations, with the upper arm performing synchronous rectification when the current IsH flows through the diode connected in parallel to the first semiconductor switching element, and the lower arm performing on / off operations to pass / cut off the forward drain current IdL of the second semiconductor switching element. At this time, the voltage Vac at the arm midpoint C, which is the connection point between the first semiconductor switching element M1 and the second semiconductor switching element M2, changes between VB + Vf, which is the voltage VB between the positive side potential PA and the negative side potential GA plus the forward voltage Vf of the diode, and the on-voltage Von due to the on-resistance of the semiconductor switching elements, with the upper and lower limits being VB + Vf.

[0023] The detection voltage VdM generated by voltage division by the second resistor group 5 alternates between being greater than the reference voltage VrefH designed by the resistance values ​​of the first resistor group 4 and being smaller than the reference voltage VrefL, and the detection voltage VdM transitions as the second semiconductor switching element M2 is turned on and off. Since degradation of the main breakdown voltage of the semiconductor switching element cannot be detected from the voltage Vac at the arm midpoint C in this switching state, the abnormality determination unit 11 holds the degradation diagnosis enable signal EDL in a low state to stop detection of degradation of the main breakdown voltage. As a result, the degradation detection signal FDL is held in a low state, preventing an erroneous output of a high state indicating degradation of the main breakdown voltage during switching operation.

[0024] FIG. 3 is a timing chart of signals immediately before and after the on / off operation of the semiconductor switching elements stops when the semiconductor switching elements are in a healthy state. This corresponds to the transition from the switching operation state shown in FIG. 2 to the state in which both the upper and lower arms are turned off. When both the upper and lower arms of the semiconductor switching elements turn off, the source current of the upper arm gradually decreases and reaches zero at time t31. After resonance occurs due to the main circuit inductance and the parasitic capacitance of the semiconductor switching elements, the source current converges to a static zero state. Correspondingly, the arm midpoint voltage Vac converges to around VB / 2, the convergence value being determined by the parasitic leakage currents of the first semiconductor switching element M1 and the second semiconductor switching element M2. Correspondingly, the detection voltage VdM converges to a value between the reference voltages VrefL and VrefH. At time t32, which is sufficiently after the arm midpoint voltage Vac has been settled into a steady state, the deterioration diagnosis enable signal EDL is set to a Hi state in the abnormality determination unit 11, thereby enabling the detection of deterioration in the main withstand voltage. However, since the reference voltage is designed so that the detection voltage VdM satisfies VrefL<VdM<VrefH when the semiconductor switching element is in a healthy state, the deterioration detection signal FDL is in a Lo state, meaning that no deterioration is detected.

[0025] 4 is a timing chart of signals after the on / off operation of the semiconductor switching element M1 is stopped when the main breakdown voltage of the first semiconductor switching element M1 is degraded. Compared to FIG. 3 , the detection voltage VdM after the on / off operation of the semiconductor switching element M1 is stopped exceeds the reference voltage VrefH, causing the comparator CP1 in the voltage range comparator 7 to determine that VdM≧VrefH, and the abnormality determination unit 11 changes the degradation detection signal FDL to a high output at time t33, indicating that degradation of the main breakdown voltage has been detected. The reason why the detection voltage VdM after the on / off operation is stopped exceeds the reference voltage VrefH is that the combined resistance of the total resistance of the third resistor group 6 and the parasitic resistance calculated from the leakage current of the first semiconductor switching element M1 and its applied voltage is smaller than the combined resistance of the total resistance of the second resistor group 5 and the parasitic resistance calculated from the leakage current of the second semiconductor switching element M2 and its applied voltage. The reference voltages VrefH and VrefL can be designed based on the range of the leakage current value to be detected and the parasitic leakage current value of a healthy product.

[0026] Here, the criterion for determining whether or not the main breakdown voltage has deteriorated can also be the time it takes for the detection voltage VdM to deviate from the voltage between the reference voltages VrefL and VrefH. That is, if the time it takes for the detection voltage VdM to deviate from the voltage between the two reference voltages is long, it is not determined that the main breakdown voltage has deteriorated, but if the time is short, it is determined that the main breakdown voltage has deteriorated. Alternatively, the amount of change in the detection voltage VdM per unit time when the detection voltage VdM deviates from the voltage between the reference voltages VrefL and VrefH can also be used as the criterion for determination. That is, if the amount of change is small, it is not determined that the main breakdown voltage has deteriorated, but if the amount of change is large, it is determined that the main breakdown voltage has deteriorated.

[0027] When the main breakdown voltage of the second semiconductor switching element M2 deteriorates, the combined resistance of the total resistance of the second resistor group 5 and the parasitic resistance calculated from the leakage current of the second semiconductor switching element M2 and the applied voltage thereto becomes smaller than when the main breakdown voltage is not deteriorated. As a result, the detection voltage VdM after the on / off operation stops becomes smaller than the reference voltage VrefL. This makes it possible to detect that the second semiconductor switching element M2 has deteriorated in the main breakdown voltage. Note that by making the combined resistance of the second resistor group 5 and the combined resistance of the third resistor group 6 equal, the accuracy of detecting deterioration in the main breakdown voltage of the first semiconductor switching element M1 and the second semiconductor switching element M2 can be made equal.

[0028] (Method for Designing Resistance Values ​​of Second Resistor Group and Third Resistor Group) The resistance values ​​of the second resistor group 5 and the third resistor group 6 are designed so that the leakage current value that flows according to the combined resistance value of each resistor group is larger than the leakage current value (the current value that flows when each semiconductor switching element is off) that is parasitic between the main terminals (between the terminals through which the main current of each semiconductor switching element flows) when the first semiconductor switching element M1 and the second semiconductor switching element M2 are in a healthy state, for example, in their initial state at the time of shipment. For example, it is conceivable to determine a detection target leakage current value that takes into account the leakage current set as a main withstand voltage screening condition at the time of shipment of the semiconductor switching elements, and add a margin to this to prevent erroneous detection, and then determine the combined resistance value of each resistor group so that this can be detected accurately.

[0029] If the leakage current through the second resistor group 5 and the third resistor group 6 is too large, the fluctuation range of the detection voltage VdM due to the increase in leakage current through the first semiconductor switching element M1 and the second semiconductor switching element M2 will be small, resulting in poor detection accuracy. Alternatively, if the leakage current through the second resistor group 5 and the third resistor group 6 is too small, the detection voltage VdM will vary greatly with respect to leakage currents within the normal range of the semiconductor switching elements, resulting in a problem of determining a normal state as an abnormal state or not being able to detect an abnormal state. For example, if the leakage current through the first semiconductor switching element M1 is negligible and the leakage current through the second semiconductor switching element M2 is equivalent to the screening condition at the time of shipment, when both semiconductor switching elements are turned off, the detection voltage VdM will be biased toward the lower arm even when the main withstand voltage is normal. However, the resistance values ​​of the second resistor group 5 and the third resistor group 6 can be designed to prevent this from being falsely detected.

[0030] (Timing for Detecting Deterioration of Main Withstand Voltage) Detection of deterioration of the main withstand voltage of the first semiconductor switching element M1 and the second semiconductor switching element M2 is performed when they are both turned off and the output voltage at the arm midpoint C, which is their series connection point, has converged to a steady value. Specifically, this can be performed when the device is started, stopped, or coasting. Note that because the main withstand voltage leakage current increases in accordance with the junction temperature of the elements (temperature of the junction), detection immediately after the device is stopped, when the junction temperature of the semiconductor switching elements is higher than the ambient temperature, allows for the most accurate determination of deterioration of the withstand voltage.

[0031] Furthermore, since the junction temperature of the switching element is not high when the device is started, the power conversion device is operated to raise the junction temperature, and by detecting the temperature at the timing when it is higher than the ambient temperature, it is possible to determine with high accuracy the deterioration of the main breakdown voltage.

[0032] (Operation after Deterioration is Detected) When it is determined that the semiconductor switching element has deteriorated in the main withstand voltage, the abnormality determination unit 11 shown in FIG. 1 or 5 notifies the receiver of the abnormality. For example, an abnormality lamp may be provided in the device, and the abnormality lamp may be turned on when it is determined that the main withstand voltage has deteriorated. When the abnormality lamp is turned on, the device may be immediately shut down. Alternatively, since the abnormality lamp is turned on when it is determined that the switching element has deteriorated before it is destroyed, the device may continue operating until the next opportunity to shut down, even if the abnormality lamp is turned on, and the semiconductor switching element may be replaced when the device is shut down.

[0033] Furthermore, if it is determined that the semiconductor switching element has deteriorated in main breakdown voltage, the operation of the power conversion device may be changed to temporarily extend the life of the semiconductor switching element by reducing the load on the semiconductor switching element. For example, the original inverter modulation method may be changed from three-phase modulation to two-phase modulation, or the switching carrier frequency may be lowered to reduce the number of switching operations. Alternatively, stress may be reduced by reducing the load current. In this way, by temporarily extending the life of the switching element after detecting an abnormality in the semiconductor switching element and displaying a warning, the device can continue to operate without stopping, enabling the device to operate according to the planned operating schedule without downtime.

[0034] (Effect of the Configuration in Which the Reference Voltages Vary According to the Main Circuit Voltage) In the first embodiment, the first reference voltage VrefH and the second reference voltage VrefL of the voltage range comparator 7 are generated by voltage division using resistors in the first resistor group 4, which are arranged between the main circuit positive-side potential PA and the main circuit negative-side potential GA. Therefore, when the main circuit voltage decreases, the range of reference voltages (VrefH-VrefL) that the abnormality determination unit 11 determines as normal narrows. Conversely, when the main circuit voltage increases, these reference voltages widen. This configuration takes into account the fact that the main breakdown voltage leakage current increases nonlinearly with increasing applied voltage. This configuration prevents a decrease in the leakage current due to a nonlinear decrease in the main circuit voltage, which would result in a deterioration in detection accuracy, and a nonlinear increase in the leakage current due to an increase in the main circuit voltage, which would result in a false detection of a normal state as an abnormality. This configuration enables detection of minute leakage currents with higher accuracy than conventional configurations, thereby extending the life of the semiconductor switching elements.

[0035] Fig. 5 is a block diagram showing another configuration of the power conversion device according to embodiment 1. In Fig. 1, the detection voltage VdM is a voltage divided by a second resistor group 5 provided in parallel to a second semiconductor switching element M2 constituting a negative arm. In the configuration of Fig. 5, the semiconductor switching element constituting the negative arm is a first semiconductor switching element M1, the semiconductor switching element constituting the positive arm is a second semiconductor switching element M2, a second resistor group 5 is provided in parallel to this second semiconductor switching element M2, and the voltage divided by this second resistor group 5 is the detection voltage VdM.

[0036] In the configuration shown in FIG. 1 , the first reference voltage VrefH and the second reference voltage VrefL are generated by a reference voltage generating circuit 4, which is a first resistor group consisting of three series-connected resistors. In the configuration shown in FIG. 5 , the first resistor group 4 as a reference voltage generating circuit is composed of two series resistors: a series combination of resistors R23 and R24 connected between the positive potential PA and the negative potential GA, and a series combination of resistors R25 and R26 connected between the positive potential PA and the negative potential GA. The first reference voltage VrefH is generated by voltage division using the series combination of resistors R23 and R24, and the second reference voltage VrefL is generated by voltage division using the series combination of resistors R25 and R26. To stabilize the reference voltages, a filter capacitor C22 is provided in parallel with resistor R24, and a filter capacitor C21 is provided in parallel with resistor R26. In this way, the reference voltage generating circuit 4 may have any configuration as long as it is configured to divide the voltage between the positive potential PA and the negative potential GA to generate a first reference voltage VrefH and a second reference voltage VrefL that is a voltage different from the first reference voltage VrefH.

[0037] In the case of the configuration of Fig. 5, it is preferable to configure the first reference voltage VrefH, the second reference voltage VrefL, and the detection voltage VdM using a circuit that uses the positive-side potential PA as a reference. Even in the configuration of Fig. 5, as in the configuration of Fig. 1, by comparing the detection voltage VdM with the first reference voltage VrefH and the second reference voltage VrefL, it is possible to determine whether the main withstand voltage of the first semiconductor switching element M1 or the second semiconductor switching element M2 has deteriorated.

[0038] As described above, the power conversion device according to the first embodiment is a power conversion device having an arm pair in which one of the DC positive terminal PA and negative terminal GA is a first pole terminal and the other is a second pole terminal, the first semiconductor switching element M1 is connected between the first pole terminal and the arm midpoint C, and the second semiconductor switching element M2 is connected between the arm midpoint and the second pole terminal, the power conversion device has a third resistor group 6 connected in parallel to the first semiconductor switching element M1 and having at least one resistor, a second resistor group 5 which is a series body of a plurality of resistors connected in parallel to the second semiconductor switching element M2 so as to divide the voltage applied to the second semiconductor switching element M2, and a second resistor group 6 which is a series body of a plurality of resistors connected in parallel to the second semiconductor switching element M2 so as to divide the voltage applied to the first pole terminal and the second pole terminal. and a reference voltage generating circuit 4 that generates a first reference voltage VrefH obtained by dividing the voltage between the first pole terminal and the second pole terminal, and a second reference voltage VrefL obtained by dividing the voltage between the first pole terminal and the second pole terminal and that is different from the first reference voltage VrefH; and an abnormality determining unit 11 that determines whether the first semiconductor switching element M1 or the second semiconductor switching element M2 has deteriorated in main withstand voltage when a detection voltage VdM divided by a second resistor group 5 is a voltage that is out of the range between the first reference voltage VrefH and the second reference voltage VrefL after the first semiconductor switching element M1 and the second semiconductor switching element M2 stop their on / off operations.

[0039] Therefore, it is possible to accurately detect whether the first semiconductor switching element M1 or the semiconductor switching element M2 has deteriorated in main withstand voltage.

[0040] Embodiment 2 Fig. 6 is a configuration diagram showing the configuration of a power conversion device according to embodiment 2. In Fig. 6, an abnormality detection unit 20 and a gate control unit 1 constitute a semiconductor drive control unit 200. Below, only the differences between the abnormality detection unit 20 and the abnormality detection unit 10 of Fig. 1 will be described.

[0041] The abnormality detection unit 20 differs from the abnormality detection unit 10 of FIG. 1 in that the abnormality determination unit 12 also performs short-circuit detection and dead time detection using the voltage range comparator 7 used for main breakdown voltage degradation detection. Short-circuit detection detects a state in which the first semiconductor switching element M1 and the second semiconductor switching element M2 are simultaneously conducting, i.e., a so-called arm short circuit. This may indicate a noise malfunction, insufficient dead time in the upper and lower arms, or a semiconductor switching element failure. Dead time detection detects the delay time from the generation of the on / off command signal generated by the gate signal generation unit 1 to the actual on / off switching of the semiconductor switching elements. Detecting the dead time and correcting it to an optimal dead time can improve the output performance of the power conversion device.

[0042] While the main breakdown voltage degradation diagnosis described in the first embodiment detects a steady state after the inverter is stopped, short circuit detection and dead time detection detect transient states during switching. Therefore, while the main breakdown voltage degradation diagnosis does not require high responsiveness of the detection circuit, short circuit detection and dead time detection require high detection accuracy. Therefore, short circuit detection and dead time detection require high responsiveness of the detection circuit but do not require precision in voltage amplitude. These requirements are in a trade-off relationship. In other words, if the resistance value of the second resistor group 5 is increased to improve the detection accuracy of the leakage current for main breakdown voltage degradation detection, even if the filter capacitor C1 is reduced, the small parasitic capacitance of the comparator in the voltage range comparator 7 increases the transition time of the detection voltage VdM, resulting in a problem of delayed short circuit detection and dead time detection.

[0043] To solve the above problem, in the second embodiment, the second resistor group 5 is composed of a resistor R1 (also referred to as a first resistor) located on the arm midpoint side and a resistor R2 (also referred to as a second resistor) connected in series with the resistor R1, and a speed-up capacitor C2 (also referred to as a second capacitor) is provided in parallel with the resistor R1 located on the arm midpoint side of the second resistor group 5. As a result, the steady-state convergence value of the detection voltage VdM is determined by the resistance ratio within the second resistor group 5, while the transient convergence value of the detection voltage VdM is determined by the capacitance ratio between the speed-up capacitor C2 and the filter capacitor C1 (first capacitor) (taking into account the input parasitic capacitance of the comparators CP1 and CP2 as necessary). This allows for a design that optimizes the detection accuracy of main withstand voltage degradation and the detection delay for short-circuit detection and dead time detection. Specifically, the resistance Rs1 of the resistor R1 at the midpoint of the arm of the second resistor group 5, the resistance Rs2 of the resistor R2 connected in series with the resistor R1, the capacitance Cs1 of the filter capacitor C1 connected in parallel with the resistor R1, and the capacitance Cs2 of the speed-up capacitor C2 connected in parallel with the resistor R2 are set to satisfy the relationship Rs2 / (Rs1+Rs2)<Cs2 / (Cs1+Cs2), thereby enabling effective response to different detection events. That is, the detection voltage during transient events such as short circuit and dead time detection can be quickly transitioned to a low voltage level for short circuit detection or dead time detection determined by the capacitor voltage, while the steady-state detection voltage thereafter can be set to a high voltage level for main withstand voltage degradation diagnosis determined by the resistor ratio. This allows a common determination circuit to be used to effectively achieve both short circuit detection and dead time detection, which require high speed, and main withstand voltage degradation diagnosis, which requires high accuracy.

[0044] The dead time detection and short circuit detection methods will be described below with reference to the timing chart of FIG. 7 . Generally, a semiconductor switching element has a turn-on time (t on ) required to switch from an off state to an on state and a turn-off time (t off ) required to switch from an on state to an off state. As the gate resistance of the semiconductor switching element increases, the turn-on time t on and the turn-off time t off increase. Furthermore, the turn-on time t on and the turn-off time t off also increase or decrease depending on variations in electrical characteristics of the semiconductor switching element, such as the gate threshold voltage, and operating conditions, such as the junction temperature. Taking this into consideration, the on-command signals SGH and SGL for the upper and lower arms generated by the gate signal generator 2 are each provided with a sufficient dead time, which is a period during which the signals indicate an off state. However, because the presence of dead time reduces the output performance of the power conversion device, control may be applied to detect the actual turn-on time t on and the turn-off time t off and optimize the dead time. In the second embodiment, the dead time is optimized by detecting the time when the detection voltage VdM crosses the reference voltage VrefH or VrefL using the voltage range comparator 7 used for detecting degradation of the main withstand voltage. For example, in FIG. 7 , the dead time from the issuance of the on command to the actual transition of the main terminal voltage can be detected by detecting the time t41 when the detection voltage VdM falls below the reference voltage VrefL as a result of a decrease in the arm midpoint voltage Vac after the issuance of the lower arm on command SGL. Based on the detected dead time, the on command signals SGH and SGL for the upper and lower arms generated by the gate signal generating unit 2 are corrected to correct the amount of dead time, thereby improving the output characteristics of the power conversion device.

[0045] Next, a short-circuit detection method will be described. Figure 7 illustrates a situation in which the second semiconductor switching element M2 breaks down at time t42 while the lower arm is turning off, resulting in a loss of the main breakdown voltage. In this case, an arm short circuit occurs when an ON command signal SGH is subsequently sent to the corresponding upper arm, turning on the first semiconductor switching element M1, causing an excessive current to flow. As a result, while the arm midpoint voltage Vac would normally rise to VB + Vf, the semiconductor switching element M1 is saturated with current, preventing the arm midpoint voltage Vac from rising. As a result, the detection voltage VdM remains below the reference voltage VrefL. In other words, a short circuit can be detected from the logical inconsistency between the ON command signal sent by the gate signal generating unit 2 and the detection voltage VdM. As a result, the short-circuit detection signal FDS goes high at time t43, reflecting factors such as filter delays within the abnormality determination unit 12. When the abnormality determination unit 12 detects a short circuit and the short circuit detection signal FDS becomes Hi, the gate signal generation unit 2 generally takes measures to turn off all ON command signals to stop the operation of the power conversion device. Also, by increasing the OFF gate resistance value when interrupting the short circuit current, it is possible to reliably prevent overvoltage breakdown.

[0046] To speed up short-circuit detection, in this second embodiment, the reference voltage used for short-circuit detection when the upper arm is turned on is VrefL. Similarly, the reference voltage used for short-circuit detection when the lower arm is turned on is assumed to be VrefH. This selection is made to select the reference voltage VrefL or VrefH, whichever is more suitable for speeding up short-circuit detection, for the following reasons. Assume that the state in which the first semiconductor switching element M1 of the upper arm turns on after time t42 in FIG. 6 is normal switching. In this case, the arm midpoint voltage Vac rises to VB+Vf during normal switching. However, when VrefH is used as the reference voltage, the time at which it exceeds the reference value is delayed compared to when VrefL is used. In other words, it takes time to identify normal switching. Therefore, during this time, it is necessary to lock the short-circuit detection function or mask the detection signal with a low-pass filter. As a result, when a short circuit actually occurs, the delay time until the short-circuit detection signal FDS is generated increases, degrading short-circuit protection performance. For this reason, it is preferable to set the determination reference voltage used for short-circuit detection when the upper arm is turned on to VrefL, and the determination reference voltage used for short-circuit detection when the lower arm is turned on to VrefH.

[0047] Third Embodiment Fig. 8 is a circuit diagram showing the configuration of a power conversion device 110 according to a third embodiment. The power conversion device 110 is an inverter that converts DC power from a DC power supply 60 into three-phase AC power and supplies it to an AC motor 70. The power conversion device 110 includes a power converter 30 having a plurality of semiconductor switching elements for converting the power into three-phase AC of U, V, and W, and a semiconductor drive control unit 100A having a gate control unit 1A that drives each of the semiconductor switching elements in the power converter 30. The semiconductor drive control unit 100A includes an abnormality detection unit 10 having the same configuration as the abnormality detection unit 10 of the first embodiment for the U-phase arm pair formed by the first semiconductor switching element M1 and the second semiconductor switching element M2. The semiconductor drive control unit 100A does not include an abnormality detection unit 10 for the semiconductor switching elements M3 and M4 that form the V-phase arm pair or the semiconductor switching elements M5 and M6 that form the W-phase arm pair.

[0048] In this embodiment 3, an abnormality detection unit 10 having the same configuration as the abnormality detection unit 10 of the semiconductor drive control unit 100 mounted in the power conversion device according to embodiment 1 can detect any deterioration in the main withstand voltage of any of the semiconductor switching elements that make up the power converter 30, thereby providing a power conversion device 110 that is inexpensive and can achieve no downtime.

[0049] The following describes the principle by which a single anomaly detection unit 10 provided in the U phase can detect any deterioration in the main withstand voltage of any of the semiconductor switching elements that make up the power converter 30. Generally, AC motors 70 have high insulation characteristics ranging from several hundred megaohms to several gigaohms or more, so leakage currents generated through the AC motor 70 are not dominant. For this reason, leakage currents do not become a factor that deteriorates the detection accuracy of deterioration in the main withstand voltage of the semiconductor switching elements, and the reference voltage of the anomaly detection unit 10 provided in the U phase can be set taking into account the insulation characteristics of the AC motor 70.

[0050] As an example, suppose the main breakdown voltage of semiconductor switching element M5 in the W-phase upper arm deteriorates, causing an increase in leakage current. When power converter 30 stops switching and the potentials at the arm midpoints (connection points of the upper and lower arms) of each phase are stable, the potential at the W-phase arm midpoint becomes higher than normal. For example, if the resistance across second resistor group 5 provided in abnormality detection unit 10 is equal to the resistance across third resistor group 6, the potential at the W-phase arm midpoint will be near half voltage VB / 2 of DC voltage VB when the main breakdown voltage is not deteriorated. However, when the main breakdown voltage deteriorates, the potential will change toward being greater than VB / 2. In this case, because the three-phase windings are electrically connected within AC motor 70, the potential at the arm midpoints of U-phase and V-phase will also be equal to the potential at the arm midpoint of W-phase. Therefore, as shown in the configuration of FIG. 8, abnormality detection unit 10 provided only in the U-phase can detect deterioration of the main breakdown voltage in any of the semiconductor switching elements constituting power converter 30.

[0051] Furthermore, although the above description has been given assuming that the insulation characteristics of the AC motor 70 are normal, if the insulation characteristics deteriorate for some reason, the potential at the arm midpoint changes to be smaller than half-voltage VB / 2 of the DC voltage VB, so the power conversion device 110 of this embodiment can also detect insulation deterioration of the AC motor 70 it is driving. Note that if the potential at the arm midpoint changes to be smaller than half-voltage VB / 2 of the DC voltage VB, it may be difficult to determine whether the deterioration is due to insulation deterioration of the AC motor 70 or deterioration of the main withstand voltage of the semiconductor switching elements. To reliably determine whether the deterioration is due to main withstand voltage deterioration of the semiconductor switching elements or insulation deterioration of the motor, for example, a switch can be provided between the arm midpoint and the motor to check for main withstand voltage deterioration of the semiconductor switching elements with the motor disconnected.

[0052] Although the power converter 30 has been described as outputting two levels of AC voltage, positive and negative, the configuration of this embodiment can also be applied to an inverter capable of outputting multilevel voltages in which any number of semiconductor switching elements are connected in series and parallel.

[0053] Fourth Embodiment. FIG. 9 is a diagram showing the configuration of a power conversion device 120 according to a fourth embodiment. Differences from the third embodiment will now be described. Like the third embodiment, the power conversion device 120 according to this embodiment is an inverter that converts DC power from a DC power supply 60 into three-phase AC power and supplies it to an AC motor 70, and each semiconductor switching element is on / off controlled by a gate control unit 1B provided in a semiconductor drive control unit 200B. The power conversion device 120 according to the fourth embodiment differs from the third embodiment in that the semiconductor drive control unit 200B includes, as an abnormality detection unit, abnormality detection units 20U, 20V, and 20W having the same configuration as the abnormality detection unit 20 in the second embodiment, for detecting abnormalities in each arm pair of the U-phase, V-phase, and W-phase, respectively. Like the abnormality detection unit 20 in the second embodiment, the abnormality detection units 20U, 20V, and 20W each detect deterioration of the main withstand voltage of the semiconductor switching elements and detect arm short-circuits or dead time based on the determination results of the respective abnormality determination units. In the third embodiment, the main breakdown voltage degradation of the semiconductor switching elements could be determined based on the detected voltage in one of the three-phase arms, but arm short-circuit detection and dead time detection must be performed using the detected voltage in each of the three-phase arm pairs. Therefore, the semiconductor drive control unit 200B of the fourth embodiment includes three abnormality detection units 20U, 20V, and 20W. When the first reference voltage and the second reference voltage are set to the same voltage in the abnormality detection units 20U, 20V, and 20W, the outputs of the first reference voltage and the second reference voltage generated by a reference voltage generation circuit provided in the abnormality detection unit 20U may be input to the abnormality detection units 20V and 20W, respectively.

[0054] In this way, by integrating the functions of detecting main breakdown voltage degradation of semiconductor switching elements, arm short circuit detection, and dead time detection, an inexpensive power conversion device 120 capable of detecting abnormalities with high accuracy can be obtained.

[0055] Fifth Embodiment. Figure 10 is a diagram showing the configuration of a power conversion device 130 according to a fifth embodiment. Differences from the third and fourth embodiments will be described below. The power conversion device 130 of this fifth embodiment includes a power converter 31 having an arm pair of a semiconductor switching element M7 and a semiconductor switching element M8, a gate control unit 1C that drives the semiconductor switching elements M7 and M8 in the power converter 31, and a semiconductor drive control unit 100C having an abnormality detection unit 10C. In this case, the power converter 31 is a boost converter that boosts the DC voltage of a DC power supply 60 and supplies it to a DC load 70B. The abnormality detection unit 10C has a configuration similar to either the abnormality detection unit 10 having the main breakdown voltage degradation diagnosis function shown in the first embodiment or the abnormality detection unit 20 having the arm short-circuit detection function and / or the dead time detection function shown in the second embodiment.

[0056] The power converter 31 includes a pair of arms each having a semiconductor switching element M7 and a semiconductor switching element M8 connected in series, an input-side smoothing capacitor 41, an output-side smoothing capacitor 42, and a boost reactor 43. In this case, too, a power conversion device 130 can be obtained that has an inexpensive configuration and a highly accurate semiconductor switching element main withstand voltage degradation diagnosis function, or that adds an arm short-circuit detection function to the main withstand voltage degradation diagnosis function, and further adds a dead time detection function. Note that while a boost converter is shown in the above example, the present invention can also be applied to a buck converter, or a buck-boost converter that combines a boost converter and a buck converter.

[0057] Sixth Embodiment. Figure 11 is a diagram showing the configuration of a power conversion device 140 according to a sixth embodiment. Differences from the power conversion device 110 according to the third embodiment shown in Figure 3 will be described below. The power conversion device 140 of this embodiment includes a power converter in which the power converter 31, which is a boost converter shown in Figure 10, is connected to the DC side of the power converter 30 shown in Figure 8, and a semiconductor drive control unit 100D having a gate control unit 1D that drives each semiconductor switching element. The semiconductor drive control unit 100D includes two sets of anomaly detection units 10 and 10C to diagnose main withstand voltage degradation of the semiconductor switching elements of the power converter 30 and the power converter 31. The anomaly detection unit 10 has the same configuration as the anomaly detection unit 10 of the first embodiment, and the anomaly detection unit 10C has the same configuration as the anomaly detection unit 10C of the fifth embodiment.

[0058] In this case as well, it is possible to obtain a power conversion device 140 that has an inexpensive configuration and can achieve no downtime by highly accurate diagnosis of deterioration of the main withstand voltage of the semiconductor switching elements.

[0059] The power conversion device 140 boosts the DC voltage of the DC power supply 60 using the power converter 31, which is a boost converter, and the boosted DC power is converted into AC power by the power converter 30 and supplied to the AC motor 70. The power conversion device 140 operates as a boost inverter system and is applied to, for example, an electric vehicle. Note that the power converter 30 in the power conversion device 140 may be an inverter capable of outputting multilevel voltages. Furthermore, the power converter 31 in the power conversion device 140 is not limited to a boost converter, and may also be a buck converter or a buck-boost converter that combines a boost converter and a buck converter.

[0060] In the above first to sixth embodiments, the semiconductor switching elements are illustrated as MOSFETs, but other semiconductor switching elements having control terminals, such as IGBTs, may also be used. Furthermore, the diodes shown in parallel with the MOSFETs are not limited to body diodes parasitic on the MOSFETs, and may be diodes provided separately.

[0061] Furthermore, a wide bandgap semiconductor material having a bandgap larger than that of Si may be used for the semiconductor switching elements of at least one arm pair, thereby increasing the switching speed of the semiconductor switching elements and realizing low loss and miniaturization of the power conversion device. As the wide bandgap semiconductor material, any of silicon carbide (SiC), gallium nitride (GaN), gallium oxide (GaO), or diamond can be used.

[0062] The abnormality determination unit in each of the above embodiments can be configured with a logic circuit or can be configured by arithmetic processing using a processor. The gate driver can be configured with a circuit combining a conventional integrated circuit and circuit elements such as resistors and capacitors. The gate signal generation unit can also be configured with a logic circuit, an integrated circuit, and other circuit elements such as resistors. For example, the gate signal generation unit 2, or the gate signal generation unit and the abnormality determination unit, can be configured together as a processing device, such as a central processing unit (CPU), 21, a storage device 22 that exchanges data with the processing unit 21, and an input / output interface 23 that inputs and outputs signals between the processing unit 21 and the outside, as shown in FIG. 12 .

[0063] Although various exemplary embodiments and examples are described in this application, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, and even cases where at least one component is extracted and combined with components of another embodiment.

[0064] 1, 1A, 1B, 1C, 1D Gate control unit, 2 Gate signal generating unit, 3 Arm pair, 4 Reference voltage generating circuit, 5 Second resistor group, 6 Third resistor group, 10, 10C, 20, 20U, 20V, 20W Abnormality detection unit, 11, 12 Abnormality determination unit, 100, 100A, 100C, 100D, 200, 200B Semiconductor drive control unit, M1 First semiconductor switching element, M2 Second semiconductor switching element, C Arm midpoint, C1 First capacitor, C2 Second capacitor, GA Negative terminal, PA Positive terminal, R1 First resistor, R2 Second resistor, VdM Detection voltage, VrefH First reference voltage, VrefL Second reference voltage

Claims

1. A power conversion device having an arm pair in which one of a DC positive terminal and a DC negative terminal is a first pole terminal and the other is a second pole terminal, a first semiconductor switching element is connected between the first pole terminal and an arm midpoint, and a second semiconductor switching element is connected between the arm midpoint and the second pole terminal, a semiconductor drive control unit having an abnormality detection unit and a gate control unit, and controlling the driving of the first semiconductor switching element and the second semiconductor switching element; The abnormality detection unit a third resistor group connected in parallel to the first semiconductor switching element and including at least one resistor; a second resistor group including a series body of a plurality of resistors connected in parallel with the second semiconductor switching element so as to divide a voltage applied to the second semiconductor switching element; a reference voltage generating circuit for generating a first reference voltage obtained by dividing a voltage between the first electrode terminal and the second electrode terminal, and a second reference voltage obtained by dividing a voltage between the first electrode terminal and the second electrode terminal, the second reference voltage being a voltage different from the first reference voltage; and an abnormality determination unit that, after the power conversion device stops the power conversion operation, compares a detection voltage, which is a voltage divided by the second resistor group, with the first reference voltage and the second reference voltage to determine whether the first semiconductor switching element or the second semiconductor switching element has deteriorated in main withstand voltage. Power conversion equipment.

2. The power conversion device according to claim 1, wherein the abnormality determination unit determines that the first semiconductor switching element or the second semiconductor switching element has undergone main voltage resistance degradation when the detected voltage is a voltage that is outside the range between the first reference voltage and the second reference voltage after the power conversion device stops its power conversion operation.

3. 2. The power conversion device according to claim 1, wherein the abnormality determination unit determines that the arm pair is in an arm short-circuit state when, when the first semiconductor switching element or the second semiconductor switching element is turned on, the detection voltage is a voltage that is logically inconsistent with the detection voltage when the first semiconductor switching element and the second semiconductor switching element are normal.

4. The power conversion device according to claim 3 , comprising a plurality of the arm pairs, each of the arm pairs being provided with the abnormality detection unit.

5. A power conversion device having a plurality of arm pairs, in which one of a positive terminal and a negative terminal of a direct current is a first pole terminal and the other is a second pole terminal, a first semiconductor switching element is connected between the first pole terminal and an arm midpoint, and a second semiconductor switching element is connected between the arm midpoint and the second pole terminal, a semiconductor drive control unit that has an abnormality detection unit and a gate control unit and controls driving of the first semiconductor switching element and the second semiconductor switching element of all arm pairs; The abnormality detection unit a third resistor group connected in parallel to the first semiconductor switching element of one of the arm pairs, the third resistor group including at least one resistor; a second resistor group including a series body of a plurality of resistors connected in parallel to the second semiconductor switching element of the first arm pair so as to divide a voltage applied to the second semiconductor switching element of the first arm pair; a reference voltage generating circuit for generating a first reference voltage obtained by dividing a voltage between the first electrode terminal and the second electrode terminal, and a second reference voltage obtained by dividing a voltage between the first electrode terminal and the second electrode terminal, the second reference voltage being a voltage different from the first reference voltage; and an abnormality determination unit that, after the power conversion device stops a power conversion operation, compares a detection voltage, which is a voltage divided by the second resistor group, with the first reference voltage and the second reference voltage to determine whether or not a main withstand voltage degradation has occurred in any of the semiconductor switching elements constituting the multiple arm pairs. Power conversion equipment.

6. The power conversion device according to claim 1 or 5, wherein the abnormality determination unit determines whether or not a main withstand voltage has deteriorated based on a time until the detected voltage deviates from a voltage between the first reference voltage and the second reference voltage after the power conversion device stops its power conversion operation, or based on an amount of change in the detected voltage per unit time.

7. The power conversion device according to claim 1 , wherein the abnormality determination unit determines whether or not a main withstand voltage has deteriorated when temperatures of all semiconductor switching elements are higher than an ambient temperature.

8. The power conversion device according to claim 1 , further comprising a capacitor connected in parallel to at least one resistor of the second resistor group.

9. 5. The power conversion device according to claim 3 or 4, wherein the second resistor group is configured in series with a first resistor having a resistance value Rs1 on the arm midpoint side and a second resistor having a resistance value Rs2 connected to the first resistor, a first capacitor having a capacitance Cs1 is connected in parallel to the second resistor, and a second capacitor having a capacitance Cs2 is connected in parallel to the first resistor, satisfying the relationship Rs2 / (Rs1+Rs2)<Cs2 / (Cs1+Cs2).

10. 10. The power conversion device according to claim 9, wherein the abnormality determination unit calculates a dead time based on a time from an on command output by a gate signal generating unit provided in the gate control unit to the first semiconductor switching element or the second semiconductor switching element to a time when the detection voltage crosses the first reference voltage or the second reference voltage, and corrects an amount of dead time due to each of the on / off signals of the first semiconductor switching element and the second semiconductor switching element output by the gate signal generating unit based on the calculated dead time.

11. 6. The power conversion device according to claim 1, wherein the resistance value across the second resistor group is set so that the current value flowing through the second resistor group is greater than the leakage current value parasitic between the main terminals in the initial state of the second semiconductor switching element connected in parallel to the second resistor group, and the resistance value across the third resistor group is set so that the current value flowing through the third resistor group is greater than the leakage current value parasitic between the main terminals in the initial state of the first semiconductor switching element connected in parallel to the third resistor group.

12. The power conversion device according to claim 1 , wherein a resistance value across the second resistor group and a resistance value across the third resistor group are equal to each other.

13. The power conversion device according to any one of claims 1 to 5, wherein the semiconductor drive control unit changes the operation of the power conversion device so as to reduce the load on any one of the semiconductor switching elements after the abnormality determination unit determines that the main withstand voltage of the semiconductor switching element has deteriorated.

14. The power conversion device according to any one of claims 1 to 5, which is a power conversion device including at least one of a power converter that performs power conversion between DC power and AC power, a boost converter that boosts a DC voltage, and a step-down converter that lowers a DC voltage.

15. 6. The power conversion device according to claim 1 or 5, wherein the pair of arms constitute a power conversion circuit that performs power conversion between DC power and AC power, and when an electric motor is connected as a load on the AC side, the abnormality determination unit determines that a main withstand voltage of any semiconductor switching element has deteriorated or that insulation of the electric motor has deteriorated when the detected voltage is a voltage that is outside the range between the first reference voltage and the second reference voltage after the power conversion device stops operating to convert power.

16. 6. The power conversion device according to claim 1, wherein the semiconductor switching elements constituting at least one arm pair are made of a wide bandgap semiconductor material having a bandgap larger than that of Si.

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