Layered ceramic electronic component

Abstract

Provided is a layered ceramic electronic component in which peeling between ceramic layers is prevented.　This layered ceramic electronic component 10 comprises: a layered body 12 comprising a plurality of layered ceramic layers 14 and a plurality of layered inner electrode layers 16, the layered body including a first main surface 12a and a second main surface 12b which face each other in a layering direction x, a first side surface 12c and a second side surface 12d which face each other in a width direction y that is orthogonal to the layering direction x, and a first end surface 12e and a second end surface 12f which face each other in a length direction z that is orthogonal to the layering direction x and the width direction y; and a plurality of outer electrodes 30. The layered ceramic electronic component is characterized in that: the plurality of inner electrode layers 16 include first inner electrode layers 16a that are layered alternately with the plurality of ceramic layers 14 and that are exposed to the first end surface 12e and the second end surface 12f, and second inner electrode layers 16b that are layered alternately with the plurality of ceramic layers 14 and that are exposed to the first side surface 12c and the second side surface 12d; the first inner electrode layers 16a and the second inner electrode layers 16b are disposed spaced apart from each other, and further include dummy electrodes 40 that are exposed from one of the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d; the plurality of outer electrodes 30 comprise a first outer electrode 30a and a second outer electrode 30b that are connected to the first inner electrode layers 16a, and a third outer electrode 30c and a fourth outer electrode 30d that are connected to the second inner electrode layers 16b; and in each of the dummy electrodes 40, a region 44 that is spaced apart from an exposed portion 42 of the dummy electrode 40 by at least 50% toward the center of the layered body 12 exhibits a conductive component wire coverage of less than 50%.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, with the increasing performance of mobile phones such as smartphones, there has been a demand for miniaturization of multilayer ceramic electronic components. For example, multilayer ceramic capacitors are multilayer ceramic electronic components in which internal electrode layers and ceramic layers are alternately stacked, and which have a desired capacitance depending on the number of layers and the thickness of the ceramic layers.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor having an element body (laminated body) in which dielectric layers (ceramic layers) and internal electrode layers are alternately laminated.

[0004] However, in the structure of the multilayer ceramic capacitor described in Patent Document 1, the planar area of ​​the internal electrode layers is smaller than the planar area of ​​the ceramic layers, and a step is formed between the ceramic layers and the peripheral portions of the internal electrode layers, excluding the portions of the internal electrode layers that are extended to the end faces of the element body. This step causes the internal electrode layers to bend, which poses a problem of making it more likely that short circuits will occur between the internal electrode layers and that reliability will decrease under high temperature loads. In particular, the thinner the dielectric layers (ceramic layers) are and the greater the number of laminated internal electrode layers and dielectric layers (ceramic layers), the more likely short circuits will occur between the internal electrode layers and the reliability will tend to decrease.

[0005] Therefore, in order to solve the above problem, it is known to place a dummy electrode in the outer layer portion, which has a thickness equivalent to the step formed between the peripheral portion of the internal electrode layer and the ceramic layer, excluding the portion of the internal electrode layer extended to the end face of the laminate.

[0006] Japanese Patent Application Laid-Open No. 2006-73623

[0007] However, current also flows through the dummy electrode, which lengthens the current path and increases ESR and ESL. Furthermore, the presence of the dummy electrode weakens the adhesive strength between the ceramic layer and the dummy electrode, which can lead to peeling between the ceramic layers.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic electronic component that prevents peeling between ceramic layers.

[0009] A multilayer ceramic electronic component according to the present invention is a multilayer ceramic electronic component comprising: a laminate including a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, the laminate including first and second main surfaces opposing each other in the lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; and a plurality of external electrodes, wherein the plurality of internal electrode layers are alternately laminated with the plurality of ceramic layers, and a first internal electrode layer exposed at the first end surface and the second end surface is alternately laminated with the plurality of ceramic layers, and and a second internal electrode layer exposed on the side surface and the second side surface, and further having a dummy electrode arranged at a distance from the first internal electrode layer and the second internal electrode layer and exposed from any of the first end face, the second end face, the first side surface, and the second side surface, and the plurality of external electrodes include a first external electrode and a second external electrode connected to the first internal electrode layer, and a third external electrode and a fourth external electrode connected to the second internal electrode layer, and in the dummy electrodes, a region spaced 50% or more from the exposed portion of the dummy electrode toward the center of the laminate has a line coverage of the conductive component of less than 50%.

[0010] In the multilayer ceramic electronic component according to the present invention, in the region of the dummy electrode that is 50% or more away from the exposed portion of the dummy electrode toward the center of the laminate, the line coverage of the conductive component is less than 50%, which allows the ceramic layers to be bonded via a gap, leading to improved bonding strength between the ceramic layers and improved moisture resistance reliability. In addition, the gap makes it difficult for current to flow to the tip of the dummy electrode, shortening the current path and leading to a reduction in ESL.

[0011] According to the present invention, it is possible to provide a multilayer ceramic electronic component that prevents peeling between ceramic layers.

[0012] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0013] 1 is an external perspective view of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention; FIG. 2 is a top view of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention; FIG. 3 is a front view of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention; FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1; FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1; FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4; and FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. (a) An enlarged view of part C in FIG. 6, showing the configuration of a dummy electrode on a side surface of the laminate; (b) An enlarged view of part D in FIG. 7, showing the configuration of a dummy electrode on an end surface of the laminate; and (c) a diagram for explaining measurement regions of line coverage in a dummy electrode. (b) An enlarged view of part A in FIG. 4; (c) An enlarged view of part B in FIG. 5; (d) An enlarged view of part C in FIG. 6; and (e) An enlarged view of part D in FIG. 7. 1A and 1B are diagrams showing printing patterns of internal electrode layers and dummy electrodes in a method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention; FIG. 1A is a printing pattern used when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on a first side surface, a second side surface, a first end surface, and a second end surface; FIG. 1B is a printing pattern used when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface and the second side surface; and FIG. 1C is a printing pattern used when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first end surface and the second end surface.

[0014] 1. Multilayer Ceramic Electronic Component A multilayer ceramic capacitor 10, which is an example of a multilayer ceramic electronic component according to the present invention, will be described. FIG. 1 is an external perspective view of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention. FIG. 2 is a top view of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention. FIG. 3 is a left side view of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8(a) is an enlarged view of portion C in FIG. 6, illustrating the configuration of a dummy electrode on a side surface of the laminate. FIG. 8(b) is an enlarged view of portion D in FIG. 7, illustrating the configuration of a dummy electrode on an end surface of the laminate. FIG. 9 is a diagram illustrating a measurement area for line coverage in a dummy electrode. FIG. 10 is an enlarged view of portion A in FIG. 4. FIG. 11 is an enlarged view of portion B in FIG. 5. Fig. 12 is an enlarged view of portion C shown in Fig. 6. Fig. 13 is an enlarged view of portion D shown in Fig. 7. Fig. 14 is a diagram showing printing patterns of internal electrode layers and dummy electrodes in a method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention, where (a) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface, the second side surface, the first end surface, and the second end surface, (b) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface and the second side surface, and (c) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first end surface and the second end surface.

[0015] The multilayer ceramic capacitor 10 includes a laminate 12 including a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14, the laminate 12 including a first main surface 12 a and a second main surface 12 b facing in a stacking direction x, a first side surface 12 c and a second side surface 12 d facing in a width direction y perpendicular to the stacking direction x, and a first end face 12 e and a second end face 12 f facing in a length direction z perpendicular to the stacking direction x and the width direction y, and a plurality of external electrodes 30 connected to the internal electrode layers 16.

[0016] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the longitudinal direction z is L M The dimensions are as follows: L M The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the width direction y is preferably W M The dimensions are as follows: W M The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the lamination direction x is preferably T M The dimensions are as follows: T M The dimension is preferably 0.2 mm or more and 1.0 mm or less.

[0017] (Laminate) The laminate 12 has a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14. Furthermore, the laminate 12 has a first main surface 12 a and a second main surface 12 b facing in a stacking direction x, a first side surface 12 c and a second side surface 12 d facing in a width direction y perpendicular to the stacking direction x, and a first end face 12 e and a second end face 12 f facing in a length direction z perpendicular to the stacking direction x and the width direction y.

[0018] The laminate 12 has a rectangular parallelepiped shape. Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. The corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0019] The laminate 12 has an effective layer portion 15a in which a plurality of internal electrode layers 16 are arranged opposite each other via ceramic layers 14 in a stacking direction x connecting the first main surface 12a and the second main surface 12b, a first outer layer portion 15b1 formed from a plurality of ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 located closest to the first main surface 12a among the plurality of internal electrode layers 16, and a second outer layer portion 15b2 formed from a plurality of ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 located closest to the second main surface 12b among the plurality of internal electrode layers 16.

[0020] The first outer layer portion 15b1 is located on the first main surface 12a side of the laminate 12 and is an assembly of multiple ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0021] The second outer layer portion 15b2 is located on the second main surface 12b side of the laminate 12 and is an assembly of multiple ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0022] The area sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the effective layer portion 15a.

[0023] The laminate 12 has side portions (W gaps) 22a, 22b of the laminate 12 that are located between one end in the width direction y of the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b (described later) and the first side surface 12c, and between one end in the width direction y of the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b (described later) and the second side surface 12d, and include the third lead portion 20c and the fourth lead portion 20d of the second internal electrode layer 16b.

[0024] The laminate 12 also has ends (L gaps) 24a, 24b of the laminate 12 that are located between one end in the longitudinal direction z of the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b (described later) and the first end face 12e, and between one end in the longitudinal direction z of the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b (described later) and the second end face 12f.

[0025] The ceramic layer 14 may be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics whose main components are BaTiO3, CaTiO3, SrTiO3, and CaZrO3. Subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components.

[0026] The number of ceramic layers 14 to be laminated is not particularly limited, but is preferably 4 to 1000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the ceramic layers 14 is preferably 0.4 μm to 1.0 μm.

[0027] The dimensions of the laminate 12 are not particularly limited. The dimension in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f of the laminate 12 is defined as the L dimension. The L dimension is preferably 0.4 mm or more and 1.6 mm or less. The dimension in the width direction y connecting the first side surface 12c and the second side surface 12d of the laminate 12 is defined as the W dimension. The W dimension is preferably 0.2 mm or more and 1.0 mm or less. The dimension in the stacking direction x connecting the first main surface 12a and the second main surface 12b of the laminate 12 is defined as the T dimension. The T dimension is preferably 0.2 mm or more and 1.0 mm or less.

[0028] (Internal Electrode Layer) The internal electrode layer 16 includes a first internal electrode layer 16a and a second internal electrode layer 16b.

[0029] The first internal electrode layer 16a is disposed on the plurality of ceramic layers 14. The first internal electrode layer 16a is extended to the first end face 12e and the second end face 12f. The first internal electrode layer 16a has a first opposing portion 18a located inside the laminate 12, a first extended portion 20a connected to the first opposing portion 18a and extended to the first end face 12e, and a second extended portion 20b extended to the second end face 12f.

[0030] The shape of the first opposing portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing portion 18a may be tapered in plan view, with a slope increasing in either direction.

[0031] The shapes of the first lead portion 20a and the second lead portion 20b of the first internal electrode layer 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0032] The second internal electrode layer 16b is disposed on the plurality of ceramic layers 14. The second internal electrode layer 16b is extended to the first side surface 12c and the second side surface 12d. The second internal electrode layer 16b has a second opposing portion 18b located inside the laminate 12, a third extended portion 20c connected to the second opposing portion 18b and extended to the first side surface 12c, and a fourth extended portion 20d extended to the second side surface 12d.

[0033] The shape of the second opposing portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing portion 18b may be tapered in plan view, with a slope increasing in either direction.

[0034] The shapes of the third lead portion 20c and the fourth lead portion 20d of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0035] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0036] The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, from 1 to 500. The number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, from 1 to 500. The total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably from 2 to 1000.

[0037] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.4 μm or more and 0.8 μm or less. The thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.4 μm or more and 0.8 μm or less.

[0038] In this embodiment, the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b face each other via the ceramic layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0039] When a piezoelectric ceramic is used for the laminate 12, the laminated ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials.

[0040] Furthermore, the multilayer ceramic electronic component functions as a thermistor element when a semiconducting ceramic is used for the laminate 12. Specific examples of semiconducting ceramic materials include spinel ceramic materials.

[0041] Furthermore, when a magnetic ceramic is used for the laminate 12, the multilayer ceramic electronic component functions as an inductor element. When functioning as an inductor element, the internal electrode layers become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0042] That is, by appropriately changing the material and structure of the laminate 12, the multilayer ceramic electronic component according to this embodiment can function favorably not only as a multilayer ceramic capacitor 10 but also as a ceramic piezoelectric element, a thermistor element, or an inductor element.

[0043] (Dummy Electrode) The dummy electrode 40 is disposed apart from the first internal electrode layer 16 a and the second internal electrode layer 16 b, and is exposed from any of the first end face 12 e, the second end face 12 f, the first side face 12 c, and the second side face 12 d. When the dummy electrode 40 is exposed from any of the first end face 12 e, the second end face 12 f, the first side face 12 c, and the second side face 12 d, the dummy electrode 40 can fill in any step corresponding to the thickness of the first internal electrode layer 16 a and the second internal electrode layer 16 b, thereby reducing distortion of the internal electrode layer 16 and the ceramic layer 14 during pressing and ensuring compaction.

[0044] In this embodiment, the dummy electrodes 40 include a first dummy electrode 40a, a second dummy electrode 40b, a third dummy electrode 40c, and a fourth dummy electrode 40d.

[0045] A first dummy electrode 40a is disposed on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is disposed, spaced apart from the first internal electrode layer 16a and exposed at the first side surface 12c. The first dummy electrode 40a faces the third lead portion 20c of the second internal electrode layer 16b across the ceramic layer 14.

[0046] The shape of the first dummy electrode 40a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed at an angle in plan view (tapered). Alternatively, the first dummy electrode 40a may be tapered in plan view, with a slope increasing in either direction.

[0047] A second dummy electrode 40b is disposed on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is disposed, spaced apart from the first internal electrode layer 16a and exposed at the second side surface 12d. The second dummy electrode 40b faces the fourth lead portion 20d of the second internal electrode layer 16b across the ceramic layer 14.

[0048] The shape of the second dummy electrode 40b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed at an angle in plan view (tapered). Alternatively, the second dummy electrode 40b may be tapered in plan view, with a slope increasing in either direction.

[0049] A third dummy electrode 40c is disposed on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is disposed, spaced apart from the second internal electrode layer 16b, and exposed at the first end face 12e. The third dummy electrode 40c faces the first lead portion 20a of the first internal electrode layer 16a across the ceramic layer 14.

[0050] The shape of the third dummy electrode 40c is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed at an angle in plan view (tapered). Alternatively, the third dummy electrode 40c may be tapered in plan view, with a slope increasing in either direction.

[0051] A fourth dummy electrode 40d is disposed on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is disposed, spaced apart from the second internal electrode layer 16b and exposed at the second end face 12f. The fourth dummy electrode 40d faces the second lead portion 20b of the second internal electrode layer 16b across the ceramic layer 14.

[0052] The shape of the fourth dummy electrode 40d is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed at an angle in plan view (tapered). Alternatively, the fourth dummy electrode 40d may be tapered in plan view, with a slope increasing in either direction.

[0053] The first dummy electrode 40a and the second dummy electrode 40b are preferably exposed on at least one of the first side surface 12c and the second side surface 12d on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is arranged. It is more preferable that the first dummy electrode 40a and the second dummy electrode 40b are exposed on both the first side surface 12c and the second side surface 12d on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is arranged. This configuration can reduce distortion that occurs when the laminate 12 is pressed.

[0054] The third dummy electrode 40c and the fourth dummy electrode 40d are preferably exposed on at least one of the first end face 12e and the second end face 12f on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is arranged. Furthermore, it is more preferable that the third dummy electrode 40c and the fourth dummy electrode 40d are exposed on both the first end face 12e and the second end face 12f on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is arranged. With this configuration, it is possible to reduce distortion that occurs when the laminate 12 is pressed.

[0055] A conductive material is included as a conductive component in the dummy electrode 40. The conductive material of the dummy electrode 40 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag—Pd alloy.

[0056] The dummy electrode 40 has an end region 44 of the dummy electrode 40 that is 50% or less in line coverage, the end region 44 being spaced 50% or more away from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12. For example, as shown in FIG. 8A , the first dummy electrode 40a has an end region 44a of the first dummy electrode 40a that has line coverage of 50% or less in a region that is 50% or more away from the exposed portion 42a of the first dummy electrode 40a toward the center of the laminate 12. Similarly, the second dummy electrode 40b has an end region 44b of the second dummy electrode 40b that has line coverage of 50% or less in a region that is 50% or more away from the exposed portion 42b of the second dummy electrode 40b toward the center of the laminate 12. 8B, the third dummy electrode 40c has an end region 44c of the second dummy electrode 40b with a line coverage of 50% or less provided in a region that is 50% or more away from the exposed portion 42c of the third dummy electrode 40c toward the center of the laminate 12. Similarly, the fourth dummy electrode 40d has an end region 44d of the fourth dummy electrode 40d with a line coverage of 50% or less provided in a region that is 50% or more away from the exposed portion 42d of the fourth dummy electrode 40d toward the center of the laminate 12.

[0057] Here, the line coverage indicates the ratio of the total length of the dummy electrode 40 over which the conductive component of the dummy electrode actually exists.

[0058] Next, a method for measuring line coverage will be described. First, in the case of the first dummy electrode 40a and the second dummy electrode 40b, polishing is performed up to 1 / 2 of the length direction z of the laminate 12 to expose the WT cross section. Furthermore, in the case of the third dummy electrode 40c and the fourth dummy electrode 40d, polishing is performed up to 1 / 2 of the width direction y of the laminate 12 to expose the LT cross section. Next, the WT cross section or the LT cross section is photographed using a digital microscope (VHX manufactured by Keyence Corporation). Next, each cross-sectional image is recognized using image processing software (HALCON manufactured by MVTec Corporation). In the case of the WT cross section, the measurement area F is preferably a square area measuring 5 μm in the width direction y and 30 μm in the stacking direction x. In the case of the LT cross section, the measurement area F is preferably a square area measuring 5 μm in the length direction z and 30 μm in the stacking direction x. The coverage is calculated as the ratio of the total length where the conductive components of the dummy electrode actually exist to the total length of the dummy electrode 40 in that region. Therefore, a region where the line coverage is 50% or less is a region where the ratio of the total length where the conductive components of the dummy electrode actually exist to the total length of the dummy electrode 40 is 50% or less. For example, FIG. 9 shows measurement regions F1 to F2 of the line coverage of the first dummy electrode 40a in the WT cross section. N Measurement areas F1 to F N In this step, the line coverage is measured by calculating the total length of the first dummy electrode 40a and the total length where the conductive component of the first dummy electrode 40a exists.

[0059] By providing an area with a line coverage of 50% or less in the end region 44 of the dummy electrode in this manner, the ceramic layers 14 can be bonded to each other via the voids 46, which has the effect of improving the bonding strength between the ceramic layers 14 and improving the moisture-resistant reliability. Furthermore, the voids 46 make it easier for current to flow to the tip of the end region 44 of the dummy electrode 40, shortening the current path, which has the effect of reducing the ESL. Furthermore, when moisture penetrates from the outside, the moisture is selectively concentrated in the end region 44 of the dummy electrode 40, where the line coverage is 50% or less, which has the effect of ensuring the moisture-resistant reliability of the effective layer portion 15a.

[0060] Furthermore, the ratio of the area of ​​the voids 46 to the area of ​​the end region 44 of the dummy electrode 40 is preferably 50% or more and 80% or less. When the ratio of the area of ​​the voids 46 to the area of ​​the end region 44 of the dummy electrode 40 is 50% or more, the ceramic layers 14 can be bonded via the voids 46, which has the effect of improving the bonding strength between the ceramic layers 14 and improving the moisture-resistant reliability. Furthermore, when moisture penetrates from the outside, the moisture is selectively concentrated in the end region 44 of the dummy electrode 40, where the line coverage is 50% or less, which has the effect of ensuring the moisture-resistant reliability of the effective layer portion 15a. When the ratio of the area of ​​the voids 46 to the area of ​​the end region 44 of the dummy electrode 40 is 80% or less, the voids 46 prevent the current path from flowing to the tip of the end region 44 of the dummy electrode 40, shortening the current path and thereby reducing the ESL. On the other hand, if the ratio of the area of ​​the void 46 to the area of ​​the end region 44 of the dummy electrode 40 is 80% or more, the thickness of the internal electrode layer 16 and the thickness of the dummy electrode 40 will differ, and the step that occurs between the internal electrode layer 16 and the dummy electrode 40 will become large.As a result, when the step is pressed in, there will be localized areas where the thickness of the laminate 12 in the stacking direction x is thin, increasing the risk of reduced moisture resistance reliability.

[0061] Here, the thickness of the first internal electrode layer 16a in the stacking direction x is denoted by t1, the thickness of the second internal electrode layer 16b in the stacking direction x is denoted by t2, the thickness of the first dummy electrode 40a in the stacking direction x is denoted by t3, the thickness of the second dummy electrode 40b in the stacking direction x is denoted by t4, the thickness of the third dummy electrode 40c in the stacking direction x is denoted by t5, and the thickness of the fourth dummy electrode 40d in the stacking direction x is denoted by t6.

[0062] The thicknesses t3, t4, t5, and t6 of the dummy electrodes 40 are preferably formed thinner than the thicknesses t1 and t2 of the internal electrode layers 16. More specifically, the thicknesses t3, t4, t5, and t6 of the dummy electrodes 40 are preferably 75% or more and 95% or less of the thicknesses t1 and t2 of the internal electrode layers 16. By making the thicknesses t3, t4, t5, and t6 of the dummy electrodes 40 75% or more and 95% or less of the thicknesses t1 and t2 of the internal electrode layers 16, the steps can be sufficiently filled and distortion of the internal electrode layers 16 and the ceramic layers 14 during pressing can be reduced.

[0063] Furthermore, the length w1 in the width direction y of the laminate 12 of the first dummy electrode 40a exposed on the first side surface 12c is preferably 50% to 60% of the length w3 in the width direction y of the laminate 12 of the third lead portion 20c of the second internal electrode layer 16b. By setting the length w1 in the width direction y of the laminate 12 of the first dummy electrode 40a exposed on the first side surface 12c to 50% to 60% of the length w3 in the width direction y of the laminate 12 of the third lead portion 20c of the second internal electrode layer 16b, it is possible to reduce distortion that occurs when pressing the laminate 12 while maintaining an appropriate distance for the current path. Similarly, the length w2 in the width direction y of the laminate 12 of the second dummy electrode 40b exposed on the second side surface 12d is preferably 50% to 60% of the length w4 in the width direction y of the laminate 12 of the fourth lead portion 20d of the second internal electrode layer 16b. By setting the length w2 in the width direction y of the laminate 12 of the second dummy electrode 40b exposed on the second side surface 12d to be 50% or more and 60% or less of the length w4 in the width direction y of the laminate 12 of the fourth lead portion 20d of the second internal electrode layer 16b, it is possible to reduce the distortion that occurs when pressing the laminate 12 while maintaining the current path at an appropriate distance.

[0064] Furthermore, the central portion M1 of the first dummy electrode 40a exposed on the first side surface 12c in the length direction z of the laminate 12 is preferably located within 3% of the central portion M of the second internal electrode layer 16b in the length direction z of the laminate 12. This arrangement allows the dummy electrode 40 and the second internal electrode layer 16b to be uniformly pressed together, thereby providing the effect of preventing structural defects such as peeling between the ceramic layers 14. Similarly, the central portion M2 of the second dummy electrode 40b exposed on the second side surface 12d in the length direction z of the laminate 12 is preferably located within 3% of the central portion M of the second internal electrode layer 16b in the length direction z of the laminate 12. This arrangement allows the dummy electrode 40 and the second internal electrode layer 16b to be uniformly pressed together, thereby providing the effect of preventing structural defects such as peeling between the ceramic layers 14.

[0065] Furthermore, the length l1 in the longitudinal direction z of the laminate 12 of the third dummy electrode 40c exposed at the first end face 12e is preferably 50% to 60% of the length l3 in the longitudinal direction z of the laminate 12 of the first lead portion 20a of the first internal electrode layer 16a. By setting the length l1 in the longitudinal direction z of the laminate 12 of the third dummy electrode 40c exposed at the first end face 12e to 50% to 60% of the length l3 in the longitudinal direction z of the laminate 12 of the first lead portion 20a of the first internal electrode layer 16a, it is possible to reduce distortion that occurs when pressing the laminate 12 while maintaining an appropriate distance for the current path. Similarly, the length l2 in the longitudinal direction z of the laminate 12 of the fourth dummy electrode 40d exposed at the second end face 12f is preferably 50% to 60% of the length l4 in the longitudinal direction z of the laminate 12 of the second lead portion 20b of the first internal electrode layer 16a. By setting the length l2 of the fourth dummy electrode 40d exposed at the second end face 12f in the longitudinal direction z of the laminate 12 to be 50% or more and 60% or less of the length l4 of the second lead portion 20b of the first internal electrode layer 16a in the longitudinal direction z of the laminate 12, it is possible to reduce distortion that occurs when pressing the laminate 12 while maintaining an appropriate distance for the current path.

[0066] Furthermore, the central portion N1 of the third dummy electrode 40c exposed at the first end face 12e in the width direction y of the laminate 12 is preferably located within 3% of the central portion N of the first internal electrode layer 16a in the width direction y of the laminate 12. This arrangement allows the dummy electrode 40 and the first internal electrode layer 16a to be pressed uniformly, thereby reducing the likelihood of structural defects such as peeling between the ceramic layers 14. Similarly, the central portion N2 of the fourth dummy electrode 40d exposed at the second end face 12f is preferably located within 3% of the central portion N of the first internal electrode layer 16a in the width direction y of the laminate 12. This arrangement allows the dummy electrode 40 and the first internal electrode layer 16a to be pressed uniformly, thereby reducing the likelihood of structural defects such as peeling between the ceramic layers 14.

[0067] (External Electrodes) The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0068] The first external electrode 30a is disposed on the first end face 12e and connected to the first internal electrode layer 16a. The first external electrode 30a may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0069] The second external electrode 30b is disposed on the second end face 12f and connected to the first internal electrode layer 16a. The second external electrode 30b may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0070] The third external electrode 30c is disposed on the first side surface 12c and connected to the second internal electrode layer 16b. The third external electrode 30c may also be disposed on a part of the first main surface 12a and a part of the second main surface 12b.

[0071] The fourth external electrode 30d is disposed on the second side surface 12d and connected to the second internal electrode layer 16b. The fourth external electrode 30d may also be disposed on a part of the first main surface 12a and a part of the second main surface 12b.

[0072] Each of the first external electrode 30 a, the second external electrode 30 b, the third external electrode 30 c and the fourth external electrode 30 d preferably has a base electrode layer 32 and a plating layer 34.

[0073] In other words, the first external electrode 30a preferably has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b preferably has a second base electrode layer 32b and a second plating layer 34b. The third external electrode 30c preferably has a third base electrode layer 32c and a third plating layer 34c. The fourth external electrode 30d preferably has a fourth base electrode layer 32d and a fourth plating layer 34d.

[0074] The base electrode layer 32 includes a first base electrode layer 32 a, a second base electrode layer 32 b, a third base electrode layer 32 c, and a fourth base electrode layer 32 d. The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0075] First, a description will be given of the case where the base electrode layer 32 is formed by a baking layer. The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. Furthermore, the baking layer may be a multi-layer structure.

[0076] The baked layer is formed by applying and baking a conductive paste containing a glass component and a metal component to the laminate 12. The baked layer may be formed by simultaneously firing a laminated chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminated chip, or by firing a laminated chip having the internal electrode layer 16 and the ceramic layer 14 to obtain the laminate 12 and then applying and baking the conductive paste. When simultaneously firing a laminated chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminated chip, it is preferable to form the baked layer by adding a ceramic component instead of a glass component.

[0077] At the center of the stacking direction x connecting the first main surface 12a and the second main surface 12b of the first baked layer and the second baked layer located at the first end surface 12e and the second end surface 12f, the thickness in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f of the first baked layer and the second baked layer (end surface center thickness) is preferably, for example, 5 μm or more and 30 μm or less.

[0078] Furthermore, when a baking layer is also provided on a portion of the first main surface 12a or a portion of the second main surface 12b, the thickness in the stacking direction x connecting the first main surface 12a and the second main surface 12b of the first baking layer and the second baking layer at the center of the length direction z connecting the first end surface 12e and the second end surface 12f of the first baking layer and the second baking layer located on the first main surface 12a or the second main surface 12b is preferably, for example, 5 μm or more and 10 μm or less.

[0079] Next, a case where the base electrode layer 32 is formed by a conductive resin layer will be described. The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 12 without providing a baked layer. The conductive resin layer may also completely cover the baked layer, or may cover only a portion of the baked layer. Furthermore, the conductive resin layer may be a multi-layer structure.

[0080] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than, for example, a baked layer made of a plating film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0081] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. It is also possible to use a metal powder whose surface is coated with Ag. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. Furthermore, it is possible to use a cheaper base metal while maintaining the above-mentioned properties of Ag.

[0082] Furthermore, the metal contained in the conductive resin layer may be Cu or Ni that has been subjected to an anti-oxidation treatment. The metal contained in the conductive resin layer may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0083] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0084] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0085] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0086] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0087] The thickness of the thickest part of the conductive resin layer is preferably, for example, 5 μm or more and 30 μm or less.

[0088] Next, a case where the base electrode layer 32 is formed as a thin film layer will be described. When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as a sputtering method or a vapor deposition method. The thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0089] (Plating Layer) The plating layer 34 includes a first plating layer 34a arranged to cover the first base electrode layer 32a, a second plating layer 34b arranged to cover the second base electrode layer 32b, a third plating layer 34c arranged to cover the third base electrode layer 32c, and a fourth plating layer 34d arranged to cover the fourth base electrode layer 32d.

[0090] The plating layer 34 contains at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0091] The plating layer 34 may also be formed of multiple layers. A two-layer structure is preferably formed by plating the layer 34, Ni plating, and Sn plating in that order. The Ni plating layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic capacitor 10, facilitating mounting.

[0092] The thickness of each plating layer 34 is preferably 4 μm or more and 10 μm or less.

[0093] Any one or each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may have a plating layer 34 formed directly on the surface of the laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure including a plating layer 34 that is directly and electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed directly after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0094] When the plating layer 34 is formed directly on the laminate 12 without providing the base electrode layer 32, the reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., thinner, or into the thickness of the laminate 12, i.e., the thickness of the effective layer portion 15a, thereby improving the design freedom of the thin chip.

[0095] When the plating layer 34 is formed directly on the laminate 12, it is preferable that the plating layer 34 includes a lower layer plating electrode formed on the surface of the laminate 12 and an upper layer plating electrode formed on the surface of the lower layer plating electrode.

[0096] The lower layer plating electrode and the upper layer plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal.

[0097] The lower layer plated electrode is preferably formed using Ni, which has solder barrier properties, and the upper layer plated electrode is preferably formed using Sn or Au, which have good solder wettability.

[0098] For example, when the first internal electrode layer 16 a and the second internal electrode layer 16 b are formed using Ni, the lower-layer plated electrode is preferably formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode and the second external electrode may each be composed of only the lower-layer plated electrode.

[0099] When the plating layer 34 is formed directly on the laminate 12, the plating layer 34 may have an upper layer plating electrode as the outermost layer, or another plating electrode may be formed on the surface of the upper layer plating electrode.

[0100] When the plating layer 34 is formed directly on the laminate 12, the thickness of each plating layer 34 is preferably 4 μm or more and 10 μm or less.

[0101] When the plating layer 34 is formed directly on the laminate 12, it is preferable that the plating layer 34 does not contain glass. In addition, it is preferable that the metal content per unit volume of the plating layer 34 is 99% by volume or more.

[0102] In the multilayer ceramic capacitor 10 shown in FIG. 1 , in the dummy electrode 40, a region 44 located 50% or more away from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12 has a line coverage of the conductive component that is less than 50%. This configuration allows the ceramic layers 14 to be bonded via the voids 46, thereby improving the bonding strength between the ceramic layers 14 and improving moisture resistance reliability. Furthermore, the voids 46 prevent current from flowing to the tip of the dummy electrode 40, shortening the current path and reducing the ESL. Furthermore, when moisture penetrates from the outside, the moisture is selectively concentrated in the end region 44 of the dummy electrode 40, where the line coverage is 50% or less, thereby ensuring the moisture resistance reliability of the effective layer portion 15 a.

[0103] 1 is preferably exposed to at least one of the first side surface 12c and the second side surface 12d on the ceramic layer 14 on which the first internal electrode layer 16a is disposed, thereby reducing distortion that occurs when the laminate 12 is pressed.

[0104] 1 is preferably exposed to at least one of the first end face 12e and the second end face 12f on the ceramic layer 14 on which the second internal electrode layer 16b is disposed, thereby reducing distortion that occurs when the laminate 12 is pressed.

[0105] 1 , the thicknesses t3, t4, t5, and t6 in the stacking direction x of the dummy electrode 40 are preferably smaller than the thicknesses t1, t2 in the stacking direction x of the first internal electrode layers 16a and the second internal electrode layers 16b. Furthermore, the thicknesses t3, t4, t5, and t6 in the stacking direction x of the dummy electrode 40 of the multilayer ceramic capacitor 10 are preferably 75% to 95% of the thicknesses t1, t2 in the stacking direction x of the first internal electrode layers 16a and the second internal electrode layers 16b. This allows the step (the difference between the thicknesses t3, t4, t5, and t6 in the stacking direction x of the dummy electrode 40 and the thicknesses t1, t2 of the first internal electrode layers 16a and the second internal electrode layers 16b) to be sufficiently filled, thereby reducing distortion of the internal electrode layers 16 and the ceramic layers 14 during pressing.

[0106] 1, the lengths w1 and w2 in the width direction y of the laminate 12 of the dummy electrodes 40a and 40b exposed on the first side surface 12c or the second side surface 12d are preferably 50% or more and 60% or less of the lengths w3 and w4 in the width direction y of the laminate 12 of the third lead portion 20c of the second internal electrode layer 16b and the fourth lead portion 20d of the second internal electrode layer 16b. This makes it possible to reduce distortion that occurs when the laminate 12 is pressed while maintaining an appropriate distance for the current path.

[0107] 1, the central portions M1, M2 in the length direction z of the laminate 12 of the dummy electrodes 40a, 40b exposed on the first side surface 12c or the second side surface 12d are preferably located within 3% of the central portion M in the length direction z of the laminate 12 of the second internal electrode layer 16b exposed on the first side surface 12c or the second side surface 12d. This allows the dummy electrodes 40a, 40b and the second internal electrode layers 16b to be pressed uniformly, which has the effect of making it less likely for structural defects such as peeling between the ceramic layers 14 to occur.

[0108] In addition, in the dummy electrode 40 of the multilayer ceramic capacitor 10 shown in FIG. 1 , the ratio of the area of ​​the voids 46 to the area of ​​the region 44 spaced 50% or more from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12 is preferably 50% or more and 80% or less. This allows the ceramic layers 14 to be bonded via the voids 46, which has the effect of improving the bonding strength between the ceramic layers 14 and improving the moisture-resistant reliability. Furthermore, when moisture penetrates from the outside, the moisture is selectively concentrated in the end region 44 of the dummy electrode 40, where the line coverage is 50% or less, thereby ensuring the moisture-resistant reliability of the effective layer portion 15a. The voids 46 prevent the current path from flowing to the tip of the end region 44 of the dummy electrode 40, shortening the current path and thereby reducing the ESL.

[0109] 2. Method for Manufacturing a Multilayer Ceramic Electronic Component A method for manufacturing a multilayer ceramic capacitor 10, which is an example of a multilayer ceramic electronic component according to the present invention, will now be described.

[0110] First, a dielectric sheet and a conductive paste for the internal electrodes and dummy electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes and dummy electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0111] Next, a conductive paste for the internal electrodes and dummy electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing. This prepares a dielectric sheet on which patterns of the internal electrode layers and dummy electrodes are formed. More specifically, a screen plate for printing the first internal electrode layer 16a and the first dummy electrode 40a and the second dummy electrode 40b, and a screen plate for printing the second internal electrode layer 16b and the third dummy electrode 40c and the fourth dummy electrode 40d are separately prepared, and the internal electrode layers 16 and dummy electrodes 40 of the present invention can be printed by printing as shown in FIG. 14(a) using a printer capable of printing the two types of screen plates separately. Note that FIG. 14(a) shows the printing patterns of the internal electrode layers and dummy electrodes in this embodiment. That is, a pattern 80 of the first internal electrode layer 16a and the first dummy electrode 40a and the second dummy electrode 40b, and a pattern 82 of the second internal electrode layer 16b and the third dummy electrode 40c and the fourth dummy electrode 40d are printed, and when the laminate is cut in a later process, it is cut along a cut line 90 shown by a dashed line in Figure 14(a), thereby making it possible to produce a laminate 12 having the first internal electrode layer 16a, the second internal electrode layer 16b, the first dummy electrode 40a, the second dummy electrode 40b, the third dummy electrode 40c and the fourth dummy electrode 40d.

[0112] In this embodiment, the first dummy electrode 40 a, the second dummy electrode 40 b, the third dummy electrode 40 c, and the fourth dummy electrode 40 d are provided, but the present invention is not limited to this. That is, for example, in the case where the first dummy electrode 40 a and the second dummy electrode 40 b are provided but the third dummy electrode 40 c and the fourth dummy electrode 40 d are not provided, by printing the first internal electrode layer 16 a, the second internal electrode layer 16 b, the first dummy electrode 40 a, and the second dummy electrode 40 b as shown in FIG. 14( b), it is possible to form a portion that becomes the effective layer portion 15 a that has the first dummy electrode 40 a and the second dummy electrode 40 b but does not have the third dummy electrode 40 c and the fourth dummy electrode 40 d. Furthermore, for example, in the case where the first dummy electrode 40a and the second dummy electrode 40b are not included but the third dummy electrode 40c and the fourth dummy electrode 40d are included, by printing the first internal electrode layer 16a, the second internal electrode layer 16b, the third dummy electrode 40c and the fourth dummy electrode 40d as shown in Figure 14(c), it is possible to form a portion that becomes the effective layer portion 15a that does not include the first dummy electrode 40a and the second dummy electrode 40b but has the third dummy electrode 40c and the fourth dummy electrode 40d.

[0113] Here, in order to obtain a desired structure, the portion that becomes the effective layer portion 15a is formed by stacking sheets on which the internal electrode layers 16 and dummy electrodes 40 are printed. In this embodiment, the patterns of the internal electrodes and dummy electrodes are printed by gravure printing.

[0114] Next, a predetermined number of dielectric sheets not printed with an internal electrode layer pattern are stacked to form the portion that will become the first outer layer portion 15b1 on the first main surface 12a side. After that, the portion that will become the effective layer portion 15a prepared above is stacked, and a predetermined number of dielectric sheets not printed with an internal electrode layer pattern are stacked on top of this effective layer portion 15a to form the portion that will become the second outer layer portion 15b2 on the second main surface 12b side. In this way, a laminated sheet is produced.

[0115] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0116] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0117] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0118] A first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the fired laminate 12. Furthermore, a third base electrode layer 32c of the third external electrode 30c and a fourth base electrode layer 32d of the fourth external electrode 30d are formed on the first side face 12c and the second side face 12d of the fired laminate 12.

[0119] When a baked layer is formed as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, and then a baking process is performed to form the base electrode layer 32. The baking process temperature at this time is preferably 700° C. or higher and 900° C. or lower. In this embodiment, the base electrode layer 32 is formed as a baked layer.

[0120] Various methods can be used to form the baked layer as the base electrode layer 32. For example, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed by extruding a conductive paste through a slit. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0121] Alternatively, the base electrode layer 32 may be formed by a roller transfer method. In the case of the roller transfer method, when the base electrode layer 32 is formed not only on the first side surface 12 c and the second side surface 12 d but also on a part of the first main surface 12 a and a part of the second main surface 12 b, the third base electrode layer 32 c and the fourth base electrode layer 32 d can be formed on a part of the first main surface 12 a and a part of the second main surface 12 b by increasing the pressing pressure during the roller transfer.

[0122] Next, a first base electrode layer 32a of the first external electrode 30a and a second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the fired laminate 12. When forming a baked layer as the base electrode layer 32 for the first base electrode layer 32a and the second base electrode layer 32b, similar to the third base electrode layer 32c and the fourth base electrode layer 32d, a conductive paste containing a glass component and a metal component is applied, followed by a baking process to form the base electrode layer 32. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0123] Various methods can be used to form the first and second base electrode layers 32 a and 32 b, such as dipping, so that they extend not only to the first end face 12 e and the second end face 12 f, but also to parts of the first and second main faces 12 a and 12 b, and parts of the first and second side faces 12 c and 12 d.

[0124] In this embodiment, the first and second base electrode layers 32a and 32b are formed using a DIP method so as to extend not only to the first end face 12e and the second end face 12f, but also to a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0125] In addition, in this embodiment, the third base electrode layer 32c and the fourth base electrode layer 32d are fired, and then the first base electrode layer 32a and the second base electrode layer 32b are fired. However, the first base electrode layer 32a and the second base electrode layer 32b, and the third base electrode layer 32c and the fourth base electrode layer 32d may be fired simultaneously.

[0126] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0127] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in a N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0128] The conductive resin paste can be applied by, for example, a method of applying the conductive paste by extruding it through a slit or a roller transfer method, similar to the method of forming the base electrode layer 32 as a baked layer.

[0129] When the base electrode layer 32 is formed as a thin film layer, masking or the like is performed, and the base electrode layer 32 can be formed in the desired location by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer is a layer of deposited metal particles having a thickness of 1 μm or less.

[0130] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0131] In this manner, the multilayer ceramic capacitor 10 shown in FIG. 1 can be manufactured.

[0132] As described above, although the embodiments of the present invention have been disclosed in the above description, the present invention is not limited thereto. In other words, various changes can be made to the above-described embodiments and modifications in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and such changes are included in the present invention.

[0133] Although the present embodiment has been described with respect to a three-terminal multilayer ceramic capacitor, the present invention can also be applied to, for example, a two-terminal multilayer ceramic electronic component. That is, a multilayer ceramic electronic component including a laminate including ceramic layers and a plurality of internal electrode layers, the laminate including first and second main surfaces opposing each other in the stacking direction, first and second side surfaces opposing each other in the width direction perpendicular to the stacking direction, and first and second end surfaces opposing each other in the length direction perpendicular to the stacking direction and the width direction, and a plurality of external electrodes, wherein the plurality of internal electrode layers are stacked alternately with the plurality of ceramic layers and include a first internal electrode layer exposed at the first end surface and the second end surface, and a second internal electrode layer exposed at the first and second side surfaces. and a second internal electrode layer formed on the first end face and a second internal electrode layer formed on the second end face, the second internal electrode layer being spaced apart from the first internal electrode layer and the second internal electrode layer, the second internal electrode layer being exposed from either the first end face or the second end face, the plurality of external electrodes including a first external electrode disposed on the first end face and connected to the first internal electrode layer, and a second external electrode disposed on the second end face and connected to the second internal electrode layer, the second external electrode having a line coverage of the conductive component of less than 50% in a region of the dummy electrode spaced 50% or more from the exposed portion of the dummy electrode toward the center of the laminate.

[0134] <1> A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, the laminate including first and second main surfaces opposing each other in a lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; and a plurality of external electrodes, wherein the plurality of internal electrode layers include: first internal electrode layers alternately laminated with the plurality of ceramic layers and exposed at the first end surfaces and the second end surfaces; and second internal electrode layers alternately laminated with the plurality of ceramic layers and exposed at the first side surfaces and the second side surfaces, and the first internal electrode layers and the second internal electrode layers are further provided with dummy electrodes spaced apart from each other and exposed from any of the first end surfaces, the second end surfaces, the first side surfaces, and the second side surfaces, and the plurality of external electrodes include: first external electrodes and second external electrodes connected to the first internal electrode layers, a third external electrode and a fourth external electrode connected to the second internal electrode layer, wherein the dummy electrodes have a line coverage of conductive components less than 50% in a region at least 50% away from an exposed portion of the dummy electrode toward the center of the laminate. <2> The multilayer ceramic electronic component according to <1>, wherein the dummy electrodes are exposed on at least one of the first side surface and the second side surface on a ceramic layer on which the first internal electrode layers are arranged. <3> The multilayer ceramic electronic component according to <1> or <2>, wherein the dummy electrodes are exposed on at least one of the first end surface and the second end surface on a ceramic layer on which the second internal electrode layers are arranged. <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the thickness of the dummy electrodes in the stacking direction is smaller than the thicknesses of the first internal electrode layers and the second internal electrode layers in the stacking direction. <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the thickness of the dummy electrodes in the stacking direction is 75% or more and 95% or less of the thickness of the first internal electrode layers and the second internal electrode layers in the stacking direction.<6> The multilayer ceramic electronic component according to <3>, wherein the second internal electrode layers have a second opposing portion opposing the first internal electrode layers, a third leading portion extending from the second opposing portion and leading to the first side surface, and a fourth leading portion extending from the second opposing portion and leading to the second side surface, and a length in the width direction of the laminate of the dummy electrode exposed on the first side surface or the second side surface is 50% to 60% of a length in the width direction of the laminate of the third leading portion of the second internal electrode layer and the fourth leading portion of the second internal electrode layer. <7> The multilayer ceramic electronic component according to any one of <1> to <6>, wherein a center portion in the length direction of the laminate of the dummy electrode exposed on the first side surface or the second side surface is located within 3% of a center portion in the length direction of the laminate of the second internal electrode layer exposed on the first side surface or the second side surface. <8> The multilayer ceramic electronic component according to any one of <1> to <7>, wherein in the dummy electrode, a ratio of an area of ​​voids to an area of ​​a region spaced 50% or more from the exposed portion of the dummy electrode toward the center of the laminate is 50% or more and 80% or less.

[0135] The present invention relates to a multilayer ceramic electronic component, and can be used as a multilayer ceramic electronic component that prevents peeling between ceramic layers.

[0136] 10 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Ceramic layer 15a Effective layer portion 15b1 First outer layer portion 15b2 Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a First opposing portion 18b Second opposing portion 20a First lead portion 20b Second lead portion 20c Third lead portion 20d Fourth lead portion 22a, 22b Side portion (W gap) of laminate 24a, 24b End portion (L gap) of laminate 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 32c Third base electrode layer 32d Fourth base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer 40 Dummy electrode 40a First dummy electrode 40b Second dummy electrode 40c Third dummy electrode 40d Fourth dummy electrode 42 Exposed portion of dummy electrode 42a Exposed portion of first dummy electrode 42b Exposed portion of second dummy electrode 42c Exposed portion of third dummy electrode 42d Exposed portion of fourth dummy electrode 44 End region of dummy electrode 44a End region of first dummy electrode 44b End region of second dummy electrode 44c End region 44d of third dummy electrode End region 46 of fourth dummy electrode Gap x Stacking direction y Width direction z Length direction L M Length of the multilayer ceramic capacitor W M Width of the multilayer ceramic capacitor T M Dimension of the multilayer ceramic capacitor in the lamination direction L Dimension of the laminate in the length direction W Dimension of the laminate in the width direction T Dimension of the laminate in the lamination direction F1 to F NMeasurement area M: Center in the length direction of the second internal electrode layer M1: Center in the length direction of the first dummy electrode M2: Center in the length direction of the second dummy electrode N: Center in the width direction of the first internal electrode layer N1: Center in the width direction of the third dummy electrode N2: Center in the width direction of the fourth dummy electrode t1: Thickness in the stacking direction of the first internal electrode layer t2: Thickness in the stacking direction of the second internal electrode layer t3: Thickness in the stacking direction of the first dummy electrode t4: Thickness in the stacking direction of the second dummy electrode t5: Thickness in the stacking direction of the third dummy electrode t6: Thickness in the stacking direction of the fourth dummy electrode w1: Length in the width direction of the first dummy electrode w2: Length in the width direction of the second dummy electrode w3: Length in the width direction of the third lead portion w4: Length in the width direction of the fourth lead portion l1: Length in the length direction of the third dummy electrode l2: Length in the length direction of the fourth dummy electrode l3: Length in the length direction of the first lead portion l4 Length of the second drawer section in the longitudinal direction

Claims

1. A multilayer ceramic electronic component comprising: a laminate including a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; and a plurality of external electrodes, The plurality of internal electrode layers are a first internal electrode layer that is alternately laminated with the plurality of ceramic layers and exposed to the first end surface and the second end surface; a second internal electrode layer that is alternately stacked with the plurality of ceramic layers and exposed to the first side surface and the second side surface; having a dummy electrode is disposed apart from the first internal electrode layer and the second internal electrode layer and is exposed from any one of the first end face, the second end face, the first side face, and the second side face, The plurality of external electrodes include a first external electrode and a second external electrode connected to the first internal electrode layer; a third external electrode and a fourth external electrode connected to the second internal electrode layer; Equipped with In the dummy electrode, a region that is 50% or more away from the exposed portion of the dummy electrode toward the center of the laminate has a line coverage of a conductive component that is less than 50%. Multilayer ceramic electronic components.

2. The dummy electrode is 2. The multilayer ceramic electronic component according to claim 1, wherein the first internal electrode layer is exposed to at least one of the first side surface and the second side surface on a ceramic layer on which the first internal electrode layer is disposed.

3. The dummy electrode is 3. The multilayer ceramic electronic component according to claim 1, wherein the second internal electrode layer is exposed to at least one of the first end face and the second end face on a ceramic layer on which the second internal electrode layer is disposed.

4. 2. The multilayer ceramic electronic component according to claim 1, wherein the thickness of said dummy electrode in said lamination direction is smaller than the thicknesses of said first internal electrode layers and said second internal electrode layers in said lamination direction.

5. 2. The multilayer ceramic electronic component according to claim 1, wherein the thickness of said dummy electrode in said lamination direction is 75% or more and 95% or less of the thickness of said first internal electrode layer and said second internal electrode layer in said lamination direction.

6. the second internal electrode layer has a second opposing portion opposing the first internal electrode layer, a third lead portion extending from the second opposing portion and drawn to the first side surface, and a fourth lead portion extending from the second opposing portion and drawn to the second side surface, 4. The multilayer ceramic electronic component according to claim 3, wherein a length in the width direction of the laminate of the dummy electrode exposed to the first side surface or the second side surface is 50% or more and 60% or less of a length in the width direction of the laminate of the third extension portion of the second internal electrode layer and the fourth extension portion of the second internal electrode layer.

7. 2. The multilayer ceramic electronic component according to claim 1, wherein a center portion in a longitudinal direction of the laminate of the dummy electrode exposed on the first side surface or the second side surface is located within 3% from a center portion in a longitudinal direction of the laminate of the second internal electrode layer exposed on the first side surface or the second side surface.

8. 2. The multilayer ceramic electronic component according to claim 1, wherein in the dummy electrode, a ratio of an area of ​​voids to an area of ​​a region spaced 50% or more from the exposed portion of the dummy electrode toward the center of the laminate is 50% or more and 80% or less.