Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor that can suppress dielectric vibration attributed to a piezoelectric phenomenon that occurs when the capacitor is mounted on a wiring board and reduce harsh vibration noise.　A multilayer ceramic capacitor 1 comprises: a laminate 2 in which dielectric layers 5 and internal electrode layers 6 are alternately laminated; and external electrodes 4 that are respectively arranged at end surfaces on both sides in the length direction L orthogonal to the lamination direction T of the laminate 2 and are connected to the internal electrode layer 6. In a plan view from the length direction L, the surface of each external electrode 4 is covered by an insulating layer 8 with the exception of a frame region 9 having a width of 1-100 µm from an outer peripheral edge.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor that can suppress the generation of vibration noise caused by piezoelectric phenomena during mounting.

[0002] Conventionally, electronic components such as multilayer ceramic capacitors have been widely used in various electronic devices, such as mobile terminal devices such as mobile phones and personal computers. A multilayer ceramic capacitor is composed of a rectangular parallelepiped laminate in which dielectric layers and internal electrode layers are alternately laminated, and external electrodes formed on both opposing ends of the laminate.

[0003] Since the dielectric that constitutes the dielectric layer is usually a dielectric ceramic with a perovskite structure such as barium titanate, when an AC voltage is applied while a DC voltage is applied, vibration occurs due to the piezoelectric phenomenon. Therefore, when a multilayer ceramic capacitor is mounted on a wiring board and an AC voltage in the audio frequency band of, for example, 20 Hz to 20 kHz is applied to the external electrodes, the multilayer ceramic capacitor undergoes expansion and contraction vibration, vibrating the surrounding air and generating sound, and also causing resonant vibration in the wiring board, amplifying the sound and making it harsh to the ear.

[0004] For this reason, there is a need to develop a multilayer ceramic capacitor that can suppress the vibration of the dielectric caused by the piezoelectric phenomenon that occurs when the capacitor is mounted on a wiring board, thereby reducing the unpleasant vibration noise.

[0005] Japanese Patent Application Laid-Open No. 2000-182888

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress vibration of the dielectric caused by the piezoelectric phenomenon that occurs when the capacitor is mounted on a wiring board, thereby reducing harsh vibration noise.

[0007] The inventors discovered that by placing an insulator at a predetermined position on the external electrode of a multilayer ceramic capacitor, it is possible to suppress vibration noise caused by the piezoelectric phenomenon that occurs when the capacitor is mounted, and this discovery led to the completion of the present invention.

[0008] That is, the present invention provides a multilayer ceramic capacitor having a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes arranged on both end faces of the laminate in a longitudinal direction perpendicular to the stacking direction and connected to the internal electrode layers, wherein the surface of the external electrodes when viewed in a plan view from the longitudinal direction is covered with an insulating layer except for a frame region having a width of 1 μm to 100 μm from the outer periphery.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the vibration of the dielectric caused by the piezoelectric phenomenon that occurs when the capacitor is mounted on a wiring board, thereby reducing unpleasant vibration noise.

[0010] Fig. 2 is an external view of a multilayer ceramic capacitor. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line A-A. Fig. 4 is an exploded perspective view schematically showing an example of an inner layer portion. Fig. 5 is an external view showing an example of a mounted state of the multilayer ceramic capacitor according to the present invention. Fig. 6 is an external view showing an example of a mounted state of a conventional multilayer ceramic capacitor. Fig. 7 is a diagram showing the effect of reducing vibration noise of the multilayer ceramic capacitor according to the present invention.

[0011] Hereinafter, a multilayer ceramic capacitor according to an embodiment of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] (Multilayer Ceramic Capacitor) FIGS. 1 to 3 show the shape and structure of a multilayer ceramic capacitor 1. FIG. 1 is an external view of the multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view (LT cross-sectional view) of the multilayer ceramic capacitor 1 taken along line A-A at the center of the width direction W shown in FIG. 1. FIG. 3 is a schematic diagram showing the structure of an inner layer portion 3. The structure of the multilayer ceramic capacitor 1 will be described using the lamination direction T, which is the direction in which the dielectric layers and internal electrode layers are stacked, the length direction L which is perpendicular to the lamination direction T, and the width direction W which is perpendicular to the lamination direction T and the length direction L. In the embodiment, the width direction W, the length direction L, and the lamination direction T are perpendicular to one another, but they do not necessarily have to be perpendicular to one another and may intersect one another.

[0013] The multilayer ceramic capacitor 1 includes a rectangular parallelepiped laminate 2. The laminate 2 includes an inner layer portion 3 and has a pair of first and second main surfaces TS1 and TS2 facing each other in a stacking direction T, a pair of first and second end surfaces LS1 and LS2 facing each other in a length direction L perpendicular to the stacking direction T, and a pair of first and second side surfaces WS1 and WS2 facing each other in a width direction W perpendicular to both the stacking direction T and the length direction L.

[0014] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited, but for example, the dimension in the stacking direction T can be approximately 0.1 mm to 2.5 mm, the dimension in the length direction L can be approximately 0.1 mm to 3.2 mm, and the dimension in the width direction W can be approximately 0.1 mm to 2.5 mm.

[0015] The internal layer portion 3 is composed of a plurality of dielectric layers 5 and a plurality of internal electrode layers 6 stacked one on top of the other. The internal electrode layers 6 are composed of a first internal electrode layer 6a and a second internal electrode layer 6b. The first internal electrode layer 6a and the second internal electrode layer 6b are disposed on the dielectric layers 5a and 5b, respectively.

[0016] The internal electrode layers 6 extend in the length direction L and have a rectangular shape when viewed from above in the stacking direction T. The first internal electrode layer 6 a is extended to a first end surface LS1 of the laminate 2, and the second internal electrode layer 6 b is extended to a second end surface LS2 of the laminate 2.

[0017] The dielectric layer 5 is made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ It is possible to use a dielectric ceramic containing components such as the above. The dielectric material may also be one in which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to the above main component.

[0018] The thickness of the dielectric layer 5 is not particularly limited, but can be, for example, about 0.3 μm to 2.0 μm in the effective region for forming capacitance formed by the first internal electrode layer 6 a and the second internal electrode layer 6 b.

[0019] The number of dielectric layers 5 is not particularly limited, but can be, for example, 1 to 6000 layers in the effective area of ​​capacitance formation formed by the first internal electrode layer 6a and the second internal electrode layer 6b.

[0020] On both the top and bottom of the inner layer portion 3, outer layer portions 7 are provided, each consisting of only a dielectric layer 5 and no internal electrode layer 6. The thickness of the outer layer portion 7 is not limited, but may be, for example, 15 μm to 150 μm. The thickness of the dielectric layer in the outer layer portion 7 may be greater than the thickness of the dielectric layer in the effective region for capacitance formation where the internal electrode layer 6 is formed. The material of the dielectric layer in the outer layer portion may be different from the material of the dielectric layer in the inner layer portion.

[0021] FIG. 3 shows the inner layer portion 3 broken down into individual dielectric layers 5 in the stacking direction T.

[0022] The internal electrode layers 6 are formed by sintering a conductive paste containing metal powder as a conductor, an organic solvent, a binder, and a dispersant on the dielectric layers. The internal electrode layers 6 and the dielectric layers 5 are alternately stacked to form the internal layer portion 3. The internal electrode layers 6 are composed of first internal electrode layers 6a and second internal electrode layers 6b, and the first internal electrode layers 6a and the second internal electrode layers 6b are disposed on the dielectric layers 5a and 5b, respectively.

[0023] Metals such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, and Au can be used for the internal electrode layers 6. These metals may also be compounds containing these metal elements or alloys with other metals.

[0024] The thickness of the internal electrode layer 6 is not particularly limited, but may be, for example, about 0.3 μm to 1.5 μm.

[0025] A first external electrode 4a and a second external electrode 4b are formed on a first end surface LS1 and a second end surface LS2 of the laminate 2, respectively.

[0026] The first external electrode 4a has a first base electrode layer 41a and a first plating layer 42a disposed on the first base electrode layer 41a.

[0027] The second external electrode 4b has a second base electrode layer 41b and a second plating layer 42b disposed on the second base electrode layer 41b.

[0028] The first base electrode layer 41a is disposed on the first end surface LS1. The first base electrode layer 41a is connected to the first internal electrode layer 6a. In this embodiment, the first base electrode layer 41a is formed to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0029] The second base electrode layer 41b is disposed on the second end surface LS2. The second base electrode layer 41b is connected to the second internal electrode layer 6b. In this embodiment, the second base electrode layer 41b is formed to extend from the second end surface LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0030] The first and second base electrode layers 41a and 41b include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like. In this embodiment, the first and second base electrode layers 41a and 41b are baked layers. The baked layer preferably includes a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, and the like. The ceramic component may be the same type of ceramic material as that of the dielectric layer 5, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0031] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having an internal electrode layer and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having an internal electrode layer and a dielectric layer to obtain a laminate, and then applying a conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having an internal electrode layer and a dielectric layer with a conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer as the added ceramic material. The baked layer may be formed in multiple layers.

[0032] The thickness in the length direction L of the first base electrode layer 41a located on the first end surface LS1 is preferably, for example, approximately 3 μm or more and 160 μm or less at the center in the stacking direction T and width direction W of the first base electrode layer 41a.

[0033] The thickness in the length direction L of the second base electrode layer 41b located on the second end surface LS2 is preferably, for example, approximately 3 μm or more and 160 μm or less at the center of the second base electrode layer 41b in the stacking direction T and width direction W.

[0034] When the first base electrode layer 41a is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness in the stacking direction T of the first base electrode layer 41a provided in this portion is, for example, approximately 3 μm or more and 40 μm or less at the center of the first base electrode layer 41a provided in this portion in the length direction L and width direction W.

[0035] When the first base electrode layer 41a is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness in the width direction W of the first base electrode layer 41a provided in this portion is, for example, approximately 3 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the first base electrode layer 41a provided in this portion.

[0036] When the second base electrode layer 41b is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness in the stacking direction T of the second base electrode layer 41b provided in this portion is, for example, approximately 3 μm or more and 40 μm or less at the center of the length direction L and width direction W of the second base electrode layer provided in this portion.

[0037] When the second base electrode layer 41b is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness in the width direction W of the second base electrode layer 41b provided in this portion is, for example, approximately 3 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 41b provided in this portion.

[0038] Alternatively, a configuration may be adopted in which a first plating layer 42a and a second plating layer 42b (described later) are disposed directly on the laminate 2 without providing the first base electrode layer 41a and the second base electrode layer 41b.

[0039] Furthermore, the first and second base electrode layers 41 a and 41 b are not limited to baked layers, but may be thin film layers formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0040] The first plating layer 42a is disposed so as to cover the first base electrode layer 41a.

[0041] The second plating layer 42b is disposed so as to cover the second base electrode layer 41b.

[0042] The first plating layer 42a and the second plating layer 42b may contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The first plating layer 42a and the second plating layer 42b may each be formed of multiple layers.

[0043] The first plating layer 42a and the second plating layer 42b preferably have a two-layer structure in which Sn plating layers 422a and 422b are formed on Ni plating layers 421a and 421b, respectively. In this case, the Ni plating layers 421a and 421b prevent the first base electrode layer 41a and the second base electrode layer 41b from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. When the first plating layer 42a and the second plating layer 42b each have a two-layer structure of a Ni plating layer and a Sn plating layer, the thickness of each of the Ni plating layer and the Sn plating layer is preferably 2 μm or more and 15 μm or less.

[0044] The surfaces of the first external electrode 4a and the second external electrode 4b when viewed in plan from the longitudinal direction L are covered with an insulating layer 8 except for a frame region 9 having a width of 1 μm to 100 μm from the outer periphery.

[0045] When the external electrode is composed of a base electrode layer and a plating layer, the insulating layer can be arranged in a predetermined area on the surface of the plating layer, but when the insulating layer is arranged in a predetermined area on the surface of the base electrode layer, the plating layer is formed on the surface of the base electrode layer excluding the area where the insulating layer is arranged.

[0046] Furthermore, when the plating layer consists of multiple layers, an insulating layer can be placed in a predetermined area on the surface of the outermost plating layer, but when an insulating layer is placed on the surface of any plating layer other than the outermost layer, the plating layer placed on top of the plating layer on which the insulating layer is placed is laminated in a part excluding the area where the insulating layer is placed, and the insulating layer is placed on the surface of the external electrode that may come into contact with the solder fillet.

[0047] In the embodiment shown in FIG. 2 , an insulating layer 8 is formed on the first base electrode layer 41 a and the second base electrode layer 41 b that respectively constitute the first external electrode 4 a and the second external electrode 4 b, in a range on the surface when viewed in a plan view from the longitudinal direction L, excluding a frame region 9 having a width of 1 μm or more and 100 μm or less from the outer periphery, and Ni plating layers 421 a, 421 b and Sn plating layers 422 a, 422 b are formed on the surfaces of the first base electrode layer 41 a and the second base electrode layer 41 b excluding the range in which the insulating layer 8 is arranged.

[0048] The multilayer ceramic capacitor 1 is connected to the lands 51a, 51b by applying solder to the surfaces of the first external electrode 4a and the second external electrode 4b below the insulating layer 8. The provision of the frame region 9 allows a solder fillet to be formed within a certain height range from below the outer periphery, thereby ensuring reliable bonding to the wiring board.

[0049] The material of the insulating layer 8 is not particularly limited as long as it has insulating properties, but synthetic resin is preferred because it allows for easy formation of an insulating layer on the surface of the external electrode. Examples of synthetic resins that can be used include thermosetting resins such as epoxy resin, polyimide resin, and phenolic resin, and thermoplastic resins such as polyethylene resin and polyamide resin.

[0050] When viewed in plan from the longitudinal direction L, by disposing the insulating layer 8 on the surfaces of the first external electrode 4a and the second external electrode 4b corresponding to the region where the internal electrode layers 6 are stacked, it is possible to prevent the solder fillets 52a, 52b from wetting up to the height where the internal electrode layers 6 are arranged during mounting, thereby effectively suppressing the generation of vibration noise caused by the piezoelectric phenomenon.

[0051] The insulating layer 8 has a thickness of 200 μm or less in the longitudinal direction L, and is thickest at approximately the center when viewed in the longitudinal direction L. This prevents the multilayer ceramic capacitor from becoming large, and when mounted on a wiring board, the central portion of the surface of the insulating layer protrudes outward from the bottom portion, making it possible to reliably prevent the solder fillet from wetting up.

[0052] The multilayer ceramic capacitor 1 is mounted by applying solder to the surfaces of the first external electrode 4a and the second external electrode 4b and connecting them to the lands 51a, 51b. However, in a conventional multilayer ceramic capacitor 1, as shown in FIG. 5, the solder fillets 52a, 52b formed during mounting wet to a high height, and when they reach the height at which the internal electrode layers 6 are arranged, a piezoelectric phenomenon occurs in the dielectric, making it easy for the multilayer ceramic capacitor 1 to undergo expansion and contraction vibration.

[0053] 4 shows an example of mounting the multilayer ceramic capacitor 1 according to this embodiment. In the multilayer ceramic capacitor 1, the insulating layer 8 is provided in a predetermined area on the surface of the first external electrode 4a and the second external electrode 4b, so the height of the solder fillets 52a, 52b that rise is kept low, and the generation of vibration noise caused by the piezoelectric phenomenon can be suppressed.

[0054] (Confirmation Test) A confirmation test was carried out on the multilayer ceramic capacitor according to the present invention to confirm the effect of suppressing vibration noise.

[0055] In the confirmation test, the sound pressure (dB) of the vibration noise generated when a DC voltage of 3 V and an AC voltage of 1 V were applied to an example in which a multilayer ceramic capacitor of the present invention in which an insulating layer was disposed in a predetermined area on the surface of the external electrode was used as a sample, and a comparative example in which a conventional multilayer ceramic capacitor not provided with an insulating layer was used as a sample.

[0056] As shown in FIG. 6, it was confirmed that the multilayer ceramic capacitor (Example) of the present invention suppresses the vibration of the dielectric caused by the piezoelectric phenomenon that occurs when the capacitor is mounted on a wiring board, thereby reducing harsh vibration noise.

[0057] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments and can be embodied in various forms without departing from the spirit and scope of the present invention. For example, although the embodiments have shown an example in which the insulating layer 8 is provided on both the first external electrode 4 a and the second external electrode 4 b, it is expected that the same effect can be obtained even when the insulating layer 8 is provided on either the first external electrode 4 a or the second external electrode 4 b.

[0058] The present invention is as follows: <1> A multilayer ceramic capacitor having a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes arranged on both end faces of the laminate in a longitudinal direction perpendicular to the stacking direction and connected to the internal electrode layers, wherein the surfaces of the external electrodes, when viewed in plan from the longitudinal direction, are covered with an insulating layer except for a frame region having a width of 1 μm to 100 μm from the outer periphery. <2> The multilayer ceramic capacitor according to <1>, wherein the surfaces of the external electrodes, when viewed in plan from the longitudinal direction, are covered with the insulating layer in a region corresponding to the region where the internal electrode layers are stacked. <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the insulating layer has a thickness in the longitudinal direction of 200 μm or less and is thickest at approximately the center when viewed from the longitudinal direction. <4> A mounting structure including the multilayer ceramic capacitor according to any one of <1> to <3>, lands arranged on a wiring board, and solder connecting the external electrodes of the multilayer ceramic capacitor and the lands, wherein the solder is arranged below the insulating layer.

[0059] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 Internal layer portion 4 External electrode 4a First external electrode 4b Second external electrode 5 Dielectric layer 5a Dielectric layer 5b Dielectric layer 6 Internal electrode layer 6a First internal electrode layer 6b Second internal electrode layer 7 External layer portion 8 Insulating layer 9 Frame region 41a First base electrode layer 41b Second base electrode layer 42a First plating layer 42b Second plating layer 421a Ni plating layer 421b Ni plating layer 422a Sn plating layer 422b Sn plating layer 50 Wiring board 51a Land 51b Land 52a Solder fillet 52b Solder fillet TS1 First main surface TS2 Second main surface WS1 First side surface WS2 Second side surface LS1 First end surface LS2 Second end surface

Claims

1. A multilayer ceramic capacitor comprising: a laminate in which dielectric layers and internal electrode layers are alternately laminated; and external electrodes disposed on both end faces of the laminate in a longitudinal direction perpendicular to a lamination direction and connected to the internal electrode layers, the surfaces of the external electrodes, when viewed in a plan view from the longitudinal direction, are covered with an insulating layer except for a frame region having a width of 1 μm to 100 μm from the outer periphery.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the external electrodes have surfaces covered with the insulating layer that correspond to regions where the internal electrode layers are laminated when viewed in a plan view from the longitudinal direction.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein said insulating layer has a thickness in said longitudinal direction of 200 [mu]m or less and is thickest at approximately the center when viewed in said longitudinal direction.

4. 4. A mounting structure comprising the multilayer ceramic capacitor according to claim 1, lands arranged on a wiring board, and solder connecting the external electrodes of the multilayer ceramic capacitor and the lands, wherein the solder is arranged below the insulating layer.