Multi-level inverter

Abstract

The present invention suppresses a voltage drop in a bootstrap circuit. A control unit (60) changes a first voltage vector, a second voltage vector, and a third voltage vector, which are adjacent to a command voltage vector in a first vector space, to a combination of a zero vector, and a fourth voltage vector and a fifth voltage vector that are adjacent to the command voltage vector, in a second vector space. The zero vector is a voltage vector resulting from a combination of potential levels at a third connection point (13) of a plurality of inverter circuits (1) becoming the potential of a negative electrode and a voltage vector resulting from a combination of the potential levels at the third connection point becoming the potential of a positive electrode. The control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) within a prescribed control period so that the command voltage vector matches a synthesis vector of the zero vector, the fourth voltage vector, and the fifth voltage vector.

Description

Multilevel Inverter

[0001] The present disclosure relates to a multilevel inverter, and more particularly to a multilevel inverter with a bootstrap circuit.

[0002] Patent Document 1 discloses a three-phase voltage-type PWM inverter circuit using a bootstrap circuit.

[0003] The three-phase voltage-type PWM inverter circuit disclosed in Patent Document 1 includes six switching elements, six gate drive circuits, a microcomputer, a main DC power supply, and three bootstrap circuits.

[0004] Furthermore, Patent Document 1 discloses an inverter control method in which a predetermined switching pattern is applied to each phase of a three-phase inverter to obtain a desired voltage vector and supply it to a load, and a control voltage is supplied by a bootstrap circuit of each phase. In this inverter control method, switching control is performed to replace a voltage vector selected during a period in which the bootstrap circuit of any phase maintains a discharging state and does not affect the output voltage, with a voltage vector that can be charged by the bootstrap circuit at predetermined intervals.

[0005] The inverter control method disclosed in Patent Document 1 is a technique related to a two-level inverter, and does not disclose a method for controlling a multilevel inverter.

[0006] Japanese Patent Application Publication No. 5-292755

[0007] An object of the present disclosure is to provide a multilevel inverter capable of suppressing a voltage drop in a bootstrap circuit.

[0008] A multilevel inverter according to one aspect of the present disclosure includes a DC power supply unit, a plurality of inverter circuits, and a control device. The DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The control device controls the plurality of inverter circuits. Each of the plurality of inverter circuits includes a switching circuit and a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode. In the switching circuit, a first switching element, a second switching element, a third switching element, and a fourth switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element. The first diode is connected in anti-parallel to the first switching element. The second diode is connected in anti-parallel to the second switching element. The third diode is connected in anti-parallel to the third switching element. The fourth diode is connected in anti-parallel to the fourth switching element. The fifth diode has a cathode connected to a first connection point between the first switching element and the second switching element and an anode connected to the intermediate potential point. The sixth diode has an anode connected to a second connection point between the third switching element and the fourth switching element and a cathode connected to the intermediate potential point. The control device includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, a plurality of second bootstrap circuits, a plurality of third bootstrap circuits, a power supply unit, and a control unit. The plurality of first gate drivers drive the first switching elements of each of the plurality of inverter circuits. The plurality of second gate drivers drive the second switching elements of each of the plurality of inverter circuits. The plurality of third gate drivers drive the third switching elements of each of the plurality of inverter circuits.The plurality of fourth gate drivers drive the fourth switching elements of each of the plurality of inverter circuits. The plurality of first bootstrap circuits correspond one-to-one to the plurality of first gate drivers. Each of the plurality of first bootstrap circuits supplies a voltage to a corresponding first gate driver. The plurality of second bootstrap circuits correspond one-to-one to the plurality of second gate drivers. Each of the plurality of second bootstrap circuits supplies a voltage to a corresponding second gate driver. The plurality of third bootstrap circuits correspond one-to-one to the plurality of third gate drivers. Each of the plurality of third bootstrap circuits supplies a voltage to a corresponding third gate driver. The power supply unit supplies a voltage to the plurality of fourth gate drivers. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. The control unit selects a first voltage vector, a second voltage vector, and a third voltage vector adjacent to a command voltage vector from a first group of voltage vectors. Each of the first group of voltage vectors is determined in a first vector space by a combination of potential levels at a third connection point between the second switching elements and the third switching elements of the multiple inverter circuits. The control unit changes the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector and a fourth voltage vector and a fifth voltage vector adjacent to the command voltage vector in a second vector space different from the first vector space. Each of the second group of voltage vectors is determined by a combination of potential levels at a third connection point between the second switching elements and the third switching elements of the multiple inverter circuits. The zero vector is a voltage vector of the second group of voltage vectors that is a combination where the potential level at the third connection point between the second switching elements and the third switching elements of the multiple inverter circuits is the negative potential and a voltage vector of the combination where the potential level at the third connection point between the second switching elements and the third switching elements of the multiple inverter circuits is the positive potential.The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so as to make a composite vector of the zero vector, the fourth voltage vector, and the fifth voltage vector in the second vector space coincide with the command voltage vector.

[0009] A multilevel inverter according to one aspect of the present disclosure includes a DC power supply unit, a plurality of inverter circuits, and a control device. The DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point. The plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply unit. The control device controls the plurality of inverter circuits. Each of the plurality of inverter circuits includes a first switching element, a second switching element, a third switching element, and a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode. The first diode, the second diode, the third diode, and the fourth diode are connected in anti-parallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively. In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series from the positive electrode side to the negative electrode side, in that order. In each of the plurality of inverter circuits, a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and an output point. The output point is a connection point between the first switching element and the second switching element. The control device includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of bootstrap circuits, a power supply unit, and a control unit. The plurality of first gate drivers drive the first switching element of each of the plurality of inverter circuits. The plurality of second gate drivers drive the second switching element of each of the plurality of inverter circuits. The plurality of third gate drivers drive the third switching element of each of the plurality of inverter circuits. The plurality of fourth gate drivers drive the fourth switching element of each of the plurality of inverter circuits. The plurality of bootstrap circuits correspond one-to-one to the plurality of first gate drivers and supply voltages to the corresponding first gate drivers. The power supply unit supplies voltages to the plurality of second gate drivers and the plurality of third gate drivers.The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers. The control unit selects, from a first group of voltage vectors, a first voltage vector, a second voltage vector, and a third voltage vector adjacent to a command voltage vector. Each of the first group of voltage vectors is determined in a first vector space by a combination of potential levels of the plurality of connection points in the plurality of inverter circuits. The control unit changes the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector and a fourth voltage vector and a fifth voltage vector adjacent to the command voltage vector in a second vector space different from the first vector space. Each of the second group of voltage vectors is determined by a combination of potential levels of the plurality of connection points in the plurality of inverter circuits. The zero vector is a voltage vector from the second group of voltage vectors that is a combination of a voltage vector where the potential levels of the plurality of connection points in the plurality of inverter circuits are the negative potential and a voltage vector where the potential levels of the plurality of connection points are the positive potential. The control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so as to make a composite vector of the zero vector, the fourth voltage vector, and the fifth voltage vector in the second vector space coincide with the command voltage vector.

[0010] FIG. 1 is a circuit diagram of a system including a multilevel inverter according to a first embodiment. FIG. 2 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter is in a first switching state. FIG. 3 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter is in a first switching state. FIG. 4 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter is in a second switching state. FIG. 5 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter is in a second switching state. FIG. 6 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter is in a third switching state. FIG. 7 is an explanatory diagram of a discharge path and a charge path when the switching circuit in the multilevel inverter is in a third switching state. FIG. 8 is an explanatory diagram of voltage command values ​​for each phase in the multilevel inverter. FIG. 9 is an explanatory diagram of a first group of voltage vectors related to the multilevel inverter. FIG. 10 is a more detailed explanatory diagram of the first group of voltage vectors related to the multilevel inverter. FIG. 11 is a vector diagram for explaining the operation of a control unit in the multilevel inverter. 12A is an explanatory diagram of a command voltage vector, a first voltage vector, a second voltage vector, and a third voltage vector for the multilevel inverter of the same embodiment. FIG. 12B is an explanatory diagram of a command voltage vector, a zero vector, a fourth voltage vector, and a fifth voltage vector for the multilevel inverter of the same embodiment. FIG. 13 is a time chart of the switching states of each phase of a multilevel inverter according to a comparative example. FIG. 14 is a time chart of the on / off states of first to fourth switching elements of a multilevel inverter according to the comparative example. FIG. 15 is a time chart of the switching states of each phase when the inverter circuit of each phase is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector in the multilevel inverter according to the first embodiment to a combination of the zero vector, the fourth voltage vector, and the fifth voltage vector.FIG. 16 is a time chart showing the on / off states of the first to fourth switching elements when the inverter circuit is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector, a fourth voltage vector, and a fifth voltage vector in the multilevel inverter of the above embodiment. FIG. 17 is a time chart showing the switching states of each phase of the multilevel inverter of the comparative example. FIG. 18 is a time chart showing the on / off states of the first to fourth switching elements of the multilevel inverter of the comparative example. FIG. 19 is a time chart showing the switching states of each phase when the inverter circuit is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector, a fourth voltage vector, and a fifth voltage vector in the multilevel inverter of the above embodiment. FIG. 20 is a time chart showing the on / off states of the first to fourth switching elements when the inverter circuit is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector, a fourth voltage vector, and a fifth voltage vector in the multilevel inverter of the above embodiment. FIG. 21 is a circuit diagram of a system including a multilevel inverter of a modified example. Fig. 22 is a circuit diagram of a system including a multilevel inverter according to a second embodiment. Fig. 23 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter is in a first switching state. Fig. 24 is an explanatory diagram of a discharge path when a switching circuit in the multilevel inverter is in the first switching state. Fig. 25 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter is in a second switching state. Fig. 26 is an explanatory diagram of a discharge path when a switching circuit in the multilevel inverter is in the second switching state. Fig. 27 is an explanatory diagram of a current path when a switching circuit in the multilevel inverter is in a third switching state. Fig. 28 is an explanatory diagram of a discharge path and a charge path when a switching circuit in the multilevel inverter is in the third switching state.FIG. 29 is an explanatory diagram of a discharge path when the switching circuit in the multilevel inverter is in a second switching state. FIG. 30 is an explanatory diagram of voltage command values ​​for each phase in the multilevel inverter. FIG. 31 is an explanatory diagram of a first group of voltage vectors for the multilevel inverter. FIG. 32 is a more detailed explanatory diagram of the first group of voltage vectors for the multilevel inverter. FIG. 33 is a vector diagram for explaining the operation of a control unit in the multilevel inverter. FIG. 34A is an explanatory diagram of a command voltage vector, a first voltage vector, a second voltage vector, and a third voltage vector for the multilevel inverter. FIG. 34B is an explanatory diagram of a command voltage vector, a zero vector, a fourth voltage vector, and a fifth voltage vector for the multilevel inverter. FIG. 35 is a time chart of the switching states of each phase of a multilevel inverter according to a comparative example. FIG. 36 is a time chart of the on / off states of first to fourth switching elements of a multilevel inverter according to a comparative example. 37 is a time chart of the switching states of each phase when the inverter circuit of each phase is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector, a fourth voltage vector, and a fifth voltage vector in the multilevel inverter according to the second embodiment. FIG. 38 is a time chart of the on / off states of the first to fourth switching elements when the inverter circuit of the multilevel inverter according to the second embodiment is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector, a fourth voltage vector, and a fifth voltage vector. FIG. 39 is a time chart of the switching states of each phase in the multilevel inverter according to the comparative example. FIG. 40 is a time chart of the on / off states of the first to fourth switching elements in the multilevel inverter according to the comparative example. FIG. 41 is a time chart of the switching states of each phase when the inverter circuit of each phase is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector, a fourth voltage vector, and a fifth voltage vector in the multilevel inverter according to the second embodiment.Fig. 42 is a time chart of the on / off states of the first to fourth switching elements when the inverter circuit is controlled by changing the combination of the first voltage vector, the second voltage vector, and the third voltage vector in the multilevel inverter of the above embodiment to a combination of a zero vector, a fourth voltage vector, and a fifth voltage vector. Fig. 43 is a circuit diagram of a system including a multilevel inverter according to a third embodiment. Fig. 44 is a circuit diagram of a system including a multilevel inverter according to a fourth embodiment. Fig. 45 is a circuit diagram of a system including a multilevel inverter according to a fifth embodiment. Fig. 46 is a circuit diagram of a system including a multilevel inverter according to a sixth embodiment.

[0011] First Embodiment A multilevel inverter 100 according to a first embodiment will be described below with reference to FIGS. 1 to 12B.

[0012] (1) Overview As shown in Fig. 1 , for example, a multilevel inverter 100 includes a DC power supply unit 3, a plurality of (e.g., three) inverter circuits 1, and a control device 6. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control device 6 controls the plurality of inverter circuits 1.

[0013] The multilevel inverter 100 is a diode-clamped three-level, three-phase inverter. In the multilevel inverter 100, each of a plurality of inverter circuits 1 has an output terminal 41. In the multilevel inverter 100, an AC load RA1 is connected to the plurality of output terminals (AC terminals) 41. The AC load RA1 is, for example, a three-phase motor. In the multilevel inverter 100, one of the plurality of inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage.

[0014] Each of the plurality of inverter circuits 1 includes a switching circuit 10, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. Each of the plurality of inverter circuits 1 also includes a fifth diode D5 and a sixth diode D6. In the multilevel inverter 100, the potential of the intermediate potential point M1 is clamped by the fifth diode D5 and the sixth diode D6 of each inverter circuit 1.

[0015] In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive electrode P1 side to the negative electrode N1 side of the DC power supply unit 3 in the order of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4.

[0016] In each inverter circuit 1, the first diode D1 is connected in anti-parallel to the first switching element Q1. The second diode D2 is connected in anti-parallel to the second switching element Q2. The third diode D3 is connected in anti-parallel to the third switching element Q3. The fourth diode D4 is connected in anti-parallel to the fourth switching element Q4. The fifth diode D5 has its cathode connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2, and its anode connected to the intermediate potential point M1. The sixth diode D6 has its anode connected to a second connection point 12 between the third switching element Q3 and the fourth switching element Q4, and its cathode connected to the intermediate potential point M1.

[0017] The control device 6 has a plurality of (e.g., three) first gate drivers 61, a plurality of (e.g., three) second gate drivers 62, a plurality of (e.g., three) third gate drivers 63, and a plurality of (e.g., three) fourth gate drivers 64. The control device 6 also has a plurality of (e.g., three) first bootstrap circuits 71, a plurality of (e.g., three) second bootstrap circuits 72, a plurality of (e.g., three) third bootstrap circuits 73, a power supply unit 9, and a control unit 60.

[0018] The plurality of first gate drivers 61 drive the first switching element Q1 of each of the plurality of inverter circuits 1. The plurality of second gate drivers 62 drive the second switching element Q2 of each of the plurality of inverter circuits 1. The plurality of third gate drivers 63 drive the third switching element Q3 of each of the plurality of inverter circuits 1. The plurality of fourth gate drivers 64 drive the fourth switching element Q4 of each of the plurality of inverter circuits 1.

[0019] The plurality of first bootstrap circuits 71 correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first bootstrap circuits 71 supplies a voltage to the corresponding first gate driver 61. The plurality of second bootstrap circuits 72 correspond one-to-one to the plurality of second gate drivers 62. Each of the plurality of second bootstrap circuits 72 supplies a voltage to the corresponding second gate driver 62. The plurality of third bootstrap circuits 73 correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third bootstrap circuits 73 supplies a voltage to the corresponding third gate driver 63. The power supply unit 9 supplies a voltage to the plurality of fourth gate drivers 64.

[0020] The control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 and a plurality of fourth gate drivers 64 .

[0021] (2) Details of the Power Conversion Device The DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. In the DC power supply unit 3, a first end of the first capacitor C1 is connected to the first DC terminal 31, a second end of the first capacitor C1 is connected to a first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1. For example, a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. The phrase "the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not necessarily mean that the capacitance of the second capacitor C2 exactly matches the capacitance of the first capacitor C1, but may mean that the capacitance of the second capacitor C2 is within a range of 95% to 105% of the capacitance of the first capacitor C1.

[0022] Hereinafter, for convenience of explanation, with regard to the multiple switching circuits 10, the switching circuit 10 included in inverter circuit 1U may be referred to as switching circuit 10U, the switching circuit 10 included in inverter circuit 1V may be referred to as switching circuit 10V, and the switching circuit 10 included in inverter circuit 1W may be referred to as switching circuit 10W. Furthermore, of the multiple output terminals 41, the output terminal 41 included in inverter circuit 1U may be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V may be referred to as output terminal 41V, and the output terminal 41 included in inverter circuit 1W may be referred to as output terminal 41W.

[0023] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, MOSFETs. Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, a normally-off n-channel MOSFET. The MOSFETs are, for example, Si-based MOSFETs or SiC-based MOSFETs.

[0024] A control terminal of the first switching element Q1 of each switching circuit 10 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0025] In each switching circuit 10, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of the DC power supply 3, and a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2. In each switching circuit 10, a second main terminal of the second switching element Q2 is connected to a first main terminal of a third switching element Q3. In each switching circuit 10, a second main terminal of the third switching element Q3 is connected to a first main terminal of a fourth switching element Q4, and a second main terminal of the fourth switching element Q4 is connected to a negative electrode N1 of the DC power supply 3.

[0026] In the inverter circuit 1U, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10U is connected to the output terminal 41U. In the inverter circuit 1V, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10V is connected to the output terminal 41V. In the inverter circuit 1W, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10W is connected to the output terminal 41W. The third connection point 13 of the inverter circuit 1U is connected to, for example, the U-phase of the AC load RA1 via the output terminal 41U. The third connection point 13 of the inverter circuit 1V is connected to, for example, the V-phase of the AC load RA1 via the output terminal 41V. The third connection point 13 of the inverter circuit 1W is connected to, for example, the W-phase of the AC load RA1 via the output terminal 41W.

[0027] In each inverter circuit 1, the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (drain terminal) of the first switching element Q1. In each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (source terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (drain terminal) of the second switching element Q2. In each inverter circuit 1, the anode of the third diode D3 is connected to the second main terminal (source terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal (drain terminal) of the third switching element Q3. In each inverter circuit 1, the anode of the fourth diode D4 is connected to the second main terminal (source terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal (drain terminal) of the fourth switching element Q4.

[0028] In each inverter circuit 1, the first diode D1 may be substituted with a parasitic diode of the MOSFET that constitutes the first switching element Q1. Also, in each inverter circuit 1, the second diode D2 may be substituted with a parasitic diode of the MOSFET that constitutes the second switching element Q2. Also, in each inverter circuit 1, the third diode D3 may be substituted with a parasitic diode of the MOSFET that constitutes the third switching element Q3. Also, in each inverter circuit 1, the fourth diode D4 may be substituted with a parasitic diode of the MOSFET that constitutes the fourth switching element Q4.

[0029] In each inverter circuit 1, the cathode of the fifth diode D5 is connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the fifth diode D5 is connected to an intermediate potential point M1 of the DC power supply unit 3. The "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3. In the first embodiment, the intermediate potential point M1 is connected to ground, and therefore the potential of the intermediate potential point M1 is 0 V. In this case, when the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2, and the potential of the negative electrode N1 is −Vdc / 2.

[0030] The cathode of the sixth diode D6 is connected to the intermediate potential point M1, and the anode of the sixth diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0031] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. The plurality of first gate drivers 61 are connected to control terminals of the corresponding first switching elements Q1. The plurality of first gate drivers 61 drive the corresponding first switching elements Q1. The plurality of first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs a plurality of first control signals S1 (see FIG. 2 ) that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0032] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. The second gate drivers 62 are connected to control terminals of the corresponding second switching elements Q2. The second gate drivers 62 drive the corresponding second switching elements Q2. The second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs second control signals S2 (see FIG. 2 ) that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0033] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. The plurality of third gate drivers 63 are connected to control terminals of the corresponding third switching elements Q3. The plurality of third gate drivers 63 drive the corresponding third switching elements Q3. The plurality of third gate drivers 63 are connected to the control unit 60. The control unit 60 outputs a plurality of third control signals S3 (see FIG. 2 ) that correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0034] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. The plurality of fourth gate drivers 64 are connected to the control terminals of the corresponding fourth switching elements Q4. The plurality of fourth gate drivers 64 drive the corresponding fourth switching elements Q4. The plurality of fourth gate drivers 64 are connected to the control unit 60. The control unit 60 outputs a plurality of fourth control signals S4 (see FIG. 2 ) that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0035] The first bootstrap circuits 71 correspond one-to-one to the first gate drivers 61. Each of the first bootstrap circuits 71 supplies a voltage to the corresponding first gate driver 61. Each of the first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (also referred to as a boost capacitor C17). In each first bootstrap circuit 71, the anode of the diode D17 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D17 is connected to a first end of the capacitor C17 via the resistor R17. The first end of the capacitor C17 is connected to a high-potential power supply terminal 61H (see FIG. 3 ) of the first gate driver 61, and the second end of the capacitor C17 is connected to a low-potential power supply terminal 61L (see FIG. 3 ) of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with a voltage required to turn on the first switching element Q1 in the first gate driver 61. Each of the plurality of first bootstrap circuits 71 further includes a Zener diode Z17 connected in parallel to the capacitor C17.

[0036] The second bootstrap circuits 72 correspond one-to-one to the second gate drivers 62. Each second bootstrap circuit 72 supplies a voltage to the corresponding second gate driver 62. Each second bootstrap circuit 72 includes a diode D27, a resistor R27, and a capacitor C27 (also referred to as a boost capacitor C27). In each second bootstrap circuit 72, the anode of the diode D27 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D27 is connected to a first end of the capacitor C27 via the resistor R27. The first end of the capacitor C27 is connected to a high-potential power supply terminal 62H (see FIG. 3 ) of the second gate driver 62, and the second end of the capacitor C27 is connected to a low-potential power supply terminal 62L (see FIG. 3 ) of the second gate driver 62. The second bootstrap circuit 72 supplies the second gate driver 62 with a voltage required to turn on the second switching element Q2 in the second gate driver 62. Each of the plurality of second bootstrap circuits 72 further includes a Zener diode Z27 connected in parallel with the capacitor C27.

[0037] The third bootstrap circuits 73 correspond one-to-one to the third gate drivers 63. Each of the third bootstrap circuits 73 supplies a voltage to the corresponding third gate driver 63. Each of the third bootstrap circuits 73 includes a diode D37, a resistor R37, and a capacitor C37 (also referred to as a boost capacitor C37). In each third bootstrap circuit 73, the anode of the diode D37 is connected to the positive terminal of the power supply unit 9, and the cathode of the diode D37 is connected to a first end of the capacitor C37 via the resistor R37. The first end of the capacitor C37 is connected to a high-potential power supply terminal 63H (see FIG. 3 ) of the third gate driver 63, and the second end of the capacitor C37 is connected to a low-potential power supply terminal 63L (see FIG. 3 ) of the third gate driver 63. The third bootstrap circuit 73 supplies the third gate driver 63 with a voltage required to turn on the third switching element Q3 in the third gate driver 63. Each of the plurality of third bootstrap circuits 73 further includes a Zener diode Z37 connected in parallel with the capacitor C37.

[0038] The power supply unit 9 supplies voltages to the plurality (three) of first bootstrap circuits 71, the plurality (three) of second bootstrap circuits 72, the plurality (three) of third bootstrap circuits 73, and the plurality (three) of fourth gate drivers 64. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91. A positive terminal of the power supply unit 9 is connected to the high-potential power supply terminal 64H (see FIG. 3) of each of the plurality of fourth gate drivers 64, and a negative terminal of the power supply unit 9 is connected to the low-potential power supply terminal 64L (see FIG. 3) of each of the plurality of fourth gate drivers 64.

[0039] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control unit 60 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0040] The control unit 60 outputs a plurality of (three) first control signals S1 (see FIG. 2 ) for controlling a plurality of (three) first switching elements Q1, a plurality of (three) second control signals S2 (see FIG. 2 ) for controlling a plurality of (three) second switching elements Q2, a plurality of (three) third control signals S3 (see FIG. 2 ) for controlling a plurality of third switching elements Q3, and a plurality of (three) fourth control signals S4 for controlling a plurality of (three) fourth switching elements Q4. Note that FIG. 2 illustrates only one inverter circuit 1 of the three inverter circuits 1 (see FIG. 1 ), and the remaining two inverter circuits 1 are not shown. Also, FIG. 2 does not illustrate a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, a plurality of fourth gate drivers 64, a plurality of first bootstrap circuits 71, a plurality of second bootstrap circuits 72, a plurality of third bootstrap circuits 73, and the power supply unit 9 shown in FIG. 1 . 3 illustrates only one of the three inverter circuits 1 (see FIG. 1 ), and omits the illustration of the remaining two inverter circuits 1. Also, in FIG. 3 , the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, the two second bootstrap circuits 72, and the two third bootstrap circuits 73 shown in FIG. 1 are omitted.

[0041] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1W that controls the first switching element Q1 of the switching circuit 10W.

[0042] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2W that controls the second switching element Q2 of the switching circuit 10W.

[0043] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3W that controls the third switching element Q3 of the switching circuit 10W.

[0044] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W that controls the fourth switching element Q4 of the switching circuit 10W.

[0045] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) higher than the first potential level. The first potential level is, for example, 0 V, and the second potential level is a potential level higher than the gate threshold voltage of the MOSFET. That is, in each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off a switching element corresponding to that control signal, and the second potential level is a potential level for turning on a switching element corresponding to that control signal.

[0046] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0047] In the multilevel inverter 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state differ from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Note that with regard to the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with one another.

[0048] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the ON state and both the third switching element Q3 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the third connection point 13 becomes the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc / 2).

[0049] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state and both the second switching element Q2 and the third switching element Q3 are in the on state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 in the second switching state, the potential of the third connection point 13 becomes the potential level of the intermediate potential point M1 (e.g., 0).

[0050] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the third connection point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., −Vdc / 2).

[0051] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in FIG. 2, a current flows through the path of the positive electrode P1 of the DC power supply unit 3 - the first switching element Q1 - the second switching element Q2 - the third connection point 13 - the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see FIG. 1) becomes Vdc / 2.

[0052] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the first gate driver 61 to turn on the first switching element Q1 is supplied from the capacitor C17 of the first bootstrap circuit 71 to the first gate driver 61. Therefore, as shown in FIG. 3 , the charge in the capacitor C17 of the first bootstrap circuit 71 is discharged through a discharge path Ru1 that connects the capacitor C17 to the high-potential power supply terminal 61H of the first gate driver 61, the low-potential power supply terminal 61L of the first gate driver 61, and the capacitor C17. As a result, in the first bootstrap circuit 71, the voltage across the capacitor C17 decreases over time.

[0053] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the second gate driver 62 to turn on the second switching element Q2 is supplied from capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62. Therefore, the charge in capacitor C27 of the second bootstrap circuit 72 is discharged via a discharge path Ru2 that runs from capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62 to the low-potential power supply terminal 62L of the second gate driver 62 and back to capacitor C27. As a result, in the second bootstrap circuit 72, the voltage across capacitor C27 decreases over time.

[0054] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the capacitor C17 is charged by the capacitor C27 if a first condition is met. As shown in FIG. 3 , if the voltages across the capacitor C17 are Vo1, Vo2, Vd1, VR1, and Vf2, respectively, the first condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). The charging path Ru21 along which the capacitor C17 is charged is the path of the capacitor C27, resistor R27, diode D17, resistor R17, capacitor C17, first node 11, second switching element Q2, and capacitor C27.

[0055] 4, for example, current flows through a path (indicated by a thick solid arrow) of the intermediate potential point M1 of the DC power supply unit 3, the fifth diode D5, the second switching element Q2, the third connection point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, current flows through a path of the intermediate potential point M1 of the DC power supply unit 3, the fifth diode D5 of the inverter circuit 1U, the second switching element Q2 of the switching circuit 10U, the third connection point 13, and the output terminal 41.

[0056] 4, for example, current flows through the path (indicated by the thick dashed arrow) of output terminal 41-third node 13-third switching element Q3-second node 12-sixth diode D6, and the voltage value of the output voltage to AC load RA1 becomes 0. More specifically, when switching circuits 10U, 10V, and 10W are in the second switching state, the second switching state, and the first switching state, respectively, current flows through the path (indicated by the thick dashed arrow) of output terminal 41-third node 13-third switching element Q3-second node 12-sixth diode D6 in inverter circuit 1U, and the voltage value of the output voltage to AC load RA1 becomes 0.

[0057] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for turning on the second switching element Q2 is supplied from capacitor C27 of the second bootstrap circuit 72 to the second gate driver 62 by the second gate driver 62. Therefore, the charge in capacitor C27 of the second bootstrap circuit 72 is discharged along a discharge path Ru2 that connects capacitor C27 to the high-potential power supply terminal 62H of the second gate driver 62, the low-potential power supply terminal 62L of the second gate driver 62, and then capacitor C27, as shown in FIG. 5 . Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for turning on the third switching element Q3 is supplied from capacitor C37 of the third bootstrap circuit 73 to the third gate driver 63 by the third gate driver 63. Therefore, the charge in the capacitor C37 of the third bootstrap circuit 73 is discharged through a discharge path Ru3 that runs from the capacitor C37 to the high potential power supply terminal 63H of the third gate driver 63 to the low potential power supply terminal 63L of the third gate driver 63 and back to the capacitor C37.

[0058] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the capacitor C27 is charged by the capacitor C37 when the second condition is met, and the capacitor C17 is charged by the capacitor C27 when the third condition is met. As shown in Fig. 5, if the voltages across the capacitors C17, C27, and C37 are Vo1, Vo2, and Vo3, respectively, the voltages across the diodes D17 and D27 are Vd1 and Vd2, respectively, the voltages across the resistors R17 and R27 are VR1 and VR2, respectively, and the voltages across the second switching element Q2 and the third switching element Q3 are Vf2 and Vf3, respectively, the second condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). The third condition is Vo2 > (Vo1 + Vd1 + VR1 + Vf2). A charging path Ru32 through which the capacitor C27 is charged by the capacitor C37 is a path of the capacitor C37-resistor R37-diode D27-resistor R27-capacitor C27-third node 13-third switching element Q3-capacitor C37. A charging path Ru21 through which the capacitor C17 is charged by the capacitor C27 is a path of the capacitor C27-resistor R27-diode D17-resistor R17-capacitor C17-first node 11-second switching element Q2-capacitor C27.

[0059] 6, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, a current flows through the path from the negative pole N1 of the DC power supply unit 3 to the fourth switching element Q4, the third switching element Q3, the third connection point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes −Vdc / 2. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C37 charges the capacitor C27 of the second bootstrap circuit 72 (see FIG. 1), so that the voltage of the capacitor C27 increases over time until the capacitor C27 is fully charged. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C37 of the third bootstrap circuit 73 supplies the third gate driver 63 with the voltage required to turn on the third switching element Q3. Therefore, the charge in capacitor C37 of the third bootstrap circuit 73 is discharged along a discharge path Ru3 that runs from capacitor C37 to the high potential side power supply terminal 63H of the third gate driver 63 to the low potential side power supply terminal 63L of the third gate driver 63 and back to capacitor C37. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, capacitor C37 is charged by the power supply unit 9 if the fourth condition is met, and capacitor C27 is charged by capacitor C37 if the fifth condition is met. 7 , the voltage across the power supply unit 9 is Voo, the voltages across the capacitors C27 and C37 are Vo2 and Vo3, the voltages across the diodes D27 and D37 are Vd2 and Vd3, the voltages across the resistors R27 and R37 are VR2 and VR3, and the voltages across the third switching element Q3 and the fourth switching element Q4 are Vf3 and Vf4. The fourth condition is Voo > (Vo3 + Vd3 + VR3 + Vf4). The fifth condition is Vo3 > (Vo2 + Vd2 + VR2 + Vf3). The charging path Ru93 along which the power supply unit 9 charges the capacitor C37 is the path from the positive terminal of the power supply unit 9 to the diode D37, the resistor R37, the capacitor C37, the second node 12, the fourth switching element Q4, and the negative terminal of the power supply unit 9.A charging path Ru32 for charging the capacitor C27 by the capacitor C37 is a path of the capacitor C37-resistor R37-diode D27-resistor R27-capacitor C27-third node 13-third switching element Q3-capacitor C37.

[0060] The control unit 60 generates first to fourth control signals S1U to S4U, first to fourth control signals S1V to S4V, and first to fourth control signals S1W to S4W based on voltage commands Vu, Vv, and Vw (see FIG. 8) related to the output voltages of the inverter circuits 1U, 1V, and 1W, respectively. The first to fourth control signals S1U to S4U are the first to fourth control signals S1 to S4 for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U. The first to fourth control signals S1V to S4V are the first to fourth control signals S1 to S4 for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V. The first to fourth control signals S1W to S4W are the first to fourth control signals S1 to S4 for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W.

[0061] As shown in FIG. 8 , the voltage commands Vu, Vv, and Vw are sinusoidal signals whose phases are, for example, 120° apart, and whose values ​​(voltage command values) change over time. The voltage commands Vu, Vv, and Vw each have the same cycle length. The control unit 60 may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detection unit 8 (see FIG. 1 ) that detects the state of the AC load RA1. If the AC load RA1 is a three-phase motor, the information output from the detection unit 8 may include, for example, at least one of the following: information on the detection results of multiple current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1; and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase motor.

[0062] Below, we will explain the operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U). The operations of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W are similar to the operation of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with each other.

[0063] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control.

[0064] The voltage vector control by the control unit 60 will be described in more detail below.

[0065] The control unit 60 stores in advance a first group of voltage vectors in a first vector space and a second group of voltage vectors in a second vector space different from the first vector space. Below, the first group of voltage vectors will be described with reference to Figures 9 to 12A, and then the second group of voltage vectors will be described with reference to Figure 12B.

[0066] Each of the voltage vectors in the first group is determined by a combination of potential levels at the connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1. In other words, the voltage vectors in the first group are determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase. The first vector space is a three-level voltage vector space as shown in FIG. 9, and includes 24 sectors, each of which is an equilateral triangle. The three-level voltage vector space shown in FIG. 9 is a vector diagram illustrating the voltage vectors in the first group on an orthogonal d-q coordinate system. The number of voltage vectors included in the voltage vectors in the first group is 3. ３ = 27 pieces.

[0067] As shown in Figure 9, the first group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. １／２ The first group includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which is 2 Vdc and points in different directions. The voltage vectors in the first group each have a magnitude of (2 / 3) １／２ The first group of voltage vectors includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3) １／２ ・3 １／２ - Includes six voltage vectors V13, V14, V15, V16, V17, and V18 that are Vdc and have different directions. In Figure 9, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is also 60 degrees.

[0068] The first group of voltage vectors can be expressed as shown in Figures 10 to 12A by representing the first switching state, the second switching state, and the third switching state with the symbols "P," "0," and "N," respectively, and notating them in the order of U phase, V phase, and W phase.

[0069] As shown in FIG. 10 , the three zero vectors V0p, V0n, and V0o in the first group of voltage vectors can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that, with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P," the switching state of the V-phase switching circuit 10V is "P," and the switching state of the W-phase switching circuit 10W is "P." For example, a voltage vector with a "p" appended, such as V10p, includes the switching state "P" but does not include the switching state "N." This also applies hereinafter. Furthermore, a voltage vector with a "n" appended, such as V10n, includes the switching state "N" but does not include the switching state "P." This also applies hereinafter. Furthermore, a voltage vector with an "o" appended thereto, such as V10o, includes a switching state of "0" but does not include a switching state of "P" or "N." When the switching state of the switching circuit 10 is "P," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "N," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "0," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0070] Furthermore, the six voltage vectors V1, V2, V3, V4, V5, and V6 in the first group of voltage vectors can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors that do not have "p," "n," or "o" added after the number added to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases.

[0071] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n in the first group of voltage vectors can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.

[0072] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 in the first group of voltage vectors can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively.

[0073] The control unit 60 calculates the instantaneous value of the command voltage for each output voltage of the plurality of inverter circuits 1 as a command voltage vector V ＊ (See FIG. 11) to convert the command voltage vector V ＊ The d-axis component of the orthogonal d-q coordinate system is Vd, and the command voltage vector V ＊ If the q-axis component on the orthogonal d-q coordinate system is Vq, then the command voltage vector V ＊ can be calculated using equation (1).

[0074]

[0075] The control unit 60 selects a command voltage vector V ＊ The first voltage vector VV1 is selected from the plurality of voltage vectors, and the magnitude of the first voltage vector VV1 is the reference magnitude and the magnitude of the command voltage vector VV2 is the reference magnitude. ＊ The reference magnitude is, for example, (2 / 3) １／２Therefore, the plurality of voltage vectors include 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0] as voltage vectors whose magnitude is a reference magnitude (reference vectors). ＊ The first voltage vector VV1 and the command voltage vector V ＊ The angle between the first voltage vector VV1 and the voltage vector V8p[PP0] is smaller than 30 degrees. In the example of FIG. 12A, the first voltage vector VV1 is a voltage vector V8p[PP0] and a voltage vector V8n[00N]. In the example of FIG. 12A, the second voltage vector VV2 is a voltage vector V7p[P00] and a voltage vector V7n[00NN]. In the example of FIG. 12A, the third voltage vector VV3 is a voltage vector V13[P0N].

[0076] Each of the voltage vectors in the second group is determined by a combination of potential levels at a connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1. In other words, the voltage vectors in the second group are determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase. The second vector space is a level vector space as shown in FIG. 12B , and includes six equilateral triangular sectors. The number of voltage vectors included in the second group is nine.

[0077] 12B, the second group of voltage vectors includes three zero vectors V0p[PPP], V0n[NNN], and V0o

[000] , and six voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP]. The expressions of the second group of voltage vectors are similar to those of the first group of voltage vectors.

[0078] The control unit 60 converts the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 (see FIG. 12A) in the first vector space into the combination of the zero vector and the command voltage vector VV3 in the second vector space. ＊ The zero vectors at this time are a zero vector V0n[NNN] of a combination where the potential level of the third connection point 13 between the second switching element Q2 and the third switching element Q3 of the plurality of inverter circuits 1 is a negative potential, and a zero vector V0p[PPP] of a combination where the potential level is a positive potential. ＊ The fourth voltage vector VV4 and the command voltage vector V ＊ The angle between them is less than 30 degrees.

[0079] The control unit 60 defines a command voltage vector V as a result of combining the zero vectors V0n[NNN] and V0p[PPP], the fourth voltage vector VV4 (in the example of FIG. 12B, the voltage vector V2[PPN]), and the fifth voltage vector VV5 (in the example of FIG. 12B, the voltage vector V1[PNN]) in the second vector space. ＊ The control circuit controls the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 within a predetermined control period Ts (see FIG. 15 ) so that the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other. The predetermined control period Ts is, for example, one period of the carrier signal.

[0080] In a comparative example in which control is performed to change the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 in the first vector space to the combination of the zero vector, the fourth voltage vector VV4, and the fifth voltage vector VV5 in the second vector space, the command voltage vector VV1 in the first vector space within the control period Ts is ＊ The resultant vector of the vectors at the vertices of the equilateral triangle surrounding ＊That is, in the comparative example, the resultant vector of the first voltage vector VV1 (in the example of FIG. 12A, the voltage vector V8p[PP0] and the voltage vector V8n[00N]), the second voltage vector VV2 (the voltage vector V7p[P00] and the voltage vector V7n[0NN]), and the third voltage vector VV3 (in the example of FIG. 12A, the voltage vector V13[P0N]) is set to the command voltage vector V ＊ In the comparative example, the control period Ts is one period of the carrier signal. In the comparative example, within half the control period Ts, for example, as shown in FIG. 13 , in two voltage vectors arranged in time series, the switching state of only one of the U phase, V phase, and W phase changes between “P” and “0” or between “0” and “N,” and the same voltage vector is output twice within the control period Ts. In FIG. 13 , the voltage vectors are output in the following order: voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. 13 illustrates an example in which the allocation time of the first voltage vector VV1 (voltage vector V8p[PP0] and voltage vector V8n[00N]) with respect to the control period Ts is T0, the allocation time of the third voltage vector VV3 (voltage vector V13[P0N]) is T1, and the allocation time of the second voltage vector VV2 (voltage vector V7p[P00]) is T2. ＊ The voltage vectors at the vertices of the equilateral triangle surrounding the vector V are Va, Vb, and Vc, and the command voltage vector V ＊ Letting the magnitude of and the angle be V and θ, respectively, T0, T1, and T2 are determined so as to satisfy equations (2) and (3). "j" in equation (2) is the imaginary unit. In the example of FIG. 13 , the voltage vector Va is the first voltage vector VV1 (voltage vectors V8p[PP0] and V8n[00N]), the voltage vector Vb is the third voltage vector VV3 (voltage vector V13[P0N]), and the voltage vector Vc is the second voltage vector VV2 (voltage vector V7p[P00]).

[0081]

[0082]

[0083] In the example of FIG. 13, for example, with respect to the first to fourth switching elements Q1 to Q4 of the switching circuit 10U, as shown in FIG. 14, the second switching element Q2 is in the on state for the entire control period Ts, resulting in a large voltage drop in the second bootstrap circuit 72.

[0084] In contrast to this, in the control unit 60 of the multilevel inverter 100 according to the first embodiment, within one period of the carrier signal, for example, as shown in FIG. 15 , the signals are output in the order of zero vector V0n[NNN] → voltage vector V1[PNN] → voltage vector V2[PPN] → zero vector V0p[PPP] → zero vector V0p[PPP] → voltage vector V2[PPN] → voltage vector V1[PNN] → zero vector V0n[NNN].

[0085] 15 illustrates an example in which the allocation time of the zero vectors (zero vector V0n[NNN] and zero vector V0p[PPP]) for the control period Ts is T0, the allocation time of the fifth voltage vector VV5 (voltage vector V1[PNN]) is T1, and the allocation time of the fourth voltage vector VV4 (voltage vector V2[PPN]) is T2. ＊ The voltage vectors at the vertices of the equilateral triangle surrounding are Va, Vb, and Vc, and the command voltage vector V ＊ 15, the voltage vector Va is a zero vector (zero vector V0n[NNN] and zero vector V0p[PPP]), the voltage vector Vb is a fifth voltage vector VV5 (voltage vector V1[PNN]), and the voltage vector Vc is a fourth voltage vector VV4 (voltage vector V2[PPN]).

[0086] The control unit 60 changes the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 in the comparative example to a combination of a zero vector (zero vector V0n[NNN] and zero vector V0p[PPP]), a fourth voltage vector VV4 (in the example of FIG. 15 , voltage vector V2[PPN]), and a fifth voltage vector VV5 (in the example of FIG. 15 , voltage vector V1[PNN]). As a result, a period in which the switching state of the U phase is “N” can be generated, as shown in FIG. 15 . As a result, the multilevel inverter 100 according to the first embodiment can generate a third switching state in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state, as shown in FIG. 16 . Therefore, the multilevel inverter 100 according to the first embodiment can suppress a voltage drop across the capacitor C27 of the second bootstrap circuit 72.

[0087] In the comparative example, the command voltage vector V ＊ 12A , the order of the voltage vectors during the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts. In the example of FIG. 17 , the voltage vectors are output in the following order: voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N] → voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0]. Similarly to the example of FIG. 13 , FIG. 17 illustrates a case in which the allocation time of the voltage vectors V8p and V8n is T0, the allocation time of the voltage vector V13 is T1, and the allocation time of the voltage vectors V7p and V7n is T2. In this case, as shown in FIG. 18 , the third switching state does not occur throughout the entire control period Ts, resulting in a large voltage drop across the second bootstrap circuit 72.

[0088] In contrast to this, in the control unit 60 of the multilevel inverter 100 according to the first embodiment, within one period of the carrier signal, for example, as shown in FIG. 19 , the signals are output in the order of zero vector V0p[PPP] → voltage vector V2[PPN] → voltage vector V1[PNN] → zero vector V0n[NNN] → zero vector V0n[NNN] → voltage vector V1[PNN] → voltage vector V2[PPN] → zero vector V0p[PPP]. The control unit 60 changes the combination of the first voltage vector VV1 (voltage vector V8p[PP0] and voltage vector V8n[00N]), the second voltage vector VV2 (voltage vector V7p[P00]), and the third voltage vector VV3 (voltage vector V13[P0N]) in the example of FIG. 17 to a combination of a zero vector (zero vector V0n[NNN] and zero vector V0p[PPP]), the fourth voltage vector VV4 (voltage vector V2[PPN] in the example of FIG. 18), and the fifth voltage vector VV5 (voltage vector V1[PNN] in the example of FIG. 18). Therefore, as shown in FIG. 19, a period in which the switching state of the U phase is “N” can be generated. As a result, the multilevel inverter 100 according to the first embodiment can generate the third switching state within the control period Ts as shown in FIG. 20. Therefore, the multilevel inverter 100 according to the first embodiment can suppress the voltage drop of the capacitor C27 of the second bootstrap circuit 72.

[0089] In the multilevel inverter 100 according to the first embodiment, the control unit 60 calculates the command voltage vector V ＊ When the polarity of the command voltage corresponding to is negative, the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 is not changed to the combination of the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector VV4, and the fifth voltage vector VV5.

[0090] Furthermore, in the multilevel inverter 100, the control unit 60 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 so that the output voltages of the plurality of first bootstrap circuits 71 and the plurality of second bootstrap circuits 72 do not fall below a predetermined value.

[0091] (3) Summary In the multilevel inverter 100 according to the first embodiment, the control unit 60 controls the command voltage vector V ＊ Each of the first group of voltage vectors is determined in the first vector space by a combination of the potential levels of the third connection point 13 between the second switching element Q2 and the third switching element Q3 of the plurality of inverter circuits 1. The control unit 60 calculates the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 by combining the zero vectors V0n[NNN] and V0p[PPP] and the command voltage vector V0p[PPP] of the second group of voltage vectors in a second vector space different from the first vector space. ＊ The control unit 60 changes the voltage vectors in the second group to a combination of the fourth voltage vector VV4 and the fifth voltage vector VV5 adjacent to each other. Each of the voltage vectors in the second group is determined by a combination of potential levels at the third connection point 13 between the second switching elements Q2 and the third switching elements Q3 of the plurality of inverter circuits 1. The zero vectors V0n[NNN] and V0p[PPP] are the voltage vectors in the second group that are combined such that the potential levels at the third connection point 13 between the second switching elements Q2 and the third switching elements Q3 of the plurality of inverter circuits 1 are negative and positive potentials, respectively. The control unit 60 converts the composite vector of the zero vectors V0n[NNN] and V0p[PPP], the fourth voltage vector VV4, and the fifth voltage vector VV5 in the second vector space into the command voltage vector V ＊ The control circuit controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 within a predetermined control period Ts so that the first gate drivers 61, the second gate drivers 62, the third gate drivers 63, and the fourth gate drivers 64 coincide with each other.

[0092] The multilevel inverter 100 according to the first embodiment can suppress voltage drops in the bootstrap circuits. More specifically, this aspect can suppress voltage drops in the capacitors C17 of the first bootstrap circuits 71, the capacitors C27 of the second bootstrap circuits 72, and the capacitors C37 of the third bootstrap circuits 73.

[0093] Moreover, in the multilevel inverter 100 according to the first embodiment, the DC-DC converter 91 included in the power supply unit 9 supplies voltage to the plurality of fourth gate drivers 64 and the plurality of third bootstrap circuits 73. This allows the multilevel inverter 100 according to the first embodiment to be miniaturized.

[0094] (Modifications) The above-described first embodiment is merely one of various embodiments of the present disclosure. The above-described first embodiment can be modified in various ways depending on the design and the like as long as the object of the present disclosure can be achieved.

[0095] For example, each of the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4 is not limited to a MOSFET, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor). In this case, the control terminal, the first main terminal, and the second main terminal of each of the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4 are a gate terminal, a collector terminal, and an emitter terminal, respectively.

[0096] In the multilevel inverter 100 according to the first embodiment, the control unit 60 calculates the command voltage vector V ＊ The combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 in the first vector space may be changed to the combination of the zero vector, the fourth voltage vector VV4, and the fifth voltage vector VV5 in the second vector space, not only when the polarity of the command voltage corresponding to VV1 is positive, but also when the polarity is negative.

[0097] Furthermore, each of the plurality of first bootstrap circuits 71 includes the Zener diode Z17, but may not include the Zener diode Z17. Furthermore, each of the plurality of second bootstrap circuits 72 includes the Zener diode Z27, but may not include the Zener diode Z27. Furthermore, each of the plurality of third bootstrap circuits 73 includes the Zener diode Z37, but may not include the Zener diode Z37.

[0098] Furthermore, the multilevel inverter 100 is not limited to a configuration including one DC-DC converter 91 as shown in FIG. 1 as the power supply unit 9 that supplies voltage to the three fourth gate drivers 64. For example, the power supply unit 9 may be configured to include multiple (three) DC-DC converters 91, as in the multilevel inverter 100 according to a modified example shown in FIG. 21 . The multiple DC-DC converters 91 correspond to the multiple (three) fourth gate drivers 64 and supply voltages to the corresponding fourth gate drivers 64. In the multilevel inverter 100 according to the modified example, in each of the multiple first bootstrap circuits 71, the anode of the diode D17 is connected to the positive terminal of the corresponding DC-DC converter 91 among the multiple DC-DC converters 91. In each of the multiple second bootstrap circuits 72, the anode of the diode D27 is connected to the positive terminal of the corresponding DC-DC converter 91 among the multiple DC-DC converters 91. In each of the third bootstrap circuits 73, the anode of a diode D37 is connected to the positive terminal of the corresponding one of the DC-DC converters 91.

[0099] The multilevel inverter 100 may be any multilevel inverter having three or more levels, and may be, for example, a five-level inverter.

[0100] Second Embodiment A multilevel inverter 100a according to a second embodiment will be described below with reference to FIGS. 22 to 343B.

[0101] (1) Overview As shown in Fig. 22, for example, a multilevel inverter 100a includes a DC power supply unit 3, a plurality of (e.g., three) inverter circuits 1a, and a control device 6a. The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1a are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control device 6a controls the plurality of inverter circuits 1a.

[0102] The multilevel inverter 100a is a T-type three-level, three-phase inverter. In the multilevel inverter 100a, each of a plurality of inverter circuits 1a has an output terminal 41a. In the multilevel inverter 100a, an AC load RA1 is connected to the plurality of output terminals (AC terminals) 41a. The AC load RA1 is, for example, a three-phase motor. In the multilevel inverter 100a, one of the plurality of inverter circuits 1a is an inverter circuit 1Ua that outputs a U-phase voltage, another is an inverter circuit 1Va that outputs a V-phase voltage, and the remaining is an inverter circuit 1Wa that outputs a W-phase voltage.

[0103] Each of the inverter circuits 1a includes a first switching element Q1a, a second switching element Q2a, a third switching element Q3a, and a fourth switching element Q4a, as well as a first diode D1a, a second diode D2a, a third diode D3a, and a fourth diode D4a. The first diode D1a, the second diode D2a, the third diode D3a, and the fourth diode D4a are connected in anti-parallel to the first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a, respectively. In each of the inverter circuits 1a, the first switching element Q1a and the second switching element Q2a are connected in series from the positive electrode P1 side to the negative electrode N1 side, with the first switching element Q1a and the second switching element Q2a arranged in this order. 22 and 23 , a series circuit (first circuit 11a) of a first switching element Q1a and a second switching element Q2a is connected between the positive electrode P1 and the negative electrode N1. In each of the multiple inverter circuits 1a, a series circuit (second circuit 12a) of a third switching element Q3a and a fourth switching element Q4a is connected between an intermediate potential point M1 and an output point. The output point is a connection point 13a between the first switching element Q1a and the second switching element Q2a. The second circuit 12a has a bidirectional switch including the third switching element Q3a, the fourth switching element Q4a, the third diode D3a, and the fourth diode D4a.

[0104] The control device 6a includes a plurality of (e.g., three) first gate drivers 61a, a plurality of (e.g., three) second gate drivers 62a, a plurality of (e.g., three) third gate drivers 63a, and a plurality of (e.g., three) fourth gate drivers 64a. The control device 6a also includes a plurality of (e.g., three) bootstrap circuits 71a (hereinafter also referred to as first bootstrap circuits 71a), a plurality of (e.g., three) second bootstrap circuits 72a, a power supply unit 9a, and a control unit 60a.

[0105] The first gate drivers 61a drive the first switching elements Q1a of the inverter circuits 1a. The second gate drivers 62a drive the second switching elements Q2a of the inverter circuits 1a. The third gate drivers 63a drive the third switching elements Q3a of the inverter circuits 1a. The fourth gate drivers 64a drive the fourth switching elements Q4a of the inverter circuits 1a.

[0106] The multiple first bootstrap circuits 71a correspond one-to-one to the multiple first gate drivers 61a. The multiple first bootstrap circuits 71a supply voltages to the corresponding first gate drivers 61a. The multiple second bootstrap circuits 72a correspond to the multiple third gate drivers 63a and the multiple fourth gate drivers 64a. The multiple second bootstrap circuits 72a supply voltages to the corresponding third gate drivers 63a and the corresponding fourth gate drivers 64a. The power supply unit 9a supplies voltages to the multiple second gate drivers 62a.

[0107] The control unit 60a controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a.

[0108] (2) Details of the Power Conversion Device The DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2. In the DC power supply unit 3, the first capacitor C1 and the second capacitor C2 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. In the DC power supply unit 3, a first end of the first capacitor C1 is connected to the first DC terminal 31, a second end of the first capacitor C1 is connected to a first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1. For example, a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1. The phrase "the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" does not necessarily mean that the capacitance of the second capacitor C2 exactly matches the capacitance of the first capacitor C1, but may mean that the capacitance of the second capacitor C2 is within a range of 95% to 105% of the capacitance of the first capacitor C1.

[0109] In the following, for ease of explanation, the output terminal 41a included in the inverter circuit 1Ua among the multiple output terminals 41a will be referred to as the output terminal 41Ua, the output terminal 41a included in the inverter circuit 1Va will be referred to as the output terminal 41Va, and the output terminal 41a included in the inverter circuit 1Wa will be referred to as the output terminal 41Wa.

[0110] The first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a of each inverter circuit 1a have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a of each inverter circuit 1a are, for example, MOSFETs. Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a of each inverter circuit 1a are, for example, normally-off n-channel MOSFETs. The MOSFETs are, for example, Si-based MOSFETs or SiC-based MOSFETs.

[0111] The control terminal of the first switching element Q1a of each inverter circuit 1a is connected to a corresponding one of the plurality of first gate drivers 61a. The control terminal of the second switching element Q2a of each inverter circuit 1a is connected to a corresponding one of the plurality of second gate drivers 62a. The control terminal of the third switching element Q3a of each inverter circuit 1a is connected to a corresponding one of the plurality of third gate drivers 63a. The control terminal of the fourth switching element Q4a of each inverter circuit 1a is connected to a corresponding one of the plurality of fourth gate drivers 64a.

[0112] In each inverter circuit 1a, a first main terminal of a first switching element Q1a is connected to a positive electrode P1 of a DC power supply unit 3, a second main terminal of the first switching element Q1a is connected to a first main terminal of a second switching element Q2a, and a second main terminal of the second switching element Q2a is connected to a negative electrode N1 of the DC power supply unit 3.

[0113] In each inverter circuit 1a, the first main terminal of the third switching element Q3a is connected to the intermediate potential point M1, the second main terminal of the third switching element Q3a is connected to the second main terminal of the fourth switching element Q4a, and the first main terminal of the fourth switching element Q4a is connected to the connection point 13a. Therefore, the bidirectional switch included in the second circuit 12a is a common-source bidirectional switch in which the second main terminals (source terminals) of the third switching element Q3a and the fourth switching element Q4a are connected to each other. The "intermediate potential point M1" is a point at an intermediate potential between the potentials of the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. In the second embodiment, the intermediate potential point M1 is connected to ground, so the potential of the intermediate potential point M1 is 0 V. In this case, when the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2, and the potential of the negative electrode N1 is −Vdc / 2.

[0114] In the inverter circuit 1Ua, a connection point 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Ua. In the inverter circuit 1Va, a connection point 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Va. In the inverter circuit 1Wa, a connection point 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Wa. The connection point 13a of the inverter circuit 1Ua is connected to, for example, the U-phase of an AC load RA1 via the output terminal 41Ua. The connection point 13a of the inverter circuit 1Va is connected to, for example, the V-phase of the AC load RA1 via the output terminal 41Va. The connection point 13a of the inverter circuit 1Wa is connected to, for example, the W-phase of the AC load RA1 via the output terminal 41Wa.

[0115] In each inverter circuit 1a, the anode of the first diode D1a is connected to the second main terminal (source terminal) of the first switching element Q1a, and the cathode of the first diode D1a is connected to the first main terminal (drain terminal) of the first switching element Q1a. In each inverter circuit 1a, the anode of the second diode D2a is connected to the second main terminal (source terminal) of the second switching element Q2a, and the cathode of the second diode D2a is connected to the first main terminal (drain terminal) of the second switching element Q2a. In each inverter circuit 1a, the anode of the third diode D3a is connected to the second main terminal (source terminal) of the third switching element Q3a, and the cathode of the third diode D3a is connected to the first main terminal (drain terminal) of the third switching element Q3a. In each inverter circuit 1a, the anode of the fourth diode D4a is connected to the second main terminal (source terminal) of the fourth switching element Q4a, and the cathode of the fourth diode D4a is connected to the first main terminal (drain terminal) of the fourth switching element Q4a.

[0116] In each inverter circuit 1a, the first diode D1a may be substituted with a parasitic diode of the MOSFET that constitutes the first switching element Q1a. Also, in each inverter circuit 1a, the second diode D2a may be substituted with a parasitic diode of the MOSFET that constitutes the second switching element Q2a. Also, in each inverter circuit 1a, the third diode D3a may be substituted with a parasitic diode of the MOSFET that constitutes the third switching element Q3a. Also, in each inverter circuit 1a, the fourth diode D4a may be substituted with a parasitic diode of the MOSFET that constitutes the fourth switching element Q4a.

[0117] The plurality of first gate drivers 61a correspond one-to-one to the plurality of first switching elements Q1a. The plurality of first gate drivers 61a are connected to control terminals of the corresponding first switching elements Q1a. The plurality of first gate drivers 61a drive the corresponding first switching elements Q1a. The plurality of first gate drivers 61a are connected to a control unit 60a. The control unit 60a outputs a plurality of first control signals S1a (see FIG. 23 ) that correspond one-to-one to the plurality of first gate drivers 61a. Each of the plurality of first gate drivers 61a controls the on / off of the first switching element Q1a based on the provided first control signal S1a.

[0118] The second gate drivers 62a correspond one-to-one to the second switching elements Q2a. The second gate drivers 62a are connected to control terminals of the corresponding second switching elements Q2a. The second gate drivers 62a drive the corresponding second switching elements Q2a. The second gate drivers 62a are connected to the control unit 60a. The control unit 60a outputs second control signals S2a (see FIG. 23) that correspond one-to-one to the second gate drivers 62a. Each of the second gate drivers 62a controls the on / off of the second switching element Q2a based on the second control signal S2a provided thereto.

[0119] The plurality of third gate drivers 63a correspond one-to-one to the plurality of third switching elements Q3a. The plurality of third gate drivers 63a are connected to control terminals of the corresponding third switching elements Q3a. The plurality of third gate drivers 63a drive the corresponding third switching elements Q3a. The plurality of third gate drivers 63a are connected to the control unit 60a. The control unit 60a outputs a plurality of third control signals S3a (see FIG. 23 ) that correspond one-to-one to the plurality of third gate drivers 63a. Each of the plurality of third gate drivers 63a controls the on / off of the third switching element Q3a based on the provided third control signal S3a.

[0120] The plurality of fourth gate drivers 64a correspond one-to-one to the plurality of fourth switching elements Q4a. The plurality of fourth gate drivers 64a are connected to control terminals of the corresponding fourth switching elements Q4a. The plurality of fourth gate drivers 64a drive the corresponding fourth switching elements Q4a. The plurality of fourth gate drivers 64a are connected to the control unit 60a. The control unit 60a outputs a plurality of fourth control signals S4a (see FIG. 23 ) that correspond one-to-one to the plurality of fourth gate drivers 64a. Each of the plurality of fourth gate drivers 64a controls the on / off of the fourth switching element Q4a based on the received fourth control signal S4a.

[0121] The first bootstrap circuits 71a correspond one-to-one to the first gate drivers 61a. Each of the first bootstrap circuits 71a supplies a voltage to the corresponding first gate driver 61a. As shown in FIGS. 22 and 24 , each of the first bootstrap circuits 71a includes a diode D11, a resistor R11, and a capacitor C11 (also referred to as a boost capacitor C11). In each first bootstrap circuit 71a, the anode of the diode D11 is connected to the positive terminal of the power supply unit 9a, and the cathode of the diode D11 is connected to a first end of the capacitor C11 via the resistor R11. The first end of the capacitor C11 is connected to a high-potential power supply terminal 61Ha (see FIG. 24 ) of the first gate driver 61a, and the second end of the capacitor C11 is connected to a low-potential power supply terminal 61La (see FIG. 24 ) of the first gate driver 61a. The first bootstrap circuit 71a supplies a voltage necessary to turn on the first switching element Q1a in the first gate driver 61a to the first gate driver 61a. Each of the first bootstrap circuits 71a further includes a Zener diode Z11 connected in parallel to the capacitor C11.

[0122] The second bootstrap circuits 72a correspond to the third gate drivers 63a and the fourth gate drivers 64a. Each second bootstrap circuit 72a supplies voltage to the corresponding third gate driver 63a and the corresponding fourth gate driver 64a. Each second bootstrap circuit 72a includes a diode D21, a resistor R21, and a capacitor C21 (also referred to as a boost capacitor C21). In each second bootstrap circuit 72a, the anode of the diode D21 is connected to the positive terminal of the power supply unit 9a, and the cathode of the diode D21 is connected to a first end of the capacitor C21 via the resistor R21. A first end of the capacitor C21 is connected to the high-potential power supply terminal 63Ha (see FIG. 24) of the third gate driver 63a and the high-potential power supply terminal 64Ha (see FIG. 24) of the fourth gate driver 64a, and a second end of the capacitor C21 is connected to the low-potential power supply terminal 63La (see FIG. 24) of the third gate driver 63a and the low-potential power supply terminal 64La (see FIG. 24) of the fourth gate driver 64a. The second bootstrap circuit 72a supplies the third gate driver 63a with a voltage required to turn on the third switching element Q3a in the third gate driver 63a, and supplies the fourth gate driver 64a with a voltage required to turn on the fourth switching element Q4a in the fourth gate driver 64a. Each of the second bootstrap circuits 72a further includes a Zener diode Z21 connected in parallel to the capacitor C21.

[0123] The power supply unit 9a supplies voltage to the multiple (three) first bootstrap circuits 71a, the multiple (three) second bootstrap circuits 72a, and the multiple (three) second gate drivers 62a. The power supply unit 9a is, for example, a DC power supply including an isolated DC-DC converter 91a. The positive terminal of the power supply unit 9a is connected to the high-potential power supply terminal 62Ha (see FIG. 24) of each of the multiple second gate drivers 62a, and the negative terminal of the power supply unit 9a is connected to the low-potential power supply terminal 62La (see FIG. 24) of each of the multiple second gate drivers 62a.

[0124] The control unit 60a controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a. Thus, the control unit 60a controls a plurality of first switching elements Q1a, a plurality of second switching elements Q2a, a plurality of third switching elements Q3a, and a plurality of fourth switching elements Q4a. The execution entity of the control unit 60a includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control unit 60a as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The electronic circuits may be integrated into one chip or may be distributed across multiple chips, and the chips may be integrated into one device or may be distributed across multiple devices.

[0125] The control unit 60a outputs a plurality of (three) first control signals S1a (see FIG. 23) for controlling a plurality of (three) first switching elements Q1a, a plurality of (three) second control signals S2a (see FIG. 23) for controlling a plurality of (three) second switching elements Q2a, a plurality of (three) third control signals S3a (see FIG. 23) for controlling a plurality of third switching elements Q3a, and a plurality of (three) fourth control signals S4a for controlling a plurality of (three) fourth switching elements Q4a. Note that FIG. 23 shows only one inverter circuit 1a of the three inverter circuits 1a, and does not show the remaining two inverter circuits 1a. 23 omits the illustration of the plurality of first gate drivers 61 a, the plurality of second gate drivers 62 a, the plurality of third gate drivers 63 a, the plurality of fourth gate drivers 64 a, the plurality of first bootstrap circuits 71 a, the plurality of second bootstrap circuits 72 a, and the power supply unit 9 a. Also, in Fig. 24 , only one of the three inverter circuits 1 a is shown, and the illustration of the remaining two inverter circuits 1 a is omitted. Also, in Fig. 24 , the illustration of the two first gate drivers 61 a, the two second gate drivers 62 a, the two third gate drivers 63 a, the two fourth gate drivers 64 a, the two first bootstrap circuits 71 a, and the two second bootstrap circuits 72 a is omitted.

[0126] The three first control signals S1a include a first control signal S1Ua that controls the first switching element Q1a of the inverter circuit 1Ua, a first control signal S1Va that controls the first switching element Q1a of the inverter circuit 1Va, and a first control signal S1Wa that controls the first switching element Q1a of the inverter circuit 1Wa.

[0127] The three second control signals S2a include a second control signal S2Ua that controls the second switching element Q2a of the inverter circuit 1Ua, a second control signal S2Va that controls the second switching element Q2a of the inverter circuit 1Va, and a second control signal S2Wa that controls the second switching element Q2a of the inverter circuit 1Wa.

[0128] The three third control signals S3a include a third control signal S3Ua that controls the third switching element Q3a of the inverter circuit 1Ua, a third control signal S3Va that controls the third switching element Q3a of the inverter circuit 1Va, and a third control signal S3Wa that controls the third switching element Q3a of the inverter circuit 1Wa.

[0129] The three fourth control signals S4a include a fourth control signal S4Ua that controls the fourth switching element Q4a of the inverter circuit 1Ua, a fourth control signal S4Va that controls the fourth switching element Q4a of the inverter circuit 1Va, and a fourth control signal S4Wa that controls the fourth switching element Q4a of the inverter circuit 1Wa.

[0130] Each of the plurality of first control signals S1a, the plurality of second control signals S2a, the plurality of third control signals S3a, and the plurality of fourth control signals S4a is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) higher than the first potential level. The first potential level is, for example, 0 V, and the second potential level is a potential level higher than the gate threshold voltage of the MOSFET. That is, in each of the plurality of control signals (the plurality of first control signals S1a, the plurality of second control signals S2a, the plurality of third control signals S3a, and the plurality of fourth control signals S4a), the first potential level is a potential level for turning off a switching element corresponding to that control signal, and the second potential level is a potential level for turning on a switching element corresponding to that control signal.

[0131] Each of the first switching elements Q1a is turned on when the corresponding first control signal S1a is at a high level and turned off when it is at a low level. Each of the second switching elements Q2a is turned on when the corresponding second control signal S2a is at a high level and turned off when it is at a low level. Each of the third switching elements Q3a is turned on when the corresponding third control signal S3a is at a high level and turned off when it is at a low level. Each of the fourth switching elements Q4a is turned on when the corresponding fourth control signal S4a is at a high level and turned off when it is at a low level.

[0132] In the multilevel inverter 100a, each of the multiple inverter circuits 1a is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100a, the switching state of each of the three inverter circuits 1Ua, 1Va, and 1Wa is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1a to Q4a. In each of the multiple inverter circuits 1a, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from one another. That is, in each of the multiple inverter circuits 1a, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1a to Q4a. Regarding the output voltages of the multiple inverter circuits 1a, the output voltage of the U-phase inverter circuit 1Ua, the output voltage of the V-phase inverter circuit 1Va, and the output voltage of the W-phase inverter circuit 1Wa are out of phase with each other.

[0133] The first switching state is a combination in which both the first switching element Q1 a and the third switching element Q3 a are in the ON state and both the second switching element Q2 a and the fourth switching element Q4 a are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 a can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 a, in the first switching state, the potential of the connection point 13 a becomes the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc / 2).

[0134] The second switching state is a combination in which both the first switching element Q1 a and the second switching element Q2 a are in the OFF state and both the third switching element Q3 a and the fourth switching element Q4 a are in the ON state. When controlled to the second switching state, each of the plurality of inverter circuits 1 a can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the plurality of inverter circuits 1 a, in the second switching state, the potential of the connection point 13 a becomes the potential level of the intermediate potential point M1 (e.g., 0).

[0135] The third switching state is a combination in which both the first switching element Q1a and the third switching element Q3a are in the OFF state and both the second switching element Q2a and the fourth switching element Q4a are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1a can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1a, in the third switching state, the potential of the connection point 13a becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., −Vdc / 2).

[0136] When the inverter circuit 1a is in the first switching state, as shown in FIG. 23, a current flows through the path from the positive electrode P1 of the DC power supply unit 3 to the first switching element Q1a, the connection point 13a, and the output terminal 41a (see FIG. 22), and the voltage value of the output voltage to the AC load RA1 (see FIG. 22) becomes Vdc / 2.

[0137] Furthermore, when the inverter circuit 1a is in the first switching state, the power supply unit 9a does not charge the capacitor C11 of the first bootstrap circuit 71a, and instead supplies the first gate driver 61a with the voltage required to turn on the first switching element Q1a via the first gate driver 61a from the capacitor C11 of the first bootstrap circuit 71a. Therefore, as shown in FIG. 24, the charge in the capacitor C11 of the first bootstrap circuit 71a is discharged via a discharge path Ru1a that connects the capacitor C11 to the high-potential power supply terminal 61Ha of the first gate driver 61a, the low-potential power supply terminal 61La of the first gate driver 61a, and the capacitor C11. As a result, the voltage across the capacitor C11 in the first bootstrap circuit 71a decreases over time.

[0138] Furthermore, when the inverter circuit 1a is in the first switching state, the power supply unit 9a does not charge the capacitor C21 of the second bootstrap circuit 72a, and instead supplies the third gate driver 63a with the voltage required to turn on the third switching element Q3a via the third gate driver 63a from the capacitor C21 of the second bootstrap circuit 72a. Therefore, as shown in FIG. 24, the charge in the capacitor C21 of the second bootstrap circuit 72a is discharged via a discharge path Ru3a that connects the capacitor C21 to the high-potential power supply terminal 63Ha of the third gate driver 63a, the low-potential power supply terminal 63La of the third gate driver 63a, and the capacitor C21. As a result, the voltage across the capacitor C21 in the second bootstrap circuit 72a decreases over time.

[0139] Furthermore, when the inverter circuit 1a is in the second switching state (when it changes from the first switching state to the second switching state), for example, as shown in Fig. 25, a current flows through a path of the intermediate potential point M1 of the DC power supply unit 3-the third switching element Q3a-the fourth switching element Q4a-the connection point 13a-the output terminal 41a (see Fig. 22), and the voltage value of the output voltage to the AC load RA1 (see Fig. 22) becomes 0. More specifically, when the inverter circuits 1Ua, 1Va, and 1Wa are in the second switching state, the third switching state, and the third switching state, respectively, a current flows through a path of the intermediate potential point M1 of the DC power supply unit 3-the third switching element Q3a of the inverter circuit 1Ua-the fourth switching element Q4a of the inverter circuit 1Ua-the connection point 13a-the output terminal 41Ua.

[0140] Furthermore, when the inverter circuit 1a is in the second switching state, the capacitor C21 of the second bootstrap circuit 72a supplies to the third gate driver 63a a voltage required to turn on the third switching element Q3a by the third gate driver 63a. Therefore, the charge in the capacitor C21 of the second bootstrap circuit 72a is discharged along a discharge path Ru3a that connects the capacitor C21 to the high-potential power supply terminal 63Ha of the third gate driver 63a, the low-potential power supply terminal 63La of the third gate driver 63a, and the capacitor C21, as shown in FIG. 26 . Furthermore, when the inverter circuit 1a is in the second switching state, the capacitor C21 of the second bootstrap circuit 72a supplies to the fourth gate driver 64a a voltage required to turn on the fourth switching element Q4a by the fourth gate driver 64a. Therefore, the charge in the capacitor C21 of the second bootstrap circuit 72a is discharged via a discharge path Ru4a from the capacitor C21 to the high potential power supply terminal 64Ha of the fourth gate driver 64a to the low potential power supply terminal 64La of the fourth gate driver 64a and back to the capacitor C21.

[0141] Furthermore, when the inverter circuit 1a is in the third switching state, as shown in FIG. 27, a current flows through the path from the output terminal 41a (see FIG. 22) to the node 13a, the second switching element Q2a, and the negative pole N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load RA1 (see FIG. 22) is −Vdc / 2. Furthermore, when the inverter circuit 1a is in the third switching state, the power supply unit 9a charges the capacitor C11 of the first bootstrap circuit 71a, and the voltage of the capacitor C11 increases over time until the capacitor C11 is fully charged. As shown in FIG. 28, the charging path Ru91 along which the power supply unit 9a charges the capacitor C11 is the path from the positive terminal of the power supply unit 9a to the diode D11, the resistor R11, the capacitor C11, the node 13a, the second switching element Q2a, and the negative terminal of the power supply unit 9a.

[0142] Furthermore, when the inverter circuit 1a is in the third switching state, the capacitor C21 of the second bootstrap circuit 72a is charged by the power supply unit 9a. As shown in Fig. 28, a charging path Ru92 along which the capacitor C21 is charged by the power supply unit 9a is a path from the positive terminal of the power supply unit 9a to the diode D21, the resistor R21, the capacitor C21, the fourth switching element Q4a, the connection point 13a, the second switching element Q2a, and the negative terminal of the power supply unit 9a.

[0143] Furthermore, when the inverter circuit 1a is in the second switching state (when it changes from the third switching state to the second switching state), for example, as shown in Fig. 29, a current flows through the path of the output terminal 41a (see Fig. 22)-connection point 13a-fourth switching element Q4a-third switching element Q3a-intermediate potential point M1, and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the inverter circuits 1Ua, 1Va, and 1Wa are in the second switching state, the second switching state, and the first switching state, respectively, a current flows through the path of the output terminal 41a of the inverter circuit 1Ua-connection point 13a-fourth switching element Q4a-third switching element Q3a-intermediate potential point M1, and the voltage value of the output voltage to the AC load RA1 becomes 0.

[0144] When the inverter circuit 1a is in the second switching state, discharge occurs through the discharge paths Ru3a and Ru4a shown in FIG.

[0145] The control unit 60a generates, for example, first to fourth control signals S1a to S4a (S1Ua to S4Ua) for the first to fourth switching elements Q1a to Q4a of the inverter circuit 1Ua, first to fourth control signals S1a to S4a (S1Va to S4Va) for the first to fourth switching elements Q1a to Q4a of the inverter circuit 1Va, and first to fourth control signals S1a to S4a (S1Wa to S4Wa) for the first to fourth switching elements Q1a to Q4a of the inverter circuit 1Wa based on voltage commands Vu, Vv, and Vw (see Figure 30) related to the output voltages of the inverter circuits 1Ua, 1Va, and 1Wa, respectively.

[0146] As shown in FIG. 30 , the voltage commands Vu, Vv, and Vw are sinusoidal signals whose phases are, for example, 120° apart, and whose values ​​(voltage command values) change over time. The voltage commands Vu, Vv, and Vw each have the same cycle length. The control unit 60a may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detector 8 (see FIG. 22 ) that detects the state of the AC load RA1. If the AC load RA1 is a three-phase motor, the information output from the detector 8 may include, for example, at least one of the following: information on the detection results of multiple current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1; and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase motor.

[0147] The operation of one of the three inverter circuits 1a (for example, the U-phase inverter circuit 1Ua) will be described below. The operations of the V-phase inverter circuit 1Va and the W-phase inverter circuit 1Wa are similar to that of the U-phase inverter circuit 1Ua. The output voltages of the U-phase inverter circuit 1Ua, the V-phase inverter circuit 1Va, and the W-phase inverter circuit 1Wa are out of phase with each other.

[0148] The control unit 60a controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a by performing voltage vector control.

[0149] The voltage vector control by the control unit 60a will be described in more detail below.

[0150] The control unit 60a stores in advance a first group of voltage vectors in a first vector space and a second group of voltage vectors in a second vector space different from the first vector space. Below, the first group of voltage vectors will be described with reference to Figures 30 to 34A, and then the second group of voltage vectors will be described with reference to Figure 34B.

[0151] Each of the voltage vectors in the first group is determined by a combination of the potential levels at the connection point 13a between the first switching element Q1a and the second switching element Q2a of the multiple inverter circuits 1a. In other words, the voltage vectors in the first group are determined by the switching state of the inverter circuit 1Ua corresponding to the U phase, the switching state of the inverter circuit 1Va corresponding to the V phase, and the switching state of the inverter circuit 1Wa corresponding to the W phase. The first vector space is a three-level voltage vector space as shown in FIG. 31, and includes 24 sectors, each of which is an equilateral triangle. The three-level voltage vector space shown in FIG. 31 is a vector diagram illustrating the voltage vectors in the first group on an orthogonal d-q coordinate system. The number of voltage vectors included in the voltage vectors in the first group is 3. ３ = 27 pieces.

[0152] As shown in Figure 31, the first group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. １／２ The first group includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which is 2 Vdc and points in different directions. The voltage vectors in the first group each have a magnitude of (2 / 3) １／２The first group of voltage vectors includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3) １／２ ・3 １／２ - Includes six voltage vectors V13, V14, V15, V16, V17, and V18 that are Vdc and have different directions. In Figure 31, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. Also, the angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees.

[0153] The first group of voltage vectors can be expressed as shown in Figures 32 to 34A by representing the first switching state, the second switching state, and the third switching state with the symbols "P," "0," and "N," respectively, and notating them in the order of U phase, V phase, and W phase.

[0154] As shown in FIG. 32 , the three zero vectors V0p, V0n, and V0o in the first group of voltage vectors can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that, with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1Ua is "P," the switching state of the V-phase inverter circuit 1Va is "P," and the switching state of the W-phase inverter circuit 1Wa is "P." For example, a voltage vector with a "p" appended, such as V10p, includes the switching state "P" but does not include the switching state "N." This applies hereinafter. Furthermore, a voltage vector with a "n" appended, such as V10n, includes the switching state "N" but does not include the switching state "P." This applies hereinafter. Furthermore, voltage vectors with "o" appended, such as V10o, include "0" as a switching state, but do not include "P" or "N" as a switching state. When the switching state of the inverter circuit 1a is "P", the potential of the connection point 13a in the inverter circuit 1a becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the inverter circuit 1a is "N", the potential of the connection point 13a in the inverter circuit 1a becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the inverter circuit 1a is "0", the potential of the connection point 13a in the inverter circuit 1a becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0155] Furthermore, the six voltage vectors V1, V2, V3, V4, V5, and V6 in the first group of voltage vectors can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors that do not have "p," "n," or "o" added after the number added to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases.

[0156] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n in the first group of voltage vectors can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.

[0157] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 in the first group of voltage vectors can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively.

[0158] The control unit 60a calculates the instantaneous value of the command voltage for each output voltage of the plurality of inverter circuits 1a as a command voltage vector V ＊ (See FIG. 33) The command voltage vector V ＊ The d-axis component of the orthogonal d-q coordinate system is Vd, and the command voltage vector V ＊ If the q-axis component on the orthogonal d-q coordinate system is Vq, then the command voltage vector V ＊ can be calculated using equation (4).

[0159]

[0160] The control unit 60a selects the command voltage vector V ＊ The first voltage vector VV1 is selected from the plurality of voltage vectors, and the magnitude of the first voltage vector VV1 is the reference magnitude and the magnitude of the command voltage vector VV2 is the reference magnitude. ＊ The reference magnitude is, for example, (2 / 3) １／２Therefore, the plurality of voltage vectors include 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0] as voltage vectors whose magnitude is a reference magnitude (reference vectors). ＊ The first voltage vector VV1 and the command voltage vector V ＊ The angle between the first voltage vector VV1 and the voltage vector V8p[PP0] is smaller than 30 degrees. In the example of FIG. 34A, the first voltage vector VV1 is the voltage vector V8p[PP0] and the voltage vector V8n[00N]. In the example of FIG. 34A, the second voltage vector VV2 is the voltage vector V7p[P00] and the voltage vector V7n[00NN]. In the example of FIG. 34A, the third voltage vector VV3 is the voltage vector V13[P0N].

[0161] Each of the voltage vectors in the second group is determined by a combination of the potential levels at the connection point 13a between the first switching element Q1a and the second switching element Q2a in the multiple inverter circuits 1a. In other words, the voltage vectors in the second group are determined by the switching state of the inverter circuit 1Ua corresponding to the U phase, the switching state of the inverter circuit 1Va corresponding to the V phase, and the switching state of the inverter circuit 1Wa corresponding to the W phase. The second vector space is a two-level vector space as shown in FIG. 34B , and each includes six equilateral triangular sectors. The number of voltage vectors included in the second group is nine.

[0162] 34B, the second group of voltage vectors includes three zero vectors V0p[PPP], V0n[NNN], and V0o

[000] , and six voltage vectors V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP]. The expressions of the second group of voltage vectors are similar to those of the first group of voltage vectors.

[0163] The control unit 60a converts the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 (see FIG. 34A) in the first vector space into the combination of the zero vector and the command voltage vector VV4 in the second vector space. ＊ The zero vectors at this time are a zero vector V0n[NNN] representing a combination where the potential level of the connection point 13a between the first switching element Q1a and the second switching element Q2a in the plurality of inverter circuits 1a is a negative potential, and a zero vector V0p[PPP] representing a combination where the potential level is a positive potential. ＊ The fourth voltage vector VV4 and the command voltage vector V ＊ The angle between them is less than 30 degrees.

[0164] The control unit 60a defines a resultant vector of the zero vectors V0n[NNN] and V0p[PPP], the fourth voltage vector VV4 (in the example of FIG. 34B, the voltage vector V2[PPN]), and the fifth voltage vector VV5 (in the example of FIG. 34B, the voltage vector V1[PNN]) as a command voltage vector V ＊ The control circuit controls the first gate drivers 61 a, the second gate drivers 62 a, the third gate drivers 63 a, and the fourth gate drivers 64 a within a predetermined control period Ts (see FIG. 37 ) so that the first gate drivers 61 a, the second gate drivers 62 a, the third gate drivers 63 a, and the fourth gate drivers 64 a coincide with each other. The predetermined control period Ts is, for example, one period of the carrier signal.

[0165] In a comparative example in which control is performed to change the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 in the first vector space to the combination of the zero vector, the fourth voltage vector VV4, and the fifth voltage vector VV5 in the second vector space, the command voltage vector VV1 in the first vector space within the control period Ts is ＊ The resultant vector of the vectors at the vertices of the equilateral triangle surrounding ＊That is, in the comparative example, the composite vector of the first voltage vector VV1 (in the example of FIG. 34A, the voltage vector V8p[PP0] and the voltage vector V8n[00N]), the second voltage vector VV2 (the voltage vector V7p[P00] and the voltage vector V7n[0NN]), and the third voltage vector VV3 (in the example of FIG. 34A, the voltage vector V13[P0N]) is set to the command voltage vector V ＊ In the comparative example, the control period Ts is one period of the carrier signal. In the comparative example, within half the control period Ts, for example, as shown in FIG. 35 , in two voltage vectors arranged in time series, the switching state of only one of the U phase, V phase, and W phase changes between “P” and “0” or between “0” and “N,” and the same voltage vector is output twice within the control period Ts. In FIG. 35 , the voltage vectors are output in the following order: voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. 35 illustrates an example in which the allocation time of the first voltage vector VV1 (voltage vector V8p[PP0] and voltage vector V8n[00N]) with respect to the control period Ts is T0, the allocation time of the third voltage vector VV3 (voltage vector V13[P0N]) is T1, and the allocation time of the second voltage vector VV2 (voltage vector V7p[P00]) is T2. ＊ The voltage vectors at the vertices of the equilateral triangle surrounding are Va, Vb, and Vc, and the command voltage vector V ＊ Letting the magnitude of and the angle be V and θ, respectively, T0, T1, and T2 are determined so as to satisfy equations (5) and (6). "j" in equation (5) is the imaginary unit. In the example of FIG. 35 , the voltage vector Va is the first voltage vector VV1 (voltage vectors V8p[PP0] and V8n[00N]), the voltage vector Vb is the third voltage vector VV3 (voltage vector V13[P0N]), and the voltage vector Vc is the second voltage vector VV2 (voltage vector V7p[P00]).

[0166]

[0167]

[0168] In the example of FIG. 35, for example, with respect to the first to fourth switching elements Q1a to Q4a of the inverter circuit 1Ua, as shown in FIG. 36, the third switching element Q3a is in the on state for the entire control period Ts, resulting in a large voltage drop across the capacitor C11 of the first bootstrap circuit 71a and the capacitor C21 of the second bootstrap circuit 72a.

[0169] In contrast to this, in the control unit 60a of the multilevel inverter 100a according to the second embodiment, within one period of the carrier signal, for example, as shown in FIG. 37, the signals are output in the order of zero vector V0n[NNN] → voltage vector V1[PNN] → voltage vector V2[PPN] → zero vector V0p[PPP] → zero vector V0p[PPP] → voltage vector V2[PPN] → voltage vector V1[PNN] → zero vector V0n[NNN].

[0170] 37 illustrates an example in which the allocation time of the zero vectors (zero vector V0n[NNN] and zero vector V0p[PPP]) for the control period Ts is T0, the allocation time of the fifth voltage vector VV5 (voltage vector V1[PNN]) is T1, and the allocation time of the fourth voltage vector VV4 (voltage vector V2[PPN]) is T2. ＊ The voltage vectors at the vertices of the equilateral triangle surrounding the vector V are Va, Vb, and Vc, and the command voltage vector V ＊ 37, the voltage vector Va is a zero vector (zero vector V0n[NNN] and zero vector V0p[PPP]), the voltage vector Vb is a fifth voltage vector VV5 (voltage vector V1[PNN]), and the voltage vector Vc is a fourth voltage vector VV4 (voltage vector V2[PPN]).

[0171] The control unit 60a changes the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 in the comparative example to a combination of a zero vector (zero vector V0n[NNN] and zero vector V0p[PPP]), a fourth voltage vector VV4 (in the example of FIG. 37, voltage vector V2[PPN]), and a fifth voltage vector VV5 (in the example of FIG. 37, voltage vector V1[PNN]), so that a period in which the switching state of the U phase is “N” can be generated as shown in FIG. 37. As a result, the multilevel inverter 100a according to the second embodiment can generate a third switching state in which both the first switching element Q1a and the third switching element Q3a are in the off state and both the second switching element Q2a and the fourth switching element Q4a are in the on state as shown in FIG. Therefore, the multilevel inverter 100a according to the second embodiment can suppress the voltage drop of the capacitor C11 of the first bootstrap circuit 71a and the capacitor C21 of the second bootstrap circuit 72a.

[0172] In the comparative example, the command voltage vector V ＊ 34A , the order of the voltage vectors during the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts. In the example of FIG. 39 , the voltage vectors are output in the following order: voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N] → voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0]. Similarly to the example of FIG. 35 , FIG. 39 illustrates a case in which the allocation time of the voltage vectors V8p and V8n is T0, the allocation time of the voltage vector V13 is T1, and the allocation time of the voltage vector V7p is T2. In this case, as shown in FIG. 40 , the third switching state does not occur throughout the entire control period Ts, resulting in a large voltage drop across the second bootstrap circuit 72a.

[0173] In contrast to this, in the control unit 60a of the multilevel inverter 100a according to the second embodiment, within one period of the carrier signal, for example, as shown in FIG. 41, the signals are output in the order of zero vector V0p[PPP] → voltage vector V2[PPN] → voltage vector V1[PNN] → zero vector V0n[NNN] → zero vector V0n[NNN] → voltage vector V1[PNN] → voltage vector V2[PPN] → zero vector V0p[PPP]. The control unit 60a changes the combination of the first voltage vector VV1 (voltage vector V8p[PP0] and voltage vector V8n[00N]), the second voltage vector VV2 (voltage vector V7p[P00]), and the third voltage vector VV3 (voltage vector V13[P0N]) in the example of FIG. 39 to a combination of a zero vector (zero vector V0n[NNN] and zero vector V0p[PPP]), the fourth voltage vector VV4 (voltage vector V2[PPN] in the example of FIG. 41), and the fifth voltage vector VV5 (voltage vector V1[PNN] in the example of FIG. 41). Therefore, a period in which the switching state of the U phase is “N” can be generated as shown in FIG. 20. As a result, the multilevel inverter 100a according to the second embodiment can generate the third switching state within the control period Ts as shown in FIG. 42. Therefore, the multilevel inverter 100a according to the second embodiment can suppress the voltage drop of the capacitor C11 of the first bootstrap circuit 71a and the capacitor C21 of the second bootstrap circuit 72a.

[0174] In the multilevel inverter 100a according to the second embodiment, the control unit 60a controls the command voltage vector V ＊ When the polarity of the command voltage corresponding to is negative, the combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 is not changed to the combination of the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector VV4, and the fifth voltage vector VV5.

[0175] Furthermore, in the multilevel inverter 100a, the control unit 60a controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a so that the output voltages of the plurality of first bootstrap circuits 71a and the plurality of second bootstrap circuits 72a do not fall below a predetermined value.

[0176] (3) Summary In the multilevel inverter 100a according to the second embodiment, the control unit 60a controls the command voltage vector V ＊ Each of the first group of voltage vectors is determined in a first vector space by a combination of the potential levels of a plurality of connection points 13a in a plurality of inverter circuits 1a. The control unit 60a calculates the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 by combining the zero vectors V0n[NNN] and V0p[PPP] and the command voltage vector V ＊ The control unit 60a changes the voltage vectors in the second group to a combination of the fourth voltage vector VV4 and the fifth voltage vector VV5 adjacent to the fourth voltage vector VV4. Each of the voltage vectors in the second group is determined by a combination of the potential levels of the multiple connection points 13a in the multiple inverter circuits 1a. The zero vectors V0n[NNN] and V0p[PPP] are the voltage vectors in the second group that are a combination of negative and positive potentials of the multiple connection points 13a in the multiple inverter circuits 1a. The control unit 60a converts the composite vector of the zero vectors V0n[NNN] and V0p[PPP], the fourth voltage vector VV4, and the fifth voltage vector VV5 in the second vector space into the command voltage vector V ＊ The control circuit controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a within a predetermined control period Ts so that the first gate drivers 61a, the second gate drivers 62a, the third gate drivers 63a, and the fourth gate drivers 64a coincide with each other.

[0177] The multilevel inverter 100a according to the second embodiment can suppress a voltage drop in the bootstrap circuit. More specifically, the multilevel inverter 100a according to the second embodiment can suppress a voltage drop in the capacitor C11 of the plurality of first bootstrap circuits 71a and the capacitor C21 of the plurality of second bootstrap circuits 72a.

[0178] In the multilevel inverter 100a according to the second embodiment, a DC-DC converter 91a included in the power supply unit 9a supplies voltage to the second gate drivers 62a, the first bootstrap circuits 71a, and the second bootstrap circuits 72a. This allows the multilevel inverter 100a according to the second embodiment to be miniaturized.

[0179] A multilevel inverter 100A according to a third embodiment will be described with reference to Fig. 43. Regarding the multilevel inverter 100A, components similar to those of the multilevel inverter 100a according to the second embodiment (see Fig. 22) are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0180] The multilevel inverter 100A differs from the multilevel inverter 100a in that the power supply unit 9a includes a plurality of (three) DC-DC converters 91a.

[0181] In the multilevel inverter 100A, the multiple DC-DC converters 91a correspond to the multiple (three) fourth gate drivers 64a and supply voltages to the corresponding fourth gate drivers 64a. Also, in the multilevel inverter 100A, the multiple DC-DC converters 91a correspond to the multiple first bootstrap circuits 71a and are connected to the corresponding first bootstrap circuits 71a. More specifically, the positive terminal of each of the multiple DC-DC converters 91a is connected to the anode of the diode D11 in the corresponding first bootstrap circuit 71a, and the negative terminal is connected to the negative electrode N1 of the DC power supply unit 3.

[0182] In the multilevel inverter 100A, the control unit 60a controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a by performing voltage vector control similar to that of the control unit 60a of the multilevel inverter 100a.

[0183] Therefore, similar to the multilevel inverter 100a, the multilevel inverter 100A according to the third embodiment can suppress voltage drops in the capacitors C11 of the plurality of first bootstrap circuits 71a and the capacitors C21 of the plurality of second bootstrap circuits 72a.

[0184] A multilevel inverter 100B according to a fourth embodiment will be described with reference to Fig. 44. Regarding the multilevel inverter 100B, components similar to those of the multilevel inverter 100a according to the second embodiment (see Fig. 22) are denoted by the same reference numerals, and description thereof will be omitted.

[0185] In the multilevel inverter 100B, the bidirectional switch including the third switching element Q3a and the fourth switching element Q4a is a common-drain bidirectional switch in which the first main terminals (source terminals) of the third switching element Q3a and the fourth switching element Q4a are connected to each other. In the bidirectional switch of the multilevel inverter 100B, the second main terminal of the fourth switching element Q4a is connected to the intermediate potential point M1, and the third switching element Q3a is connected to the connection point 13a.

[0186] Furthermore, in the multilevel inverter 100B, the power supply unit 9a has a DC-DC converter 91a (hereinafter also referred to as a first DC-DC converter 91a) and a plurality (three) of second DC-DC converters 92. Note that in Fig. 44, each of the plurality of second DC-DC converters 92 is illustrated with the symbol for a DC power supply.

[0187] The first DC-DC converter 91a supplies voltage to the plurality of second gate drivers 62a, the plurality of first bootstrap circuits 71a, and the plurality of second bootstrap circuits 72a.

[0188] The second DC-DC converters 92 correspond one-to-one to the fourth gate drivers 64a and supply voltages to the corresponding fourth gate drivers 64a. The positive terminal of each second DC-DC converter 92 is connected to the high-potential power supply terminal of the fourth gate driver 64a, and the negative terminal is connected to the intermediate potential point M1, the low-potential power supply terminal of the fourth gate driver 64a, and the second main terminal of the fourth switching element Q4a.

[0189] In the multilevel inverter 100B, the control unit 60a controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a by performing voltage vector control similar to that of the control unit 60a of the multilevel inverter 100a.

[0190] Therefore, similar to the multilevel inverter 100a, the multilevel inverter 100B according to the fourth embodiment can suppress voltage drops in the capacitors C11 of the plurality of first bootstrap circuits 71a and the capacitors C21 of the plurality of second bootstrap circuits 72a.

[0191] Fifth Embodiment A multilevel inverter 100C according to a fifth embodiment will be described with reference to Fig. 45. Regarding the multilevel inverter 100C, components similar to those of the multilevel inverter 100a according to the second embodiment (see Fig. 22) are denoted by the same reference numerals, and description thereof will be omitted.

[0192] The multilevel inverter 100C does not include the multiple second bootstrap circuits 72a in the multilevel inverter 100a, and the power supply unit 9a has a DC-DC converter 91a (hereinafter also referred to as the first DC-DC converter 91a) and multiple (three) second DC-DC converters 92. Note that in Fig. 45, each of the multiple second DC-DC converters 92 is illustrated with the symbol for a DC power supply.

[0193] The first DC-DC converter 91a supplies voltage to the plurality of second gate drivers 62a, the plurality of first bootstrap circuits 71a, and the plurality of second bootstrap circuits 72a.

[0194] The second DC-DC converters 92 correspond to the third gate drivers 63a and the fourth gate drivers 64a, and supply voltages to the corresponding third gate drivers 63a and the corresponding fourth gate drivers 64a. The positive terminal of each of the second DC-DC converters 92 is connected to the high-potential power supply terminal of the corresponding third gate driver 63a and the high-potential power supply terminal of the corresponding fourth gate driver 64a. The negative terminal of each of the second DC-DC converters 92 is connected to the low-potential power supply terminal of the corresponding third gate driver 63a and the low-potential power supply terminal of the corresponding fourth gate driver 64a.

[0195] In the multilevel inverter 100C, the control unit 60a controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a by performing voltage vector control similar to that of the control unit 60a of the multilevel inverter 100a.

[0196] Therefore, the multilevel inverter 100C according to the fifth embodiment can suppress a voltage drop across the capacitor C11 of each of the first bootstrap circuits 71a.

[0197] Sixth Embodiment A multilevel inverter 100D according to a sixth embodiment will be described with reference to Fig. 46. Regarding the multilevel inverter 100D, components similar to those of the multilevel inverter 100C according to the fifth embodiment (see Fig. 45) are denoted by the same reference numerals, and description thereof will be omitted.

[0198] In the multilevel inverter 100D, the first DC-DC converter 91a is not connected to the plurality of first bootstrap circuits 71a, and the positive terminal of the second DC-DC converter 92 is connected to the anode of the diode D17 of the first bootstrap circuit 71a.

[0199] In the multilevel inverter 100D, the control unit 60 controls a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a by performing voltage vector control similar to that of the control unit 60a of the multilevel inverter 100a according to the second embodiment.

[0200] Therefore, the multilevel inverter 100D according to the sixth embodiment can suppress a voltage drop across the capacitor C11 of each of the first bootstrap circuits 71a.

[0201] (Modifications) The above-described second to sixth embodiments are merely examples of various embodiments of the present disclosure. The above-described second to sixth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0202] For example, each of the first switching elements Q1 a, the second switching elements Q2 a, the third switching elements Q3 a, and the fourth switching elements Q4 a is not limited to a MOSFET and may be, for example, an IGBT (Insulated Gate Bipolar Transistor). In this case, the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1 a, the second switching elements Q2 a, the third switching elements Q3 a, and the fourth switching elements Q4 a are a gate terminal, a collector terminal, and an emitter terminal, respectively.

[0203] In the multilevel inverters 100a, 100A to 100D according to the second, third to sixth embodiments, the control unit 60a controls the command voltage vector V ＊ The combination of the first voltage vector VV1, the second voltage vector VV2, and the third voltage vector VV3 in the first vector space may be changed to the combination of the zero vector, the fourth voltage vector VV4, and the fifth voltage vector VV5 in the second vector space, not only when the polarity of the command voltage corresponding to VV1 is positive, but also when the polarity is negative.

[0204] Each of the first bootstrap circuits 71a includes a Zener diode Z11, but may not include the Zener diode Z11. Each of the second bootstrap circuits 72a includes a Zener diode Z21, but may not include the Zener diode Z21.

[0205] Furthermore, the multilevel inverters 100a, 100A to 100D may be any multilevel inverter having three or more levels, and may be, for example, a five-level inverter.

[0206] (Aspects) The following aspects are disclosed in this specification.

[0207] A multilevel inverter (100) according to a first aspect includes a DC power supply unit (3), a plurality of inverter circuits (1), and a control device (6). The DC power supply unit (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of inverter circuits (1) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The control device (6) controls the plurality of inverter circuits (1). Each of the plurality of inverter circuits (1) includes a switching circuit (10), a first diode (D1), a second diode (D2), a third diode (D3), a fourth diode (D4), a fifth diode (D5), and a sixth diode (D6). In the switching circuit (10), a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series from the positive electrode (P1) side to the negative electrode (N1) side in the order of the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4). The first diode (D1) is connected in anti-parallel to the first switching element (Q1). The second diode (D2) is connected in anti-parallel to the second switching element (Q2). The third diode (D3) is connected in anti-parallel to the third switching element (Q3). The fourth diode (D4) is connected in anti-parallel to the fourth switching element (Q4). The fifth diode (D5) has a cathode connected to a first connection point (11) between the first switching element (Q1) and the second switching element (Q2), and an anode connected to an intermediate potential point (M1). The sixth diode (D6) has an anode connected to the second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4), and a cathode connected to the intermediate potential point (M1). The control device (6) has a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64), a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a power supply unit (9), and a control unit (60).The plurality of first gate drivers (61) drive the first switching elements (Q1) of the plurality of inverter circuits (1). The plurality of second gate drivers (62) drive the second switching elements (Q2) of the plurality of inverter circuits (1). The plurality of third gate drivers (63) drive the third switching elements (Q3) of the plurality of inverter circuits (1). The plurality of fourth gate drivers (64) drive the fourth switching elements (Q4) of the plurality of inverter circuits (1). The plurality of first bootstrap circuits (71) correspond one-to-one to the plurality of first gate drivers (61). Each of the plurality of first bootstrap circuits (71) supplies a voltage to a corresponding first gate driver (61). The plurality of second bootstrap circuits (72) correspond one-to-one to the plurality of second gate drivers (62). Each of the plurality of second bootstrap circuits (72) supplies a voltage to a corresponding second gate driver (62). The plurality of third bootstrap circuits (73) correspond one-to-one to the plurality of third gate drivers (63). Each of the plurality of third bootstrap circuits (73) supplies a voltage to the corresponding third gate driver (63). The power supply unit (9) supplies a voltage to the plurality of fourth gate drivers (64). The control unit (60) controls the plurality of first gate drivers (61), the plurality of second gate drivers (62), the plurality of third gate drivers (63), and the plurality of fourth gate drivers (64). The control unit (60) controls a command voltage vector (V) from among the first group of voltage vectors. ＊ ), and selects a first voltage vector (VV1), a second voltage vector (VV2), and a third voltage vector (VV3) adjacent to the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3). Each of the first group of voltage vectors is determined in a first vector space by a combination of potential levels at a third connection point (13) between the second switching element (Q2) and the third switching element (Q3) of the plurality of inverter circuits (1). The control unit (60) calculates the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3) in a second vector space different from the first vector space by combining the zero vectors (V0n[NNN], V0p[PPP]) and the command voltage vector (V ＊) to a combination of a fourth voltage vector (VV4) and a fifth voltage vector (VV5) adjacent to the second voltage vector (VV6). Each of the second group of voltage vectors is determined by a combination of potential levels at a third connection point (13) between the second switching element (Q2) and the third switching element (Q3) of the plurality of inverter circuits (1). The zero vectors (V0n[NNN], V0p[PPP]) are, among the voltage vectors of the second group, a voltage vector of a combination where the potential level at the third connection point (13) between the second switching element (Q2) and the third switching element (Q3) of the plurality of inverter circuits (1) is a negative potential and a voltage vector of a combination where the potential level is a positive potential. The control unit (60) converts a composite vector of the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector (VV4), and the fifth voltage vector (VV5) in the second vector space into a command voltage vector (V ＊ A plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64) are controlled within a predetermined control period (Ts) so as to match the gate voltage Vcc of the first gate driver (61), the second gate driver (62), the third gate driver (63), and the fourth gate driver (64).

[0208] According to this aspect, it is possible to suppress voltage drops in the bootstrap circuits. More specifically, according to this aspect, it is possible to suppress voltage drops in the capacitors (C17) of the plurality of first bootstrap circuits (71), the capacitors (C27) of the plurality of second bootstrap circuits (72), and the capacitors (C37) of the plurality of third bootstrap circuits (73).

[0209] In the multilevel inverter (100) according to the second aspect, in the first aspect, the control unit (60) calculates a command voltage vector (V ＊ When the polarity of the command voltage corresponding to V0n[NNN], V0p[PPP] is positive, the combination of the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3) is changed to a combination of the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector (VV4), and the fifth voltage vector (VV5).

[0210] According to this aspect, the number of times that the combination of the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3) is changed to the combination of the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector (VV4), and the fifth voltage vector (VV5) can be reduced.

[0211] In the multilevel inverter (100) according to the third aspect, in the first or second aspect, the control unit (60) controls the plurality of first gate drivers (61), the plurality of second gate drivers (62), the plurality of third gate drivers (63), and the plurality of fourth gate drivers (64) so ​​that the output voltages of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) do not fall below a predetermined value.

[0212] According to this aspect, it is possible to prevent the output voltages of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) from falling below a predetermined value.

[0213] In a multilevel inverter (100) according to a fourth aspect, in any one of the first to third aspects, each of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) includes capacitors (C17, C27), diodes (D17, D27), and resistors (R17, R27). The diodes (D17, D27) are connected in series with the capacitors (C17, C27). The resistors (R17, R27) are connected in series with the capacitors (C17, C27).

[0214] In a multilevel inverter (100) according to a fifth aspect, in any one of the first to fourth aspects, the power supply unit (9) includes a DC-DC converter (91). The DC-DC converter (91) supplies voltage to a plurality of fourth gate drivers (64) and a plurality of third bootstrap circuits (73).

[0215] According to this aspect, it is possible to reduce the size of the multilevel inverter (100).

[0216] A multilevel inverter (100a; 100A; 100B; 100C; 100D) according to a sixth aspect includes a DC power supply unit (3), a plurality of inverter circuits (1a), and a control device (6a). The DC power supply unit (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1). The plurality of inverter circuits (1a) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply unit (3). The control device (6a) controls the plurality of inverter circuits (1a). Each of the plurality of inverter circuits (1a) includes a first switching element (Q1a), a second switching element (Q2a), a third switching element (Q3a), and a fourth switching element (Q4a), as well as a first diode (D1a), a second diode (D2a), a third diode (D3a), and a fourth diode (D4a). The first diode (D1a), the second diode (D2a), the third diode (D3a), and the fourth diode (D4a) are connected in anti-parallel to the first switching element (Q1a), the second switching element (Q2a), the third switching element (Q3a), and the fourth switching element (Q4a), respectively. In each of the multiple inverter circuits (1a), the first switching element (Q1a) and the second switching element (Q2a) are connected in series from the positive electrode (P1) side to the negative electrode (N1) side, in that order, the first switching element (Q1a) and the second switching element (Q2a). In each of the multiple inverter circuits (1a), a series circuit of the third switching element (Q3a) and the fourth switching element (Q4a) is connected between the intermediate potential point (M1) and the output point. The output point is the connection point (13a) between the first switching element (Q1a) and the second switching element (Q2a). The control device (6a) has a plurality of first gate drivers (61a), a plurality of second gate drivers (62), a plurality of third gate drivers (63), a plurality of fourth gate drivers (64a), a plurality of bootstrap circuits (71a), a power supply unit (9a), and a control unit (60a). The plurality of first gate drivers (61a) drive the first switching elements (Q1a) of the plurality of inverter circuits (1a). The plurality of second gate drivers (62a) drive the second switching elements (Q2a) of the plurality of inverter circuits (1a).The plurality of third gate drivers (63a) drive the third switching elements (Q3a) of the plurality of inverter circuits (1a). The plurality of fourth gate drivers (64a) drive the fourth switching elements (Q4a) of the plurality of inverter circuits (1a). The plurality of bootstrap circuits (71a) correspond one-to-one to the plurality of first gate drivers (61a) and supply voltages to the corresponding first gate drivers (61a). The power supply unit (9a) supplies voltages to the plurality of second gate drivers (62a) and the plurality of third gate drivers (63a). The control unit (60a) controls the plurality of first gate drivers (61a), the plurality of second gate drivers (62a), the plurality of third gate drivers (63a), and the plurality of fourth gate drivers (64a). The control unit (60a) controls a command voltage vector (V) of the first group of voltage vectors. ＊ ), and selects a first voltage vector (VV1), a second voltage vector (VV2), and a third voltage vector (VV3) adjacent to the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3). Each of the first group of voltage vectors is determined in a first vector space by a combination of potential levels of a plurality of connection points (13a) in a plurality of inverter circuits (1a). The control unit (60a) calculates the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3) in a second vector space different from the first vector space by combining the zero vectors (V0n[NNN], V0p[PPP]) and the command voltage vector (V ＊ The control unit (60a) changes the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector (VV4), and the fifth voltage vector (VV5) adjacent to the zero vector (V0n[NNN], V0p[PPP]), into a combination of a fourth voltage vector (VV4) and a fifth voltage vector (VV5) adjacent to the zero vector (V0n[NNN], V0p[PPP]). Each of the second group of voltage vectors is a voltage vector of a combination where the potential levels of the plurality of connection points (13a) in the plurality of inverter circuits (1a) become negative potential and a voltage vector of a combination where the potential levels of the plurality of connection points (13a) become positive potential. The control unit (60a) changes the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector (VV4), and the fifth voltage vector (VV5) in the second vector space into a command voltage vector (V ＊The control circuit controls a plurality of first gate drivers (61 a), a plurality of second gate drivers (62 a), a plurality of third gate drivers (63 a), and a plurality of fourth gate drivers (64 a) within a predetermined control period (Ts) so as to match the gate voltage Vcc of the first gate driver (61 a), the second gate driver (62 a), the third gate driver (63 a), and the fourth gate driver (64 a).

[0217] According to this aspect, it is possible to suppress a voltage drop in the bootstrap circuit (71 a). More specifically, according to this aspect, it is possible to suppress a voltage drop in the capacitor (C11) of the plurality of bootstrap circuits (71 a).

[0218] In the multilevel inverter (100a; 100A; 100B; 100C; 100D) according to the seventh aspect, in the sixth aspect, the control unit (60a) ＊ When the polarity of the command voltage corresponding to V0n[NNN], V0p[PPP] is positive, the combination of the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3) is changed to a combination of the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector (VV4), and the fifth voltage vector (VV5).

[0219] According to this aspect, the number of times that the combination of the first voltage vector (VV1), the second voltage vector (VV2), and the third voltage vector (VV3) is changed to the combination of the zero vector (V0n[NNN], V0p[PPP]), the fourth voltage vector (VV4), and the fifth voltage vector (VV5) can be reduced.

[0220] In a multilevel inverter (100a; 100A; 100B; 100C; 100D) according to an eighth aspect, in the sixth or seventh aspect, the control unit (60a) controls the plurality of first gate drivers (61a), the plurality of second gate drivers (62a), the plurality of third gate drivers (63a), and the plurality of fourth gate drivers (64a) so that the output voltage of each of the plurality of bootstrap circuits (71a) does not drop below a predetermined value.

[0221] According to this aspect, it is possible to prevent the output voltage of each of the plurality of bootstrap circuits (71a) from falling below a predetermined value.

[0222] A multilevel inverter (100a; 100A; 100B; 100C; 100D) according to a ninth aspect is any one of the sixth to eighth aspects, wherein each of the plurality of bootstrap circuits (71a) includes a capacitor (C11), a diode (D11), and a resistor (R11). The diode (D11) is connected in series with the capacitor (C11). The resistor (R11) is connected in series with the capacitor (C11).

[0223] In a multilevel inverter (100a; 100B; 100C; 100D) according to a tenth aspect, in any one of the sixth to ninth aspects, the power supply unit (9a) includes a DC-DC converter (91a). The DC-DC converter (91a) supplies voltage to the plurality of second gate drivers (62a) and the plurality of bootstrap circuits (71a).

[0224] According to this aspect, it is possible to reduce the size of the multilevel inverter (100a; 100B; 100C; 100D).

[0225] In a multilevel inverter (100a; 100B; 100C; 100D) according to an eleventh aspect, in any one of the sixth to ninth aspects, the power supply unit (9a) includes one first DC-DC converter (91a) and a plurality of second DC-DC converters (92). The first DC-DC converter (91a) supplies voltage to a plurality of second gate drivers (62a) and a plurality of bootstrap circuits (71a). The plurality of second DC-DC converters (92) supply voltage to a plurality of fourth gate drivers (64a).

[0226] According to this aspect, it is possible to reduce the size of the multilevel inverter (100a; 100B; 100C; 100D).

[0227] REFERENCE SIGNS LIST 1 inverter circuit 3 DC power supply unit 6 control device 60 control unit 61 first gate driver 62 second gate driver 63 third gate driver 64 fourth gate driver 9 power supply unit 91 DC-DC converter 10 switching circuit 11 first connection point 12 second connection point 13 third connection point 71 first bootstrap circuit 72 second bootstrap circuit 73 third bootstrap circuit 100 multilevel inverter C17, C27, C37 capacitor D1 first diode D2 second diode D3 third diode D4 fourth diode D5 fifth diode D6 sixth diode D17, D27, D37 diode P1 positive pole Q1 first switching element Q2 second switching element Q3 third switching element Q4 fourth switching element M1 intermediate potential point N1 negative pole R17, R27, R37 resistor Ts Control period V0 to V18 Voltage vector V ＊ Command voltage vector VV1 First voltage vector VV2 Second voltage vector VV3 Third voltage vector VV4 Fourth voltage vector VV5 Fifth voltage vector 1a Inverter circuit 6a Control device 60a Control unit 61a First gate driver 62a Second gate driver 63a Third gate driver 64a Fourth gate driver 9a Power supply unit 91a DC-DC converter (first DC-DC converter) 92 Second DC-DC converter 11a First circuit 12a Second circuit 13a Connection point (output point) 71a Bootstrap circuit (first bootstrap circuit) 72a Second bootstrap circuit 100a, 100A, 100B, 100C, 100D Multilevel inverters C11, C21 Capacitors D1a First diode D2a Second diode D3a Third diode D4a Fourth diode D11, D21 Diode Q1a First switching element Q2a Second switching element Q3a Third switching element Q4a Fourth switching element R11, R21 Resistor Ts Control period

Claims

1. A DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point; A plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; A control device that controls the plurality of inverter circuits, Each of the plurality of inverter circuits is a switching circuit in which a first switching element, a second switching element, a third switching element, and a fourth switching element are connected in series to be arranged in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element from the positive electrode side to the negative electrode side; a first diode connected in anti-parallel to the first switching element; a second diode connected in anti-parallel to the second switching element; a third diode connected in anti-parallel to the third switching element; a fourth diode connected in anti-parallel to the fourth switching element; a fifth diode having a cathode connected to a first connection point between the first switching element and the second switching element and an anode connected to the intermediate potential point; a sixth diode having an anode connected to a second connection point between the third switching element and the fourth switching element and a cathode connected to the intermediate potential point, The control device includes: a plurality of first gate drivers each driving the first switching element of each of the plurality of inverter circuits; a plurality of second gate drivers each driving the second switching element of each of the plurality of inverter circuits; a plurality of third gate drivers each driving the third switching element of each of the plurality of inverter circuits; a plurality of fourth gate drivers each driving the fourth switching element of each of the plurality of inverter circuits; a plurality of first bootstrap circuits each corresponding to one of the first gate drivers and supplying a voltage to the corresponding first gate driver; a plurality of second bootstrap circuits each corresponding to one of the second gate drivers and supplying a voltage to the corresponding second gate driver; a plurality of third bootstrap circuits each corresponding to the third gate drivers and supplying a voltage to the corresponding third gate drivers; a power supply unit for supplying a voltage to the plurality of fourth gate drivers; a control unit that controls the first gate drivers, the second gate drivers, the third gate drivers, and the fourth gate drivers, The control unit is selecting a first voltage vector, a second voltage vector, and a third voltage vector adjacent to a command voltage vector from a first group of voltage vectors, each of which is determined by a combination of potential levels of a third connection point between the second switching element and the third switching element of the plurality of inverter circuits, in a first vector space; changing the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector and a fourth voltage vector and a fifth voltage vector adjacent to the command voltage vector, among a second group of voltage vectors each determined by a combination of potential levels of a third connection point between the second switching element and the third switching element of the plurality of inverter circuits, in a second vector space different from the first vector space; the zero vector is a voltage vector of a combination of voltage vectors of the second group in which a potential level of the third connection point between the second switching elements and the third switching elements of the plurality of inverter circuits becomes the negative potential and a voltage vector of a combination of voltage vectors in which a potential level of the third connection point between the second switching elements and the third switching elements of the plurality of inverter circuits becomes the positive potential, The control unit is controlling the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so as to make a composite vector of the zero vector, the fourth voltage vector, and the fifth voltage vector in a second vector space coincide with the command voltage vector; Multilevel inverter.

2. the control unit, when a polarity of a command voltage corresponding to the command voltage vector is positive, changes a combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of the zero vector, the fourth voltage vector, and the fifth voltage vector.

2. The multilevel inverter according to claim 1.

3. The control unit is controlling the first gate drivers, the second gate drivers, the third gate drivers, and the fourth gate drivers so that output voltages of the first bootstrap circuits and the second bootstrap circuits do not fall below a predetermined value; The multilevel inverter according to claim 1 or 2.

4. Each of the first bootstrap circuits and the second bootstrap circuits comprises: A capacitor; a diode connected in series with the capacitor; a resistor connected in series with the capacitor; The multilevel inverter according to claim 1 or 2.

5. The power supply unit includes: a DC-DC converter that supplies a voltage to the fourth gate drivers and the third bootstrap circuits; The multilevel inverter according to claim 1 or 2.

6. A DC power supply unit having a positive electrode, a negative electrode, and an intermediate potential point; A plurality of inverter circuits connected between the positive electrode and the negative electrode of the DC power supply unit; A control device that controls the plurality of inverter circuits, Each of the plurality of inverter circuits is a first switching element, a second switching element, a third switching element and a fourth switching element; a first diode, a second diode, a third diode, and a fourth diode, which are connected in anti-parallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively; In each of the plurality of inverter circuits, the first switching element and the second switching element are connected in series to be arranged in the order of the first switching element and the second switching element from the positive electrode side to the negative electrode side, a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and an output point, the output point is a connection point between the first switching element and the second switching element, The control device includes: a plurality of first gate drivers each driving the first switching element of each of the plurality of inverter circuits; a plurality of second gate drivers each driving the second switching element of each of the plurality of inverter circuits; a plurality of third gate drivers each driving the third switching element of each of the plurality of inverter circuits; a plurality of fourth gate drivers each driving the fourth switching element of each of the plurality of inverter circuits; a plurality of bootstrap circuits each corresponding to one of the first gate drivers and supplying a voltage to the corresponding first gate driver; a power supply unit that supplies a voltage to the second gate drivers and the third gate drivers; a control unit that controls the first gate drivers, the second gate drivers, the third gate drivers, and the fourth gate drivers, The control unit is selecting a first voltage vector, a second voltage vector, and a third voltage vector adjacent to a command voltage vector from a first group of voltage vectors, each of which is determined by a combination of potential levels of a plurality of the connection points in the plurality of inverter circuits, in a first vector space; changing the first voltage vector, the second voltage vector, and the third voltage vector to a combination of a zero vector and a fourth voltage vector and a fifth voltage vector adjacent to the command voltage vector, among a second group of voltage vectors each determined by a combination of potential levels of the plurality of connection points in the plurality of inverter circuits, in a second vector space different from the first vector space; the zero vector is a voltage vector of a combination of potential levels of the plurality of connection points in the plurality of inverter circuits that is a potential of the negative electrode and a voltage vector of a combination of potential levels of the plurality of connection points in the plurality of inverter circuits that is a potential of the positive electrode, among the voltage vectors of the second group; The control unit is controlling the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so as to make a composite vector of the zero vector, the fourth voltage vector, and the fifth voltage vector in a second vector space coincide with the command voltage vector; Multilevel inverter.

7. the control unit, when a polarity of a command voltage corresponding to the command voltage vector is positive, changes a combination of the first voltage vector, the second voltage vector, and the third voltage vector to a combination of the zero vector, the fourth voltage vector, and the fifth voltage vector.

7. The multilevel inverter according to claim 6.

8. The control unit is controlling the first gate drivers, the second gate drivers, the third gate drivers, and the fourth gate drivers so that an output voltage of each of the bootstrap circuits does not fall below a predetermined value; The multilevel inverter according to claim 6 or 7.

9. Each of the plurality of bootstrap circuits comprises: A capacitor; a diode connected in series with the capacitor; a resistor connected in series with the capacitor; The multilevel inverter according to claim 6 or 7.

10. The power supply unit includes: a DC-DC converter that supplies a voltage to the second gate drivers and the bootstrap circuits; The multilevel inverter according to claim 6 or 7.

11. The power supply unit includes: a first DC-DC converter that supplies a voltage to the second gate drivers and the bootstrap circuits; a plurality of second DC-DC converters supplying voltages to the plurality of fourth gate drivers; The multilevel inverter according to claim 6 or 7.