Semiconductor device, electronic apparatus, and vehicle

Abstract

A semiconductor device 1 comprises: an output switch 9; an overcurrent protection circuit 34 that detects an output current IOUT flowing to the output switch 9 and applies overcurrent protection; an overheat protection circuit 36 that detects a temperature to be monitored and applies overheat protection; and a mode control circuit 53 that switches between setting each of the overcurrent protection circuit 34 and the overheat protection circuit 36 to a normal mode or to a capacitive load drive mode. In the capacitive load drive mode, the overcurrent protection circuit 34 limits the output current IOUT to an overcurrent protection threshold value or less. The overheat protection circuit 36 repeats forcibly turning off and restarting the output switch 9 each time the temperature to be monitored rises to a second overheat protection threshold value, which is lower than a first overheat protection threshold value set in the normal mode.

Description

Semiconductor devices, electronic devices, vehicles

[0001] The invention disclosed in this specification relates to a semiconductor device, an electronic device, and a vehicle.

[0002] The applicant of the present application has proposed many new technologies relating to semiconductor devices such as in-vehicle intelligent power devices (IPDs) (see, for example, Patent Document 1).

[0003] International Publication No. 2017 / 187785

[0004] However, in the conventional semiconductor device, there is room for further study on the method of driving the capacitive load (combined with the abnormality protection function).

[0005] For example, a semiconductor device disclosed in this specification includes an output switch, an overcurrent protection circuit configured to detect an output current flowing through the output switch and apply overcurrent protection, an overheat protection circuit configured to detect a monitored temperature and apply overheat protection, and a mode control circuit configured to switch between setting each of the overcurrent protection circuit and the overheat protection circuit in a normal mode or a capacitive load drive mode, wherein in the capacitive load drive mode, the overcurrent protection circuit limits the output current to an overcurrent protection threshold or less, and the overheat protection circuit is configured to repeatedly force-off and restart the output switch every time the monitored temperature rises to a second overheat protection threshold that is lower than a first overheat protection threshold set in the normal mode.

[0006] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0007] According to the present disclosure, it is possible to provide a semiconductor device, an electronic device, and a vehicle that can appropriately drive a capacitive load without impairing the abnormality protection function.

[0008] FIG. 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. FIG. 2 is a block circuit diagram showing the electrical structure of the semiconductor device. FIG. 3 is a diagram showing an example of an electronic device including a mechanical fuse. FIG. 4 is a diagram showing an example of a semiconductor device that replaces a mechanical fuse. FIG. 5 is a diagram showing a first example of an abnormality protection operation. FIG. 6 is a diagram showing a second example of an abnormality protection operation. FIG. 7 is a diagram showing a third example of an abnormality protection operation. FIG. 8 is a diagram showing a fourth example of an abnormality protection operation. FIG. 9 is a diagram showing a first example of a startup operation. FIG. 10 is a diagram showing a second example of a startup operation. FIG. 11 is a diagram showing a third example of a startup operation. FIG. 12 is an external view showing an example of the configuration of a vehicle.

[0009] 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. An electronic device A of this configuration example includes a semiconductor device 1, a DC power supply 2, and a load 3.

[0010] The semiconductor device 1 is a high-side switch IC (a type of IPD) that connects / disconnects a DC power supply 2 and a load 3, and is configured by integrating a power MISFET (metal insulator semiconductor field effect transistor) 9 and a controller 10.

[0011] The semiconductor device 1 also includes a plurality of external electrodes as means for establishing electrical connection with the outside of the device. Referring to the figure, the semiconductor device 1 includes a drain electrode 11 (corresponding to the power supply electrode VBB), a source electrode 12 (corresponding to the output electrode OUT), an input electrode 13 (corresponding to the input electrode IN), and a reference voltage electrode 14 (corresponding to the ground electrode GND).

[0012] The power MISFET 9 is an example of an insulated gate power transistor (=output switch), and functions as a high-side switch element that connects / disconnects the drain electrode 11 and the source electrode 12 .

[0013] The controller 10 includes a plurality of types of functional circuits that realize various functions, including, for example, a circuit that generates a gate control signal VG that drives and controls the power MISFET 9 based on an external electrical signal.

[0014] The drain electrode 11 transmits a power supply voltage VB to the drain of the power MISFET 9 and various circuits of the controller 10. The source electrode 12 is connected to the source of the power MISFET 9 and transmits an output voltage VOUT and an output current IOUT to the load 3. Note that a signal line (e.g., a wire harness) laid between the source electrode 12 and the load 3 generally has an inductance component L (and a resistance component). The input electrode 13 transmits an input voltage (=input signal IN) for driving the controller 10. The reference voltage electrode 14 transmits a reference voltage (e.g., ground voltage) to the controller 10. Note that a resistance component R generally accompanies the reference voltage electrode 14 and the ground terminal.

[0015] <Semiconductor Device> Fig. 2 is a block circuit diagram showing the electrical structure of the semiconductor device 1 shown in Fig. 1. The following description will be given taking as an example a case where the semiconductor device 1 is mounted on a vehicle. When mounted on a vehicle, the semiconductor device 1 can be used as a high-side switch for controlling the supply of current to a light source such as a bulb lamp or an LED (light emitting diode) lamp, or to other types of electronic control devices.

[0016] The semiconductor device 1 includes a drain electrode 11 , a source electrode 12 , an input electrode 13 , a reference voltage electrode 14 , an enable electrode 15 , a sense electrode 16 , a gate control wiring 17 , a power MISFET 9 , and a controller 10 .

[0017] The drain electrode 11 (=power supply electrode VBB) is connected to a DC power supply 2. The drain electrode 11 provides a power supply voltage VB to the power MISFET 9 and the controller 10. The power supply voltage VB may be 10 V or more and 20 V or less. On the other hand, the source electrode 12 (=output electrode OUT) is connected to a load 3.

[0018] The input electrode 13 (=input electrode IN) may be connected to an MCU (micro controller unit), a DC / DC converter, an LDO (low drop out) regulator, or the like. The input electrode 13 provides an input voltage to the controller 10. The input voltage may be 1 V or more and 10 V or less. The reference voltage electrode 14 is connected to a reference voltage wiring (ground terminal). The reference voltage electrode 14 provides a reference voltage to the power MISFET 9 and the controller 10.

[0019] The enable electrode 15 may be connected to the MCU. An electrical signal for enabling or disabling some or all of the functions of the controller 10 is input to the enable electrode 15. The sense electrode 16 transmits an electrical signal for detecting an abnormality in the controller 10 to an external device. The sense electrode 16 may be pulled up or down by a resistor.

[0020] The gate of the power MISFET 9 is connected to the controller 10 (particularly, a gate control circuit 25 described later) via a gate control wiring 17. The drain of the power MISFET 9 is connected to a drain electrode 11. The source of the power MISFET 9 is connected to the controller 10 (particularly, a current detection circuit 27 described later) and a source electrode 12.

[0021] The controller 10 includes a sensor MISFET 21 , an input circuit 22 , a current / voltage control circuit 23 , a protection circuit 24 , a gate control circuit 25 , an active clamp circuit 26 , a current detection circuit 27 , a power supply reverse connection protection circuit 28 , and an abnormality detection circuit 29 .

[0022] The gate of the sensor MISFET 21 is connected to the gate control circuit 25. The drain of the sensor MISFET 21 is connected to the drain electrode 11. The source of the sensor MISFET 21 is connected to the current detection circuit 27.

[0023] The input circuit 22 is connected to the input electrode 13 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0024] The current / voltage control circuit 23 is connected to a protection circuit 24, a gate control circuit 25, a power supply reverse connection protection circuit 28, and an abnormality detection circuit 29. The current / voltage control circuit 23 may include a logic circuit.

[0025] The current / voltage control circuit 23 generates various voltages in response to the electrical signals from the input circuit 22 and the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage / reference current generation circuit 33.

[0026] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 30 may generate a drive voltage between 5 V and 15 V, which is obtained by subtracting 5 V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0027] The first constant voltage generating circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generating circuit 31 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The first constant voltage is input to the protection circuit 24 (more specifically, to the open load detection circuit 35, etc., which will be described later).

[0028] The second constant voltage generating circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generating circuit 32 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The second constant voltage is input to the protection circuit 24 (more specifically, an overheat protection circuit 36 ​​and an undervoltage lockout circuit 37, which will be described later).

[0029] The reference voltage / reference current generating circuit 33 generates a reference voltage and a reference current for the various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to the various circuits. If the various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0030] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The protection circuit 24 includes an overcurrent protection circuit 34, an open load detection circuit 35, an overheat protection circuit 36, and an undervoltage lockout circuit 37.

[0031] The overcurrent protection circuit 34 protects the power MISFET 9 from an overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25 and the source of the sensor MISFET 21. The overcurrent protection circuit 34 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, to a drive signal output circuit 40, which will be described later).

[0032] The open load detection circuit 35 detects a short state and an open state of the power MISFET 9. The open load detection circuit 35 is connected to the current / voltage control circuit 23 and the source of the power MISFET 9. A signal generated by the open load detection circuit 35 is input to the current / voltage control circuit 23.

[0033] The overheat protection circuit 36 ​​monitors the temperature of the power MISFET 9 and protects the power MISFET 9 from an excessive temperature rise. The overheat protection circuit 36 ​​is connected to the current / voltage control circuit 23. The overheat protection circuit 36 ​​may include a temperature-sensing device such as a temperature-sensing diode or a thermistor. A signal generated by the overheat protection circuit 36 ​​is input to the current / voltage control circuit 23.

[0034] The undervoltage lockout circuit 37 prevents the power MISFET 9 from malfunctioning when the power supply voltage VB is less than a predetermined value. The undervoltage lockout circuit 37 is connected to the current / voltage control circuit 23. A signal generated by the undervoltage lockout circuit 37 is input to the current / voltage control circuit 23.

[0035] The gate control circuit 25 controls the on and off states of the power MISFET 9 and the sensor MISFET 21. The gate control circuit 25 is connected to the current / voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0036] The gate control circuit 25 outputs a gate control signal VG to the gate control wiring 17 in response to an electric signal from the current / voltage control circuit 23 and an electric signal from the protection circuit 24. The gate control signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. Specifically, the gate control circuit 25 controls the gate control signal VG in response to an electric signal (input signal) applied to the input electrode 13, thereby turning the power MISFET 9 on / off.

[0037] More specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates in response to an electrical signal from the current / voltage control circuit 23 to generate a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 generates a boosted voltage VCP based on the electrical signal from the oscillation circuit 38. The boosted voltage VCP generated by the charge pump circuit 39 is input to the drive signal output circuit 40.

[0038] The drive signal output circuit 40 operates by receiving the boosted voltage VCP output from the charge pump circuit 39, and generates a gate control signal VG in response to an electrical signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). The gate control signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. The sensor MISFET 21 and the power MISFET 9 are simultaneously controlled by a gate control circuit 25.

[0039] The active clamp circuit 26 protects the power MISFET 9 from back electromotive force. The active clamp circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamp circuit 26 may include a plurality of diodes.

[0040] The active clamp circuit 26 may include a plurality of diodes connected to each other in a forward bias state. The active clamp circuit 26 may include a plurality of diodes connected to each other in a reverse bias state. The active clamp circuit 26 may include a plurality of diodes connected to each other in a forward bias state and a plurality of diodes connected to each other in a reverse bias state.

[0041] The multiple diodes may include pn junction diodes, Zener diodes, or a combination of pn junction diodes and Zener diodes. The active clamp circuit 26 may include multiple Zener diodes connected to each other in a biased manner. The active clamp circuit 26 may include a Zener diode and a pn junction diode connected to each other in a reverse biased manner.

[0042] The current detection circuit 27 detects the currents flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal in response to the electrical signal (=output current IOUT) generated by the power MISFET 9 and the electrical signal (=sense current ISNS that behaves in the same way as the output current IOUT) generated by the sensor MISFET 21. The current detection signal is input to the abnormality detection circuit 29.

[0043] The power supply reverse connection protection circuit 28 protects the current / voltage control circuit 23, the power MISFET 9, etc. from reverse voltage when the DC power supply 2 is reverse connected. The power supply reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current / voltage control circuit 23.

[0044] Abnormality detection circuit 29 monitors the voltage of protection circuit 24. Abnormality detection circuit 29 is connected to current / voltage control circuit 23, protection circuit 24, and current detection circuit 27. If an abnormality (such as a voltage fluctuation) occurs in any of overcurrent protection circuit 34, open load detection circuit 35, overheat protection circuit 36, and undervoltage malfunction suppression circuit 37, abnormality detection circuit 29 generates an abnormality detection signal corresponding to the voltage of protection circuit 24 and outputs it to the outside.

[0045] More specifically, the abnormality detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two inputs, one output, and one selection control input. The protection circuit 24 and the current detection circuit 27 are connected to the inputs of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output of the first multiplexer circuit 41. The current / voltage control circuit 23 is connected to the selection control input of the first multiplexer circuit 41.

[0046] The first multiplexer circuit 41 generates an abnormality detection signal in response to the electrical signal from the current / voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0047] The second multiplexer circuit 42 has two inputs and one output. The inputs of the second multiplexer circuit 42 are connected to the output of the second multiplexer circuit 42 and the enable electrode 15. The output of the second multiplexer circuit 42 is connected to the sense electrode 16.

[0048] When an MCU is connected to enable electrode 15 and a pull-up or pull-down resistor is connected to sense electrode 16, an ON signal is input from the MCU to enable electrode 15, and an abnormality detection signal is extracted from sense electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to sense electrode 16. An abnormal state of semiconductor device 1 is detected based on this electrical signal.

[0049] 3 is a diagram showing an example of an electronic device equipped with a mechanical fuse. The electronic device B of this configuration example includes a control unit B10, a battery B20, a load B30, and a fuse box B40.

[0050] The control unit B10 drives a load B30 by receiving a power supply voltage VB from a battery B20 via a fuse box B40. Referring to the figure, the control unit B10 includes a DC / DC converter B11, a microcomputer B12, an upper switch B13, a power supply electrode B14, an output electrode B15, and a reference voltage electrode B16. The control unit B10 may be, for example, an ECU (electronic control unit).

[0051] The DC / DC converter B11 generates a desired internal power supply voltage from the power supply voltage VB and outputs it to each part (such as the microcomputer B12) of the control unit B10.

[0052] The microcomputer B12 receives the internal power supply voltage from the DC / DC converter B11 and controls the on / off of the upper switch B13.

[0053] The upper switch B13 is connected between the power supply electrode B14 and the output electrode B15, and is controlled to be turned on / off in response to an instruction from the microcomputer B12.

[0054] The power supply electrode B14 is supplied with a power supply voltage VB from a battery B20 via a fuse box B40. The output electrode B15 is connected to a load B30 via a wire W3, for example. The reference voltage electrode B16 is connected to a ground terminal, for example.

[0055] The fuse box B40 includes n fuses B41(1) to B41(n), an input electrode B42, and output electrodes B43(1) to B43(n).

[0056] The fuse B41(i) (where i = 1, 2, ..., n) is connected between the input electrode B42 and the output electrode B43(i). The fuse B41(i) is a so-called mechanical fuse, and when a current exceeding the rated current flows through it, it melts down due to Joule heat, thereby protecting the circuit.

[0057] The input electrode B42 is connected to the positive terminal of the battery B20 (=the terminal to which the power supply voltage VB is applied) via, for example, a wire W1. The output electrode B43(1) is connected to the power supply electrode B14 of the control unit B10 via, for example, a wire W2.

[0058] Electronic device B using fuse box B40 has two problems. First, the reaction time of fuse B41(i) (i.e., the time required for it to blow) is unknown and inaccurate. As a result, damage to the control unit B10 it protects can often be a problem. Second, blown fuse B41(i) must be replaced. In many cases, a complete system replacement (i.e., a replacement of fuse box B40) is required.

[0059] To solve the above problem, it is conceivable to use an electronic fuse (so-called e-fuse) using an IPD instead of a mechanical fuse. However, the control unit B10 often has its own input capacitor in a subsystem such as the DC / DC converter B11. Therefore, from the perspective of the electronic fuse, the control unit B10 functions as a capacitive load with a large capacitance (generally in the mF range).

[0060] Therefore, in a typical IPD with an electronic fuse, the output switch must be large so that the overheat protection function does not activate even if a large inrush current flows when the control unit B10 starts up, which increases the cost of the IPD.

[0061] Incidentally, if a precharge circuit using discrete components is provided, it is possible to avoid increasing the size of the IPD output switch, but this would require an increase in the number of components and a larger PCB (printed circuit board), which could result in an increase in the cost of the entire electronic device.

[0062] A novel semiconductor device that can solve the above problems will be proposed below.

[0063] 4 is a diagram showing an example of a semiconductor device that replaces a mechanical fuse. In the electronic device B of this configuration example, the fuse box B40 is replaced with a semiconductor device 1, based on the electronic device B shown in FIG.

[0064] The control unit B10, which is externally attached to the source electrode 12 (=output electrode OUT) of the semiconductor device 1, functions as a capacitive load with a large capacitance value when viewed from the semiconductor device 1. Therefore, the control unit B10 is depicted equivalently as a parallel circuit of a capacitor C1 and a resistor R1. Also shown in this figure is a resistor R2 for pulling down the sense electrode 16 to the ground terminal.

[0065] 2, and further includes a CMODE enable electrode 51, an input circuit 52, and a mode control circuit 53. Therefore, the components already described are given the same reference numerals as in FIG. 2 to avoid redundant explanation, and the following description will focus on new components and components related to them.

[0066] The power MISFET 9 is an output switch that connects / disconnects the drain electrode 11 and the source electrode 12 in response to a gate control signal VG.

[0067] The overcurrent protection circuit 34 detects the output current IOUT flowing through the power MISFET 9 and controls the gate control signal VG to provide overcurrent protection.

[0068] The overheat protection circuit 36 ​​detects the temperature to be monitored and controls the gate control signal VG to provide overheat protection.

[0069] The temperature to be monitored may be a first temperature Temp1 detected in the power element formation region including the power MISFET 9. The first temperature Temp1 may be, for example, a pn junction temperature Tj1 in the power element formation region.

[0070] The temperature to be monitored may be a temperature difference ΔTemp (=Temp1-Temp2) between a first temperature Temp1 and a second temperature Temp2 detected in an area other than the power element forming area. The second temperature Temp2 may be, for example, a pn junction temperature Tj2 in the analog circuit forming area or the logic circuit forming area, or may be a case temperature Tc of the semiconductor device 1 or an ambient temperature Ta.

[0071] The CMODE enable electrode 51 is an external electrode for switching the mode control circuit 53 between enabled and disabled.

[0072] The input circuit 52 shapes the waveform of the electrical signal applied to the CMODE enable electrode 51 and outputs it to the mode control circuit 53 .

[0073] The mode control circuit 53 generates a mode control signal S1 for switching between the normal mode and the capacitive load drive mode for each of the overcurrent protection circuit 34 and the overheat protection circuit 36. The mode control signal S1 is output to each of the overcurrent protection circuit 34 and the overheat protection circuit 36.

[0074] The mode control circuit 53 is enabled, for example, when the electrical signal applied to the CMODE enable electrode 51 is at a high level, and is in a state where it can switch the logic level of the mode control signal S1. For example, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode when the mode control signal S1 is at a high level, and are set to the capacitive load drive mode when the mode control signal S1 is at a low level.

[0075] In the capacitive load driving mode, the overcurrent protection circuit 34 performs a current limiting operation to limit the output current IOUT to an overcurrent protection threshold Iocp or less. In particular, in the capacitive load driving mode, the overcurrent protection threshold Iocp is set to a second overcurrent protection threshold I2 (e.g., I2 = I1 × 0.7) that is lower than the first overcurrent protection threshold I1 set in the normal mode.

[0076] Moreover, the overheat protection circuit 36 ​​repeatedly forcibly turns off and restarts the power MISFET 9 every time the monitored temperature (for example, the aforementioned temperature difference ΔTemp) rises up to the overheat protection threshold Ttsd. In particular, in the capacitive load drive mode, the overheat protection threshold Ttsd is set to a second overheat protection threshold T2 (for example, T2=30° C.) that is lower than the first overheat protection threshold T1 (for example, T1=90° C.) that is set in the normal mode.

[0077] On the other hand, the mode control circuit 53 is disabled, for example, when the electrical signal applied to the CMODE enable electrode 51 is at a low level. In this case, the mode control signal S1 is fixed at a high level. Therefore, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode.

[0078] As described above, in the electronic device B of this configuration example, the aforementioned fuse box B40 is replaced with the semiconductor device 1. That is, when the output current IOUT becomes excessive (for example, several tens to 100 A), the power MISFET 9 is forcibly turned off, thereby limiting or cutting off the output current IOUT quickly and accurately. Therefore, both the semiconductor device 1 and the control unit B10 can be safely protected. Furthermore, unlike a configuration using a mechanical fuse, there is no need to replace a blown fuse B41(i) even if a failure occurs.

[0079] Furthermore, the semiconductor device 1 has a capacitive load driving mode as one of its operation modes, and can therefore appropriately drive a capacitive load (control unit B10 in this figure) without increasing the size of the power MISFET 9 or requiring additional external components.

[0080] The following describes the difference between the normal mode and the capacitive load driving mode of the semiconductor device 1, focusing on the abnormality protection operation of the semiconductor device 1. This description will make clear the advantages of using the capacitive load driving mode.

[0081] <Fault Protection Operation> Fig. 5 is a diagram showing a first example of fault protection operation in the semiconductor device 1 of Fig. 4. In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0082] This figure shows the behavior when a resistive load (or an inductive load) is driven by the semiconductor device 1 of Figure 4. In this case, when the electrical signal applied to the input electrode IN rises to a high level, the output voltage VOUT rises to the power supply voltage VB. Furthermore, the output current IOUT reaches a target value (nominal value) without exceeding the overcurrent protection threshold Iocp.

[0083] The above behavior occurs regardless of whether the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode or the capacitive load drive mode. In other words, when a resistive load or an inductive load is driven by the semiconductor device 1 of FIG. 4, there is no particular effect on the operation of the semiconductor device 1 even if the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode.

[0084] On the other hand, when a capacitive load is driven by the semiconductor device 1 of Figure 4, the behavior of the semiconductor device 1 differs depending on whether the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to normal mode or capacitive load drive mode.

[0085] Fig. 6 is a diagram showing a second example of the abnormality protection operation in the semiconductor device 1 of Fig. 4. In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0086] 4. This figure shows the behavior when a capacitive load (e.g., control unit B10) is driven by the semiconductor device 1 of FIG. 4. Also, this figure assumes that the electrical signal applied to the CMODE enable electrode 51 is at a low level and the mode control signal S1 is fixed at a high level. In other words, this figure shows the behavior when the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the normal mode.

[0087] In this case, when the electrical signal applied to the input electrode IN rises to a high level, a large inrush current flows through the capacitive load, causing the output current IOUT to increase sharply. At this time, the overcurrent protection circuit 34 performs a current limiting operation so that the output current IOUT is equal to or less than the overcurrent protection threshold Iocp (=I1).

[0088] Furthermore, when the capacitance value of the capacitive load is large and the element size of the power MISFET 9 is small, the heat generated by the power MISFET 9 increases. As a result, the overheat protection circuit 36 ​​repeatedly forcibly turns off and restarts the power MISFET 9 every time the temperature to be monitored (for example, the aforementioned temperature difference ΔTemp) rises up to the overheat protection threshold Ttsd (=T1).

[0089] Note that a certain cooling time Tcd is required from when the power MISFET 9 is forcibly turned off by the overheat protection operation until it is restarted. During this time, the output current IOUT continues to be not supplied to the capacitive load. Therefore, as shown in the figure, there is a risk that this will cause problems in starting up the output voltage VOUT.

[0090] If the element size of the power MISFET 9 is increased, the overheat protection operation is less likely to be activated, and the output voltage VOUT can be raised correctly. However, as described above, increasing the size of the power MISFET 9 leads to an increase in the cost of the semiconductor device 1.

[0091] Fig. 7 is a diagram showing a third example of the abnormality protection operation in the semiconductor device 1 of Fig. 4. In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0092] 6, this figure shows the behavior when a capacitive load (e.g., control unit B10) is driven by the semiconductor device 1 of FIG. 4. Also, as in the previous figure, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to normal mode. However, the overcurrent protection operation in normal mode differs from that in the previous figure.

[0093] Referring to this figure, the overcurrent protection circuit 34 performs an off-latch operation to forcibly keep the power MISFET 9 off when the output current IOUT increases to the overcurrent protection threshold Iocp (=I1).

[0094] This type of off-latch operation is extremely effective when the objective is to comply with strict safety standards such as the AEC-Q100-012 standard. However, when considering driving a capacitive load, it must be said to be inappropriate. This is because the forced off-latch of the power MISFET 9 completely cuts off the supply of the output current IOUT to the capacitive load, preventing the output voltage VOUT from rising at all.

[0095] Therefore, when the overcurrent protection circuit 34 performs an off-latch operation, there is no point in increasing the size of the power MISFET 9, and an external precharge circuit becomes essential.

[0096] Fig. 8 is a diagram showing a fourth example of the abnormality protection operation in the semiconductor device 1 of Fig. 4. In this diagram, from top to bottom, the applied voltage (=input voltage) of the input electrode IN, the output current IOUT, and the output voltage VOUT are depicted.

[0097] 6 and 7, this figure shows the behavior when a capacitive load (e.g., control unit B10) is driven by the semiconductor device 1 of Fig. 4. However, it differs from the previous figures in that the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode rather than the normal mode.

[0098] Referring to this figure, in the capacitive load drive mode, the overcurrent protection circuit 34 performs a current limiting operation to limit the output current IOUT to an overcurrent protection threshold Iocp (=I2<I1) or less. The overheat protection circuit 36 ​​repeatedly forcibly turns off and restarts the power MISFET 9 every time the monitored temperature (for example, the aforementioned temperature difference ΔTemp) rises up to the overheat protection threshold Ttsd (=T2<T1).

[0099] In this way, in the capacitive load drive mode, both the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd (at least the overheat protection threshold Ttsd) are lowered compared to the normal mode, and the power MISFET 9 is repeatedly forced off and restarted.

[0100] Therefore, the cooling time Tcd from when the power MISFET 9 is forcibly turned off by the overheat protection operation until it is restarted is shortened. As a result, it becomes possible to charge the capacitive load and raise the output voltage VOUT without increasing the size of the power MISFET 9 or requiring an external precharge circuit.

[0101] In this way, in the capacitive load drive mode, it is possible to appropriately drive a capacitive load that is difficult to drive in the normal mode.

[0102] As described above, in the capacitive load drive mode, the overcurrent protection threshold Iocp and the overheat protection threshold Ttsd are lowered compared to those in the normal mode, so that the semiconductor device 1 and the capacitive load (e.g., the control unit B10) connected thereto are maintained within a safe operation area (SOA) while the capacitive load is being charged.

[0103] In addition, in the capacitive load driving mode, at least one of the second overcurrent protection threshold I2 and the second overheat protection threshold T2 may be gradually raised to the first overcurrent protection threshold I1 and the first overheat protection threshold T1 in response to an increase in the output voltage VOUT or over time.

[0104] Furthermore, the mode control circuit 53 may switch the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​from the capacitive load drive mode to the normal mode when a predetermined recovery condition (described in detail later) is satisfied (see "CMODE EXIT" in the figure).

[0105] For example, the overcurrent protection operation after returning to the normal mode may be a current limiting operation that limits the output current IOUT to an overcurrent protection threshold Iocp (=I1) or less, similar to the capacitive load driving mode.

[0106] Furthermore, for example, the overcurrent protection operation after returning to the normal mode may be a hiccup operation in which the power MISFET 9 is repeatedly forced off and restarted every time the output current IOUT increases up to the overcurrent protection threshold Iocp (=I1). Such a hiccup operation can suppress heat generation in the power MISFET 9 more effectively than the above-described current limiting operation.

[0107] Furthermore, for example, the overcurrent protection operation after returning to the normal mode may be an off-latch operation that continues to forcibly turn off the power MISFET 9 when the output current IOUT increases to the overcurrent protection threshold Iocp (=I1). Such an off-latch operation further enhances safety when an overcurrent occurs compared to the above-mentioned current limiting operation and hiccup operation.

[0108] In this way, the semiconductor device 1 of this configuration example can switch between the normal mode and the capacitive load drive mode as needed, and is therefore compatible with process technologies in which the on-resistance of the power MISFET 9 is relatively high and stricter overcurrent protection operation is required.

[0109] To summarize the operation and architecture of the capacitive load driving mode described above, the most important attributes are:

[0110] (1) In the capacitive load drive mode, an overheat detection / restart operation (a state in which the power MISFET 9 is repeatedly forced off by overheat detection and restarted by overheat release) is forced as an overheat protection operation. As a result, the capacitive load is repeatedly charged until the output voltage VOUT rises sufficiently.

[0111] (2) In the capacitive load driving mode, the current limiting operation is forced as an overcurrent protection operation, which prevents the output current IOUT from being latched off before the capacitive load is fully charged.

[0112] (3) In the capacitive load driving mode, the overcurrent protection threshold Iocp is lowered (I1 → I2). This reduces the peak inrush current flowing through the capacitive load during charging. For example, the second overcurrent protection threshold I2 set in the capacitive load driving mode may be 70% of the first overcurrent protection threshold I1 set in the normal mode (i.e., I2 = I1 × 0.7). However, the above ratio is not limited to this.

[0113] (4) In the capacitive load drive mode, the overheat protection threshold Ttsd is lowered (T1 → T2). This has two effects. The first effect is that the semiconductor device 1 is maintained in the safe operating area while the capacitive load is not fully charged, i.e., while the capacitive load functions as a virtual short circuit. The second effect is that the semiconductor device 1 is quickly cooled to the overheat release temperature (safe temperature), which accelerates the timing of restarting the power MISFET 9 and allows the capacitive load to continue to be charged. In other words, a charge pump effect is obtained, which allows the output voltage VOUT to be reliably raised.

[0114] (5) When the output voltage VOUT becomes higher than a predetermined threshold voltage Vth, the capacitive load driving mode is automatically restored to the normal mode. That is, the threshold voltage Vth corresponds to the termination threshold of the capacitive load driving mode. As described above, the overcurrent protection operation after restoration to the normal mode may be any of the current limiting operation, the hiccup operation, and the off-latch operation.

[0115] (6) The semiconductor device 1 may be automatically restored to the normal mode after a predetermined time (e.g., 50 ms) has elapsed since the capacitive load drive mode was set, thereby maintaining the semiconductor device 1 within the safe operating area even in the event of an output short circuit or other fault.

[0116] (7) The semiconductor device 1 includes a CMODE enable electrode 51 for enabling / disabling the mode control circuit 53 (and thus the capacitive load drive mode). This allows the user to freely decide whether or not to use the capacitive load drive mode. Furthermore, the mode control circuit 53 can be easily enabled / disabled without applying any special mechanism (such as high-frequency PWM [pulse width modulation] drive or multi-level input) to the input electrode IN.

[0117] <Start-up Operation> Fig. 9 is a diagram showing a first example of the startup operation of the semiconductor device 1 of Fig. 4. In this diagram, from top to bottom, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are depicted.

[0118] 4 shows the behavior when a purely resistive load (for example, R1=2Ω, C1=0F) is driven by the semiconductor device 1 of FIG. 4. The on-resistance of the power MISFET 9 is set to 4 mΩ.

[0119] As shown in the figure, the mode control circuit 53 drops the mode control signal S1 to low level when the power MISFET 9 transitions to on. Therefore, the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode described above. Note that the capacitive load drive mode does not have any effect on the drive operation (e.g., slew rate) of the resistive load.

[0120] Furthermore, when a predetermined recovery condition is satisfied, the mode control circuit 53 raises the mode control signal S1 to a high level, thereby switching the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​from the capacitive load drive mode to the normal mode.

[0121] Referring to this figure, the recovery condition is that the output voltage VOUT has been detected to be higher than a predetermined threshold voltage Vth. For example, the threshold voltage Vth may be set to a voltage value (Vth = VB - Vx) that is lower than the power supply voltage VB (e.g., 14 V) by a bias voltage Vx (e.g., 2 V). With this setting, the capacitive load drive mode is automatically terminated when the output voltage VOUT has risen sufficiently.

[0122] Alternatively, the above-mentioned restoration condition may be that a predetermined time (for example, 50 ms) has elapsed since the mode control signal S1 was made low.

[0123] Fig. 10 is a diagram showing a second example of the startup operation of the semiconductor device 1 of Fig. 4. In this diagram, as in Fig. 9, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are depicted in this order from top to bottom.

[0124] 4 shows the behavior when a capacitive load (for example, R1=2Ω, C1=1 mF) is driven by the semiconductor device 1 of FIG. 4. The on-resistance of the power MISFET 9 is set to 4 mΩ.

[0125] As shown in the figure, when the power MISFET 9 transitions to ON, the mode control signal S1 is pulled down to a low level, and the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode. As a result, the output voltage VOUT rises to the threshold voltage Vth within a startup time t1 (e.g., less than 2 ms) within the required range. The conditions for returning from the capacitive load drive mode to the normal mode (output voltage monitoring or timer monitoring) are the same as those described above.

[0126] Fig. 11 is a diagram showing a third example of the startup operation of the semiconductor device 1 of Fig. 4. In this diagram, as in Figs. 9 and 10, the output current IOUT, the output voltage VOUT, and the mode control signal S1 are depicted from top to bottom.

[0127] 10. The figure shows the behavior when a capacitive load (for example, R1=2Ω, C1=4 mF) larger than that in FIG. 10 is driven by the semiconductor device 1 in FIG. 4. The on-resistance of the power MISFET 9 is set to 4 mΩ.

[0128] As shown in the figure, when the power MISFET 9 transitions to ON, the mode control signal S1 is pulled down to a low level, and the overcurrent protection circuit 34 and the overheat protection circuit 36 ​​are set to the capacitive load drive mode. As a result, the output voltage VOUT rises to the threshold voltage Vth within a startup time t2 within the required range (e.g., less than 7.5 ms). The conditions for returning from the capacitive load drive mode to the normal mode (output voltage monitoring or timer monitoring) are the same as those described above.

[0129] <Application to Vehicles> Fig. 12 is an external view showing an example of the configuration of a vehicle X. The vehicle X of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0130] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0131] The semiconductor device 1 described above can be incorporated into any of the electronic devices mounted on the vehicle X.

[0132] <Summary> The various embodiments described above will be summarized below.

[0133] For example, a semiconductor device disclosed in this specification includes an output switch, an overcurrent protection circuit configured to detect an output current flowing through the output switch and apply overcurrent protection, an overheat protection circuit configured to detect a monitored temperature and apply overheat protection, and a mode control circuit configured to switch between setting each of the overcurrent protection circuit and the overheat protection circuit in a normal mode or a capacitive load drive mode, wherein in the capacitive load drive mode, the overcurrent protection circuit limits the output current to an overcurrent protection threshold or less, and the overheat protection circuit is configured to repeatedly force-off and restart the output switch every time the monitored temperature rises to a second overheat protection threshold that is lower than a first overheat protection threshold set in the normal mode (first configuration).

[0134] The semiconductor device according to the first configuration may be configured (second configuration) such that, in the capacitive load driving mode, the second overheat protection threshold is increased in stages to the first overheat protection threshold.

[0135] In a semiconductor device having the above first or second configuration, in the capacitive load driving mode, the overcurrent protection threshold may be set to a second overcurrent protection threshold that is lower than the first overcurrent protection threshold set in the normal mode (third configuration).

[0136] The semiconductor device according to the third configuration may be configured (fourth configuration) such that, in the capacitive load driving mode, the second overcurrent protection threshold is increased in stages to the first overcurrent protection threshold.

[0137] The semiconductor device according to any one of the first to fourth configurations may be configured (fifth configuration) to further include an enable electrode configured to switch between enabling and disabling the mode control circuit.

[0138] In the semiconductor device according to any one of the first to fifth configurations, the mode control circuit may be configured (sixth configuration) to set the overcurrent protection circuit and the overheat protection circuit to the capacitive load drive mode when the output switch transitions to on.

[0139] In a semiconductor device having any of the first to sixth configurations described above, the mode control circuit may be configured (seventh configuration) to switch the overcurrent protection circuit and the overheat protection circuit from the capacitive load drive mode to the normal mode when a recovery condition is satisfied.

[0140] In a semiconductor device having any of the first to seventh configurations, in the normal mode, the overcurrent protection circuit may be configured (eighth configuration) to perform one of a current limiting operation that limits the output current to equal to or less than the overcurrent protection threshold, a hiccup operation that repeatedly forcibly turns off and restarts the output switch every time the output current increases to the overcurrent protection threshold, or an off-latch operation that continues to forcibly turn off the output switch when the output current increases to the overcurrent protection threshold.

[0141] In the semiconductor device according to any one of the first to eighth configurations above, the monitored temperature may be a first temperature detected in a power element region including the output switch, or a temperature difference between the first temperature and a second temperature detected outside the power element region (ninth configuration).

[0142] Furthermore, for example, the electronic device disclosed in this specification is configured (tenth configuration) to include a semiconductor device having any of the first to ninth configurations described above and a load configured to receive the output current from the semiconductor device.

[0143] Furthermore, for example, the vehicle disclosed in this specification is configured (eleventh configuration) to include the electronic device according to the tenth configuration.

[0144] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation.

[0145] For example, in the above embodiment, a high-side switch IC that replaces a mechanical fuse is illustrated, but the capacitive load driving mode is not limited to this. That is, the capacitive load driving mode can be widely implemented in other IPDs (such as low-side switch ICs).

[0146] As such, the above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is defined by the claims, and it should be understood that all modifications within the meaning and scope of the claims are included.

[0147] 1 Semiconductor device (high-side switch IC) 2 DC power supply 3 Load 9 Power MISFET (output switch) 10 Controller 11 Drain electrode (power supply electrode) 12 Source electrode (output electrode) 13 Input electrode 14 Reference voltage electrode 15 Enable electrode 16 Sense electrode 17 Gate control wiring 21 Sensor MISFET 22 Input circuit 23 Current / voltage control circuit 24 Protection circuit 25 Gate control circuit 26 Active clamp circuit 27 Current detection circuit 28 Power supply reverse connection protection circuit 29 Abnormality detection circuit 30 Drive voltage generation circuit 31 First constant voltage generation circuit 32 Second constant voltage generation circuit 33 Reference voltage / reference current generation circuit 34 Overcurrent protection circuit 35 Open load detection circuit 36 ​​Overheat protection circuit 37 Undervoltage malfunction suppression circuit 38 Oscillator circuit 39 Charge pump circuit 40 Drive signal output circuit 41 First multiplexer circuit 42 Second multiplexer circuit 51 CMODE enable electrode 52 Input circuit 53 Mode control circuit A Electronic device B Electronic device B10 Control unit (ECU) B11 DC / DC converter B12 Microcomputer B13 Upper switch B14 Power supply electrode B15 Output electrode B16 Reference voltage electrode B20 Battery B30 Load B40 Fuse box B41(1) to B41(n) Fuses B42 Input electrode B43(1) to B43(n) Output electrode C1 Capacitor L Inductance component R Resistance component R1 Resistor W1 to W3 Wires X Vehicle

Claims

1. An output switch; an overcurrent protection circuit configured to detect an output current flowing through the output switch and apply overcurrent protection; an overheat protection circuit configured to detect a monitored temperature and activate overheat protection; a mode control circuit configured to switch between setting each of the overcurrent protection circuit and the overheat protection circuit to a normal mode or a capacitive load drive mode; Equipped with In the capacitive load drive mode, the overcurrent protection circuit limits the output current to below an overcurrent protection threshold, and the overheat protection circuit repeatedly forces off and restarts the output switch each time the monitored temperature rises to a second overheat protection threshold that is lower than a first overheat protection threshold set in a normal mode.

2. The semiconductor device according to claim 1 , wherein in the capacitive load driving mode, the second overheat protection threshold is increased stepwise to the first overheat protection threshold.

3. 2 . The semiconductor device according to claim 1 , wherein in the capacitive load driving mode, the overcurrent protection threshold is set to a second overcurrent protection threshold that is lower than a first overcurrent protection threshold that is set in the normal mode.

4. The semiconductor device according to claim 2 , wherein in the capacitive load driving mode, the second overcurrent protection threshold is increased stepwise to the first overcurrent protection threshold.

5. The semiconductor device according to claim 1 , further comprising an enable electrode configured to enable / disable the mode control circuit.

6. 2 . The semiconductor device according to claim 1 , wherein said mode control circuit sets said overcurrent protection circuit and said overheat protection circuit to said capacitive load drive mode when said output switch transitions to an on state.

7. 2 . The semiconductor device according to claim 1 , wherein said mode control circuit switches said overcurrent protection circuit and said overheat protection circuit from said capacitive load drive mode to said normal mode when a recovery condition is satisfied.

8. 2. The semiconductor device according to claim 1, wherein, in the normal mode, the overcurrent protection circuit performs either a current limiting operation that limits the output current to equal to or less than the overcurrent protection threshold, a hiccup operation that repeatedly forcibly turns off and restarts the output switch every time the output current increases to the overcurrent protection threshold, or an off latch operation that continues to forcibly turn off the output switch when the output current increases to the overcurrent protection threshold.

9. 2. The semiconductor device according to claim 1, wherein the monitored temperature is a first temperature detected in a power element region including the output switch, or a temperature difference between the first temperature and a second temperature detected outside the power element region.

10. A semiconductor device according to any one of claims 1 to 9, a load configured to receive the output current from the semiconductor device; An electronic device comprising:

11. A vehicle comprising the electronic device according to claim 10.