Transfer circuit

Abstract

A transmission circuit 200 supplies, to a primary winding Wp, a current signal ITX that has polarity corresponding to a change in the level of an input signal Din. An active termination circuit 310 is connected with a secondary winding Ws for a transformer T1 and includes a first transistor and a second transistor that are cross-coupled. A common voltage change suppression circuit 330 is configured from a combinational circuit. When a first input node in1 and a second input node in2 have changed with the same polarity, the common voltage change suppression circuit 330 does not change the state of a first output node out1 and a second output node out2. A latch circuit 340 latches output from the common voltage change suppression circuit 330.

Description

Transmission circuit

[0001] The present invention relates to signal transmission between two isolated domains.

[0002] In systems such as commercial power supplies, motors, measuring instruments, and other automotive, industrial, and medical equipment, high electrical insulation is required for digital signal transmission between semiconductor chips for the following purposes: (i) to protect humans and equipment from surge currents and high voltages, (ii) to prevent malfunctions by isolating noise, and (iii) to protect transistors in signal transmission between areas with large potential differences.

[0003] As signal transmission methods that ensure insulation, wireless methods, photocoupler methods, capacitor methods, transformer methods, GMR (Giant Magneto Resistive) methods, and the like have been proposed.

[0004] Among these, the transformer method has many advantages over other methods in terms of transmission speed, power consumption, and common mode transient immunity (CMTI).

[0005] Patent No. 6125690

[0006] The transformer method is a transmission method that uses magnetic fields, and electric field changes caused by common voltage fluctuations are not transmitted to the secondary side, so in principle it can be said to have high CMTI. However, in reality, there is electric field coupling via parasitic capacitance between the primary and secondary windings of the transformer, so it may be affected by common mode noise. In applications that require extremely high levels of reliability, further improvement of CMTI is required.

[0007] The present disclosure has been made in view of the above-mentioned problems, and one exemplary purpose of an embodiment thereof is to provide an isolated signal transmission circuit with improved CMTI.

[0008] A transmission circuit according to one aspect of the present disclosure includes: a transformer having a primary winding and a secondary winding; a transmission circuit connected to the primary winding of the transformer and supplying the primary winding with a current signal having a polarity corresponding to a change in the level of an input signal; an active termination circuit connected to the secondary winding of the transformer and including a first transistor and a second transistor that are cross-coupled; a common voltage variation suppression circuit formed by a combinational circuit and having first and second input nodes connected to the secondary winding of the transformer and a first and second output node, wherein the states of the first output node and the second output node do not change when the first input node and the second input node change with the same polarity; and a latch circuit having a first input node connected to the first output node of the common voltage variation suppression circuit and a second input node connected to the second output node of the common voltage variation suppression circuit.

[0009] Any combination of the above components or conversion of the present invention between methods, devices, etc. are also valid aspects of the present invention.

[0010] According to certain aspects of the present disclosure, CMTI can be improved.

[0011] FIG. 1 is a circuit diagram of a transmission circuit according to an embodiment. FIG. 2 is a circuit diagram of a transmission circuit including a receiver circuit according to Example 1. FIG. 3 is a waveform diagram illustrating the basic operation of the transmission circuit of FIG. 2. FIG. 4 is a waveform diagram illustrating the operation of the transmission circuit of FIG. 2 when a common-mode voltage fluctuation of a first polarity occurs in the transmission circuit of FIG. 2. FIG. 5 is a waveform diagram illustrating the operation of the transmission circuit of Example 2. FIG. 6 is a diagram illustrating the operation of a transmission circuit according to Comparative Technique 1. FIG. 7 is a circuit diagram of a transmission circuit including a receiver circuit according to Example 2. FIG. 8 is a circuit diagram illustrating a configuration example of a first inverter. FIG. 9 is an operational waveform diagram of the receiver circuit according to Example 1. FIG. 10 is an operational waveform diagram of the receiver circuit according to Example 2. FIG. 11 is an operational waveform diagram of the transmission circuit according to Comparative Technique 2. FIG. 12 is a circuit diagram of a receiver circuit according to Example 3. FIG. 13 is a circuit diagram of a receiver circuit according to Example 4. FIG. 14 is a circuit diagram of a first NOR gate (second NOR gate). FIG. 15 is a circuit diagram of a receiver circuit according to Example 5. Fig. 16 is a circuit diagram of a receiving circuit according to a sixth embodiment. Fig. 17 is a circuit diagram of a receiving circuit according to a seventh embodiment. Fig. 18 is a circuit diagram of a receiving circuit according to an eighth embodiment. Fig. 19 is a circuit diagram of a first NAND gate (second NAND gate). Fig. 20 is a circuit diagram showing a configuration example of a transmitting circuit.

[0012] (Summary of the Embodiments) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a basic understanding of one or more embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not intended to be a comprehensive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0013] A transmission circuit according to one embodiment includes: a transformer having a primary winding and a secondary winding; a transmission circuit connected to the primary winding of the transformer and supplying the primary winding with a current signal having a polarity corresponding to a change in the level of an input signal; an active termination circuit connected to the secondary winding of the transformer and including a cross-coupled first transistor and a second transistor; a common voltage fluctuation suppression circuit formed by a combinational circuit and having first and second input nodes connected to the secondary winding of the transformer and a first and second output node, wherein the states of the first output node and the second output node do not change when the first input node and the second input node change with the same polarity; and a latch circuit having a first input node connected to the first output node of the common voltage fluctuation suppression circuit and a second input node connected to the second output node of the common voltage fluctuation suppression circuit.

[0014] According to this configuration, by combining the active termination circuit and the common voltage fluctuation suppression circuit, common voltage fluctuations are not transmitted to the latch circuit, thereby preventing malfunctions.

[0015] In one embodiment, the transmission circuit may further include a protection circuit connected to the secondary winding of the transformer.

[0016] In one embodiment, the active termination circuitry may be constructed with depletion MOS (Metal Oxide Semiconductor) transistors or native MOS transistors.

[0017] In one embodiment, the active termination circuit is comprised of enhancement metal oxide semiconductor (MOS) transistors, and may further include a first resistor connected in parallel with the first transistor and a second resistor connected in parallel with the second transistor.

[0018] In one embodiment, the termination level of the active termination circuit is ground voltage, and the common voltage fluctuation suppression circuit may include a first inverter having an input connected to the first input node, a second inverter having an input connected to the second input node, a first NOR gate having a first input connected to the output of the first inverter and a second input connected to the second input node, and a second NOR gate having a first input connected to the output of the second inverter and a second input connected to the first input node.

[0019] In one embodiment, the ground line of the first inverter may be connected to the second input node, and the ground line of the second inverter may be connected to the first input node. In this configuration, when a common voltage fluctuation occurs, the first inverter and the second inverter are disabled, thereby preventing the common mode voltage fluctuation from being transmitted to the latch circuit.

[0020] In one embodiment, the termination level of the active termination circuit is the power supply voltage, and the common voltage variation suppression circuit may include a first inverter having an input connected to the second input node, a second inverter having an input connected to the first input node, a first NOR gate having a first input connected to the output of the first inverter and a second input connected to the first input node, and a second NOR gate having a first input connected to the output of the second inverter and a second input connected to the second input node.

[0021] In one embodiment, the power supply line of the first NOR gate may be connected to the second input node, and the power supply line of the second NOR gate may be connected to the first input node. In this configuration, when a common voltage fluctuation occurs, the first NOR gate and the second NOR gate become inoperative, thereby preventing the common mode voltage fluctuation from being transmitted to the latch circuit.

[0022] In one embodiment, the termination level of the active termination circuit is the power supply voltage, and the common voltage variation suppression circuit may include a first inverter having an input connected to the first input node, a second inverter having an input connected to the second input node, a first NAND gate having a first input connected to the output of the first inverter and a second input connected to the second input node, and a second NAND gate having a first input connected to the output of the second inverter and a second input connected to the first input node.

[0023] In one embodiment, the power supply line of the first inverter may be connected to the second input node, and the power supply line of the second inverter may be connected to the first input node. In this configuration, when a common voltage fluctuation occurs, the first inverter and the second inverter are disabled, thereby preventing the common mode voltage fluctuation from being transmitted to the latch circuit.

[0024] In one embodiment, the termination level of the active termination circuit is ground voltage, and the common voltage fluctuation suppression circuit may include a first inverter having an input connected to the second input node, a second inverter having an input connected to the first input node, a first NAND gate having a first input connected to the output of the first inverter and a second input connected to the second input node, and a second NAND gate having a first input connected to the output of the second inverter and a second input connected to the first input node.

[0025] In one embodiment, the ground line of the first NAND gate may be connected to the second input node, and the ground line of the second NAND gate may be connected to the first input node. In this configuration, when a common voltage fluctuation occurs, the first NAND gate and the second NAND gate become inoperative, thereby preventing the common mode voltage fluctuation from being transmitted to the latch circuit.

[0026] In one embodiment, the termination level of the active termination circuit is ground voltage, and the first and second transistors may be NMOS transistors with their sources connected to ground.

[0027] In one embodiment, the termination level of the active termination circuit is a power supply voltage, and the first and second transistors may be PMOS transistors with their sources connected to the power supply line.

[0028] In one embodiment, the latch circuit may include a cross-coupled third NOR gate and a fourth NOR gate.

[0029] In one embodiment, the latch circuit may include a cross-coupled third NAND gate and a fourth NAND gate.

[0030] (Embodiments) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0031] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their connection.

[0032] Similarly, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected to each other, but also a case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the functions or effects achieved by their combination.

[0033] 1 is a circuit diagram of a transmission circuit 100 according to an embodiment. The transmission circuit 100 includes a transformer T1, a transmission circuit 200, and a reception circuit 300. The transformer T1 has a primary winding (primary coil) Wp and a secondary winding (secondary coil) Ws.

[0034] The transmission circuit 200 is connected to the primary winding Wp of the transformer T1 and receives an input signal D ｉｎ The polarity (direction) of the current signal I changes in response to a change in the level of ＴＸ is supplied to the primary winding Wp.

[0035] The receiving circuit 300 generates a signal RX in the secondary winding Ws. ｐ , RX ｎ The receiver circuit 300 includes an active termination circuit 310, a protection circuit 320, a common voltage fluctuation suppression circuit 330, and a latch circuit 340.

[0036] The active termination circuit 310 is connected to the secondary winding Ws of the transformer T1. As will be described later, the active termination circuit 310 includes a cross-coupled transistor pair. The termination level V of the active termination circuit 310 is ｔｅｒｍ is either the power supply voltage or the ground voltage.

[0037] The protection circuit 320 is connected to the termination level V ｔｅｒｍ Based on this, the signal line RX ｐ , RX ｎ Clamps the voltage.

[0038] The common voltage fluctuation suppressor circuit 330 is configured as a combinational circuit. A first input node in1 and a second input node in2 of the common voltage fluctuation suppressor circuit 330 are connected to the secondary winding Ws of the transformer T1.

[0039] When a pulse is generated at the first input node in1, the common voltage fluctuation suppressor 330 outputs a pulse Pulse from the first output node out1. ｐ When a pulse occurs at the second input node in2, a pulse Pulse is output from the second output node out2. ｎ Output.

[0040] The common voltage variation suppressor 330 does not change the states of the first output node out1 and the second output node out2 when the first input node in1 and the second input node in2 change with the same polarity. ｐ ,Pulse ｎdoes not output any of the following.

[0041] The latch circuit 340 outputs a pulse ｐ , Pulse ｎ is set and reset in response to

[0042] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0043] First Embodiment FIG. 2 is a circuit diagram of a transmission circuit 100A including a receiving circuit 300A according to a first embodiment.

[0044] The receiver circuit 300A includes an active termination circuit 310A, a protection circuit 320A, a common voltage fluctuation suppression circuit 330A, and a latch circuit 340A.

[0045] In this embodiment, the termination level on the secondary side is the ground voltage GND2. The active termination circuit 310A includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first resistor R1, and a second resistor R2. The first NMOS transistor MN1 and the second NMOS transistor MN2 are enhancement-type metal oxide semiconductor field effect transistors (MOSFETs).

[0046] The source of the first NMOS transistor MN1 is grounded, and the drain is connected to the node RX ｐ and the gate is connected to node RX ｎ The source of the second NMOS transistor MN2 is grounded, and the drain is connected to the node RX ｎ and the gate is connected to node RX ｐ The first resistor R1 is connected in parallel with the first NMOS transistor MN1, and the second resistor R2 is connected in parallel with the second NMOS transistor MN2.

[0047] When both the first NMOS transistor MN1 and the second NMOS transistor MN2 are off, the first resistor R1 and the second resistor R2 connect the node RX ｐ , RX ｎ is terminated.

[0048] The first NMOS transistor MN1 and the second NMOS transistor MN2 may be configured as native MOS transistors or depletion MOS transistors having a small or negative threshold voltage, in which case the first resistor R1 and the second resistor R2 may be omitted.

[0049] The protection circuit 320A prevents electrostatic breakdown of the elements that make up the active termination circuit 310A and the common voltage fluctuation suppression circuit 330A, and also protects the node RX ｐ , RX ｎ The potential of the terminal level V ｔｅｒｍ For example, the protection circuit 320A includes diodes D1 and D2 as protection elements.

[0050] The common voltage fluctuation suppressor circuit 330A includes a first inverter 331, a second inverter 332, a first NOR gate 333, and a second NOR gate 334. The input of the first inverter 331 is connected to a first input node in1. The input of the second inverter 334 is connected to a second input node in2.

[0051] A first input of the first NOR gate 333 is connected to the output of the first inverter 331, and a second input of the first NOR gate 333 is connected to the second input node in2. A first input of the second NOR gate 334 is connected to the output of the second inverter 324, and a second input of the second NOR gate 334 is connected to the first input node in1.

[0052] Latch circuit 340A includes a third NOR gate 342 and a fourth NOR gate 344 that are cross-coupled.

[0053] The above is the configuration of the transmission circuit 100A. Next, the operation of the transmission circuit 100A will be described.

[0054] 3 is a waveform diagram illustrating the basic operation of the transmission circuit 100A of FIG. 2. FIG. 3 shows the operation when there is no fluctuation in the common-mode voltage. ＴＸｐ , I ＴＸｎ is the output node TX of the transmission circuit 200 ｐ , TX ｎ The direction of current flowing out of each node is taken as positive, and the direction of current flowing into each node is taken as negative.

[0055] The primary winding Wp receives an input signal D ｉｎ In response to the positive edge of ＴＸ A driving current I of the first polarity flows. ＴＸ In response to this, the node RX of the receiving circuit 300A ｐ A pulse-like voltage change occurs in the common voltage fluctuation suppressor circuit 330A, and a pulse signal Pulse ｐ This pulse signal Pulse ｐ In response, the output Doutp transitions high.

[0056] In addition, the input signal D ｉｎ In response to the negative edge of ＴＸ A second polarity drive current I ＴＸ In response to this, the node RX of the receiving circuit 300A ｎ A pulse-like voltage change occurs in the common voltage fluctuation suppressor circuit 330A, and a pulse signal Pulse ｎ This pulse signal Pulse ｎ In response, the output Doutp transitions low.

[0057] 4 is a waveform diagram showing a case where a common-mode voltage fluctuation of a first polarity occurs in the transmission circuit 100A of FIG. 2. In this example, the common-mode voltage fluctuation occurs in a steady state (t １ ) The common mode voltage is changing from 0 V to 50 V at a rate of 50 V / ns.

[0058] Due to the influence of common mode voltage fluctuations, the voltage waveform RX on the receiving side ｐ , RX ｎHowever, the common voltage fluctuation suppression circuit 330A eliminates the effect of noise. ｐ , Pulse ｎ Neither of the above occurs, and the common mode voltage fluctuation does not affect the outputs Doutp and Doutn.

[0059] 5 is a waveform diagram showing the waveforms when a common-mode voltage fluctuation of the second polarity occurs in the transmission circuit 100A of FIG. 2. In this example, as in FIG. 4, the common-mode voltage fluctuation occurs in a steady state (t １ The common mode voltage is changing from 50V to 0V at a rate of 50V / ns.

[0060] Due to the influence of common mode voltage fluctuations, the voltage waveform RX on the receiving side ｐ , RX ｎ Noise occurs in the voltage waveform RX on the receiving side in FIG. ｐ , RX ｎ The noises in Fig. 4 have smaller amplitudes than those in Fig. 4. This is because the voltage is clamped by the protection circuit 320A.

[0061] In the case of FIG. ｐ , Pulse ｎ Neither of the above occurs, and the common mode voltage fluctuation does not affect the outputs Doutp and Doutn.

[0062] The advantages of the transmission circuit 100 will be explained in comparison with comparative techniques.

[0063] (Comparative Technique 1) Comparative technique 1 is obtained by omitting the common voltage fluctuation suppression circuit 330A from the transmission circuit 100A of FIG.

[0064] 6 is a diagram illustrating the operation of the transmission circuit according to the comparative technique 1. Here, as in FIG. 4, the common voltage on the primary side changes from 0 V to 50 V. In the comparative technique 1, the common voltage fluctuation suppression circuit 330A is not present, so the signal RX ｐ , RX ｎThis change in the signal level is input as is to the latch circuit 340A, causing the latch circuit 340A to malfunction and changing the outputs Doutp and Doutn.

[0065] In contrast, in the transmission circuit 100A according to the first embodiment, as shown in FIG. 4, the common voltage fluctuation suppression circuit 330A eliminates the influence of common mode voltage fluctuation, thereby preventing malfunction.

[0066] The above are the advantages of the transmission circuit 100A. ｉｎ In a steady state where there is no change in the common mode voltage, malfunctions can be prevented when a common mode voltage fluctuation occurs.

[0067] 7 is a circuit diagram of a transmission circuit 100B including a receiving circuit 300B according to a second embodiment. The receiving circuit 300B has a common voltage fluctuation suppressor circuit 330B configured differently from the common voltage fluctuation suppressor circuit 330A shown in FIG. 2. Specifically, in the common voltage fluctuation suppressor circuit 330B, the ground line of the first inverter 331 is connected to the second input node in2, and the ground line of the second inverter 332 is connected to the first input node in1.

[0068] 8 is a circuit diagram showing an example configuration of the first inverter 331. The source of the NMOS transistor MN11 is the ground line GL, and this ground line GL is connected to the second input node in2 of the common voltage fluctuation suppression circuit 330B instead of the secondary side ground GND2. The back gate of the NMOS transistor MN11 may also be connected to the ground line GL.

[0069] The above is the configuration of the receiver circuit 300 B. The advantages of the receiver circuit 300 B of the second embodiment become clear when compared with the receiver circuit 300 A of the first embodiment.

[0070] 9 is an operational waveform diagram of the receiver circuit 300A according to the first embodiment. Here, the common mode voltage fluctuation that changes from 0 V to 50 V is generated by the input signal D ｉｎ Time t during the change ２ This is occurring in.

[0071] Internal signal RX of the common voltage fluctuation suppressor circuit 330Aｐｘ As a result, the pulse signal Pulse ｎ The input signal D ｉｎ If a common mode voltage fluctuation occurs during the change of the voltage, the signal can be transmitted from the primary side to the secondary side, but this is not a desirable operation.

[0072] 10 is an operational waveform diagram of the receiver circuit 300B according to the second embodiment. Similar to FIG. 9, the common mode voltage fluctuations that change from 0 V to 50 V are generated by the input signal D ｉｎ Time t during the change ２ This is occurring in.

[0073] In the second embodiment, the ground line of the first inverter 331 is connected to the input node in2. Therefore, the voltage RX of the input node in2 is changed by the common mode voltage fluctuation. ｎ When the voltage of the first inverter 331 increases, the first inverter 331 stops operating. ｎ This prevents the output signals Doutp and Doutn from erroneously transitioning to high, thereby ensuring that the output signals Doutp and Doutn have the correct pulse widths.

[0074] The active termination circuit 310A also receives the input signal D ｉｎ This is made clear by comparison with the comparative technique 2.

[0075] (Comparative Technique 2) Comparative technique 2 is obtained by omitting the active termination circuit 310B from the receiver circuit 300B of FIG.

[0076] 11 is an operational waveform diagram of the transmission circuit according to the comparative technique 2. If the active termination circuit 310B is not present, the voltage RX ｐ Not only voltage RX ｎ The pulse signal Pulse ｐ does not reach the threshold value of the latch circuit 340B in the next stage, and the output signal Dout ｐ does not change.

[0077] In contrast, in the transmission circuit 100B according to the second embodiment, as shown in FIG. ｎ The rise of the pulse signal Pulse ｐ is generated with sufficient amplitude to prevent common mode voltage fluctuations from ｉｎ The correct output signal Dout ｐ , Dout ｎ can be generated.

[0078] 12 is a circuit diagram of a receiver circuit 300C according to Example 3. The receiver circuit 300C includes an active termination circuit 310C, a protection circuit 320C, a common voltage fluctuation suppression circuit 330C, and a latch circuit 340C.

[0079] The termination level of the active termination circuit 310C is the power supply voltage VDD2. The active termination circuit 310C includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1, and a second resistor R2. The source of the first PMOS transistor MP1 is connected to the secondary side power supply line VDD2, and the drain of the first PMOS transistor MP1 is connected to a node RX ｐｘ The source of the second PMOS transistor MP2 is connected to the secondary side power supply line VDD2, and the drain of the second PMOS transistor MP2 is connected to the node RX ｎｘ The first resistor R1 is connected in parallel with the first PMOS transistor MP1, and the second resistor R2 is connected in parallel with the second PMOS transistor MP2.

[0080] The protection circuit 320C includes diodes D1 and D2. The cathode of the diode D1 is connected to the power supply line VDD2, and the anode is connected to the RXpx node. The cathode of the diode D2 is connected to the power supply line VDD2, and the anode is connected to the RXnx node.

[0081] The common voltage fluctuation suppression circuit 330C includes a first inverter 331, a second inverter 332, a first NOR gate 333, and a second NOR gate 334. The input of the first inverter 331 is connected to the second input node in2, and the input of the second inverter 332 is connected to the first input node in1. The first input of the first NOR gate 333 is connected to the output of the first inverter 331, and the second input of the first NOR gate 333 is connected to the first input node in1. The first input of the second NOR gate 334 is connected to the output of the second inverter 332, and the second input of the second NOR gate 334 is connected to the second input node in2.

[0082] Latch circuit 340C includes a third NOR gate 342 and a fourth NOR gate 344 that are cross-coupled.

[0083] 13 is a circuit diagram of a receiver circuit 300D according to Example 4. The receiver circuit 300D includes an active termination circuit 310D, a protection circuit 320D, a common voltage fluctuation suppression circuit 330D, and a latch circuit 340D.

[0084] The configurations of the active termination circuit 310D, the protection circuit 320D, and the latch circuit 340D are the same as those in FIG.

[0085] 12, the common voltage fluctuation suppression circuit 330C includes a first inverter 331, a second inverter 332, a first NOR gate 333, and a second NOR gate 334. The power supply line of the first NOR gate 333 is connected to the second input node in2, and the power supply line of the second NOR gate 334 is connected to the first input node in1.

[0086] 14 is a circuit diagram of the first NOR gate 333 (second NOR gate 334). The first NOR gate 333 includes PMOS transistors MP21 and MP22 and NMOS transistors MN21 and MN22. The power supply line PL, which is the source of the PMOS transistor MP21, is connected to the input node in2.

[0087] 15 is a circuit diagram of a receiver circuit 300E according to Example 5. The receiver circuit 300E includes an active termination circuit 310E, a protection circuit 320E, a common voltage fluctuation suppression circuit 330E, and a latch circuit 340E.

[0088] The common voltage fluctuation suppressor circuit 330E includes a first inverter 331, a second inverter 332, a first NAND gate 335, and a second NAND gate 336. The input of the first inverter 331 is connected to a first input node in1, and the input of the second inverter 332 is connected to a second input node in2.

[0089] A first input of the first NAND gate 335 is connected to the output of the first inverter 331, and a second input of the first NAND gate 335 is connected to the second input node in2. A first input of the second NAND gate 336 is connected to the output of the second inverter 332, and a second input of the second NAND gate 336 is connected to the first input node in1.

[0090] Latch circuit 340E includes a third NAND gate 346 and a fourth NAND gate 348 that are cross-coupled.

[0091] 16 is a circuit diagram of a receiver circuit 300F according to Example 6. The receiver circuit 300F includes an active termination circuit 310F, a common voltage fluctuation suppressor circuit 330F, a latch circuit 340F, and a protection circuit (not shown in FIG. 16, 320C in FIG. 12).

[0092] The power supply line of the first inverter 331 of the common voltage fluctuation suppressor circuit 330F is connected to the second input node in2, and the power supply line of the second inverter 332 is connected to the first input node in1.

[0093] 17 is a circuit diagram of a receiver circuit 300G according to Example 7. The receiver circuit 300G includes an active termination circuit 310G, a common voltage fluctuation suppressor circuit 330G, a latch circuit 340G, and a protection circuit (not shown in FIG. 17, 320 in FIG. 1).

[0094] The configuration of the active termination circuit 310G is similar to that of the active termination circuit 310A in FIG.

[0095] The common voltage fluctuation suppression circuit 330G includes a first inverter 331, a second inverter 332, a first NAND gate 335, and a second NAND gate 336. The input of the first inverter 331 is connected to the second input node in2, and the input of the second inverter 332 is connected to the first input node in1. The first input of the first NAND gate 335 is connected to the first input node n1, and the second input of the first NAND gate 335 is connected to the output of the first inverter 331. The first input of the second NAND gate 336 is connected to the second input node n2, and the second input of the second NAND gate 336 is connected to the output of the second inverter 332.

[0096] The configuration of the latch circuit 340G is similar to that of the latch circuit 340F in FIG.

[0097] 18 is a circuit diagram of a receiver circuit 300H according to Example 8. The receiver circuit 300H includes an active termination circuit 310H, a common voltage fluctuation suppressor circuit 330H, a latch circuit 340H, and a protection circuit (not shown in FIG. 18, 320 in FIG. 1).

[0098] 17, the common voltage fluctuation suppressor circuit 330H includes a first inverter 331, a second inverter 332, a first NAND gate 335, and a second NAND gate 336. The ground line of the first NAND gate 335 is connected to the second input node in2, and the ground line of the second NAND gate 336 is connected to the first input node in1.

[0099] 19 is a circuit diagram of the first NAND gate 335 (second NAND gate 336). The first NAND gate 335 includes PMOS transistors MP31 and MP32 and NMOS transistors MN31 and MN32. The ground line GL, which is the source of the NMOS transistor MN32, is connected to the second input node in2 (in1).

[0100] 20 is a circuit diagram showing an example of the configuration of a transmission circuit 200. The transmission circuit 200 includes a first output stage 202, a second output stage 204, and a delay circuit 224. The delay circuit 224 delays an input signal D ｉｎThe first output stage 202 delays the delayed input signal D ｉｎ (D ｄｅｌａｙ ) is driven based on

[0101] The configuration of the transmission circuit 200 is not limited to that shown in FIG. 20, and known techniques can be used.

[0102] The present invention has been described using specific terms based on the embodiments, but the embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present invention defined in the claims.

[0103] (Additional Note) The following techniques are disclosed in this specification.

[0104] (Item 1) A transmission circuit comprising: a transformer having a primary winding and a secondary winding; a transmission circuit connected to the primary winding of the transformer and supplying the primary winding with a current signal having a polarity corresponding to a change in the level of an input signal; an active termination circuit connected to the secondary winding of the transformer and including a first transistor and a second transistor that are cross-coupled; a common voltage fluctuation suppression circuit formed by a combinational circuit and having first and second input nodes connected to the secondary winding of the transformer and a first and second output node, wherein when the first input node and the second input node change with the same polarity, the states of the first output node and the second output node do not change; and a latch circuit having a first input node connected to the first output node of the common voltage fluctuation suppression circuit and a second input node connected to the second output node of the common voltage fluctuation suppression circuit.

[0105] (Item 2) The transmission circuit according to item 1, further comprising a protection circuit connected to the secondary winding of the transformer.

[0106] (Item 3) The transmission circuit according to item 1 or 2, wherein the active termination circuit is configured with a depletion MOS (Metal Oxide Semiconductor) transistor or a native MOS transistor.

[0107] (Item 4) The transmission circuit according to item 1 or 2, wherein the active termination circuit is configured with an enhancement MOS (Metal Oxide Semiconductor) transistor, and the active termination circuit further includes: a first resistor connected in parallel with the first transistor; and a second resistor connected in parallel with the second transistor.

[0108] (Item 5) A transmission circuit according to any one of items 1 to 4, wherein the termination level of the active termination circuit is ground voltage, and the common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the first input node; a second inverter having an input connected to the second input node; a first NOR gate having a first input connected to the output of the first inverter and a second input connected to the second input node; and a second NOR gate having a first input connected to the output of the second inverter and a second input connected to the first input node.

[0109] (Item 6) The transmission circuit according to Item 5, wherein a ground line of the first inverter is connected to the second input node, and a ground line of the second inverter is connected to the first input node.

[0110] (Item 7) A transmission circuit according to any one of items 1 to 4, wherein the termination level of the active termination circuit is a power supply voltage, and the common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the second input node; a second inverter having an input connected to the first input node; a first NOR gate having a first input connected to the output of the first inverter and a second input connected to the first input node; and a second NOR gate having a first input connected to the output of the second inverter and a second input connected to the second input node.

[0111] (Item 8) The transmission circuit according to item 7, wherein a power supply line of the first NOR gate is connected to the second input node, and a power supply line of the second NOR gate is connected to the first input node.

[0112] (Item 9) A transmission circuit described in any one of items 1 to 4, wherein the termination level of the active termination circuit is a power supply voltage, and the common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the first input node; a second inverter having an input connected to the second input node; a first NAND gate having a first input connected to the output of the first inverter and a second input connected to the second input node; and a second NAND gate having a first input connected to the output of the second inverter and a second input connected to the first input node.

[0113] (Item 10) The transmission circuit according to item 9, wherein a power supply line of the first inverter is connected to the second input node, and a power supply line of the second inverter is connected to the first input node.

[0114] (Item 11) A transmission circuit described in any one of items 1 to 4, wherein the termination level of the active termination circuit is ground voltage, and the common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the second input node; a second inverter having an input connected to the first input node; a first NAND gate having a first input connected to the output of the first inverter and a second input connected to the second input node; and a second NAND gate having a first input connected to the output of the second inverter and a second input connected to the first input node.

[0115] (Item 12) The transmission circuit according to item 11, wherein a ground line of the first NAND gate is connected to the second input node, and a ground line of the second NAND gate is connected to the first input node.

[0116] (Item 13) The transmission circuit according to any one of items 1 to 4, wherein a termination level of the active termination circuit is a ground voltage, and the first transistor and the second transistor are NMOS transistors with their sources grounded.

[0117] (Item 14) The transmission circuit according to any one of items 1 to 4, wherein a termination level of the active termination circuit is a power supply voltage, and the first transistor and the second transistor are PMOS transistors having sources connected to a power supply line.

[0118] (Item 15) The transmission circuit according to any one of items 1 to 4, wherein the latch circuit includes a third NOR gate and a fourth NOR gate that are cross-coupled.

[0119] (Item 16) The transmission circuit according to any one of items 1 to 4, wherein the latch circuit includes a third NAND gate and a fourth NAND gate that are cross-coupled.

[0120] The present invention relates to signal transmission between two isolated domains.

[0121] T1 Transformer Wp Primary winding Ws Secondary winding 100 Transmission circuit 200 Transmitting circuit 202 First output stage 204 Second output stage 224 Delay circuit 300 Receiving circuit 310 Active termination circuit MP1 First PMOS transistor MP2 Second PMOS transistor MN1 First NMOS transistor MN2 Second NMOS transistor R1 First resistor R2 Second resistor 320 Protection circuit 330 Common voltage fluctuation suppression circuit in1 First input node in2 Second input node out1 First output node out2 Second output node 331 First inverter 332 Second inverter 333 First NOR gate 334 Second NOR gate 335 First NAND gate 336 Second NAND gate 340 Latch circuit 342 Third NOR gate 344 Fourth NOR gate 346 Third NAND gate 348 Fourth NAND gate

Claims

1. a transformer having a primary winding and a secondary winding; a transmission circuit connected to the primary winding of the transformer and configured to supply a current signal having a polarity corresponding to a change in level of an input signal to the primary winding; an active termination circuit connected to the secondary winding of the transformer and including a first transistor and a second transistor that are cross-coupled; a common voltage variation suppression circuit which is composed of a combinational circuit and has a first input node and a second input node connected to the secondary winding of the transformer, and a first output node and a second output node, and in which when the first input node and the second input node change with the same polarity, the states of the first output node and the second output node do not change; a latch circuit having a first input node connected to the first output node of the common voltage variation suppressor circuit and a second input node connected to the second output node of the common voltage variation suppressor circuit; A transmission circuit comprising:

2. The transmission circuit of claim 1 , further comprising a protection circuit connected to the secondary winding of the transformer.

3. 3. The transmission circuit according to claim 1, wherein the active termination circuit is composed of a depletion metal oxide semiconductor (MOS) transistor or a native MOS transistor.

4. the active termination circuit is composed of enhancement metal oxide semiconductor (MOS) transistors; The active termination circuit comprises: a first resistor connected in parallel with the first transistor; a second resistor connected in parallel with the second transistor; The transmission circuit according to claim 1 or 2, further comprising:

5. the termination level of the active termination circuit is ground voltage; The common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the first input node; a second inverter having an input connected to the second input node; a first NOR gate having a first input connected to the output of the first inverter and a second input connected to the second input node; a second NOR gate having a first input connected to the output of the second inverter and a second input connected to the first input node; The transmission circuit according to claim 1 or 2, comprising:

6. a ground line of the first inverter is connected to the second input node; 6. The transmission circuit according to claim 5, wherein a ground line of said second inverter is connected to said first input node.

7. the termination level of the active termination circuit is the power supply voltage; The common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the second input node; a second inverter having an input connected to the first input node; a first NOR gate having a first input connected to the output of the first inverter and a second input connected to the first input node; a second NOR gate having a first input connected to the output of the second inverter and a second input connected to the second input node; The transmission circuit according to claim 1 or 2, comprising:

8. a power supply line of the first NOR gate is connected to the second input node; 8. The transmission circuit according to claim 7, wherein a power supply line of said second NOR gate is connected to said first input node.

9. the termination level of the active termination circuit is the power supply voltage; The common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the first input node; a second inverter having an input connected to the second input node; a first NAND gate having a first input connected to the output of the first inverter and a second input connected to the second input node; a second NAND gate having a first input connected to the output of the second inverter and a second input connected to the first input node; The transmission circuit according to claim 1 or 2, comprising:

10. a power supply line of the first inverter is connected to the second input node; The transmission circuit according to claim 9 , wherein a power supply line of the second inverter is connected to the first input node.

11. the termination level of the active termination circuit is ground voltage; The common voltage fluctuation suppression circuit includes: a first inverter having an input connected to the second input node; a second inverter having an input connected to the first input node; a first NAND gate having a first input connected to the output of the first inverter and a second input connected to the second input node; a second NAND gate having a first input connected to the output of the second inverter and a second input connected to the first input node; The transmission circuit according to claim 1 or 2, comprising:

12. a ground line of the first NAND gate is connected to the second input node; 12. The transmission circuit according to claim 11, wherein a ground line of said second NAND gate is connected to said first input node.

13. the termination level of the active termination circuit is ground voltage; 3. The transmission circuit according to claim 1, wherein the first transistor and the second transistor are NMOS transistors whose sources are grounded.

14. the termination level of the active termination circuit is the power supply voltage; 3. The transmission circuit according to claim 1, wherein the first transistor and the second transistor are PMOS transistors having sources connected to a power supply line.

15. 3. The transmission circuit according to claim 1, wherein said latch circuit includes a third NOR gate and a fourth NOR gate which are cross-coupled.

16. 3. The transmission circuit according to claim 1, wherein said latch circuit includes a third NAND gate and a fourth NAND gate which are cross-coupled.