Multilayer ceramic electronic component

Abstract

The purpose of the present invention is to provide a multilayer ceramic electronic component capable of reducing ESR.　A multilayer ceramic capacitor 1 has a first external electrode 40A and a second external electrode 40B. The first external electrode 40A has a first base electrode layer 50A, a first conductive resin layer 60A including a thermosetting resin and a metal component disposed on the first base electrode layer 50A, and a first Ni plating layer 71A disposed on the first conductive resin layer 60A. The second external electrode 40B has a second base electrode layer 50B, a second conductive resin layer 60B including a thermosetting resin and a metal component disposed on the second base electrode layer 50B, and a second Ni plating layer 71B disposed on the second conductive resin layer 60B. Tensile stress remains as internal stress inside the first Ni plating layer 71A and the second Ni plating layer 71B.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, multilayer ceramic electronic components, such as multilayer ceramic capacitors, have been required to be durable in harsh environments, such as those exposed to bending stresses caused by thermal expansion. To address this demand, a technique using a thermosetting conductive resin paste for the external electrodes of multilayer ceramic electronic components has been known. Patent Document 1 (JP-A-2003-102666) describes this type of technique. Patent Document 1 describes a multilayer ceramic capacitor having external electrodes with a layered structure in which an electrode layer formed by applying a conductive paste by dipping and baking the paste, a conductive epoxy-based thermosetting resin layer, a nickel-plated layer, and a tin-based layer are sequentially laminated.

[0003] Japanese Patent Application Publication No. 11-162771

[0004] Meanwhile, in order to ensure durability in harsh environments while satisfying the required performance, various measures have been taken to reduce ESR and the like for multilayer ceramic electronic components, and further improvements in performance are being sought.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component capable of reducing ESR.

[0006] A multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of stacked ceramic layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height and width directions; first internal conductor layers arranged on the plurality of ceramic layers and exposed at the first end surfaces; second internal conductor layers arranged on the plurality of ceramic layers and exposed at the second end surfaces; a first external electrode arranged on the first end surfaces; and a second external electrode arranged on the second end surfaces. The first external electrode has a first base electrode layer containing a metal component, a first conductive resin layer containing a thermosetting resin and a metal component that is arranged on the first base electrode layer, and a first Ni plating layer that is arranged on the first conductive resin layer, and the second external electrode has a second base electrode layer containing a metal component, a second conductive resin layer containing a thermosetting resin and a metal component that is arranged on the second base electrode layer, and a second Ni plating layer that is arranged on the second conductive resin layer, and tensile stress remains as internal stress inside the first Ni plating layer, and tensile stress remains as internal stress inside the second Ni plating layer.

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component capable of reducing ESR.

[0008] 1 is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1; FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 2; FIG. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 2; FIG. 5 is an enlarged view of a V portion of the multilayer ceramic capacitor shown in FIG. 2, and is a schematic diagram for explaining the state of forces generated on the end face side of the multilayer ceramic capacitor; FIG. 6 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a double structure; FIG. 7 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a triple structure; and FIG. 8 is a schematic diagram showing an example of the configuration of a multilayer ceramic capacitor with a quadruple structure.

[0009] Embodiments A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to a first embodiment of the present disclosure will now be described with reference to FIGS. 1 to 4. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 1 taken along line II-II. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 2 taken along line III-III. FIG. 4 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 2 taken along line IV-IV.

[0010] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40 .

[0011] 1 to 4 show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T as the height direction of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as the WT cross section. The cross section shown in FIG. 4 is also referred to as the LW cross section.

[0012] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T and the width direction W.

[0013] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness or the like may be formed on part or all of the surfaces constituting the laminate 10.

[0014] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first outer layer portion 12A as a first main surface side outer layer portion and a second outer layer portion 12B as a second outer layer portion arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0016] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 in the stacking direction T to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0017] The plurality of dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., added to the above main components.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 700 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0019] The multiple internal electrode layers 30 include first internal electrode layers 31 as multiple first internal conductor layers and second internal electrode layers 32 as multiple second internal conductor layers. The multiple first internal electrode layers 31 are arranged on the multiple dielectric layers 20. The multiple second internal electrode layers 32 are arranged on the multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20 therebetween.

[0020] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32, and a first lead portion 31B led from the first opposing portion 31A to the first end face LS1. The first lead portion 31B is exposed at the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led from the second opposing portion 32A to the second end face LS2. The second lead portion 32B is exposed at the second end face LS2.

[0022] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first draw-out portion 31B and the second draw-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0024] The width direction W of the first opposing portion 31A and the width direction W of the first lead portion 31B may be the same, or one of the dimensions may be smaller. The width direction W of the second opposing portion 32A and the width direction W of the second lead portion 32B may be the same, or one of the dimensions may be smaller.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 700 or less.

[0027] The first main surface side outer layer portion 12A is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12A is an assembly of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface side outer layer portion 12A may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0028] The second main surface side outer layer portion 12B is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 12B is an assembly of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface side outer layer portion 12B may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Fig. 4 shows the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0030] The laminate 10 has side surface outer layer portions. The side surface outer layer portions include a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side surface WS2. Figures 3 and 4 show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portions are also referred to as W gaps or side gaps.

[0031] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second end surface LS2. Figures 2 and 4 show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portion is also referred to as an L gap or end gap.

[0032] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0033] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0034] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] As described above, in the laminate 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0036] The first external electrode 40A has a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A has a first Ni plating layer 71A as a lower plating layer and a first Sn plating layer 72A as an upper plating layer.

[0037] The second external electrode 40B has a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B has a second Ni plating layer 71B as a lower plating layer and a second Sn plating layer 72B as an upper plating layer.

[0038] 2 and 4, the first Ni plating layer 71A has a first end surface side Ni plating layer 71A1 and a first side surface side Ni plating layer 71A2. The first end of the first Ni plating layer 71A refers to a portion of the first Ni plating layer 71A that is closer to the second end surface LS2 than the first conductive resin layer 60A in the longitudinal direction L.

[0039] 2 and 4, the second Ni plating layer 71B has a second end surface side Ni plating layer 71B1 and a second side surface side Ni plating layer 71B2. The second end of the second Ni plating layer 71B refers to a portion of the second Ni plating layer 71B that is closer to the first end surface LS1 than the second conductive resin layer 60B in the longitudinal direction L.

[0040] Here, the layers constituting the first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to a cross section LW at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40. When there is no need to distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the base electrode layer 50. Furthermore, when it is not necessary to particularly distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, the first conductive resin layer 60A and the second conductive resin layer 60B may be collectively referred to as the conductive resin layer 60. Furthermore, when it is not necessary to particularly distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B may be collectively referred to as the plating layer 70. Furthermore, when it is not necessary to particularly distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as the Ni plating layer 71. Furthermore, when there is no need to particularly distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72. When there is no need to particularly distinguish between the first end surface side Ni plating layer 71A1 and the second end surface side Ni plating layer 71B1, the first end surface side Ni plating layer 71A1 and the second end surface side Ni plating layer 71B1 may be collectively referred to as the end surface side Ni plating layer 711. When there is no need to particularly distinguish between the first side surface side Ni plating layer 71A2 and the second side surface side Ni plating layer 71B2, the first side surface side Ni plating layer 71A2 and the second side surface side Ni plating layer 71B2 may be collectively referred to as the side surface side Ni plating layer 712.Furthermore, when there is no need to particularly distinguish between the first end face LS1 and the second end face LS2, the first end face LS1 and the second end face LS2 may be collectively referred to as end face LS.

[0041] The base electrode layer 50 includes a first base electrode layer 50A and a second base electrode layer 50B.

[0042] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. The first base electrode layer 50A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0043] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. The second base electrode layer 50B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0044] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. This improves the adhesion between the laminate 10 and the base electrode layers. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The presence of a glass component can help sinter the metal component in the base electrode layer and promote sintering. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0045] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate and then applying a conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer with a conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a layer containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be formed in multiple layers.

[0046] The longitudinal thickness of the first base electrode layer 50A located on the first end surface LS1 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0047] The longitudinal thickness of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0048] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the first base electrode layer 50A provided on this portion is preferably, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and width direction W of the first base electrode layer 50A provided on this portion.

[0049] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the widthwise thickness of the first base electrode layer 50A provided on this portion is, for example, approximately 4 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the first base electrode layer 50A provided on this portion.

[0050] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the second base electrode layer 50B provided on this portion is preferably, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0051] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the widthwise thickness of the second base electrode layer 50B provided on this portion is, for example, approximately 4 μm or more and 40 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 50B provided on this portion.

[0052] The external electrode 40 has a conductive resin layer 60 containing a resin component and a metal component that is disposed on the base electrode layer 50. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0053] The first conductive resin layer 60A is disposed so as to cover the first base electrode layer 50A. Preferably, an end of the first conductive resin layer 60A is in contact with the laminate 10. The end of the first conductive resin layer 60A refers to a portion of the first conductive resin layer 60A that is closer to the second end face LS2 than the first base electrode layer 50A in the longitudinal direction L. The second conductive resin layer 60B is disposed so as to cover the second base electrode layer 50B. Preferably, an end of the second conductive resin layer 60B is in contact with the laminate 10. The end of the second conductive resin layer 60B refers to a portion of the second conductive resin layer 60B that is closer to the first end face LS1 than the second base electrode layer 50B in the longitudinal direction L.

[0054] The longitudinal thickness of the first conductive resin layer 60A located on the first end face LS1 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the first conductive resin layer 60A.

[0055] The longitudinal thickness of the second conductive resin layer 60B located on the second end face LS2 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the second conductive resin layer 60B.

[0056] When the first conductive resin layer 60A is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and width direction W of the first conductive resin layer 60A provided on this portion.

[0057] When the first conductive resin layer 60A is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the first conductive resin layer 60A provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the first conductive resin layer 60A provided on this portion.

[0058] When the second conductive resin layer 60B is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and width direction W of the second conductive resin layer 60B provided on this portion.

[0059] When the second conductive resin layer 60B is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the second conductive resin layer 60B provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the second conductive resin layer 60B provided on this portion.

[0060] The conductive resin layer 60 is disposed on the base electrode layer 50. Then, the plating layer 70 is disposed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0061] The conductive resin layer 60 has a resin portion and conductive fillers dispersed in the resin portion.

[0062] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin portion of the conductive resin layer 60 preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0063] Because the conductive resin layer 60 contains such a resin portion, it is more flexible than the base electrode layer 50, which is made of, for example, a plating film or a fired product of a metal component and a glass component. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer 60 functions as a buffer layer. Therefore, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0064] The conductive fillers are dispersed in a substantially uniform distribution within the resin portion, and are primarily responsible for the electrical conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed within the conductive resin layer 60, providing electrical continuity between the base electrode layer 50 and the plating layer 70.

[0065] The metal constituting the conductive filler may be Ag alone, an alloy containing Ag, or a metal powder with Ag coated on its surface. Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and highly weather-resistant. Therefore, Ag metal powder is suitable as a conductive filler. Furthermore, when using a metal powder with Ag coated on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder containing any of these metal powders.

[0066] Furthermore, the conductive filler may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive filler may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0067] The shape of the conductive filler is not particularly limited. The conductive filler may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0068] The conductive filler may have an average particle size of, for example, 0.3 μm or more and 10 μm or less.

[0069] The average particle size of the conductive filler contained in the conductive resin layer 60 is measured by calculation using a laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0070] The plating layer 70 includes a first plating layer 70A and a second plating layer 70B.

[0071] The first plating layer 70A is disposed so as to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the first plating layer 70A is disposed such that the first end face-side Ni plating layer 71A1 described above is disposed on the first end face LS1, and the first side face-side Ni plating layer 71A2 described above extends from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0072] The second plating layer 70B is disposed so as to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the second plating layer 70B is disposed such that the second end face-side Ni plating layer 71B1 described above is disposed on the second end face LS2, and the second side face-side Ni plating layer 71B2 described above extends from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0073] The plating layer 70 preferably has a two-layer structure of a Ni plating layer 71 and a Sn plating layer 72. A first Sn plating layer 72A is preferably disposed on the first Ni plating layer 71A, and a second Sn plating layer 72B is preferably disposed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the base electrode layer 50 and the conductive resin layer 60 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating the mounting of the multilayer ceramic capacitor 1.

[0074] The thickness of each of the first Ni plating layer 71A and the first Sn plating layer 72A is preferably 1 μm or more and 15 μm or less.

[0075] The thickness of each of the second Ni plating layer 71B and the second Sn plating layer 72B is preferably 1 μm or more and 15 μm or less.

[0076] FIG. 5 is an enlarged view of the V portion of the multilayer ceramic capacitor 1 shown in FIG. 2 , and is a schematic diagram for explaining the state of forces generated on the end surface LS side of the multilayer ceramic capacitor 1. As described above, the first Ni plating 71A and the second Ni plating 71B have the same basic structure, and therefore, in FIG. 5 , they will be collectively referred to as the Ni plating 71. The same applies to the other layers constituting the first external electrode 40A and the second external electrode 40B. As shown in FIG. 5 , the conductive resin layer 60 is disposed on the base electrode layer 50. The plating layer 70, which will be described later, is disposed so as to cover the conductive resin layer 60. The plating layer 70 includes a Ni plating layer 71 and a Sn plating layer 72. The Ni plating layer 71 includes an end surface side Ni plating layer 711 and a side surface side Ni plating layer 712.

[0077] The Ni plating layer 71 is formed so that tensile stress is uniformly generated throughout the entire Ni plating layer 70 in a direction intersecting the thickness direction of the plating layer 70. In other words, tensile stress remains as internal stress within the Ni plating layer 71. The end-side Ni plating layer 711 experiences tensile stress in a direction intersecting the thickness direction of the plating layer 70, causing the end-side Ni plating layer 711 to shrink in a direction intersecting the thickness direction of the plating layer 70. As shown in FIG. 5 , the side-side Ni plating layers 712 formed on both ends of the end-side Ni plating layer 711 are each pulled toward the center of the end-side Ni plating layer 711. That is, the side-side Ni plating layers 712 formed on both sides of the end-side Ni plating layer 711 are each subjected to a force in a direction pressing the conductive resin layer 60 against the base electrode layer 50. This improves the conductivity of the conductive resin layer 60, and reduces the ESR (equivalent series resistance).

[0078] Furthermore, tensile stress is generated in the side-side Ni plating layer 712 in a direction intersecting the thickness direction of the plating layer 70, causing the side-side Ni plating layer 712 to shrink in a direction intersecting the thickness direction of the plating layer 70. Therefore, while the side-side Ni plating layer 712 is fastened to the conductive resin layer 60 in the circumferential direction of the side-side Ni plating layer 712, the side-side Ni plating layer 712 pulls the end-face-side Ni plating layer 711 in the length direction L, pressing the conductive resin layer 60 against the base electrode layer 50. This improves the conductivity of the conductive resin layer 60 and produces the effect of reducing ESR.

[0079] The tensile stress is preferably 50 MPa or more, which can further enhance the ESR reduction effect.

[0080] If the stress of the Ni plating layer 71 exceeds 206 MPa, it becomes difficult to manufacture the multilayer ceramic capacitor 1. Therefore, the tensile stress is preferably 206 MPa or less. This allows the multilayer ceramic capacitor 1 to be manufactured easily while further enhancing the ESR reduction effect.

[0081] If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 in the stacking direction is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. The widthwise dimension of the multilayer ceramic capacitor 1 is defined as W. The W dimension is preferably 0.1 mm or more and 10 mm or less.

[0082] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described.

[0083] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0084] On the dielectric sheets, the conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0085] A predetermined number of dielectric sheets on which no pattern of internal electrode layers is printed are stacked to form a portion that will become the first main surface side outer layer portion 12A on the first main surface TS1 side. A dielectric sheet on which the pattern of the first internal electrode layer 31 and a dielectric sheet on which the pattern of the second internal electrode layer 32 are printed are stacked in order on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layers is not printed are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface side outer layer portion 12B on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0086] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0087] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0088] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0089] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0090] Next, the conductive resin layer 60 is formed. The conductive resin layer 60 may be formed on the surface of the base electrode layer 50, or may be formed directly on the laminate 10. In this embodiment, the conductive resin layer 60 is formed on the surface of the base electrode layer 50.

[0091] First, a conductive resin paste is prepared by dispersing conductive fillers in a thermosetting resin as a base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive fillers. Therefore, the conductive fillers are uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0092] Thereafter, a conductive resin paste is applied onto the base electrode layer 50 by a dipping method, and a heat treatment is performed at a temperature of 200° C. to 550° C. This causes the resin portion to be thermally hardened, forming the conductive resin layer 60. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, it is preferable that the oxygen concentration be kept at 100 ppm or less.

[0093] Thereafter, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0094] The stress generated throughout the first Ni plating layer 71A and the second Ni plating layer 71B of the present invention can be controlled by the following method.

[0095] It is known that the stress generated in the plating varies depending on the current density applied during film formation. The current density applied to the multilayer ceramic capacitor 1 is random. At the tip end of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2, the average current density applied to each tip end from the initial stage of Ni plating film formation until the Ni plating reaches a thickness of, for example, 3 μm is the same for all surfaces of the tip end of the Ni plating layer located on the first main surface TS1, the second main surface TS2, the first side surface WS1, or the second side surface WS2. Therefore, the same stress is applied to all surfaces of the Ni plating layer 70 on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2.

[0096] The first Ni layer 71A and the second Ni plating layer 71B can be formed using a plating bath with a plating solution prepared by adjusting the amounts of Ni sulfate and Ni sulfamate added, for example. By adjusting the ratio of Ni sulfate to Ni sulfamate in the plating solution, the residual stress value inside the formed Ni plating layer 71 can be adjusted.

[0097] In this embodiment, an Sn plating layer 72 is further formed on the Ni plating layer 71, with a first Sn plating layer 72A formed on the first Ni plating layer 71A and a second Sn plating layer 72B formed on the second Ni plating layer 71B. Electrolytic plating is used to form the Sn plating layer 72. Barrel plating is preferably used as the plating method. This improves the wettability of the solder used for mounting when mounting the multilayer ceramic capacitor 1, facilitating mounting. The multilayer ceramic capacitor 1 is manufactured by the above manufacturing method.

[0098] The multilayer ceramic capacitor 1 of this embodiment has the following advantages.

[0099] In recent years, ceramic electronic components, such as multilayer ceramic capacitors, have come to be used in harsher environments than before. For example, electronic components used in mobile devices such as mobile phones and portable music players are required to be able to withstand shocks when dropped. Specifically, it is necessary to ensure that the electronic components do not fall off the mounting board or crack even when subjected to a drop shock.

[0100] Furthermore, electronic components used in in-vehicle devices such as ECUs (Electronic Control Units) are required to withstand the impact of thermal cycles. Specifically, they must be able to withstand the bending stresses that occur when a mounting board expands and contracts due to thermal cycles, preventing cracks from occurring in the electronic components.

[0101] In response to this, the use of thermosetting conductive resin paste for the external electrodes of ceramic electronic components has been proposed as a measure to prevent cracks from occurring in the main body of the ceramic electronic component even in harsh environments. For example, an epoxy-based thermosetting resin layer is formed between a conventional electrode layer and a Ni-plated layer.

[0102] In such a configuration, when stress is generated due to an impact when dropped or deflection stress is generated due to the thermal expansion and contraction of the mounting substrate caused by a thermal cycle, the stress transmitted to the mounting substrate due to distortion of the mounting substrate is released by the epoxy-based thermosetting resin layer, thereby preventing cracks from occurring in the ceramic electronic component body.

[0103] However, in the multilayer ceramic electronic component disclosed in Patent Document 1, the stress in the Ni plating layer disposed on the conductive resin layer is not specified.

[0104] In the present invention, the residual tensile stress in the Ni plating layer causes the Ni plating layer to press the conductive resin layer against the base electrode layer, compressing the conductive resin layer and increasing the amount of contact between the conductive fillers in the conductive resin layer, thereby improving the conductivity of the conductive resin layer. Therefore, it is possible to provide a multilayer ceramic electronic component with a reduced ESR and improved initial characteristics.

[0105] (1) The multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20 (ceramic layers 20), and having a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W; first internal electrode layers 31 (first internal conductor layers 31) disposed on the plurality of dielectric layers 20 and exposed at the first end surface LS1; second internal electrode layers 32 (second internal conductor layers 32) disposed on the plurality of dielectric layers 20 and exposed at the second end surface LS2; a first external electrode 40A disposed on the first end surface LS1; In the multilayer ceramic capacitor 1 having the first external electrode 40A and the second external electrode 40B formed thereon, the first external electrode 40A has a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A containing a thermosetting resin and a metal component and arranged on the first base electrode layer 50A, and a first Ni plating layer 71A arranged on the first conductive resin layer 60A, and the second external electrode 40B has a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B containing a thermosetting resin and a metal component and arranged on the second base electrode layer 50B, and a second Ni plating layer 71B arranged on the second conductive resin layer 60B, and tensile stress remains as internal stress inside the first Ni plating layer 71A, and tensile stress remains as internal stress inside the second Ni plating layer 71B.

[0106] This makes it possible to provide a multilayer ceramic electronic component capable of reducing ESR.

[0107] (2) In the multilayer ceramic capacitor 1 of this embodiment, the tensile stress generated in the first Ni plating layer 71A and the second Ni plating layer 71B is 50 MPa or more.

[0108] This allows the ESR to be further reduced.

[0109] (3) The multilayer ceramic capacitor 1 of this embodiment has a first Sn plating layer 72A disposed on the first Ni plating layer 71A and a second Sn plating layer 72B disposed on the second Ni plating layer 71B.

[0110] This makes it possible to improve the solder wettability and reduce the ESR.

[0111] (4) In the multilayer ceramic capacitor 1 of this embodiment, the first underlying electrode layer 50A contains a glass component or a ceramic component, and the second underlying electrode layer 50B contains a glass component or a ceramic component.

[0112] This makes it possible to improve the adhesion between the laminate and the underlying electrode layer while reducing the ESR.

[0113] Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors having the structures shown in Figures 1 to 4 were fabricated as samples of the example and comparative example. The samples were fabricated by controlling the stress of the Ni plating layer using the manufacturing method described above so as to achieve the stress shown in Table 1, and 22 samples were fabricated for each stress condition. The specifications of the multilayer ceramic capacitors were as follows: Dimensions of multilayer ceramic capacitor: 3.2 mm (length direction L) × 2.5 mm (width direction W) × 2.5 mm (stacking direction T) Ceramic material: BaTiO3 Capacitance: 0.01 μF Rated voltage: 50 V Structure of external electrodes (1) Base electrode layer: electrode containing conductive metal (Cu) and glass component Thickness of base electrode layer at center in height direction located on first end face and second end face: 15 μm Thickness of base electrode layer at center in length direction located on first main face and second main face, first side face and second side face: 4 μm (2) Conductive resin layer Conductive resin layer portion: conductive filler: Ag Resin: epoxy-based Heat curing temperature: 200° C. Thickness of first conductive resin layer portion at center in height direction located on first end face and second end face: 20 μm Thickness of the base electrode layer at the center in the length direction of the base electrode layer located on the first and second main surfaces, the first and second side surfaces: 20 μm (3) Ni plating layer Ni plating layer thickness: Thickness of the Ni plating layer at the center in the height direction of the Ni plating layer located on the first end surface and the second end surface: 2 μm Thickness of the Ni plating layer at the center in the length direction of the Ni plating layer located on the first and second main surfaces, the first and second side surfaces: 2.0 μm (4) Sn plating layer Sn plating layer thickness: Thickness of the Sn plating layer at the center in the height direction of the Sn plating layer located on the first and second end surfaces: 1.5 μm Thickness of the Sn plating layer at the center in the length direction of the Sn plating layer located on the first and second main surfaces, the first and second side surfaces: 1.0 μm

[0114] Next, Ni plating stress and ESR measurements were performed on the samples of the example and comparative example. The Ni plating stress and ESR measurements were performed using different multilayer ceramic capacitors manufactured in the same lot. The stress measurement of the Ni plating layer was performed using an average of n=2 data points. The ESR measurement result for each of the example and comparative example was performed using an average of n=20 data points at a measurement frequency of 1 MHz. The evaluation criteria were as follows: an ESR value of 8 mΩ or less was evaluated as "Good", a value of 10 mΩ or less was evaluated as "Average", and a value greater than 10 mΩ was evaluated as "Poor".

[0115] <Measurement of Stress of Ni Plating> Hereinafter, the measurement of stress of Ni plating in this example will be described. The stress of the Ni plating layer was measured by the following method.

[0116] First, the multilayer ceramic capacitor 1 was immersed in a metal stripping agent (Melstrip (registered trademark) HN980M manufactured by Meltex Inc.) for 5 minutes, and then rinsed with water to remove the Sn plating layer. Measurements were performed on the Ni plating layers on the first end face LS1 side and the second end face LS2 side of the multilayer ceramic capacitor 1 using X-ray diffraction (μ-XRD) in a range of φ100 μm at approximately the center of the surface of the Ni plating layers located on the first main surface TS1, the second main surface TS2, the first side surface WS1, and the second side surface WS2.

[0117] More specifically, the stress of the Ni plating layer on the first main surface TS1 was measured at the center in the length direction L and the center in the width direction W of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the first main surface TS1. The stress of the Ni plating layer on the second main surface TS2 was measured at the center in the length direction L and the center in the width direction W of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the second main surface TS2. The stress of the Ni plating layer on the first side surface WS1 was measured at the center in the length direction L and the center in the stacking direction T of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the first side surface WS1. The stress of the Ni plating layer on the second side surface WS2 was measured at the center of each of the first Ni plating layer 71A and the second Ni plating layer 71B on the second side surface WS2 in the length direction L and in the stacking direction T. The two prepared samples were measured, and the average value of the measurements at the eight locations was used as the measured stress value.

[0118] <Measurement of ESR of Multilayer Ceramic Capacitor> The measurement of ESR in this example will be described below. The ESR of the multilayer ceramic capacitor 1 was measured by subjecting the multilayer ceramic capacitor 1 to heat treatment in an air atmosphere at 150°C for 1 hour before the measurement, then mounting it on a measurement substrate, and measuring the ESR using a network analyzer at a measurement frequency of 1 MHz 24±2 hours after the completion of the heat treatment. The 20 samples produced were measured, and the average values ​​were recorded as the values ​​in Table 1 above.

[0119] From the above results, it has been shown that in the present invention, by making the stress of the Ni plating layer disposed on the conductive resin layer tensile stress, the Ni plating presses the conductive resin layer toward the base electrode layer, compressing the conductive resin layer, increasing the amount of contact between conductive fillers in the conductive resin layer, and improving the conductivity of the conductive resin layer.

[0120] Furthermore, by setting the stress of the Ni plating layer to 50 MPa or more, the effects of the present invention can be made more pronounced, and a multilayer ceramic capacitor with improved initial characteristics can be provided.

[0121] The configuration of the multilayer ceramic capacitor 1 is not limited to the configuration shown in Figures 1 to 4. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 6, 7, and 8.

[0122] The multilayer ceramic capacitor 1 shown in FIG. 6 is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33, a second internal electrode layer 34, and a floating internal electrode layer 35 that is not extended to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in FIG. 7 is a triple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 8 is a quadruple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. By providing the floating internal electrode layers 35 as the internal electrode layers 30 in this way, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby achieving a high withstand voltage for the multilayer ceramic capacitor 1. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-row structure of four or more rows.

[0123] The multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having many external electrodes.

[0124] In the above-described embodiment, a multilayer ceramic capacitor in which the dielectric layers 20 made of a dielectric ceramic are used as ceramic layers has been described as an example of the multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramics as ceramic layers, thermistors using semiconductor ceramics as ceramic layers, and inductors using magnetic ceramics as ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ceramics such as ferrite.

[0125] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0126] <1> A multilayer ceramic electronic component including: a laminate including a plurality of stacked ceramic layers, the laminate having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height and width directions; first internal conductor layers disposed on the plurality of ceramic layers and exposed at the first end surfaces; second internal conductor layers disposed on the plurality of ceramic layers and exposed at the second end surfaces; a first external electrode disposed on the first end surfaces; and a second external electrode disposed on the second end surfaces, wherein the first external electrode has a first base electrode layer containing a metal component, a first conductive resin layer disposed on the first base electrode layer and containing a thermosetting resin and a metal component, and a first Ni plating layer disposed on the first conductive resin layer, A multilayer ceramic electronic component, wherein the second external electrode includes a second base electrode layer containing a metal component, a second conductive resin layer containing a thermosetting resin and a metal component and disposed on the second base electrode layer, and a second Ni plating layer disposed on the second conductive resin layer, wherein tensile stress remains as internal stress within the first Ni plating layer, and tensile stress remains as internal stress within the second Ni plating layer. <2> The multilayer ceramic electronic component according to <1>, wherein the tensile stress is 50 MPa or more. <3> The multilayer ceramic electronic component according to <1> or <2>, wherein a first Sn plating layer is disposed on the first Ni plating layer, and a second Sn plating layer is disposed on the second Ni plating layer. <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein the first base electrode layer contains a glass component or a ceramic component, and the second base electrode layer contains a glass component or a ceramic component.

[0127] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 31 First internal electrode layer (first internal conductor layer) 32 Second internal electrode layer (second internal conductor layer) 40A First external electrode 40B Second external electrode 50A First base electrode layer 50B Second base electrode layer 60A First conductive resin layer 60B Second conductive resin layer 71A First Ni plating layer 71B Second Ni plating layer T Height direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface L Length direction LS1 First end face LS2 Second end face

Claims

1. a laminate including a plurality of laminated ceramic layers, the laminate having a first main surface and a second main surface opposed to each other in a height direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the height direction and the width direction; a first internal conductor layer disposed on the plurality of ceramic layers and exposed at the first end surface; a second internal conductor layer disposed on the plurality of ceramic layers and exposed at the second end surface; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface; In a multilayer ceramic electronic component having the first external electrode has a first base electrode layer containing a metal component, a first conductive resin layer containing a thermosetting resin and a metal component and disposed on the first base electrode layer, and a first Ni plating layer disposed on the first conductive resin layer; the second external electrode has a second base electrode layer containing a metal component, a second conductive resin layer containing a thermosetting resin and a metal component and disposed on the second base electrode layer, and a second Ni plating layer disposed on the second conductive resin layer; A tensile stress remains as an internal stress inside the first Ni plating layer, Tensile stress remains as internal stress inside the second Ni plating layer. Multilayer ceramic electronic components.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein the tensile stress is 50 MPa or more.

3. A first Sn plating layer is disposed on the first Ni plating layer; 3. The multilayer ceramic electronic component according to claim 1, further comprising a second Sn plating layer disposed on the second Ni plating layer.

4. the first base electrode layer contains a glass component or a ceramic component, 3. The multilayer ceramic electronic component according to claim 1, wherein the second base electrode layer contains a glass component or a ceramic component.