Electric power supply control device and switching electric power supply

Abstract

This electric power supply control device 200 comprises: a control circuit 180 that turns an upper-side switch 111 and a lower-side switch 112 of a switching output circuit 110 on and off, thereby driving an inductor current IL and generating an output voltage VOUT from an input voltage PVDD; an error amplifier 140 that compares a prescribed reference voltage REF and a feedback voltage FB that corresponds to the output voltage VOUT, and outputs an error signal ERR including voltage feedback information Vinfo; an information-retaining unit 230 that samples current feedback information Iinfo corresponding to the inductor current ILL flowing to the lower-side switch 112 in a period in which the lower-side switch 112 is on, and outputs a hold as a retention signal HLD in a period in which the upper-side switch 111 is on; and an off-timing control unit 190 that individually receives input of each of the error signal ERR and the retention signal HLD, and determines an off timing of the upper-side switch 111.

Description

Power supply control device, switching power supply

[0001] The present disclosure relates to a power supply control device and a switching power supply using the same.

[0002] 2. Description of the Related Art Conventionally, switching power supplies (so-called DC / DC converters) that generate a desired output voltage from an input voltage have been used as power supply means for various applications.

[0003] An example of the related art is Patent Document 1 by the applicant of the present application, which proposes a configuration in a current feedback system that detects a current flowing through a lower switch of a half bridge, in which voltage feedback information and current feedback information are added together and then input to a sample-and-hold circuit, thereby stabilizing the output feedback control loop by adjusting the timing.

[0004] International Publication No. 2019 / 244374

[0005] However, in conventional switching power supplies (particularly power supply control devices used therein), there is room for improvement in response characteristics (load response characteristics, power supply fluctuation response characteristics, etc.).

[0006] For example, a power supply control device disclosed in this specification includes: a control circuit configured to drive an inductor current by turning on / off an upper switch and a lower switch of a switching output circuit to generate an output voltage from an input voltage; an error amplifier configured to compare the output voltage or a feedback voltage corresponding to the output voltage with a predetermined reference voltage and output an error signal including voltage feedback information; an information holding unit configured to sample current feedback information corresponding to the inductor current flowing through the lower switch during an on-period of the lower switch, and hold and output the current feedback information as a hold signal including the current feedback information during an on-period of the upper switch; and an off-timing control unit configured to receive the error signal and the hold signal separately and determine the off-timing of the upper switch.

[0007] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0008] According to the present disclosure, it is possible to provide a power supply control device that can improve the response characteristics of a current feedback system that detects the current flowing through the lower switch of a half bridge, and a switching power supply that uses the same.

[0009] Fig. 1 is a diagram showing a comparative example of a switching power supply. Fig. 2 is a diagram showing a first embodiment of the switching power supply. Fig. 3 is a diagram showing an improvement effect of response characteristics in the first embodiment. Fig. 4 is a diagram showing a second embodiment of the switching power supply. Fig. 5 is a diagram showing a third embodiment of the switching power supply. Fig. 6 is a diagram showing a fourth embodiment of the switching power supply.

[0010] <Comparative Example> Fig. 1 is a diagram showing a comparative example of a switching power supply (= a general configuration to be compared with the embodiments described later). The switching power supply 100 of this comparative example is a DC / DC converter of a PWM (pulse width modulation) drive system that generates an output voltage VOUT from an input voltage PVDD and supplies the output voltage VOUT to a load Z. The switching power supply 100 can be used in a variety of fields. For example, the switching power supply 100 is suitably used as an in-vehicle secondary power supply.

[0011] Referring to this figure, the switching power supply 100 includes a switching output circuit 110, a feedback voltage generation circuit 120, a reference voltage generation circuit 130, an error amplifier 140, a ramp signal generation circuit 150, an oscillator 160, a PWM comparator 170, a control circuit 180, a lower-side current detection unit 210, an information synthesis unit 220, and an information holding unit 230.

[0012] The above components, except for some components included in switching output circuit 110 (inductor 113 and capacitor 114 in this figure), may be integrated into semiconductor integrated circuit device 200 (corresponding to a power supply control device) which serves as the main controller of switching power supply 100. Note that semiconductor integrated circuit device 200 can also incorporate any other components (such as various protection circuits) as appropriate.

[0013] The switching output circuit 110 is a step-down switching output stage that drives an inductor current IL and generates an output voltage VOUT from an input voltage PVDD by turning on and off an upper switch and a lower switch connected to form a half bridge.

[0014] Referring to the figure, the switching output circuit 110 includes an output transistor 111 , a synchronous rectifier transistor 112 , an inductor 113 , and a capacitor 114 .

[0015] The output transistor 111 is a P-channel metal oxide semiconductor field effect transistor (PMOSFET) that functions as the upper switch of the half bridge. The source of the output transistor 111 is connected to the application terminal of the input voltage PVDD. The drain of the output transistor 111 is connected to the application terminal of the switch voltage SW. The gate of the output transistor 111 is connected to the application terminal of the upper gate signal G1. The output transistor 111 is in the off state when the upper gate signal G1 is at a high level, and in the on state when the upper gate signal G1 is at a low level.

[0016] The synchronous rectifier transistor 112 is an N-channel type MOSFET (NMOSFET) that functions as the lower switch of the half bridge. The source of the synchronous rectifier transistor 112 is connected to the application terminal (=ground terminal) of the ground voltage PVSS. The drain of the synchronous rectifier transistor 112 is connected to the application terminal of the switch voltage SW. The gate of the synchronous rectifier transistor 112 is connected to the application terminal of the lower gate signal G2. The synchronous rectifier transistor 112 is turned on when the lower gate signal G2 is at a high level, and turned off when the lower gate signal G2 is at a low level.

[0017] The inductor 113 and the capacitor 114 are discrete components externally attached to the semiconductor integrated circuit device 200, and form an LC filter that rectifies and smoothes the switch voltage SW to generate the output voltage VOUT. A first end of the inductor 113 is connected to the application terminal of the switch voltage SW. A second end of the inductor 113 and a first end of the capacitor 114 are connected to the application terminal of the output voltage VOUT and the feedback voltage generation circuit 120, respectively. A second end of the capacitor 114 is connected to the ground terminal. The inductor 113 and the capacitor 114 are accompanied by resistance components DCR and ESR, respectively.

[0018] The output transistor 111 and the synchronous rectifier transistor 112 are complementarily turned on / off in response to the upper gate signal G1 and the lower gate signal G2. This on / off operation generates a square-wave switch voltage SW at the first end of the inductor 113, which is pulse-driven between the input voltage PVDD and the ground voltage GND. The term "complementary" used above includes not only the case where the on / off states of the output transistor 111 and the synchronous rectifier transistor 112 are completely reversed, but also the case where a period (dead time) during which both transistors are simultaneously off is provided.

[0019] The output format of the switching output circuit 110 is not limited to the step-down type described above, but may be any of step-up type, step-up / step-down type, and inverting type. Furthermore, the rectification method of the switching output circuit 110 is not limited to the synchronous rectification type described above, but may be a diode rectification method using a rectifier diode as a lower switch.

[0020] The output transistor 111 can also be replaced with an NMOSFET. In that case, however, a bootstrap circuit or a charge pump circuit is required to raise the high level of the upper gate signal G1 to a voltage value higher than the input voltage PVDD.

[0021] Furthermore, the output transistor 111 and the synchronous rectification transistor 112 may be externally attached to the semiconductor integrated circuit device 200 .

[0022] In particular, when a high voltage is applied to the switching output circuit 110, it is preferable to use high-voltage elements such as a power MOSFET, an IGBT (insulated gate bipolar transistor), or a SiC transistor as the output transistor 111 and the synchronous rectifier transistor 112. Furthermore, GaN devices may also be used as the output transistor 111 and the synchronous rectifier transistor 112.

[0023] The feedback voltage generating circuit 120 includes resistors 121 and 122 connected in series between an application terminal of the output voltage VOUT and a ground terminal. The feedback voltage generating circuit 120 outputs a feedback voltage FB (= a divided voltage of the output voltage VOUT) corresponding to the output voltage VOUT from a connection node of the resistors 121 and 122.

[0024] If the output voltage VOUT is within the input dynamic range of the error amplifier 140, the feedback voltage generating circuit 120 may be omitted and the output voltage VOUT may be input directly to the error amplifier 140.

[0025] Furthermore, the resistors 121 and 122 may be externally attached to the semiconductor integrated circuit device 200 .

[0026] The reference voltage generation circuit 130 generates a predetermined reference voltage REF (corresponding to a target setting value for the output voltage VOUT). It is preferable to use a DAC (digital-to-analog converter) that converts a digital reference voltage setting signal into an analog reference voltage REF as the reference voltage generation circuit 130. With this configuration, it is possible to use the reference voltage setting signal to realize a soft start operation at startup and to adjust the output voltage VOUT.

[0027] The error amplifier 140 generates an error signal ERR (=ERRP-ERRN) including voltage feedback information Vinfo according to the difference between a feedback voltage FB applied to the inverting input terminal (-) and a reference voltage REF applied to the non-inverting input terminal (+). The error signal ERR increases when the feedback voltage FB is lower than the reference voltage REF, and decreases when the feedback voltage FB is higher than the reference voltage REF.

[0028] In this figure, a current output amplifier that outputs differential current signals IP and IN is used as the error amplifier 140. The differential current signals IP and IN are currents that flow in opposite directions to each other and increase or decrease according to the difference between the feedback voltage FB and the reference voltage REF.

[0029] More specifically, when REF>FB, the differential current signal IP increases in the positive direction (= the direction flowing out of the error amplifier 140) as the difference between the two increases, and when REF<FB, the differential current signal IP increases in the negative direction (= the direction flowing into the error amplifier 140) as the difference between the two increases.

[0030] In contrast to the differential current signal IP, when REF>FB, the differential current signal IN increases in the negative direction as the difference between the two increases, and when REF<FB, the differential current signal IN increases in the positive direction as the difference between the two increases.

[0031] The lower-side current detection unit 210 detects the inductor current IL (hereinafter referred to as the lower-side inductor current ILL) that flows during the on-period of the synchronous rectification transistor 112, and acquires the current feedback information Iinfo.

[0032] For example, during the on-period of the synchronous rectifier transistor 112, a lower-side sense signal SNSL (=SW-PVSS=-ILL×RonL, where RonL is the on-resistance of the synchronous rectifier transistor 112) corresponding to the lower-side inductor current ILL is transmitted to the information combiner 220 as the current feedback information Iinfo. On the other hand, during the off-period of the synchronous rectifier transistor 112, the lower-side sense signal SNSL is fixed to a zero value. Therefore, the high level of the switch voltage SW (≈PVDD) is not transmitted to the information combiner 220.

[0033] The lower inductor current ILL can be detected by any method other than detecting the drain-source voltage of the synchronous rectifier transistor 112. For example, the voltage across a sense resistor connected in series to the synchronous rectifier transistor 112 may be detected, or the drain-source voltage of a current detection transistor connected in parallel to the synchronous rectifier transistor 112 may be detected.

[0034] The information combiner 220 generates combined feedback information VIinfo by combining the voltage feedback information Vinfo acquired by the error amplifier 140 and the current feedback information Iinfo acquired by the lower-side current detection unit 210. Referring to this figure, the information combiner 220 includes resistors 221 and 222 (each having a resistance value R).

[0035] A first terminal of the resistor 221 is connected to a first output terminal (=output terminal of the differential current signal IP) of the error amplifier 140. A second terminal of the resistor 221 is connected to a first output terminal (=output terminal of the low-side sense signal SNSL) of the low-side current detection unit 210.

[0036] A first terminal of the resistor 222 is connected to a second output terminal (=output terminal of the differential current signal IN) of the error amplifier 140. A second terminal of the resistor 222 is connected to a second output terminal (=application terminal of the ground voltage PVSS) of the lower-side current detection unit 210.

[0037] The positive differential error signal (voltage signal) output from the first terminal of resistor 221 can be expressed as ERRP=IP×R+SW. The negative differential error signal (voltage signal) output from the first terminal of resistor 222 can be expressed as ERRN=IN×R+PVSS (where IN=−IP).

[0038] Therefore, the difference signal between the differential error signals ERRP and ERRN is expressed as ERRP-ERRN=2IP×R-ILL×RonL. Here, the first term on the right-hand side (2IP×R) can be understood as the voltage feedback information Vinfo acquired by the error amplifier 140. Furthermore, the second term on the right-hand side (-ILL×RonL) can be understood as the current feedback information Iinfo acquired by the lower-side current detection unit 210. Therefore, the above difference signal (ERRP-ERRN) can be understood as the combined feedback information VIinfo obtained by combining the voltage feedback information Vinfo with the current feedback information Iinfo.

[0039] The information holding unit 230 samples the composite feedback information VIinfo during the on-period of the synchronous rectification transistor 112, and holds and outputs the sampled information as differential hold signals HLDP and HLDN during the on-period of the output transistor 111. The composite feedback information VIinfo includes current feedback information Iinfo (e.g., information about the lower peak value of the inductor current IL).

[0040] Referring to this figure, the information holding unit 230 samples the differential error signals ERRP and ERRN while the synchronous rectification transistor 112 is on, and holds and outputs the differential hold signals HLDP and HLDN while the output transistor 111 is on.

[0041] The ramp signal generating circuit 150 generates a ramp signal RAMP having a triangular waveform, a sawtooth waveform, or an n-th order slope waveform (for example, n=2) that rises during the on-period Ton of the output transistor 111. Note that the ramp signal RAMP starts to rise from zero when the output transistor 111 is turned on, and is reset to zero when the output transistor 111 is turned off, for example.

[0042] The oscillator 160 generates an ON signal ON (=clock signal) that is pulse-driven at a predetermined switching frequency fsw (=1 / Tsw).

[0043] The PWM comparator 170 generates an off signal OFF by comparing the ramp signal RAMP input to the inverting input terminal (-) (more precisely, the differential hold signal HLDN to which the ramp signal RAMP is added) with the differential hold signal HLDP input to the non-inverting input terminal (+) during the on period of the output transistor 111. The off timing of the output transistor 111 is determined by this comparison process.

[0044] The off signal OFF is at a high level when the ramp signal RAMP is lower than the error signal ERR (=ERRP-ERRN), and is at a low level when the ramp signal RAMP is higher than the error signal ERR. That is, the pulse generation timing of the off signal OFF is delayed as the error signal ERR is higher, and is accelerated as the error signal ERR is lower.

[0045] The control circuit 180 generates an upper gate signal G1 and a lower gate signal G2 in response to an on signal ON and an off signal OFF. Specifically, when a pulse is generated in the on signal ON, the control circuit 180 causes both the upper gate signal G1 and the lower gate signal G2 to fall to a low level (= a logical level when the switch voltage SW is at a high level). On the other hand, when a pulse is generated in the off signal OFF, the control circuit 180 causes both the upper gate signal G1 and the lower gate signal G2 to rise to a high level (= a logical level when the switch voltage SW is at a low level).

[0046] Therefore, the on-period Ton (=high-level period of the switch voltage SW) of the output transistor 111 becomes longer as the timing of generating the pulse of the off signal OFF becomes later, and conversely, becomes shorter as the timing of generating the pulse of the off signal OFF becomes earlier. In other words, the on-duty D (=Ton / Tsw) of the output transistor 111 becomes larger as the error signal ERR (=ERRP-ERRN) becomes higher, and becomes smaller as the error signal ERR becomes lower.

[0047] The switching power supply 100 of this embodiment can realize output feedback control of the current mode control type, which makes it possible to improve the response characteristics of the output voltage VOUT compared to output feedback control of the voltage mode control type.

[0048] In particular, the switching power supply 100 of this comparative example employs a configuration in which a lower inductor current ILL flowing through the synchronous rectifier transistor 112 is detected, rather than an inductor current IL (hereinafter referred to as an upper inductor current ILH) flowing through the output transistor 111. This configuration makes it possible to perform output feedback control of the current-mode control method without any problems, even when the on-period of the output transistor 111 is short (for example, when a high voltage is input or a low voltage is output).

[0049] In addition, in order to perform output feedback control of the current mode control method using current feedback information Iinfo corresponding to the lower inductor current ILL, an information holding unit 230 is required to hold the current feedback information Iinfo acquired during the on period of the synchronous rectification transistor 112 (= the off period of the output transistor 111).

[0050] Here, the information holding unit 230 is provided between the information combining unit 220 and the PWM comparator 170, and holds combined feedback information VIinfo obtained by combining the voltage feedback information Vinfo with the current feedback information Iinfo.

[0051] With this configuration, even if noise is superimposed on the upstream stage of the information holding unit 230 during the hold output period of the information holding unit 230, this does not affect the signal comparison process in the PWM comparator 170. Therefore, stable duty control can be achieved.

[0052] Furthermore, by adding the voltage feedback information Vinfo and the current feedback information Iinfo and then sampling and holding the result, it is possible to prevent a time discrepancy between the voltage feedback information Vinfo and the current feedback information Iinfo, thereby improving the performance of the switching power supply 100.

[0053] However, in the switching power supply 100 of this comparative example, a response delay occurs due to the sample / hold process not only in the current feedback control loop but also in the voltage feedback control loop. Therefore, there is room for further improvement in response characteristics.

[0054] In view of the above considerations, a novel embodiment capable of pushing the limits of response characteristics will be proposed below.

[0055] <First Embodiment> Figure 2 is a diagram showing a first embodiment of a switching power supply. The switching power supply 100 of this embodiment is based on the comparative example (Figure 1) described above, but further includes an adder 250, and the synthesis path of the voltage feedback information Vinfo and the current feedback information Iinfo is changed. The following description will focus on the changes.

[0056] The lower sense signal SNSL including the current feedback information Iinfo is not input to the information combiner 220 (= the second terminals of the resistors 221 and 222), but is directly input to the information holder 230. The second terminals of the resistors 221 and 222 are both connected to the ground terminal. In this way, the information combiner 220 is no longer a functional unit that combines the voltage feedback information Vinfo and the current feedback information Iinfo, but can be understood as simply a functional unit (phase compensation resistor unit) that generates differential error signals ERRP and ERRN in response to the differential current signals IP and IN.

[0057] The information holding unit 230 samples current feedback information Iinfo (e.g., information regarding the lower peak value of the inductor current IL) during the on period of the synchronous rectification transistor 112, and holds and outputs the current feedback information Iinfo as differential hold signals HLDP and HLDN during the on period of the output transistor 111.

[0058] The adder 250 adds the differential error signals ERRP and ERRN and the differential hold signals HLDP and HLDN to output differential sum signals AP and AN containing the combined feedback information VIinfo. Referring to this figure, the adder 250 includes adders 251 and 252.

[0059] The adder 251 adds the differential error signal ERRP and the differential hold signal HLDP together to output a differential addition signal AP. The adder 252 adds the differential error signal ERRN and the differential hold signal HLDN on which the ramp signal RAMP is superimposed to output a differential addition signal AN.

[0060] The PWM comparator 170 generates an off signal OFF by comparing the differential addition signal AN input to the inverting input terminal (-) with the differential addition signal AP input to the non-inverting input terminal (+) during the on period of the output transistor 111. That is, the PWM comparator 170 determines the off timing of the output transistor 111 by comparing the ramp signal RAMP with the addition signal ADD (=AP-AN).

[0061] Among the above components, the ramp signal generating circuit 150, the PWM comparator 170, and the adding unit 250 can be understood as an off-timing control unit 190 that receives the differential error signals ERRP and ERRN and the differential hold signals HLDP and HLDN individually as inputs and determines the off-timing of the output transistor 111.

[0062] In the switching power supply 100 of this embodiment, the voltage feedback information Vinfo is input directly to the PWM comparator 170 without passing through the information holding unit 230. Therefore, the voltage feedback control loop can be freely adjusted by adjusting the gain of the error amplifier 140. As a result, the response delay caused by the sample / hold process in the information holding unit 230 can be eliminated.

[0063] 3 is a diagram showing the improvement effect of the response characteristics (load response characteristics in this figure) in the first embodiment. In this figure, from top to bottom, the output voltage VOUT and the output current IOUT supplied to the load Z are depicted. Furthermore, for the output voltage VOUT, the solid line shows the behavior of the first embodiment ( FIG. 2 ), and the dashed line shows the behavior of the comparative example ( FIG. 1 ).

[0064] As shown in this figure, the switching power supply 100 of this embodiment can significantly improve response characteristics compared to the comparative example (FIG. 1). Although stability is somewhat sacrificed, the oscillation margin can be adjusted to a negligible level.

[0065] <Second Embodiment> Figure 4 is a diagram showing a second embodiment of the switching power supply 100. The switching power supply 100 of this embodiment is based on the first embodiment (Figure 2) described above, and further includes an error correction unit 240 that detects an input error Vofs (=FB-REF) of an error amplifier 140 that does not have an integral element and corrects an input signal (=at least one of the feedback voltage FB and the reference voltage REF) of the error amplifier 140. The error correction unit 240 includes a comparator 241 and a digital calibration unit 242.

[0066] The comparator 241 is a means for detecting an input error Vofs (=FB-REF) of the error amplifier 140, and generates an input error detection signal S11 by comparing a feedback voltage FB input to a non-inverting input terminal (+) with a reference voltage REF input to an inverting input terminal (-). The input error detection signal S11 goes high when FB>REF (i.e., Vofs>0), and goes low when FB<REF (i.e., Vofs<0).

[0067] The control circuit 180 generates the digital calibration signal S12 based on the input error detection signal S11 so as to reduce the input error Vofs. For example, when the input error detection signal S11 is at a high level, the digital calibration signal S12 may be generated so as to lower the feedback voltage FB, raise the reference voltage REF, or both. Conversely, when the input error detection signal S11 is at a low level, the digital calibration signal S12 may be generated so as to raise the feedback voltage FB, lower the reference voltage REF, or both.

[0068] The digital calibration unit 242 corrects at least one of the feedback voltage FB and the reference voltage REF in response to the digital calibration signal S12. A DAC or the like is preferably used as the digital calibration unit 242. Alternatively, the input error detection signal S11 may be directly input to the digital calibration unit 242, and the digital calibration signal S12 may be generated therein. In this case, the control circuit 180 is not required, and the correction process for the input error Vofs can be completed by the error correction unit 240 alone.

[0069] Next, the significance of introducing the error correction unit 240 will be described in detail.

[0070] A typical error amplifier has a phase compensation capacitor (e.g., several tens of pF) that acts as an integral element, and generates an error signal by charging and discharging this capacitor. This makes it less likely to oscillate, but it also limits the signal bandwidth, making it unsuitable for speeding up the voltage feedback control loop. On the other hand, eliminating the integral element from the error amplifier makes it possible to speed up the voltage feedback control loop, but the tradeoff is that it becomes more difficult to cancel the input error of the error amplifier.

[0071] Therefore, in the switching power supply 100 of this embodiment, an error amplifier 140 having no integral element is used to increase the speed of the voltage feedback control loop (from several tens of kHz to several MHz), while an error correction unit 240 is introduced separately from the error amplifier 140 to correct the input error Vofs of the error amplifier 140.

[0072] In this way, by parallelizing high-speed voltage feedback and error correction, it is possible to separate the design parameters of each, making it possible to achieve both high speed and high accuracy in the voltage feedback control loop. Also, unlike general error amplifiers, no phase compensation capacitor is required, which makes it possible to reduce the chip area and pin count.

[0073] <Third Embodiment> Fig. 5 is a diagram showing a third embodiment of the switching power supply 100. The switching power supply 100 of this embodiment includes an error correction unit 240, as in the second embodiment (Fig. 4) described above, but the circuit configuration is different.

[0074] More specifically, the error correction unit 240 of this embodiment includes the aforementioned comparator 241, as well as a digital calibration unit 246 and an error correction amplifier 247, and detects the input error Vofs of the error amplifier 140 and corrects the output signal (=differential error signals ERRP and ERRN) of the error amplifier 140.

[0075] The digital calibration unit 246 generates a differential input signal to the error correction amplifier 247 from the reference voltage REF in response to the digital calibration signal S12.

[0076] The error correction amplifier 247 generates correction currents IadjP and IadjN according to the differential input signals from the digital calibration unit 246 and adds them to the differential current signals IP and IN of the error amplifier 140 .

[0077] In this way, even with a configuration in which the output signal of the error amplifier 140 is corrected rather than the input signal of the error amplifier 140 being corrected, it is possible to achieve both high speed and high accuracy in the voltage feedback control loop.

[0078] <Fourth Embodiment> Fig. 6 is a diagram showing a fourth embodiment of the switching power supply 100. The switching power supply 100 of this embodiment includes an error correction unit 240, as in the second embodiment (Fig. 4) and the third embodiment (Fig. 5) described above, but the circuit configuration is different.

[0079] More specifically, the error correction unit 240 of this embodiment includes an error correction amplifier 243, a capacitor 244, and a resistor 245, and detects the input error Vofs of the error amplifier 140 and corrects the output signal (=error signal ERR) of the error amplifier 140.

[0080] In this embodiment, for the sake of simplicity, the error amplifier 140 is of a single output type. However, the error amplifier 140 may be of a differential output type, following the first embodiment (FIG. 2), the second embodiment (FIG. 4), and the third embodiment (FIG. 5) described above.

[0081] Error correction amplifier 243 generates a correction current Iadj according to the difference (=input error Vofs) between feedback voltage FB applied to its inverting input terminal (-) and reference voltage REF applied to its non-inverting input terminal (+). When FB<REF (i.e., Vofs>0), the larger the difference between the two, the larger the correction current Iadj becomes in the positive direction (=direction from the output terminal of error correction amplifier 243 toward the output terminal of error amplifier 140 via resistor 245). On the other hand, when FB>REF (i.e., Vofs<0), the larger the difference between the two, the larger the correction current Iadj becomes in the negative direction (=direction from the output terminal of error amplifier 140 toward the output terminal of error correction amplifier 243 via resistor 245).

[0082] However, error correction amplifier 243 is connected in parallel to error amplifier 140 solely as a means for correcting input error Vofs, and its current capability is kept sufficiently smaller (for example, several μA) than the current capability of error amplifier 140. In addition, a capacitor 244 with a small capacity (for example, several pF) is connected to the output terminal of error correction amplifier 243. In other words, error correction amplifier 243 can be said to be a current output type amplifier that has an integral element and is slower than error amplifier 140.

[0083] Resistor 245 (resistance value: Radj) is connected between the output terminal of error amplifier 140 and the output terminal of error correction amplifier 243, and the voltage across it is added to error signal ERR as correction voltage Vadj (= Iadj × Radj) to generate corrected error signal ERR2 (= ERR + Vadj).

[0084] For example, when FB<REF, a positive correction current Iadj flows, and the error signal ERR2 is increased by the correction voltage Vadj. As a result, the turn-off timing of the output transistor 111 is delayed by the amount of the increase in the corrected error signal ERR2, so the output voltage VOUT (and therefore the feedback voltage FB) increases and the input error Vofs decreases.

[0085] On the other hand, when FB>REF, the negative correction current Iadj flows, and the error signal ERR2 is reduced by the correction voltage Vadj. As a result, the turn-off timing of the output transistor 111 is advanced by the amount of the reduction in the corrected error signal ERR2, so that the output voltage VOUT (and therefore the feedback voltage FB) is reduced, and the input error Vofs is reduced.

[0086] In this way, by connecting the error correction amplifier 243 in parallel to the error amplifier 140, it is possible to achieve both high speed and high accuracy in the voltage feedback control loop, as in the second embodiment (FIG. 4) and the third embodiment (FIG. 5).

[0087] <Summary> The various embodiments described above will be summarized below.

[0088] For example, the power supply control device disclosed in this specification is configured (first configuration) to include: a control circuit configured to drive an inductor current by turning on / off an upper switch and a lower switch of a switching output circuit to generate an output voltage from an input voltage; an error amplifier configured to compare the output voltage or a feedback voltage corresponding to the output voltage with a predetermined reference voltage and output an error signal including voltage feedback information; an information holding unit configured to sample current feedback information corresponding to the inductor current flowing through the lower switch during an on-period of the lower switch, and hold and output the current feedback information as a hold signal including the current feedback information during an on-period of the upper switch; and an off-timing control unit configured to receive the error signal and the hold signal separately and determine the off-timing of the upper switch.

[0089] In the power supply control device according to the first configuration, the off-timing control unit may be configured (second configuration) to include an adder configured to add the error signal and the hold signal together to output an addition signal including composite feedback information, a ramp signal generation circuit configured to generate a ramp signal, and a PWM comparator configured to compare the ramp signal with the addition signal during an on-period of the upper switch to determine the off-timing of the upper switch.

[0090] Furthermore, the power supply control device according to the first or second configuration may be configured (third configuration) to further include an error correction unit configured to detect an input error of the error amplifier that does not have an integral element and correct the input signal or output signal of the error amplifier.

[0091] Furthermore, in the power supply control device according to the third configuration, the error correction unit may be configured (fourth configuration) to include a comparator that detects an input error of the error amplifier, and a digital calibration unit that is configured to correct the input signal or output signal of the error amplifier according to the detection result of the comparator.

[0092] In the power supply control device according to the third configuration, the error correction unit may be configured (fifth configuration) to include an error correction amplifier connected in parallel to the error amplifier and slower than the error amplifier.

[0093] Furthermore, the power supply control device according to any one of the first to fifth configurations may be configured to be integrated into a semiconductor integrated circuit device (sixth configuration).

[0094] Furthermore, for example, the switching power supply disclosed in this specification has a configuration (seventh configuration) that includes the switching output circuit and a power supply control device having any of the first to sixth configurations.

[0095] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0096] 100 Switching power supply 110 Switching output circuit 111 Output transistor (PMOSFET) 112 Synchronous rectification transistor (NMOSFET) 113 Inductor 114 Capacitor 120 Feedback voltage generation circuit 121, 122 Resistor 130 Reference voltage generation circuit 140 Error amplifier 150 Ramp signal generation circuit 160 Oscillator 170 PWM comparator 180 Control circuit 190 Off timing control unit 200 Semiconductor integrated circuit device (power supply control device) 210 Lower current detection unit 220 Information synthesis unit 221, 222 Resistor 230 Information holding unit 240 Error correction unit 241 Comparator 242 Digital calibration unit 243 Error correction amplifier 244 Capacitor 245 Resistor 246 Digital calibration unit 247 Error correction amplifier 250 Adder 251, 252 Adder DCR Resistance component ESR Resistance component Z Load

Claims

1. a control circuit configured to drive an inductor current by turning on and off an upper switch and a lower switch of the switching output circuit to generate an output voltage from an input voltage; an error amplifier configured to compare the output voltage or a feedback voltage corresponding to the output voltage with a predetermined reference voltage and output an error signal including voltage feedback information; an information holding unit configured to sample current feedback information corresponding to the inductor current flowing through the lower switch during an on-period of the lower switch, and to hold and output the current feedback information as a hold signal during an on-period of the upper switch; an off-timing control unit configured to receive the error signal and the hold signal separately and determine an off-timing of the upper switch; A power supply control device comprising:

2. The off timing control unit is an adder configured to add the error signal and the held signal to output a sum signal including composite feedback information; a ramp signal generating circuit configured to generate a ramp signal; a PWM comparator configured to compare the ramp signal and the sum signal during an on-period of the upper switch to determine an off-timing of the upper switch; The power control device of claim 1 .

3. 2. The power supply control device according to claim 1, further comprising an error correction unit configured to detect an input error of the error amplifier having no integral element and correct an input signal or an output signal of the error amplifier.

4. The error correction unit a comparator for detecting an input error of the error amplifier; a digital calibration unit configured to correct an input signal or an output signal of the error amplifier according to a detection result of the comparator; The power supply control device of claim 3 .

5. 4. The power supply control device according to claim 3, wherein the error correction unit includes an error correction amplifier connected in parallel to the error amplifier and slower than the error amplifier.

6. 2. The power supply control device according to claim 1, which is integrated into a semiconductor integrated circuit device.

7. the switching output circuit; A power supply control device according to any one of claims 1 to 6, A switching power supply comprising: