Chip-type electronic component

Abstract

Provided is a chip-type electronic component that is less likely to cause separation of a spacer and a mounting substrate. A chip-type electronic component 1 of the present invention comprises a multilayered ceramic capacitor 1A and spacers 10. The multilayered ceramic capacitor 1A comprises: a stack 2 that includes internal electrode layers 5 and dielectric layers 4 that are alternately disposed; and external electrodes 3. When the two surfaces of the stack 2 opposing each other in the multilayered direction are capacitor main surfaces A, the two surfaces thereof opposing each other in the width direction are capacitor side surfaces B, and the two surfaces thereof opposing each other in the length direction are capacitor end surfaces C, the external electrodes 3 are respectively provided on the capacitor end surfaces C. The spacers 10 are disposed on both sides in the length direction of the capacitor main surface A on the mounting substrate side of the multilayered ceramic capacitor 1A. When the two surfaces opposing each other in the multilayered direction of each of the spacers 10 are spacer main surfaces AS, a recess 11 is formed in the surface of the spacer main surface AS on the mounting substrate side.

Description

Chip-type electronic components

[0001] The present invention relates to a chip-type electronic component.

[0002] A multilayer ceramic capacitor includes a laminate having an inner layer portion in which dielectric layers and internal electrodes are alternately stacked, and external electrodes provided on both longitudinal end surfaces of the laminate. When a voltage is applied to the multilayer ceramic capacitor, the dielectric layers may polarize, causing the multilayer ceramic capacitor to vibrate in the polarization direction. This vibration may then be transmitted to the mounting substrate, potentially causing cracks in the mounting substrate. For this reason, a conventional technology has been proposed in which a spacer is placed on the mounting surface of the multilayer ceramic capacitor to form a chip-type electronic component, buffering the vibration with the spacer and suppressing the vibration from being transmitted to the mounting substrate (see Patent Document 1).

[0003] International Publication No. 2015 / 098990

[0004] However, for example, if a dielectric layer contains a material with a high dielectric constant, vibrations will increase, and if the bonding strength between the mounting board and the spacer is weak, the spacer may peel off from the mounting board.

[0005] An object of the present invention is to provide a chip-type electronic component in which the spacer is less likely to separate from the mounting substrate.

[0006] In order to solve the above-mentioned problems, the present invention provides a chip-type electronic component comprising: a laminate including a plurality of internal electrode layers and a plurality of internal dielectric layers arranged alternately with each other; a multilayer ceramic capacitor including external electrodes provided on each of the capacitor end faces, when two surfaces of the laminate opposing each other in the stacking direction are defined as capacitor main faces, two surfaces opposing each other in a width direction intersecting the stacking direction are defined as capacitor side faces, and two surfaces opposing each other in a length direction intersecting the stacking direction and the width direction are defined as capacitor end faces; and spacers arranged on both sides in the length direction of the capacitor main face that faces a mounting substrate of the multilayer ceramic capacitor, wherein when the two surfaces of the spacer opposing each other in the stacking direction are defined as spacer main faces, a recess is formed in the surface of the spacer main face that faces the mounting substrate.

[0007] According to the present invention, it is possible to provide a chip-type electronic component in which the spacer is less likely to separate from the mounting substrate.

[0008] FIG. 1 is a schematic perspective view of a chip-type electronic component 1 according to an embodiment. FIG. 2 is a partial cross-sectional view of the chip-type electronic component 1 taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view of the chip-type electronic component 1 taken along line III-III in FIG. 1. FIG. 4 is a diagram of the spacer 10 with the second spacer main surface AS2 facing upward. FIG. 5 is a flowchart illustrating a method for manufacturing the chip-type electronic component 1. FIG. 6 is a modified form of the partial cross-sectional view of the chip-type electronic component 1.

[0009] An embodiment of the present invention will now be described. Fig. 1 is a schematic perspective view of a chip-type electronic component 1 according to an embodiment. Fig. 2 is a partial cross-sectional view of the chip-type electronic component 1 taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the chip-type electronic component 1 taken along line III-III in Fig. 1. Figs. 1, 2, and 3 show the chip-type electronic component 1 bonded onto a mounting substrate 210.

[0010] The chip-type electronic component 1 includes a multilayer ceramic capacitor 1A having a substantially rectangular parallelepiped laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2, and a spacer 10 attached to the multilayer ceramic capacitor 1A. The laminate 2 also includes an inner layer portion 6 including multiple pairs of dielectric layers 4 and internal electrode layers 5.

[0011] In the following description, the direction in which the pair of external electrodes 3 are provided will be referred to as the length direction L, and the direction in which the dielectric layers 4 and the internal electrode layers 5 are stacked will be referred to as the stacking direction T. The direction intersecting both the length direction L and the stacking direction T will be referred to as the width direction W. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0012] Furthermore, of the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T are designated as the first capacitor main surface A1 and the second capacitor main surface A2, a pair of outer surfaces facing each other in the width direction W are designated as the first capacitor side surface B1 and the second capacitor side surface B2, and a pair of outer surfaces facing each other in the length direction L are designated as the first capacitor end surface C1 and the second capacitor end surface C2.

[0013] In addition, when there is no need to particularly distinguish between the first capacitor main surface A1 and the second capacitor main surface A2, they will be collectively referred to as the capacitor main surface A; when there is no need to particularly distinguish between the first capacitor side surface B1 and the second capacitor side surface B2, they will be collectively referred to as the capacitor side surface B; and when there is no need to particularly distinguish between the first capacitor end surface C1 and the second capacitor end surface C2, they will be collectively referred to as the capacitor end surface C.

[0014] (Laminate 2) The laminate 2 includes an inner layer portion 6, an outer layer portion 7 disposed on the capacitor main surface A side of the inner layer portion 6, and a side gap portion 8. The laminate 2 preferably has rounded ridge portions R. The ridge portions R are portions where two surfaces of the laminate 2, i.e., the capacitor main surface A and the capacitor side surface B, the capacitor main surface A and the capacitor end surface C, or the capacitor side surface B and the capacitor end surface C, intersect, and also include corners where the capacitor main surface A, the capacitor side surface B, and the capacitor end surface C intersect.

[0015] (Inner Layer Portion 6) The inner layer portion 6 includes a plurality of pairs of dielectric layers 4 and internal electrode layers 5 alternately stacked along the stacking direction T.

[0016] (Dielectric Layer 4) The dielectric layer 4 is made of a ceramic material, such as BaTiO ３ The dielectric ceramic mainly contains the above-mentioned compound. Alternatively, the ceramic material may contain at least one of a manganese compound, an iron compound, a chromium compound, a cobalt compound, a nickel compound, or the like.

[0017] (Internal Electrode Layer 5) The internal electrode layer 5 is preferably formed from a metal material typified by, for example, nickel, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0018] The internal electrode layers 5 include a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layers 5A and the second internal electrode layers 5B are arranged alternately. Note that, when there is no need to particularly distinguish between the first internal electrode layers 5A and the second internal electrode layers 5B, they will be collectively referred to as the internal electrode layers 5.

[0019] The internal electrode layers 5 include opposing portions 52 that face each other between the first internal electrode layer 5A and the second internal electrode layer 5B, and lead portions 51 that do not face each other between the first internal electrode layer 5A and the second internal electrode layer 5B and are drawn from the opposing portions 52 toward one of the capacitor end faces C. Ends of the lead portions 51 are exposed at the capacitor end face C and electrically connected to the external electrodes 3. The extending directions of the lead portions 51 differ between the first internal electrode layer 5A and the second internal electrode layer 5B, and the lead portions 51 are drawn alternately toward the first capacitor end face C1 and the second capacitor end face C2. Charge is accumulated between the opposing portions 52 of the first internal electrode layer 5A and the second internal electrode layer 5B that are adjacent in the stacking direction T, and the lead portions 51 function as a capacitor.

[0020] (Outer Layer Portions 7 ) The outer layer portions 7 are disposed on both capacitor main surface A sides of the inner layer portions 6 , and are made of the same material as the dielectric layers 4 of the inner layer portions 6 .

[0021] (Side Gap Portions 8) The side gap portions 8 are provided on both capacitor side surfaces B of the inner layer portions 6 in the laminate 2. The side gap portions 8 are manufactured integrally with the dielectric layers 4 using the same material.

[0022] (External Electrodes 3) The external electrodes 3 are provided on both capacitor end faces C of the laminate 2. That is, a first external electrode 3A is formed on the first capacitor end face C1, and a second external electrode 3B is formed on the second capacitor end face C2. The external electrodes 3 cover not only the capacitor end face C, but also parts of the capacitor main face A and the capacitor side face B on the capacitor end face C side. The external electrodes 3 include a base electrode layer 30 and a plating layer 31 formed on the outer periphery of the base electrode layer 30.

[0023] (Base electrode layer 30) The base electrode layer 30 is electrically connected to the end of the lead portion 51 of the internal electrode layer 5 exposed on the capacitor end face C. In this embodiment, the base electrode layer 30 is a so-called fired electrode obtained by firing a conductive paste containing a conductive metal such as copper, nickel, silver, palladium, a silver-palladium alloy, or gold. The fired electrode contains a glass component and a metal. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The fired electrode is obtained by applying a conductive paste containing glass and a metal to the laminate 2 and firing it. The fired electrode may be fired simultaneously with the internal electrode layer 5 and the dielectric layer 4, or may be fired after firing the internal electrode layer 5. Note that when firing simultaneously with the internal electrode layer 5 and the dielectric layer 4, it is preferable to form the fired electrode by adding a dielectric material instead of the glass component.

[0024] (Plating Layer 31) The plating layer 31 includes a Ni plating layer 31a disposed around the outer periphery of the base electrode layer 30 so as to cover the base electrode layer 30, and a Sn plating layer 31b disposed around the outer periphery of the Ni plating layer 31a so as to cover the Ni plating layer 31a. The Ni plating layer 31a prevents the base electrode layer 30 from being eroded by solder when mounting a ceramic electronic component, and the Sn plating layer 31b improves the wettability of solder when mounting the multilayer ceramic capacitor 1A, facilitating mounting. The Ni plating layer 31a is made of nickel or a nickel-containing alloy. The Sn plating layer 31b is made of Sn or a Sn-containing alloy. In addition to the above metals, the plating layer 31 may also include at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0025] (Spacer 10) The spacer 10 includes a pair of two spacers, a first spacer 10A and a second spacer 10B. Hereinafter, when it is not necessary to distinguish between the first spacer 10A and the second spacer 10B, they will be described as the spacer 10. The first spacer 10A is disposed on one side of the second capacitor main surface A2 of the multilayer ceramic capacitor 1A in the length direction L, and the second spacer 10B is disposed on the other side. The first spacer 10A and the second spacer 10B have the same substantially rectangular shape and face each other, being spaced a certain distance apart.

[0026] The spacer 10 is an approximately rectangular parallelepiped, and of its six outer surfaces, a pair of outer surfaces facing each other in the stacking direction T are the first spacer main surface AS1 and the second spacer main surface AS2, a pair of outer surfaces facing each other in the width direction W are the first spacer side surface BS1 and the second spacer side surface BS2, and a pair of outer surfaces facing each other in the length direction L are the first spacer end surface CS1 and the second spacer end surface CS2.

[0027] The first spacer main surface AS1 is the surface facing the laminate 2, and the second spacer main surface AS2 is the mounting surface that is mounted on the mounting substrate 210. The first spacer main surface AS1 of the first spacer 10A contacts the second capacitor main surface A2 side of the first external electrode formed on the first capacitor end surface C1, and the first spacer main surface AS1 of the second spacer 10B contacts the second capacitor main surface A2 side of the first external electrode formed on the second capacitor end surface C2.

[0028] The cross-sectional shape of the spacer 10 perpendicular to the stacking direction T is a rectangle with short sides extending in the length direction L and long sides extending in the width direction W. The first spacer side surface BS1 and the second spacer side surface BS2 are surfaces along the short sides of the spacer 10, and the first spacer end surface CS1 and the second spacer end surface CS2 are surfaces along the short sides of the spacer 10. The first spacer end surface CS1 of the first spacer 10A is formed on the first capacitor end surface C1 side of the first external electrode 3A, and the second spacer end surface CS2 of the second spacer 10B is formed on the second capacitor end surface C2 side of the second external electrode 3B.

[0029] In addition, when there is no need to particularly distinguish between the first spacer main surface AS1 and the second spacer main surface AS2, they will be collectively referred to as the spacer main surface AS, when there is no need to particularly distinguish between the first spacer side surface BS1 and the second spacer side surface BS2, they will be collectively referred to as the spacer side surface BS, and when there is no need to particularly distinguish between the first spacer end surface CS1 and the second spacer end surface CS2, they will be collectively referred to as the spacer end surface CS.

[0030] The spacer 10 is not limited to a rectangular parallelepiped shape, and may be another hexahedral shape in which the first spacer main surface AS1 has a larger area than the second spacer main surface AS2. Furthermore, the spacer side surface BS and the spacer end surface CS do not have to be arranged perpendicular to the second spacer main surface AS2, which is the mounting surface. Furthermore, for example, the first spacer side surface BS1, the second spacer side surface BS2, the first spacer end surface CS1, the second spacer end surface CS2, etc. may be curved surfaces.

[0031] The spacer 10 is made of a so-called high-temperature solder, which is mainly composed of an intermetallic compound containing a high-melting-point metal and a low-melting-point metal. In this specification, "mainly composed" means that the content is 50% or more. When the main component is an intermetallic compound, the reaction rate is fast and there is little change in shape.

[0032] The high-melting-point metal includes at least one of Cu and Ni, and the low-melting-point metal includes Sn. When an intermetallic compound containing a high-melting-point metal including at least one of Cu and Ni and a low-melting-point metal including Sn is used as the main component, it has a melting point that does not melt even at soldering temperatures, and can be arranged while maintaining a desired shape during soldering. Furthermore, it is particularly preferable that the intermetallic compound be an intermetallic compound produced by the reaction of Sn with a Cu-Ni alloy. Furthermore, the high-melting-point metal constituting the intermetallic compound may further include Ag.

[0033] (Conductive Resin) The spacer 10 may also be made of a conductive resin. The conductive resin contains a metal and a thermosetting resin. When the spacer 10 is made of a conductive resin, the spacer 10 is more flexible than a conductive layer made of, for example, a plating film or a baked product of a conductive paste, because the spacer 10 contains resin.

[0034] (Metal of Conductive Resin) The metal contained in the conductive resin can be Ag, Cu, or an alloy thereof. Alternatively, a metal powder with an Ag coating on its surface can be used. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu or Ni as the metal powder. Cu powder that has been subjected to an oxidation prevention treatment can also be used. The metal contained in the conductive resin is preferably contained in an amount of 35 vol% to 75 vol% of the total volume of the conductive resin. The metal contained in the conductive resin can be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical and flat metal powders. The average particle size of the metal contained in the conductive resin is not particularly limited. The average particle size of the conductive filler may be, for example, approximately 0.3 μm to 10 μm. The metal contained in the conductive resin is mainly responsible for the electrical conductivity of the conductive resin. Specifically, contact between conductive fillers forms an electrical path within the conductive resin.

[0035] (Conductive Resin) The resin contained in the conductive resin can be, for example, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin, which has excellent heat resistance, moisture resistance, adhesion, etc., is one of the most suitable resins. The resin contained in the conductive resin is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin. Furthermore, the conductive resin preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0036] (Surface Shape) The spacer 10 has recesses 11 formed on the surface of the second spacer main surface AS2, which is the mounting surface. Multiple recesses 11 are formed. Fig. 4 is a view of the spacer 10 with the second spacer main surface AS2 facing upward. According to this embodiment, by forming the recesses 11 on the surface on the second spacer main surface AS2 side, when the chip-type electronic component 1 is mounted on the mounting substrate 210, the solder 240 can enter the recesses 11, and the anchor effect can improve the adhesive strength between the solder 240 and the spacer 10.

[0037] (Total Opening Area of ​​Recesses 11) The total opening area of ​​the recesses 11 is preferably 25% to 75% of the surface area of ​​the second spacer main surface AS2. This is because if the total opening area of ​​the recesses 11 is greater than 75% of the area of ​​the second spacer main surface AS2, much of the solder 240 is trapped in the recesses 11, making it difficult for the solder 240 to reach the spacer end surface CS and spacer side surface BS of the spacer 10, thereby weakening the bonding strength between the spacer 10 and the mounting substrate 210. If the total opening area of ​​the recesses 11 is less than 25% of the entire area of ​​the second spacer main surface AS2, the bonding area between the solder 240 and the spacer 10 is reduced, and the anchor effect with the solder 240 is not sufficiently achieved. The total opening area of ​​the recesses 11 of the spacer 10 is the sum of the areas of the openings of the recesses 11 when viewed from the second spacer main surface AS2 side.

[0038] (Definition of Recess 11) The second spacer main surface AS2 of the spacer 10 is not flat but has projections and depressions. Here, the distance in the stacking direction T between the most protruding position on the second spacer main surface AS2 of the spacer 10, i.e., the apex of the convex portion, and the first spacer main surface AS1 is defined as the thickness of the spacer 10. If the second spacer main surface AS2 is abutted against a flat surface, the flat surface abuts against the apex of the convex portion of the second spacer main surface AS2. The portion of the spacer 10 within 1% of the thickness of the spacer 10 from the position of this flat surface, i.e., the apex of the convex portion, toward the first spacer main surface AS1 is considered to be included in the flat surface of the second spacer main surface AS2, and the portion recessed by more than 1% of the thickness of the spacer 10 is defined as the recess 11.

[0039] (Opening Area of ​​Each Recess 11) The opening area of ​​each recess 11 is preferably 0.1% or more and 70% or less of the surface area of ​​the second spacer main surface AS2. The reason for this is that if the opening area of ​​each recess 11 is greater than 70% of the area of ​​the second spacer main surface AS2, too much solder 240 is trapped in the recess 11, making it difficult for the solder 240 to reach the spacer end surface CS and spacer side surface BS of the spacer 10, which may reduce the bonding strength between the spacer 10 and the mounting substrate 210. If the opening area of ​​each recess 11 is smaller than 0.1% of the area of ​​the second spacer main surface AS2, the solder 240 will not sufficiently enter the recess 11 of the spacer 10, and therefore will not be able to fully benefit from the anchor effect. Furthermore, the opening area of ​​one recess 11 is more preferably 0.5% or more and 65% or less of the area of ​​the second spacer main surface AS2, even more preferably 1% or more and 60% or less, and particularly preferably 5% or more and 50% or less.

[0040] (Number of Recesses 11) The number of recesses 11 is appropriately selected so as to satisfy the above-mentioned conditions of the total opening area of ​​the recesses 11 and the opening area of ​​one recess 11.

[0041] (Internal Shape of Recess 11) There is no particular limitation on the internal shape of the recess 11. For example, the recess 11 may have a tapered shape that narrows from the second spacer main surface AS2 toward the first spacer main surface AS1, or may have an octopus-hole shape in which the interior is larger than the opening.

[0042] (Depth of Recess 11) The depth of recess 11 is preferably 1% or more and 50% or less of the thickness of spacer 10 in stacking direction T. Note that stacking direction T is the direction in which dielectric layers 4 and internal electrode layers 5 are stacked in the above-mentioned multilayer ceramic capacitor 1A, and in the case of spacer 10, it is the direction connecting first spacer main surface AS1 and second spacer main surface AS2. Note that the "depth" is the length in the stacking direction T from the opening to the bottom of recess 11.

[0043] The reason why the depth of the recess 11 is preferably 1% or more of the thickness of the spacer 10 in the stacking direction T is that if the depth of the recess 11 is less than 1%, the surface will be smooth, making it difficult to obtain the anchor effect described below.

[0044] The reason why it is preferable that the depth of the recess 11 be 50% or less of the thickness of the spacer 10 in the stacking direction T is that if the depth of the recess 11 is greater than 50%, the length of the part of the spacer 10 where the recess 11 is provided in the stacking direction T will be shortened, which may result in a decrease in the mechanical strength of the spacer 10.

[0045] In the embodiment, the recesses 11 include a mixture of recesses 11 of 1% or more but less than 5% and recesses 11 of 5% or more. The average depth of the recesses 11 of 5% or more is more preferably 5% or more but 35% or less, and even more preferably 10% or more but 20% of the thickness of the spacer 10 in the stacking direction T. It is preferable that the recesses 11 include a mixture of recesses 11 of 1% or more but less than 5% and recesses 11 of 5% or more. The recesses 11 may include only recesses 11 of 1% or more but less than 5% or only recesses 11 of 5% or more.

[0046] (Side and End Faces) It is preferable that recesses 11 are also formed on the surfaces of two spacer end faces CS of the spacer 10 that face each other in the length direction L. It is also preferable that recesses 11 are also formed on the surfaces of two spacer side faces BS of the spacer 10 that face each other in the width direction W. When recesses 11 are thus formed on the surfaces of the spacer end faces CS and the spacer side faces BS, the solder 240 wets the surfaces of the spacer end faces CS and the spacer side faces BS, thereby improving the adhesive strength between the solder 240 and the external electrodes 3.

[0047] However, as long as the recesses 11 of the spacer 10 are provided on the second spacer main surface AS2, they do not necessarily have to be provided on other surfaces. Furthermore, if recesses 11 are provided on other surfaces, they may be provided on some, not all, surfaces. The "some surfaces" may be any surfaces. For example, as long as recesses 11 are provided on the second spacer main surface AS2, they may be provided on both or one of the spacer side surfaces BS, or on both or one of the spacer end surfaces CS. If recesses 11 are provided on one of the spacer end surfaces CS1, CS2 of the first spacer 10A and CS2 of the second spacer 10B, respectively. Since the solder 240 attempting to wet and rise up the first spacer end surface CS1 and the second spacer end surface CS2 is absorbed by the recesses 11 on the end surface CS1 of the first spacer 10A and the recesses 11 on the end surface CS2 of the second spacer 10B, excessive fillet formation can be suppressed. Furthermore, the recesses 11 of the spacers 10 may be disposed on different surfaces in the first spacer 10A and the second spacer 10B, as long as they are provided on the second spacer main surface AS2.

[0048] (Mounting Board 210) The mounting board 210 on which the chip-type electronic component 1 is mounted has lands 230 arranged thereon. The lands 230 have a first land 230A and a second land 230B. The first spacer 10A is connected to the first land 230A, and the second spacer 10B is connected to the second land 230B, by solder 240, respectively.

[0049] Here, a recess 11 is formed on the surface on the second spacer main surface AS2 side, and the solder 240 fills this recess 11. Therefore, the chip-type electronic component 1 and the mounting substrate 210 are joined with high adhesive strength due to the anchor effect.

[0050] (Method for Manufacturing Chip-Type Electronic Component 1) Next, a method for manufacturing the chip-type electronic component 1 according to the embodiment will be described. Fig. 5 is a flowchart illustrating the method for manufacturing the chip-type electronic component 1. The manufacturing process for the chip-type electronic component 1 includes a laminate manufacturing step S1, an external electrode forming step S2, a spacer arranging step S3, and a recess forming step S4.

[0051] (Laminate Manufacturing Process S1) First, in the laminate manufacturing process S1, material sheets are prepared, in which patterns of internal electrode layers 5 are printed with conductive paste on ceramic green sheets for lamination, which are formed by molding ceramic slurry into sheets. Then, multiple material sheets are stacked so that the internal electrode patterns are shifted by half a pitch between adjacent material sheets in the longitudinal direction. Furthermore, outer layer ceramic green sheets, which will become outer layer portions, are stacked on both sides of the multiple stacked material sheets, and then thermocompression-bonded to form a mother block member. Multiple laminates 2 are manufactured by dividing the mother block member along cutting lines corresponding to the dimensions of the laminate.

[0052] (External Electrode Forming Step S2) Next, in the external electrode forming step S2, external electrodes 3 are formed on both ends of the laminate 2. First, the base electrode layer 30 is formed by, for example, applying a conductive paste containing a conductive metal and glass to both ends of the laminate 2 and baking it. As shown in FIG. 2 , the base electrode layer 30 is formed not only on the capacitor end faces C on both sides of the laminate 2 but also extending to the capacitor main surface A to cover a portion of the capacitor main surface A on the capacitor end face C side. Next, a Ni plating layer 31a is formed on the outer periphery of the base electrode layer 30 so as to cover the base electrode layer 30. Next, a Sn plating layer 31b is formed on the outer periphery of the Ni plating layer 31a so as to cover the Ni plating layer 31a. Through the above steps, a multilayer ceramic capacitor 1A having external electrodes 3 formed on the laminate 2 is manufactured.

[0053] (Spacer Arranging Step S3) In the spacer arranging step S3, an intermetallic compound paste, which is the material of the spacers 10, is arranged on the outer periphery of the external electrode 3 on the second capacitor main surface A2 side of the multilayer ceramic capacitor 1A.

[0054] The intermetallic compound paste is a so-called high-temperature solder whose main component is an intermetallic compound containing at least one of Cu and Ni as a high-melting-point metal and Sn as a low-melting-point metal. Such an intermetallic compound paste is applied to the surface of the Sn plating layer 31b in a liquid state after being melted at 200°C or higher. High-temperature solder has a melting point that does not melt even at general soldering temperatures, and it can be applied while maintaining the desired shape during soldering.

[0055] (Recess Forming Step S4) Before the high-temperature solder hardens, the intermetallic compound paste is bonded to, for example, an alumina plate from the second main surface side, forming a plate with the desired irregularities that will not be bonded to the high-temperature solder. After the intermetallic compound paste hardens, the alumina plate is removed. This allows the recesses 11 to be formed on the second spacer main surface AS2 of the spacer 10. The recesses 11 on the spacer end surface CS and the spacer side surface BS can be formed by, for example, arranging the alumina plate so that it wraps around the end surface and side surface. The area and depth of the recesses 11 can be adjusted by adjusting the area and height of the irregularities formed on the alumina plate.

[0056] When forming recesses 11 having a depth of 5% or more of the thickness of spacer 10 in the stacking direction T, such a method of abutting an alumina plate is preferable. When the depth of recesses 11 is 1% or more and less than 5% of the thickness of spacer 10 in the stacking direction T, a method of forming recesses 11 by sandblasting or the like is preferable. However, regardless of the depth of recesses 11, either method may be used to form recesses 11.

[0057] The method for forming the recesses 11 is not limited to this, and other methods may be used. For example, after the intermetallic compound paste has hardened, the recesses may be formed by roughening the hardened surface with a file or by a chemical method such as etching. The chip-type electronic component 1 is manufactured by the above steps.

[0058] As described above, according to the chip-type electronic component 1 of this embodiment, a recess 11 is formed on the surface on the second spacer main surface AS2 side, so that when the chip-type electronic component 1 is mounted on the mounting substrate 210, the solder 240 enters the recess 11, and the anchor effect improves the adhesive strength between the solder 240 and the spacer 10.

[0059] 2, the solder 240 may be disposed not only between the spacer 10 and the land 230, but also in some cases as shown in Fig. 6, where the solder 240 covers the spacer 10 and also covers the side surfaces of the external electrodes 3. In the spacer 10 of the embodiment, recesses 11 are formed also on the surfaces of the spacer end faces CS and the spacer side faces BS, so that when the solder 240 covers the spacer 10 and also covers the side surfaces of the external electrodes 3 as shown in Fig. 6, the solder 240 penetrates into the surface recesses 11 on the surfaces of the spacer end faces CS and the spacer side faces BS, thereby providing a stronger anchor effect and further improving the fixing strength between the solder 240 and the spacer 10.

[0060] Although the preferred embodiments of the present invention have been described above, the present invention also includes the following combinations: <1> A chip-type electronic component comprising: a laminate including a plurality of internal electrode layers and a plurality of internal dielectric layers arranged alternately with each other, a multilayer ceramic capacitor including external electrodes provided on each of the capacitor end faces, when two surfaces of the laminate facing each other in the stacking direction are defined as capacitor main faces, two surfaces facing each other in a width direction intersecting the stacking direction are defined as capacitor side faces, and two surfaces facing each other in a length direction intersecting the stacking direction and the width direction are defined as capacitor end faces, and spacers arranged on both sides in the length direction of the capacitor main face that faces a mounting substrate of the multilayer ceramic capacitor, wherein when the two surfaces of the spacer facing each other in the stacking direction are defined as spacer main faces, a recess is formed in the surface of the spacer main face that faces the mounting substrate.

[0061] <2> The chip-type electronic component according to <1>, wherein the spacer is mainly composed of an intermetallic compound containing a high-melting-point metal and a low-melting-point metal.

[0062] <3> The chip-type electronic component according to <2>, wherein the high-melting-point metal includes at least one of Cu and Ni, and the low-melting-point metal includes Sn.

[0063] <4> The chip-type electronic component according to <1>, wherein the spacer is made of a conductive resin.

[0064] <5> A chip-type electronic component according to any one of <1> to <4>, wherein the total opening area of ​​the recesses of the spacer is 25% to 75% of the surface area of ​​the main surface of the spacer on the mounting substrate side.

[0065] <6> A chip-type electronic component described in any one of <1> to <5>, wherein the opening area of ​​one of the recesses of the spacer is 0.1% or more and 70% or less of the surface area of ​​the main surface of the spacer on the mounting substrate side.

[0066] <7> The chip-type electronic component according to any one of <1> to <6>, wherein the depth of the recess in the stacking direction is 1% to 50% of the thickness of the spacer in the stacking direction.

[0067] <8> The chip-type electronic component according to any one of <1> to <7>, wherein the spacer has recesses formed on the surfaces of two spacer end faces CS that face each other in the length direction.

[0068] <9> The chip-type electronic component according to any one of <1> to <8>, wherein the spacer has recesses formed on the surfaces of two spacer side surfaces that face each other in the width direction.

[0069] the first spacer end face is in contact with a portion of a first external electrode of the external electrodes that is disposed on the side of the first capacitor end face, the second spacer end face is in contact with a portion of a second external electrode of the external electrodes that is disposed on the side of the second capacitor end face, the second spacer end face is in contact with a portion of a first external electrode of the external electrodes that is disposed on the side of the second capacitor end face, the second spacer end face is in contact with a portion of a second external electrode of the external electrodes that is disposed on the side of the second capacitor end face, the second spacer end face is in contact with a portion of a first external electrode of the external electrodes that is disposed on the side of the second capacitor end face, the first spacer end face being a surface of the first spacer that is on the side of the first capacitor end face, and the second spacer end face is in contact with a portion of a second external electrode of the second spacer that is on the side of the second capacitor end face, the first spacer end face being a surface of the first spacer that is on the side of the second capacitor end face, the second spacer end face being a surface of the second spacer that is on the side of the second capacitor end face.

[0070] A Capacitor main surface B Capacitor side surface C Capacitor end surface AS Spacer main surface AS1 First spacer main surface AS2 Second spacer main surface BS Spacer side surface CS Spacer end surface 1 Chip-type electronic component 1A Multilayer ceramic capacitor 2 Laminate 3 External electrode 4 Dielectric layer 5 Internal electrode layer 10 Spacer 10A First spacer 10B Second spacer 11 Recess 210 Mounting substrate 230 Land 230A First land 230B Second land 240 Solder

Claims

1. A chip-type electronic component comprising: a laminate including a plurality of internal electrode layers and a plurality of internal dielectric layers arranged alternately; a multilayer ceramic capacitor having, when two surfaces of the laminate opposing each other in the stacking direction are defined as capacitor main surfaces, two surfaces opposing each other in a width direction intersecting the stacking direction are defined as capacitor side surfaces, and two surfaces opposing each other in a length direction intersecting the stacking direction and the width direction are defined as capacitor end surfaces, external electrodes provided on each of the capacitor end surfaces; and spacers arranged on both sides in the length direction of the capacitor main surface that faces a mounting substrate of the multilayer ceramic capacitor, wherein, when the two surfaces of the spacer opposing each other in the stacking direction are defined as spacer main surfaces, a recess is formed in the surface of the spacer main surface that faces the mounting substrate.

2. The chip-type electronic component according to claim 1, wherein the spacer is mainly composed of an intermetallic compound containing a high-melting-point metal and a low-melting-point metal.

3. The chip-type electronic component according to claim 2, wherein the high-melting-point metal includes at least one of Cu and Ni, and the low-melting-point metal includes Sn.

4. The chip-type electronic component according to claim 1, wherein the spacer is made of a conductive resin.

5. The chip-type electronic component according to claim 1, wherein the total opening area of ​​the recesses of the spacer is 25% to 75% of the surface area of ​​the main surface of the spacer on the mounting substrate side.

6. The chip-type electronic component according to claim 1, wherein the opening area of ​​one of the recesses of the spacer is 0.1% to 70% of the surface area of ​​the main surface of the spacer on the mounting substrate side.

7. The chip-type electronic component according to claim 1, wherein the depth of the recess in the stacking direction is 1% to 50% of the thickness of the spacer in the stacking direction.

8. The chip-type electronic component according to claim 1, wherein the spacer has recesses formed on the surfaces of two spacer end faces that face each other in the length direction.

9. The chip-type electronic component according to claim 1, wherein the spacer has recesses formed on the surfaces of two spacer side surfaces that face each other in the width direction.

10. The chip-type electronic component according to claim 1, wherein one of the two capacitor end faces of the laminate is designated as a first capacitor end face and the other is designated as a second capacitor end face, and the face of the two capacitor main faces facing the spacer is designated as a second capacitor main face, and when one of the two spacer end faces facing each other in the length direction of each of the spacers is designated as a first spacer end face and the other is designated as a second spacer end face, the spacer has: a first spacer in contact with a portion of a first external electrode of the external electrodes arranged on the side of the first capacitor end face that extends toward the second capacitor main face; and a second spacer in contact with a portion of a second external electrode of the external electrodes arranged on the side of the second capacitor end face that extends toward the second capacitor main face, and a recess is formed in the first spacer end face that is the face of the first spacer that faces the first capacitor end face, and a recess is formed in the second spacer end face that is the face of the second spacer that faces the second capacitor end face.