Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a semiconductor circuit part; a first conduction member electrically connected to the semiconductor circuit part; a second conduction member electrically connected to the semiconductor circuit part; an insulating member which is in contact with the first conduction member and the second conduction member; and a sealing resin which covers the semiconductor circuit part, the first conduction member, the second conduction member, and a portion of the insulating member. The first conduction member and the second conduction member are fixed by the insulating member.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, semiconductor devices in which semiconductor elements such as diodes or transistors are covered with a resin package have been known (see, for example, Patent Document 1). The semiconductor device described in Patent Document 1 includes first to third lead frames, a power semiconductor chip, a first inner lead, a second inner lead, and a molding resin. The power semiconductor chip includes a first power semiconductor chip bonded to the first lead frame and a second power semiconductor chip bonded to the second lead frame. The first and second power semiconductor chips each function as a switching element. The first inner lead connects the first power semiconductor chip to the second lead frame. The second inner lead connects the second power semiconductor chip to the third lead frame. In a manufacturing process of such a semiconductor device, the two inner leads are individually positioned.

[0003] Japanese Patent Application Laid-Open No. 2021-166215

[0004] In the semiconductor device described in Patent Document 1, the two inner leads must be arranged individually. In other words, it is difficult to arrange the two individual inner leads together. Therefore, in the conventional semiconductor device, there is still room for improvement in terms of improving production efficiency.

[0005] An object of the present disclosure is to provide an improved semiconductor device and a method for manufacturing the semiconductor device, and in particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that improve production efficiency.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor circuit unit, a first conductive member electrically connected to the semiconductor circuit unit, a second conductive member electrically connected to the semiconductor circuit unit, an insulating member in contact with the first conductive member and the second conductive member, and a sealing resin covering the semiconductor circuit unit, the first conductive member, the second conductive member, and a portion of the insulating member. The first conductive member and the second conductive member are fixed by the insulating member.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure includes the steps of preparing a lead frame including a first conductive member and a second conductive member, fixing the first conductive member and the second conductive member in the lead frame state with an insulating member, joining the first conductive member and the second conductive member to a semiconductor circuit unit while they are fixed with the insulating member, and forming a sealing resin that covers the first conductive member, the second conductive member, and the semiconductor circuit unit.

[0008] According to the above configuration, it is possible to improve production efficiency.

[0009] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. FIG. 3 is a view showing the sealing resin in the plan view of FIG. 2, with the sealing resin indicated by imaginary lines. FIG. 4 is a partially enlarged view of FIG. 3. FIG. 5 is a bottom view showing the semiconductor device according to the first embodiment. FIG. 6 is a front view showing the semiconductor device according to the first embodiment. FIG. 7 is a right side view showing the semiconductor device according to the first embodiment. FIG. 8 is a partially enlarged view of FIG. 7, with the sealing resin indicated by imaginary lines. FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 3. FIG. 10 is a partially enlarged view of FIG. 9. FIG. 11 is a partially enlarged view of FIG. 9. FIG. 12 is a partially enlarged view of FIG. 9. FIG. 13 is a cross-sectional view taken along line XIII-XIII of FIG. 3. FIG. 14 is a partially enlarged view of FIG. 13. FIG. 15 is a cross-sectional view taken along line XV-XV of FIG. 3. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 3 . FIG. 17 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to the first embodiment. FIG. 18 is a plan view illustrating a step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 19 is a plan view illustrating a step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 20 is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 21 is a plan view illustrating a semiconductor device according to a first modified example of the first embodiment, with the sealing resin indicated by imaginary lines. FIG. 22 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a first modified example of the first embodiment. FIG. 23 is a plan view illustrating a semiconductor device according to a second modified example of the first embodiment, with the sealing resin indicated by imaginary lines. FIG. 24 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a second modified example of the first embodiment. FIG. 25 is a plan view illustrating a semiconductor device according to a third modified example of the first embodiment, with the sealing resin indicated by imaginary lines. FIG. 26 is a diagram illustrating an example of a circuit configuration of a semiconductor device according to a third modified example of the first embodiment. Fig. 27 is a plan view showing a semiconductor device according to a second embodiment, in which a sealing resin is indicated by imaginary lines. Fig. 28 is a partially enlarged view of a part of Fig. 27. Fig. 29 is a cross-sectional view taken along line XXIX-XXIX in Fig. 27.FIG. 30 is a diagram showing an example of a circuit configuration of a semiconductor device according to the second embodiment. FIG. 31 is a plan view showing a semiconductor device according to a first modified example of the second embodiment, in which the sealing resin is shown by imaginary lines. FIG. 32 is a plan view showing a semiconductor device according to a second modified example of the second embodiment, in which the sealing resin is shown by imaginary lines. FIG. 33 is a plan view showing a semiconductor device according to a third modified example of the second embodiment, in which the sealing resin is shown by imaginary lines. FIG. 34 is a cross-sectional view showing a semiconductor device according to a modified example, corresponding to the cross-section of FIG. 13. FIG. 35 is a cross-sectional view showing a semiconductor device according to a modified example, corresponding to the cross-section of FIG. 13. FIG. 36 is an enlarged plan view of a main portion of a semiconductor device according to a modified example. FIG. 37 is a cross-sectional view showing the semiconductor device of FIG. 36, corresponding to the cross-section of FIG. 9. FIG. 38 is an enlarged plan view of a main portion of a semiconductor device according to a modified example. FIG. 39 is a cross-sectional view showing a semiconductor device according to a modified example, corresponding to the cross-section of FIG. 13. FIG. 40 is an enlarged plan view of a main portion of a semiconductor device according to a modified example. FIG. 41 is a front view showing the semiconductor device of FIG. 40, in which the sealing resin is indicated by imaginary lines.

[0010] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant descriptions will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, "an object A (is made of) a certain material C" includes "an object A (is made of) a certain material C" and "an object A (is made of) a certain material C as its main component."

[0012] 1 to 17 show a semiconductor device A10 according to a first embodiment. The semiconductor device A10 includes a first mounting portion 10A, a second mounting portion 10B, a plurality of terminal leads 13, a semiconductor circuit portion 20, two conductive members 31 and 32, a plurality of conductive members 41A, 41B, 42A, and 42B, a sealing resin 50, and an insulating member 60. The plurality of terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a sixth terminal lead 172, a fifth terminal lead 181, and a seventh terminal lead 182. The semiconductor circuit portion 20 includes a first chip 21 and a second chip 22.

[0013] For ease of explanation, the thickness direction of the semiconductor device A10 will be referred to as the "thickness direction z." In the following explanation, one side of the thickness direction z may be referred to as the upper side, and the other side as the lower side. Note that terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. Furthermore, "plan view" refers to the view in the thickness direction z. The direction perpendicular to the thickness direction z is referred to as the "first direction x." The direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y."

[0014] The semiconductor device A10 converts a DC power supply voltage applied to a first terminal lead 14 and a second terminal lead 15 of the plurality of terminal leads 13 into an AC voltage using a semiconductor circuit unit 20 (a first chip 21 and a second chip 22). The converted AC voltage is input to a power supply target such as a motor from a third terminal lead 16 of the plurality of terminal leads 13. The semiconductor device A10 is used in a power conversion circuit such as an inverter.

[0015] As shown in Figures 3 and 9, the first mounting portion 10A and the second mounting portion 10B are positioned apart from each other in the first direction x. The first mounting portion 10A, the second mounting portion 10B, and the multiple terminal leads 13 are configured from the same lead frame. The lead frame is made of copper (Cu) or a copper alloy. Therefore, the first mounting portion 10A, the second mounting portion 10B, and the multiple terminal leads 13 each contain copper. Each of the first mounting portion 10A and the second mounting portion 10B is, for example, approximately rectangular in plan view.

[0016] As shown in FIG. 9 , the first mounting portion 10A and the second mounting portion 10B each have a main surface 101 and a back surface 102. The main surface 101 and the back surface 102 described below are common to the first mounting portion 10A and the second mounting portion 10B unless otherwise specified. The main surface 101 faces one side (upward) in the thickness direction z. The main surface 101 is covered with a sealing resin 50. A first chip 21 is mounted on the main surface 101 of the first mounting portion 10A. The back surface 102 of the first mounting portion 10A faces the side opposite the first chip 21 in the thickness direction z. A second chip 22 is mounted on the main surface 101 of the second mounting portion 10B. The back surface 102 of the second mounting portion 10B faces the side opposite the second chip 22 in the thickness direction z. The back surface 102 is exposed from the sealing resin 50. The rear surface 102 is plated with, for example, tin (Sn).

[0017] As shown in FIGS. 3, 5, and 9 to 11, the sealing resin 50 covers the semiconductor circuit unit 20 (the first chip 21 and the second chip 22), the two conductive members 31 and 32, and at least a portion of each of the first mounting portion 10A and the second mounting portion 10B. The sealing resin 50 also covers a portion of each of the terminal leads 13 and the conductive members 41A, 41B, 42A, and 42B. The sealing resin 50 has electrical insulation properties. The sealing resin 50 includes, for example, a black epoxy resin. As shown in FIG. 2, the dimension L1 of the sealing resin 50 in the first direction x is longer than the dimension L2 of the sealing resin 50 in the second direction y. The sealing resin 50 has a resin main surface 51, a resin back surface 52, a pair of first side surfaces 53, a second side surface 54, a third side surface 55, a plurality of recesses 56, a groove 57, and a plurality of recesses 581 and 582.

[0018] 9, the resin main surface 51 faces the same side as the main surfaces 101 of the first mounting portion 10A and the second mounting portion 10B in the thickness direction z. As shown in Fig. 9, the resin back surface 52 faces the opposite side to the resin main surface 51 in the thickness direction z. As shown in Fig. 5, the back surfaces 102 of the first mounting portion 10A and the second mounting portion 10B are exposed from the resin back surface 52.

[0019] 2 , 5 , and 6 , the pair of first side surfaces 53 are spaced apart from each other in the first direction x. The pair of first side surfaces 53 face the first direction x and extend in the second direction y. The pair of first side surfaces 53 are connected to the resin main surface 51 and the resin back surface 52.

[0020] 2, 5, and 7, the second side surface 54 and the third side surface 55 are spaced apart from each other in the second direction y. The second side surface 54 and the third side surface 55 face opposite each other in the second direction y and extend in the first direction x. The second side surface 54 and the third side surface 55 are connected to the resin main surface 51 and the resin back surface 52. As shown in FIG. 6, a plurality of terminal leads 13 are exposed from the third side surface 55.

[0021] 2 , 5 , and 6 , the plurality of recesses 56 are recessed in the second direction y from the third side surface 55 and extend in the thickness direction z from the resin main surface 51 to the resin back surface 52. In the first direction x, the plurality of recesses 56 are located individually between the seventh terminal lead 182 and the third terminal lead 16, between the third terminal lead 16 and the first terminal lead 14, between the first terminal lead 14 and the second terminal lead 15, and between the second terminal lead 15 and the fifth terminal lead 181.

[0022] 5, 6, and 9, the groove 57 is recessed from the resin rear surface 52 in the thickness direction z and extends along the second direction y. Both sides of the groove 57 in the second direction y are connected to the second side surface 54 and the third side surface 55. When viewed in the thickness direction z, the groove 57 separates the rear surface 102 of the first mounting portion 10A from the rear surface 102 of the second mounting portion 10B.

[0023] As shown in FIGS. 1 , 6 , 7 , and 9 , each of the recesses 581, 582 is recessed from the resin main surface 51 in the thickness direction z. The planar shape of each of the recesses 581, 582 is not particularly limited, but is circular in the illustrated example. Each of the recesses 581 overlaps the first mounting portion 10A in planar view. In the illustrated example, the recesses 581 are individually located near the four corners of the first mounting portion 10A in planar view. Each of the recesses 582 overlaps the second mounting portion 10B in planar view. In the illustrated example, the recesses 582 are individually located near the four corners of the second mounting portion 10B in planar view. The recesses 581 are formed by pins for fixing the first mounting portion 10A during the manufacturing of the semiconductor device A10. The pins are pressed against the first mounting portion 10A to fix the first mounting portion 10A before the sealing resin 50 is formed. In this state, the formation of the sealing resin 50 begins. Then, the pin is pulled out before the formation of the sealing resin 50 is completed. As a result, the sealing resin 50 is formed in at least a part of the area where the pin was located, so that the main surface 101 of the first mounting portion 10A is covered with the sealing resin 50. The multiple recesses 581 are marks formed by the molding process of the sealing resin 50. Similarly, the multiple recesses 582 are formed by pins for fixing the second mounting portion 10B during the manufacture of the semiconductor device A10. The multiple recesses 582 are marks formed by the molding process of the sealing resin 50.

[0024] As shown in FIGS. 4 and 5 , the first mounting portion 10A and the second mounting portion 10B have a first end face 111, a second end face 112, a third end face 113, and a fourth end face 114. The first end face 111, the second end face 112, the third end face 113, and the fourth end face 114 are covered with the sealing resin 50. The first end face 111 faces in the first direction x and extends in the second direction y. The first end face 111 is located closest to the pair of first side faces 53 of the sealing resin 50. The second end face 112 faces in the second direction y and extends in the first direction x. The second end face 112 is located closest to the second side face 54 of the sealing resin 50. The third end face 113 faces the opposite side to the second end face 112 in the second direction y and extends in the first direction x. The third end face 113 is located closest to the third side surface 55 of the sealing resin 50. The fourth end face 114 faces the opposite side to the first end face 111 in the first direction x and extends in the second direction y. As shown in Figure 9, a groove portion 57 is located between the fourth end face 114 of the first mounting portion 10A and the fourth end face 114 of the second mounting portion 10B.

[0025] As shown in FIGS. 8 and 13 , the distance P2 between the third end face 113 and the third side face 55 is longer than the distance P1 between the second end face 112 and the second side face 54 .

[0026] 12 , the second mounting portion 10B has a first seating surface 103 and a first upright surface 104. The first seating surface 103 faces the same side as the main surface 101 in the thickness direction z and is located between the main surface 101 and the back surface 102 in the thickness direction z. The first seating surface 103 is connected to the fourth end surface 114. The first upright surface 104 faces a direction perpendicular to the thickness direction z and is connected to the first seating surface 103 and the main surface 101. The first seating surface 103 and the first upright surface 104 form a step on the second mounting portion 10B.

[0027] Each of the first chip 21 and the second chip 22 is, for example, a transistor. The transistor is, for example, any one of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a bipolar transistor, and an IGBT (Insulated Gate Bipolar Transistor). In this embodiment, the first chip 21 and the second chip 22 are each an RC-IGBT with a built-in reverse conducting diode, as shown in FIG. 17 . Note that the first chip 21 and the second chip 22 may also be an IGBT without a built-in reverse conducting diode. Each of the first chip 21 and the second chip 22 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon (Si) or silicon carbide (SiC).

[0028] The first chip 21 is mounted on the first mounting portion 10A as shown in Figures 3, 4, 9, and 10. Preferably, in a plan view, the center of gravity of the first chip 21 overlaps the center of the first mounting portion 10A. The center of the first mounting portion 10A is the center when the first mounting portion 10A is divided into Nx portions (Nx is a positive odd number) in the first direction x, and is also the region corresponding to the center when the first mounting portion 10A is divided into Ny portions (Ny is a positive odd number) in the second direction y. Nx and Ny are not limited to any particular value, but may be, for example, 3 or 5.

[0029] 10 , the first chip 21 has a first main surface 21a and a first back surface 21b. The first main surface 21a and the first back surface 21b are spaced apart in the thickness direction z. The first main surface 21a faces the same direction as the main surface 101 of the first mounting portion 10A. The first back surface 21b faces the opposite side to the first main surface 21a in the thickness direction z and faces the main surface 101 of the first mounting portion 10A.

[0030] As shown in FIGS. 4 and 10, the first chip 21 has a first principal surface electrode 211 , a plurality of principal surface electrodes 212 and 214 , and a first back surface electrode 213 .

[0031] The first principal surface electrode 211 is disposed on the first principal surface 21a. A current corresponding to the power converted by the first chip 21 flows through the first principal surface electrode 211. In an example where the first chip 21 is an IGBT, the first principal surface electrode 211 is, for example, an emitter electrode, and in an example where the first chip 21 is a MOSFET, the first principal surface electrode 211 is, for example, a source electrode. The first principal surface electrode 211 includes multiple metal plating layers. The first principal surface electrode 211 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. Alternatively, the first principal surface electrode 211 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.

[0032] The principal surface electrode 212 is disposed on the first principal surface 21 a. A first drive signal (gate voltage) for driving the first chip 21 is applied to the principal surface electrode 212. The principal surface electrode 212 is, for example, a gate electrode in either the case where the first chip 21 is an IGBT or a MOSFET. In a plan view, the area of ​​the principal surface electrode 212 is smaller than the area of ​​the first principal surface electrode 211.

[0033] The pair of principal surface electrodes 214 are arranged on the first principal surface 21 a. Each of the pair of principal surface electrodes 214 has the same potential as the first principal surface electrode 211. In an example where the first chip 21 is an IGBT, each of the pair of principal surface electrodes 214 is, for example, an emitter sense electrode, and in an example where the first chip 21 is a MOSFET, each of the pair of principal surface electrodes 214 is, for example, a source sense electrode. The pair of principal surface electrodes 214 are arranged on both sides of the principal surface electrode 212 in the second direction y in a plan view. Note that the first chip 21 may have only one of the pair of principal surface electrodes 214, or may have neither of the pair of principal surface electrodes 214.

[0034] The first back surface electrode 213 is disposed on the first back surface 21b. The first back surface electrode 213 is provided facing the main surface 101 of the first mounting portion 10A. A current corresponding to the power before being converted by the first chip 21 flows through the first back surface electrode 213. In an example where the first chip 21 is an IGBT, the first back surface electrode 213 is, for example, a collector electrode, and in an example where the first chip 21 is a MOSFET, the first back surface electrode 213 is, for example, a drain electrode.

[0035] The second chip 22 is mounted on the main surface 101 of the second mounting portion 10B, as shown in Figures 3, 4, 9, and 11. Preferably, the center of gravity of the second chip 22 overlaps the center of the second mounting portion 10B in a plan view. The center of the second mounting portion 10B is the center when the second mounting portion 10B is divided into Lx (Lx is a positive odd number) in the first direction x, and is also a region corresponding to the center when the second mounting portion 10B is divided into Ly (Ly is a positive odd number) in the second direction y. Lx and Ly are not limited to any particular value, but may be, for example, 3 or 5.

[0036] 11 , the second chip 22 has a second main surface 22a and a second back surface 22b. The second main surface 22a and the second back surface 22b are spaced apart in the thickness direction z. The second main surface 22a faces the same direction as the main surface 101 of the second mounting portion 10B. The second back surface 22b faces the opposite side to the second main surface 22a in the thickness direction z and faces the main surface 101 of the second mounting portion 10B.

[0037] As shown in FIGS. 4 and 11, the second chip 22 has a second principal surface electrode 221 , a plurality of principal surface electrodes 222 and 224 , and a second back surface electrode 223 .

[0038] The second principal surface electrode 221 is disposed on the second principal surface 22a. A current corresponding to the power converted by the second chip 22 flows through the second principal surface electrode 221. In an example where the second chip 22 is an IGBT, the second principal surface electrode 221 is, for example, an emitter electrode. In an example where the second chip 22 is a MOSFET, the second principal surface electrode 221 is, for example, a source electrode. Like the first principal surface electrode 211, the second principal surface electrode 221 includes multiple metal plating layers. The second principal surface electrode 221 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. Alternatively, the second principal surface electrode 221 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.

[0039] The principal surface electrode 222 is disposed on the second principal surface 22 a. A second drive signal (gate voltage) for driving the second chip 22 is applied to the principal surface electrode 222. The principal surface electrode 222 is, for example, a gate electrode in either the IGBT or MOSFET example. In a plan view, the area of ​​the principal surface electrode 222 is smaller than the area of ​​the second principal surface electrode 221.

[0040] The pair of principal surface electrodes 224 are arranged on the second principal surface 22a. Each of the pair of principal surface electrodes 224 has the same potential as the second principal surface electrode 221. In an example where the second chip 22 is an IGBT, each of the pair of principal surface electrodes 224 is, for example, an emitter sense electrode, and in an example where the second chip 22 is a MOSFET, each of the pair of principal surface electrodes 224 is, for example, a source sense electrode. The pair of principal surface electrodes 224 are arranged on both sides of the principal surface electrode 222 in the second direction y in a plan view. Note that the second chip 22 may have only one of the pair of principal surface electrodes 224, or may have neither of the pair of principal surface electrodes 224.

[0041] The second back surface electrode 223 is disposed on the second back surface 22b. The second back surface electrode 223 is provided facing the main surface 101 of the second mounting portion 10B. A current corresponding to the power before being converted by the second chip 22 flows through the second back surface electrode 223. In an example where the second chip 22 is an IGBT, the second back surface electrode 223 is, for example, a collector electrode, and in an example where the second chip 22 is a MOSFET, the second back surface electrode 223 is, for example, a drain electrode.

[0042] The semiconductor device A10 further includes two die bonding layers 231 and 232. Each of the two die bonding layers 231 and 232 is electrically conductive. Each of the die bonding layers 231 and 232 is made of, for example, solder. Alternatively, each of the die bonding layers 231 and 232 may be made of sintered metal.

[0043] 9 and 10 , the die bonding layer 231 is interposed between the main surface 101 of the first mounting portion 10A and the first back surface electrode 213 of the first chip 21. The die bonding layer 231 joins the main surface 101 of the first mounting portion 10A and the first back surface electrode 213 of the first chip 21. This establishes electrical conduction between the first back surface electrode 213 of the first chip 21 and the first mounting portion 10A.

[0044] 9 and 11 , the die bonding layer 232 is interposed between the main surface 101 of the second mounting portion 10B and the second back-side electrode 223 of the second chip 22. The die bonding layer 232 joins the main surface 101 of the second mounting portion 10B and the second back-side electrode 223 of the second chip 22. This establishes electrical continuity between the second back-side electrode 223 of the second chip 22 and the second mounting portion 10B.

[0045] 3 and 4 , the multiple terminal leads 13 are located on the side opposite to the side where the second end face 112 faces the first mounting portion 10A and the second mounting portion 10B in the second direction y. At least one of the multiple terminal leads 13 is electrically connected to either the first chip 21 or the second chip 22. The multiple terminal leads 13 are arranged along the first direction x. The multiple terminal leads 13 include a first terminal lead 14, a second terminal lead 15, a third terminal lead 16, a fourth terminal lead 171, a fifth terminal lead 181, a sixth terminal lead 172, and a seventh terminal lead 182.

[0046] As shown in FIG. 3 , the first terminal lead 14 is located away from the first mounting portion 10A and the second mounting portion 10B in the second direction y and between the second terminal lead 15 and the third terminal lead 16 in the first direction x. The first terminal lead 14 extends along the second direction y. The first terminal lead 14 is electrically connected to the second principal surface electrode 221 of the second chip 22. The first terminal lead 14 includes a covering portion 14A and an exposed portion 14B. As shown in FIG. 3 , the covering portion 14A is covered with the sealing resin 50. As shown in FIGS. 3 , 5 , and 6 , the exposed portion 14B is connected to the covering portion 14A and exposed from a third side surface 55 of the sealing resin 50. The exposed portion 14B extends away from the first mounting portion 10A and the second mounting portion 10B in the second direction y. The surface of the exposed portion 14B is, for example, tin-plated.

[0047] As shown in Figure 14, the covering portion 14A of the first terminal lead 14 has a second seating surface 14C and a second upright surface 14D. The second seating surface 14C faces the same side as the main surfaces 101 of the first mounting portion 10A and the second mounting portion 10B in the thickness direction z and is located lower in the thickness direction z than the upper surface of the covering portion 14A (the surface facing upward in the thickness direction z). The second upright surface 14D faces in a direction perpendicular to the thickness direction z and is connected to the second seating surface 14C and the upper surface of the covering portion 14A. The second seating surface 14C and the second upright surface 14D form a step in the covering portion 14A of the first terminal lead 14.

[0048] As shown in FIG. 3 , the second terminal lead 15 includes a portion extending in the second direction y and is connected to the first mounting portion 10A. Therefore, the second terminal lead 15 is electrically connected to the first back electrode 213 of the first chip 21 via the first mounting portion 10A. The second terminal lead 15 is a P terminal (positive electrode) to which a DC power supply voltage to be converted is applied. The second terminal lead 15 includes a covering portion 15A and an exposed portion 15B. As shown in FIG. 4 , the covering portion 15A is connected to the third end surface 113 of the first mounting portion 10A and is covered with the sealing resin 50. When viewed in the first direction x, the covering portion 15A is bent. As shown in FIGS. 3 , 5 , and 6 , the exposed portion 15B is connected to the covering portion 15A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 15B extends away from the first mounting portion 10A in the second direction y. The surface of the exposed portion 15B is plated with, for example, tin.

[0049] As shown in FIG. 3 , the third terminal lead 16 includes a portion extending along the second direction y and is connected to the second mounting portion 10B. Therefore, the third terminal lead 16 is electrically connected to the second back electrode 223 of the second chip 22 via the second mounting portion 10B. AC power converted by the first chip 21 and the second chip 22 is output from the third terminal lead 16. The third terminal lead 16 includes a covering portion 16A and an exposed portion 16B. As shown in FIG. 4 , the covering portion 16A is connected to the third end surface 113 of the second mounting portion 10B and is covered with the sealing resin 50. When viewed in the first direction x, the covering portion 16A is bent in the same manner as the covering portion 15A of the second terminal lead 15. As shown in FIGS. 3 , 5 , and 6 , the exposed portion 16B is connected to the covering portion 16A and exposed from the third side surface 55 of the sealing resin 50. The exposed portion 16B extends away from the second mounting portion 10B in the second direction y. The surface of the exposed portion 16B is plated with, for example, tin.

[0050] As shown in FIG. 3 , the fourth terminal lead 171 is located away from the first mounting portion 10A in the second direction y and on one side in the first direction x. As shown in FIG. 3 , the sixth terminal lead 172 is located away from the second mounting portion 10B in the second direction y and on the other side in the first direction x. The fourth terminal lead 171 is electrically connected to the principal surface electrode 212 (gate electrode) of the first chip 21. A drive signal (gate voltage) for driving the first chip 21 is applied to the fourth terminal lead 171. The sixth terminal lead 172 is electrically connected to the principal surface electrode 222 (gate electrode) of the second chip 22. A drive signal (gate voltage) for driving the second chip 22 is applied to the sixth terminal lead 172.

[0051] As shown in Fig. 3, the fourth terminal lead 171 includes a covering portion 171A and an exposed portion 171B. The covering portion 171A is covered with the sealing resin 50. As shown in Figs. 3, 5, and 6, the exposed portion 171B is connected to the covering portion 171A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 171B extends in the second direction y away from the first mounting portion 10A. The surface of the exposed portion 171B is plated with, for example, tin.

[0052] As shown in Fig. 3, the sixth terminal lead 172 includes a covered portion 172A and an exposed portion 172B. The covered portion 172A is covered with the sealing resin 50. As shown in Figs. 3, 5, and 6, the exposed portion 172B is connected to the covered portion 172A and is exposed from the sealing resin 50. The exposed portion 172B extends in the second direction y away from the second mounting portion 10B. The surface of the exposed portion 172B is plated with, for example, tin.

[0053] As shown in FIG. 3 , the fifth terminal lead 181 is located away from the first mounting portion 10A in the second direction y and is located between the second terminal lead 15 and the fourth terminal lead 171 in the first direction x. As shown in FIG. 3 , the seventh terminal lead 182 is located away from the second mounting portion 10B in the second direction y and is located between the third terminal lead 16 and the sixth terminal lead 172 in the first direction x. The fifth terminal lead 181 is electrically connected to the principal surface electrode 214 (emitter sense electrode) of the first chip 21. A voltage corresponding to the current flowing through the principal surface electrode 214 (first principal surface electrode 211) of the first chip 21 is applied to the fifth terminal lead 181. The seventh terminal lead 182 is electrically connected to the second principal surface electrode 221 (emitter sense electrode) of the second chip 22. A voltage corresponding to the current flowing through the main surface electrode 224 (second main surface electrode 221 ) of the second chip 22 is applied to the seventh terminal lead 182 .

[0054] As shown in Fig. 3, the fifth terminal lead 181 includes a covering portion 181A and an exposed portion 181B. The covering portion 181A is covered with the sealing resin 50. As shown in Figs. 3, 5, and 6, the exposed portion 181B is connected to the covering portion 181A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 181B extends in the second direction y away from the first mounting portion 10A. The surface of the exposed portion 181B is plated with, for example, tin.

[0055] As shown in Fig. 3, the seventh terminal lead 182 includes a covered portion 182A and an exposed portion 182B. The covered portion 182A is covered with the sealing resin 50. As shown in Figs. 3, 5, and 6, the exposed portion 182B is connected to the covered portion 182A and is exposed from the third side surface 55 of the sealing resin 50. The exposed portion 182B extends in the second direction y away from the second mounting portion 10B. The surface of the exposed portion 182B is plated with, for example, tin.

[0056] 6, in the semiconductor device A10, the heights h of the exposed portions 14B of the first terminal lead 14, 15B of the second terminal lead 15, and 16B of the third terminal lead 16 are all the same (or approximately the same). Furthermore, the thicknesses of these are all the same (or approximately the same). Therefore, when viewed in the first direction x, at least a portion (exposed portion 14B) of the first terminal lead 14 overlaps with each of the second terminal lead 15 and the third terminal lead 16 (see FIG. 7).

[0057] The conductive member 31 is electrically connected to the semiconductor circuit unit 20 (first chip 21). The conductive member 31 is an example of a "first conductive member" as defined in the claims. As shown in FIG. 3 , the conductive member 31 is bonded to the first principal surface electrode 211 of the first chip 21 and the second mounting portion 10B. This electrically connects the first principal surface electrode 211 to the second mounting portion 10B and the second back surface electrode 223 of the second chip 22. The conductive member 31 contains copper. In the semiconductor device A10, the conductive member 31 is a metal clip. The conductive member 31 includes a first body portion 311, a plurality of first bonding portions 312, a second bonding portion 313, a plurality of first connecting portions 314, and a second connecting portion 315.

[0058] As shown in FIGS. 3 and 4 , the first body portion 311 forms a main portion of the conductive member 31. The first body portion 311 extends in the first direction x. In the illustrated example, the first body portion 311 extends linearly between the first chip 21 and the second chip 22 in a plan view. As shown in FIG. 8 , the first body portion 311 straddles the first mounting portion 10A and the second mounting portion 10B. The first body portion 311 is located higher in the thickness direction z than the multiple first bonding portions 312 and second bonding portions 313. As shown in FIG. 4 , the first body portion 311 includes two partition portions 311a and 311b.

[0059] As shown in FIG. 4 , the partition 311a is connected to a plurality of first connecting portions 314 and a partition 311b. The edge of the partition 311a that is connected to the plurality of first connecting portions 314 branches into multiple portions. The partition 311b is connected to the partition 311a and the second connecting portion 315. The width of the partition 311b (the dimension in the second direction y) is smaller than the width of the partition 311a (the dimension in the second direction y). In this configuration, as shown in FIG. 4 , the first main body portion 311 has an L-shape in plan view.

[0060] As shown in FIGS. 3 , 4 , 11 , and 15 , the multiple first bonding portions 312 are each bonded to the first principal surface electrode 211 of the first chip 21. As shown in FIGS. 3 , 4 , and 15 , the multiple first bonding portions 312 are spaced apart from one another in the second direction y. The multiple first bonding portions 312 are arranged parallel (or approximately parallel) to one another in a plan view. Each of the multiple first bonding portions 312 is connected to the first main body portion 311 (partition portion 311 a) via a corresponding one of the multiple first connecting portions 314. The multiple first connecting portions 314 are connected to the first main body portion 311 and the multiple first bonding portions 312. As shown in FIG. 9 , each of the first connecting portions 314 is bent in the thickness direction z.

[0061] As shown in FIGS. 3 , 9 , and 12 , the second joint portion 313 is joined to the first seating surface 103 of the second mounting portion 10B. The second joint portion 313 extends in the second direction y. At least a portion of the second joint portion 313 is contained within an area defined by the first seating surface 103 and the first upright surface 104 of the second mounting portion 10B. The second joint portion 313 is connected to the first main body portion 311 (compartment portion 311b) via a second connecting portion 315. As shown in FIG. 9 , the second connecting portion 315 is bent in the thickness direction z. The second joint portion 313 is located on the opposite side of the first joint portion 312 from the first joint portion 312, with the first main body portion 311 sandwiched therebetween.

[0062] 9 and 11 , the semiconductor device A10 further includes a first bonding layer 33. The first bonding layer 33 is interposed between the first main surface electrode 211 of the first chip 21 and each of the first bonding portions 312. The first bonding layer 33 bonds the first main surface electrode 211 to each of the first bonding portions 312. The first bonding layer 33 is conductive. The first bonding layer 33 is, for example, solder. Alternatively, the first bonding layer 33 may be a sintered metal.

[0063] The thickness t (see FIG. 10) of each of the multiple first bonding portions 312 is 0.1 mm or more and is not more than twice the maximum thickness Tmax (see FIG. 10) of the first bonding layer 33. The maximum thickness Tmax of the first bonding layer 33 is greater than the thickness of the first chip 21.

[0064] 9 and 12, the semiconductor device A10 further includes a second bonding layer 34. The second bonding layer 34 is interposed between the first seating surface 103 of the second mounting portion 10B and the second bonding portion 313. The second bonding layer 34 bonds the second mounting portion 10B and the second bonding portion 313. The second bonding layer 34 is electrically conductive. The second bonding layer 34 is, for example, solder. Alternatively, the second bonding layer 34 may be a sintered metal.

[0065] The conductive member 32 is electrically connected to the semiconductor circuit unit 20 (second chip 22). The conductive member 32 is an example of a "second conductive member" as defined in the claims. As shown in FIG. 3 , the conductive member 32 is bonded to the second principal surface electrode 221 of the second chip 22 and the covering portion 14A of the first terminal lead 14. This provides electrical continuity between the second principal surface electrode 221 and the first terminal lead 14. The conductive member 32 contains copper. In the semiconductor device A10, the conductive member 32 is a metal clip. The conductive member 32 has a second body portion 321, a third bonding portion 322, a plurality of fourth bonding portions 323, a third connecting portion 324, and a plurality of fourth connecting portions 325.

[0066] 3 and 4, the second main body portion 321 forms a main portion of the conductive member 32. In a plan view, the second main body portion 321 is bent in a hook shape. In a plan view, the second main body portion 321 overlaps the main surface 101 of the second mounting portion 10B. The second main body portion 321 is located higher in the thickness direction z than the third joint portion 322 and the plurality of fourth joint portions 323. As shown in FIG. 4, the second main body portion 321 includes a plurality of partition portions 321a, 321b, and 321c.

[0067] As shown in FIG. 4 , the partition 321a is connected to the third connecting portion 324 and the partition 321b. In a plan view, the partition 321a extends from the third connecting portion 324 in the second direction y. The partition 321b is connected to the two partitions 321a and 321c. In a plan view, the partition 321b extends in the first direction x. In this embodiment, when the semiconductor device A10 is energized, the currents flowing through the partition 311b and the partition 321b are opposite to each other. The partition 321c is connected to the partition 321b and a plurality of fourth connecting portions 325. In a plan view, the partition 321c is strip-shaped with the second direction y as its longitudinal direction.

[0068] As shown in FIGS. 3 , 4 , 13 , and 14 , the third bonding portion 322 is bonded to the second seating surface 14C of the first terminal lead 14. The third bonding portion 322 extends in the first direction x. At least a portion of the third bonding portion 322 is contained in the area defined by the second seating surface 14C and the second upright surface 14D of the first terminal lead 14. The third bonding portion 322 is connected to the second main body portion 321 (compartment portion 321a) via the third connecting portion 324. As shown in FIG. 13 , the third connecting portion 324 is bent in the thickness direction z. The third bonding portion 322 is located on the opposite side of the fourth bonding portion 323 with the second main body portion 321 interposed therebetween.

[0069] As shown in FIGS. 3 , 4 , 9 , 11 , and 16 , the multiple fourth bonding portions 323 are each bonded to the second principal surface electrode 221 of the second chip 22. As shown in FIGS. 3 , 4 , and 16 , the multiple fourth bonding portions 323 are spaced apart from one another in the second direction y. The multiple fourth bonding portions 323 are arranged parallel (or approximately parallel) to one another in a plan view. Each of the multiple fourth bonding portions 323 is connected to the second main body portion 321 (partition portion 321c) via a corresponding one of the multiple fourth linking portions 325. The multiple fourth linking portions 325 are connected to the second main body portion 321 and the multiple fourth bonding portions 323. As shown in FIG. 9 , each fourth linking portion 325 is bent in the thickness direction z.

[0070] 9 and 14, the semiconductor device A10 further includes a third bonding layer 35. The third bonding layer 35 is interposed between the second seating surface 14C of the first terminal lead 14 and the third bonding portion 322. The third bonding layer 35 bonds the covering portion 14A of the first terminal lead 14 to the third bonding portion 322. The third bonding layer 35 is conductive. The third bonding layer 35 is, for example, solder. Alternatively, the third bonding layer 35 may be a sintered metal.

[0071] As shown in FIGS. 9, 11, and 16, the semiconductor device A10 further includes a fourth bonding layer 36. The fourth bonding layer 36 is interposed between the second main surface electrode 221 of the second chip 22 and the plurality of fourth bonding portions 323. The fourth bonding layer 36 bonds the second main surface electrode 221 of the second chip 22 to the plurality of fourth bonding portions 323. The fourth bonding layer 36 is conductive. The fourth bonding layer 36 is, for example, solder. Alternatively, the fourth bonding layer 36 may be a sintered metal.

[0072] The thickness t (see FIG. 11) of each of the multiple fourth bonding portions 323 is 0.1 mm or more and is not more than twice the maximum thickness Tmax (see FIG. 11) of the fourth bonding layer 36. The maximum thickness Tmax of the fourth bonding layer 36 is greater than the thickness of the second chip 22.

[0073] Each of the plurality of conductive members 41A, 41B, 42A, and 42B is, for example, a bonding wire. Each of the plurality of conductive members 41A, 41B, 42A, and 42B contains gold. Alternatively, each of the plurality of conductive members 41A, 41B, 42A, and 42B may contain copper or aluminum (Al).

[0074] 3 and 4, the conductive member 41A is joined to the main surface electrode 212 of the first chip 21 and the covering portion 171A of the fourth terminal lead 171. This establishes electrical continuity between the fourth terminal lead 171 and the main surface electrode 212 of the first chip 21. The conductive member 41B is joined to the main surface electrode 222 of the second chip 22 and the covering portion 172A of the sixth terminal lead 172. This establishes electrical continuity between the sixth terminal lead 172 and the main surface electrode 222 of the second chip 22.

[0075] 3 and 4 , the conductive member 42A is joined to one of the pair of principal surface electrodes 214 of the first chip 21 and to the covering portion 181A of the fifth terminal lead 181. This provides electrical continuity between the fifth terminal lead 181 and the principal surface electrode 214 of the first chip 21. As shown in FIGS. 3 and 4 , the conductive member 42B is joined to one of the pair of principal surface electrodes 224 of the second chip 22 and to the covering portion 182A of the seventh terminal lead 182. This provides electrical continuity between the seventh terminal lead 182 and the principal surface electrode 224 of the second chip 22.

[0076] As shown in FIGS. 3 , 4 , and 9 , the insulating member 60 contacts the two conductive members 31 and 32. The insulating member 60 secures the two conductive members 31 and 32 to each other. The insulating member 60 is covered with the sealing resin 50. The insulating member 60 contains, for example, the same resin material as the sealing resin 50. Note that the insulating member 60 is not limited as long as it contains an insulating material. The shape of the insulating member 60 in a planar view is not limited, but is rectangular in the illustrated example. For example, the insulating member 60 is formed in a portion where the two conductive members 31 and 32 are close to each other in a planar view. A portion of the conductive member 31 and a portion of the conductive member 32 are sandwiched by the insulating member 60 in the thickness direction z. For example, the insulating member 60 is formed to straddle the first main body portion 311 of the conductive member 31 and the second main body portion 321 of the conductive member 32 in a planar view. 3 and 9 , in this embodiment, the insulating member 60 is not in contact with any of the first connecting portion 314, the second connecting portion 315, the third connecting portion 324, and the fourth connecting portion 325. Note that the formation range of the insulating member 60 is not limited to the size and shape shown in the drawings, as long as it spans the two conductive members 31 and 32.

[0077] 17 , in the semiconductor device A10 configured as described above, the first main surface electrode 211 of the first chip 21 and the second back surface electrode 223 of the second chip 22 are electrically connected to each other. Therefore, the semiconductor device A10 configures a half-bridge circuit using two transistors (the first chip 21 and the second chip 22).

[0078] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 18 to 20. Figures 18 and 19 are plan views showing one step in the method for manufacturing the semiconductor device A10. Figure 20 is a cross-sectional view showing one step in the method for manufacturing the semiconductor device A10, and corresponds to the cross section of Figure 9.

[0079] First, a lead frame 30 shown in Fig. 18 is prepared. The lead frame 30 includes a frame portion 301, a plurality of hanging portions 302, and two conductive members 31 and 32. The two conductive members 31 and 32 are each supported by the frame portion 301 via some of the plurality of hanging portions 302.

[0080] 19 , an insulating member 60 is formed on the lead frame 30. The insulating member 60 is formed so as to straddle the two conductive members 31. As a result, the two conductive members 31, 32 are fixed by the insulating member 60 in the state of the lead frame 30. The insulating member 60 contains, for example, an epoxy resin, and in this example, the insulating member 60 is formed by, for example, molding.

[0081] Next, the two conductive members 31 and 32 are cut off from the frame portion 301. For example, they are cut along cutting lines CL shown in Fig. 19. As a result, the two conductive members 31 and 32 fixed by the insulating member 60 are formed.

[0082] Next, as shown in FIG. 20 , the two conductive members 31, 32 are bonded to the semiconductor circuit unit 20 (the first chip 21 and the second chip 22) while being fixed with the insulating member 60. Prior to the step shown in FIG. 20 , a lead frame including a first mounting portion 10A, a second mounting portion 10B, and a plurality of terminal leads 13 is prepared, and the first chip 21 and the second chip 22 are bonded to the first mounting portion 10A and the second mounting portion 10B, respectively. In this lead frame state, the plurality of terminal leads 13 are connected to each other. When bonding the two conductive members 31, 32, the conductive member 31 is bonded to the first chip 21 and the second mounting portion 10B, and the conductive member 32 is bonded to the second chip 22 and the first terminal lead 14.

[0083] Next, after forming the plurality of conductive members 41A, 41B, 42A, and 42B, a sealing resin 50 is formed to cover the two conductive members 31 and 32 and the insulating member 60. Thereafter, the plurality of interconnected terminal leads 13 are cut off. Through the above steps, the semiconductor device A10 is manufactured.

[0084] The functions and effects of the semiconductor device A10 and the manufacturing method thereof according to the first embodiment are as follows.

[0085] The semiconductor device A10 includes an insulating member 60 in contact with the two conductive members 31, 32. The two conductive members 31, 32 are fixed by the insulating member 60. With this configuration, during the manufacturing process of the semiconductor device A10, the two conductive members 31, 32 can be fixed by the insulating member 60 and then bonded to the semiconductor circuit unit 20 (the first chip 21 and the second chip 22). Therefore, the two conductive members 31, 32 can be arranged together, which improves the production efficiency of the semiconductor device A10.

[0086] Furthermore, in the semiconductor device A10, the two conductive members 31, 32 are fixed and positioned by the insulating member 60, thereby suppressing misalignment of their relative positions. This prevents the two conductive members 31, 32 from contacting each other. Furthermore, suppressing misalignment of their relative positions allows the distance between the two conductive members 31, 32 to be reduced. This increases the mutual inductance generated by the current flowing through the conductive member 31 and the current flowing through the conductive member 32, thereby enabling the semiconductor device A10 to reduce parasitic inductance. Furthermore, as described above, reducing the distance between the two conductive members 31, 32 allows each of the two conductive members 31, 32 to be enlarged, thereby reducing the wiring resistance and self-inductance of the two conductive members 31, 32. This allows the semiconductor device A10 to reduce parasitic inductance.

[0087] In the semiconductor device A10, the first bonding portion 312 of the conductive member 31 is bonded to the first main surface electrode 211 by a first bonding layer 33. The second bonding portion 313 of the conductive member 31 is bonded to the second mounting portion 10B by a second bonding layer 34. The third bonding portion 322 of the conductive member 32 is bonded to the first terminal lead 14 by a third bonding layer 35. The fourth bonding portion 323 of the conductive member 32 is bonded to the second main surface electrode 221 by a fourth bonding layer 36. The first bonding layer 33, the second bonding layer 34, the third bonding layer 35, and the fourth bonding layer 36 are each, for example, solder. In this configuration, the first bonding layer 33, the second bonding layer 34, the third bonding layer 35, and the fourth bonding layer 36 are heated by reflow bonding. Therefore, if the two conductive members 31, 32 are not fixed with the insulating member 60, relative misalignment between the two conductive members 31, 32 is likely to occur. Therefore, in a configuration that requires heating the first bonding layer 33, the second bonding layer 34, the third bonding layer 35, and the fourth bonding layer 36, fixing the two conductive members 31, 32 with the insulating member 60 is effective in suppressing relative misalignment between the two conductive members 31, 32. In other words, this is effective in reducing the parasitic inductance of the semiconductor device A10. Furthermore, reducing the parasitic inductance of the semiconductor device A10 can suppress surge voltages associated with switching operations of the first chip 21 and the second chip 22.

[0088] In the semiconductor device A10, the insulating member 60 is formed in a portion adjacent to the two conductive members 31, 32. In this configuration, an insulator can be disposed in the portion adjacent to the two conductive members 31, 32, thereby ensuring the dielectric strength voltage between the two conductive members 31, 32.

[0089] In the semiconductor device A10, the insulating member 60 contains the same resin material as the sealing resin 50. With this configuration, the dielectric strength voltage between the two conductive members 31, 32 can be made the same as when the sealing resin 50 is disposed between the two conductive members 31, 32. Furthermore, since the difference in the linear expansion coefficients of the insulating member 60 and the sealing resin 50 can be reduced, thermal stress caused by the difference in these linear expansion coefficients can be reduced.

[0090] In the semiconductor device A10, as shown in FIG. 3 , the insulating member 60 is disposed at approximately the center of the two conductive members 31, 32 in a plan view. During the manufacturing process of the semiconductor device A10, for example, after cutting along the cutting line CL in FIG. 19 , the two conductive members 31, 32 are transported while being fixed by the insulating member 60. At this time, even if the insulating member 60 is sucked and the two conductive members 31, 32 are transported, the semiconductor device A10 can prevent the two conductive members 31, 32 from becoming tilted. Furthermore, by transporting the insulating member 60 while sucking, the two conductive members 31, 32 do not come into contact with the transporting member, and deformation of the two conductive members 31, 32 can also be prevented.

[0091] In the semiconductor device A10, the semiconductor circuit unit 20 includes a first chip 21 and a second chip 22. The first chip 21 and the second chip 22 are covered with a sealing resin 50. According to this configuration, the semiconductor device A10 has two chips (the first chip 21 and the second chip 22) packaged in a single sealing resin 50. Therefore, the semiconductor device A10 can reduce the mounting area on the circuit board on which the semiconductor device A10 is mounted.

[0092] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0093] 21 and 22 show a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: the first chip 21 of the semiconductor device A11 is a diode rather than a transistor.

[0094] The first chip 21 of the semiconductor device A11 has a first main surface electrode 211 and a first back surface electrode 213. As shown in Fig. 21 , the first chip 21 of the semiconductor device A11 does not have main surface electrodes 212, 214. As shown in Fig. 22 , the first chip 21 of the semiconductor device A11 is a diode, in which the first main surface electrode 211 is, for example, an anode electrode, and the first back surface electrode 213 is, for example, a cathode electrode.

[0095] As shown in Figure 21, the semiconductor device A11 does not include either of the two conductive members 41A, 42A. In this configuration, as shown in Figures 21 and 22, the fourth terminal lead 171 and the fifth terminal lead 181 are not electrically connected to either the first chip 21 or the second chip 22, respectively. Therefore, in the semiconductor device A11, the fourth terminal lead 171 and the fifth terminal lead 181 are each non-connect terminals. Note that, although the semiconductor device A11 includes the conductive member 42B in the example shown in Figure 21, in a configuration different from this example, the semiconductor device A11 may not include the conductive member 42B.

[0096] 22 , in the semiconductor device A11, the first main surface electrode 211 (anode electrode) of the first chip 21 and the second back surface electrode 223 (collector electrode) of the second chip 22 are electrically connected. In the semiconductor device A11, with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15, the high-voltage side serves as a diode and the low-voltage side serves as a transistor. The semiconductor device A11 is used, for example, as a boost chopper circuit.

[0097] 23 and 24 show a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following respect: the second chip 22 of the semiconductor device A12 is a diode rather than a transistor.

[0098] The second chip 22 of the semiconductor device A12 has a second main surface electrode 221 and a second back surface electrode 223. As shown in Fig. 23, the second chip 22 of the semiconductor device A12 does not have main surface electrodes 222, 224. As shown in Fig. 24, the second chip 22 of the semiconductor device A12 is a diode, in which the second main surface electrode 221 is, for example, an anode electrode, and the second back surface electrode 223 is, for example, a cathode electrode.

[0099] As shown in Figure 23, the semiconductor device A12 does not include either of the two conductive members 41B, 42B. In this configuration, as shown in Figures 23 and 24, the sixth terminal lead 172 and the seventh terminal lead 182 are not electrically connected to either the first chip 21 or the second chip 22, respectively. Therefore, in the semiconductor device A12, the sixth terminal lead 172 and the seventh terminal lead 182 are each non-connect terminals. Note that, although the semiconductor device A12 includes the conductive member 42A in the example shown in Figure 23, the semiconductor device A12 may not include the conductive member 42A in a configuration different from this example.

[0100] 24 , in the semiconductor device A12, the first main surface electrode 211 (emitter electrode) of the first chip 21 and the second back surface electrode 223 (cathode electrode) of the second chip 22 are electrically connected. In the semiconductor device A12, with respect to the DC voltage applied between the first terminal lead 14 and the second terminal lead 15, the high-voltage side serves as a transistor and the low-voltage side serves as a diode. The semiconductor device A12 is used, for example, as a step-down chopper circuit.

[0101] 25 and 26 show a semiconductor device A13 according to a third modification of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following respect: each of the first chip 21 and the second chip 22 of the semiconductor device A13 is a diode rather than a transistor.

[0102] The first chip 21 of the semiconductor device A13 has a first main surface electrode 211 and a first back surface electrode 213. As shown in FIG. 25, the first chip 21 of the semiconductor device A13 does not have main surface electrodes 212, 214. As shown in FIG. 26, the first chip 21 of the semiconductor device A13 is a diode, with the first main surface electrode 211 being an anode electrode and the first back surface electrode 213 being a cathode electrode. The second chip 22 of the semiconductor device A13 has a second main surface electrode 221 and a second back surface electrode 223. As shown in FIG. 25, the second chip 22 of the semiconductor device A13 does not have main surface electrodes 222, 224. As shown in FIG. 26, the second chip 22 of the semiconductor device A13 is a diode, with the second main surface electrode 221 being an anode electrode and the second back surface electrode 223 being a cathode electrode.

[0103] 25 , semiconductor device A13 does not include any of multiple conductive members 41A, 42A, 41B, 42B. In this configuration, as shown in FIGS. 24 and 25 , fourth terminal lead 171, fifth terminal lead 181, sixth terminal lead 172, and seventh terminal lead 182 are not electrically connected to either first chip 21 or second chip 22. Therefore, in semiconductor device A13, fourth terminal lead 171, fifth terminal lead 181, sixth terminal lead 172, and seventh terminal lead 182 are each non-connect terminals.

[0104] 26 , in the semiconductor device A13, the first main surface electrode 211 (anode electrode) of the first chip 21 and the second back surface electrode 223 (cathode electrode) of the second chip 22 are electrically connected. In the semiconductor device A13, both the high-voltage side and the low-voltage side are diodes with respect to the power supply voltage (DC voltage) applied between the first terminal lead 14 and the second terminal lead 15. The semiconductor device A13 is a diode bridge circuit.

[0105] In the semiconductor devices A11 to A13 according to the modifications of the first embodiment, the two conductive members 31 and 32 are fixed by an insulating member 60, similar to the semiconductor device A10. Therefore, in each of the semiconductor devices A11 to A13, the two conductive members 31 and 32 can be arranged together, similar to the semiconductor device A10, thereby improving production efficiency. Furthermore, each of the semiconductor devices A11 to A13 has the same configuration as the semiconductor device A10, thereby achieving the same effects as the semiconductor device A10. For example, each of the semiconductor devices A11 to A13 can prevent the two conductive members 31 and 32 from contacting each other. Furthermore, each of the semiconductor devices A11 to A13 can increase the mutual inductance generated by the current flowing through the conductive member 31 and the current flowing through the conductive member 32, thereby reducing parasitic inductance.

[0106] As can be seen from the semiconductor devices A10 to A13, the semiconductor device of the present disclosure can be configured with four types of power conversion circuits (a transistor bridge circuit, a step-up chopper circuit, a step-down chopper circuit, and a diode bridge circuit) by combining the first chip 21 and the second chip 22. Meanwhile, the configurations of the terminal leads 13 and the sealing resin 50 are common to the semiconductor devices A10 to A13. Therefore, the semiconductor device of the present disclosure can configure any of the four types of power conversion circuits while maintaining the same package appearance. Furthermore, the semiconductor device of the present disclosure can utilize the same configurations of the terminal leads 13 and the sealing resin 50 even if the first chip 21 and the second chip 22 are transistors or diodes. This allows the semiconductor device of the present disclosure to share a common package structure regardless of the four types of power conversion circuits described above, which is advantageous in terms of improving productivity.

[0107] As can be seen from the above semiconductor devices A10 to A13, the semiconductor device of the present disclosure is arranged so that the center of gravity of the first chip 21 overlaps the center of the first mounting portion 10A in a plan view. This configuration is preferable for sharing the conductive member 31. Similarly, the semiconductor device of the present disclosure is arranged so that the center of gravity of the second chip 22 overlaps the center of the second mounting portion 10B in a plan view. This configuration is preferable for sharing the conductive member 32.

[0108] 27 to 30 show a semiconductor device A20 according to the second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respects. First, each of the plurality of conductive members 41A, 42A, 41B, and 42B is a conductive plate-like member rather than a bonding wire. Second, the semiconductor device A20 includes a first insulating member 61, a second insulating member 62, and a third insulating member 63 instead of the insulating member 60. Note that in the semiconductor device A20, the first chip 21 and the second chip 22 are each a MOSFET, as shown in FIG. 30, but may also be an IGBT (or an RC-IGBT), as in the semiconductor device A10.

[0109] Each of the conductive members 41A, 42A, 41B, and 42B contains copper or a copper alloy. Unlike this example, each of the conductive members 41A, 42A, 41B, and 42B may contain other metal materials. The conductive member 41A is bonded to the principal surface electrode 212 (first chip 21) and the covering portion 171A (fourth terminal lead 171) with a conductive adhesive. The conductive member 42A is bonded to the principal surface electrode 214 (first chip 21) and the covering portion 181A (fifth terminal lead 181) with a conductive adhesive. The conductive member 41B is bonded to the principal surface electrode 222 (second chip 22) and the covering portion 172A (sixth terminal lead 172) with a conductive adhesive. The conductive member 42B is joined to the main surface electrode 224 (second chip 22) and the covering portion 182A (seventh terminal lead 182) by a conductive bonding material.

[0110] The first insulating member 61, the second insulating member 62, and the third insulating member 63 each contain, for example, the same resin material as the sealing resin 50. However, unlike this example, the first insulating member 61, the second insulating member 62, and the third insulating member 63 may each contain another insulating material.

[0111] The first insulating member 61 is formed across the two conductive members 31 and 32 and fixes them together, similar to the insulating member 60 of the semiconductor device A10.

[0112] The second insulating member 62 contacts and fixes the two conductive members 41A, 42A. A portion of the conductive member 41A and a portion of the conductive member 42A are covered in the thickness direction z by the second insulating member 62. The shape of the second insulating member 62 in a plan view is not limited in any way, but is rectangular in the illustrated example.

[0113] The third insulating member 63 contacts and fixes the two conductive members 41B, 42B. A portion of the conductive member 41B and a portion of the conductive member 42B are covered in the thickness direction z by the third insulating member 63. The shape of the third insulating member 63 in a plan view is not limited in any way, but is rectangular in the illustrated example.

[0114] In the semiconductor device A20, the first joint portion 312 of the conductive member 31 includes two strip portions 312a, as shown in FIGS. 27 and 28 . As shown in FIGS. 27 and 28 , the two strip portions 312a are spaced apart from each other in the second direction y. The longitudinal direction of each of the two strip portions 312a is the first direction x. The two strip portions 312a are arranged parallel (or approximately parallel) to each other in a plan view. Unlike this example, the first joint portion 312 does not have to be separated into two strip portions 312a.

[0115] In the semiconductor device A20, the fourth joint 323 of the conductive member 32 includes two strip-shaped portions 323a, as shown in FIGS. 27 and 28 . As shown in FIGS. 27 and 28 , the two strip-shaped portions 323a are spaced apart from each other in the second direction y. The longitudinal direction of each of the two strip-shaped portions 323a is the first direction x. The two strip-shaped portions 323a are arranged parallel (or approximately parallel) to each other in a plan view. Unlike this example, the fourth joint 323 does not have to be separated into two strip-shaped portions 323a.

[0116] In the semiconductor device A20, the two conductive members 41A, 42A are fixed by a second insulating member 62 and then bonded to the first chip 21 (principal surface electrodes 212 and 214) and the coverings 171A and 181A. The two conductive members 41A, 42A are formed from the same lead frame and are fixed by the second insulating member 62 in the lead frame state. Similarly, the two conductive members 41B, 42B are fixed by a third insulating member 63 and then bonded to the second chip 22 (principal surface electrodes 222 and 224) and the coverings 172A and 182A. The two conductive members 41B, 42B are formed from the same lead frame and are fixed by the third insulating member 63 in the lead frame state.

[0117] In the semiconductor device A20, the two conductive members 31, 32 are fixed by the first insulating member 61. Therefore, the semiconductor device A20 allows the two first conductive members 31, 32 to be arranged together, thereby improving production efficiency. Furthermore, like the semiconductor device A10, the semiconductor device A20 can prevent misalignment of the relative positional relationship between the two conductive members 31, 32, thereby preventing them from contacting each other. Furthermore, like the semiconductor device A10, the semiconductor device A20 can increase the mutual inductance generated by the current flowing through the conductive member 31 and the current flowing through the conductive member 32, thereby reducing parasitic inductance. Furthermore, the semiconductor device A20 achieves the same effects as the semiconductor device A10 due to the configuration shared with the semiconductor device A10.

[0118] In the semiconductor device A20, the two conductive members 41A, 42A are fixed by the second insulating member 62. With this configuration, during the manufacturing process of the semiconductor device A20, the two conductive members 41A, 42A can be fixed by the second insulating member 62 and then bonded to the semiconductor circuit unit 20. Therefore, since the two conductive members 41A, 42A can be arranged together, the semiconductor device A20 can improve production efficiency. Furthermore, because the two conductive members 41A, 42A are arranged while being fixed by the second insulating member 62, deviation in their relative positional relationship is suppressed. As a result, the semiconductor device A20 can suppress contact between the two conductive members 41A, 42A.

[0119] In the semiconductor device A20, the two conductive members 41B, 42B are fixed by the third insulating member 63. With this configuration, during the manufacturing process of the semiconductor device A20, the two conductive members 41B, 42B can be fixed by the third insulating member 63 and then bonded to the semiconductor circuit unit 20. Therefore, the two conductive members 41B, 42B can be arranged together, thereby improving the production efficiency of the semiconductor device A20. Furthermore, because the two conductive members 41B, 42B are arranged after being fixed by the third insulating member 63, deviation in their relative positional relationship is suppressed. As a result, the semiconductor device A20 can suppress contact between the two conductive members 41B, 42B.

[0120] In the second embodiment described above, the semiconductor device A20 includes the first insulating member 61, the second insulating member 62, and the third insulating member 63. In a configuration different from this example, the semiconductor device A20 may include one or two of the first insulating member 61, the second insulating member 62, and the third insulating member 63. For example, the semiconductor device A20 may include only the second insulating member 62. In this case, the conductive member 41A is an example of a "first conductive member" recited in the claims, and the conductive member 42A is an example of a "second conductive member" recited in the claims.

[0121] 31 shows a semiconductor device A21 according to a first modification of the second embodiment. Similar to the semiconductor device A11, the semiconductor device A21 has a first chip 21 that is a diode rather than a transistor. As shown in FIG. 31 , unlike the semiconductor device A20, the semiconductor device A21 does not include either of the two conductive members 41A, 42A, and does not include the second insulating member 62.

[0122] 32 shows a semiconductor device A22 according to a second modification of the second embodiment. Similar to the semiconductor device A12, the semiconductor device A22 has a second chip 22 that is a diode rather than a transistor. As shown in FIG. 32 , unlike the semiconductor device A20, the semiconductor device A22 does not include either of the two conductive members 41B, 42B, and does not include the third insulating member 63.

[0123] 33 shows a semiconductor device A23 according to a third modification of the second embodiment. Similar to the semiconductor device A13, the semiconductor device A23 has a first chip 21 and a second chip 22 that are diodes rather than transistors. As shown in FIG. 33 , unlike the semiconductor device A20, the semiconductor device A23 does not include any of the plurality of conductive members 41A, 42A, 41B, and 42B, and does not include any of the second insulating member 62 and the third insulating member 63.

[0124] In the semiconductor devices A21 to A23 according to the modifications of the second embodiment, the two conductive members 31 and 32 are fixed by the first insulating member 61, similar to the semiconductor device A20. Therefore, in each of the semiconductor devices A21 to A23, the two conductive members 31 and 32 can be arranged together, similar to the semiconductor device A20, thereby improving production efficiency. Furthermore, each of the semiconductor devices A21 to A23 achieves the same effects as the semiconductor device A20 due to the common configuration with the semiconductor device A20. For example, each of the semiconductor devices A21 to A23 can prevent the two conductive members 31 and 32 from contacting each other. Furthermore, each of the semiconductor devices A21 to A23 can increase the mutual inductance generated by the current flowing through the conductive member 31 and the current flowing through the conductive member 32, thereby reducing parasitic inductance.

[0125] Semiconductor devices according to other modifications will be described below with reference to the drawings as appropriate. Unless otherwise specified, the modifications described below can be applied to each of the semiconductor devices A10 to A13 and A20 to A23 shown in the first and second embodiments (including their modifications).

[0126] In a configuration different from the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments, the insulating member 60 (first insulating member 61) does not have to sandwich the conductive members 31 and 32 in the thickness direction z. For example, FIG. 34 shows a configuration example in which the insulating member 60 is not formed below the conductive members 31 and 32 in the thickness direction z in the semiconductor device A10. Also, for example, FIG. 35 shows a configuration example in which the insulating member 60 is not formed above the conductive members 31 and 32 in the thickness direction z in the semiconductor device A10. Even in such a modified example, the two conductive members 31 and 32 can be fixed by the insulating member 60 (first insulating member 61) and arranged together. However, configuring the insulating member 60 (first insulating member 61) to sandwich the conductive members 31 and 32 in the thickness direction z allows the two conductive members 31 and 32 to be more firmly fixed. Furthermore, such a modification can be applied not only to the insulating member 60 (first insulating member 61 ), but also to each of the second insulating member 62 and the third insulating member 63 .

[0127] In a configuration different from that of each of the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments, the insulating member 60 (first insulating member 61) may be in contact with any of the first connecting portion 314, the second connecting portion 315, the third connecting portion 324, and the fourth connecting portion 325. For example, FIGS. 36 and 37 show a configuration example in which the insulating member 60 in the semiconductor device A10 is in contact with the second connecting portion 315. Even in this modification, the two conductive members 31 and 32 can be fixed by the insulating member 60 (first insulating member 61) and arranged together. Furthermore, in this modification, the formation area of ​​the insulating member 60 is larger, so that the two conductive members 31 and 32 can be more firmly fixed by the insulating member 60.

[0128] In a configuration different from that of each of the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments, a through hole may be formed in a portion of the conductive member 31 that is covered by the insulating member 60. Similarly, a through hole may be formed in a portion of the conductive member 32 that is covered by the insulating member 60. For example, FIG. 38 shows a configuration example in which a through hole 319 is formed in the conductive member 31 and a through hole 329 is formed in the conductive member 32 of the semiconductor device A10. The through hole 319 is formed in a portion of the first body portion 311 of the conductive member 31 that is covered by the insulating member 60. The through hole 319 penetrates the first body portion 311 in the thickness direction z. The through hole 329 is formed in a portion of the second body portion 321 of the conductive member 32 that is covered by the insulating member 60. The through hole 329 penetrates the second body portion 321 in the thickness direction z. Each through hole 319, 329 is filled with an insulating member 60. Even in this modified example, the two conductive members 31, 32 can be fixed by the insulating member 60 and arranged together. Furthermore, this modified example has the following advantages. First, during the formation (molding) of the insulating member 60, the resin material flows from above the conductive member 31 in the thickness direction z to below the conductive member 31 in the thickness direction z through each through hole 319, 329, thereby preventing voids from occurring in the insulating member 60. Second, the insulating member 60 formed in the through holes 319, 329 prevents the insulating member 60 from peeling off from the conductive members 31 and 32.

[0129] In a configuration different from the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments, the conductive member 31 may have a surface that contacts the insulating member 60 and that is partially uneven. Similarly, the conductive member 32 may have a surface that contacts the insulating member 60 and that is partially uneven. For example, FIG. 39 illustrates a configuration example in which the upper surface (the surface facing upward in the thickness direction z) of the first main body portion 311 of the conductive member 31 and the upper surface (the surface facing upward in the thickness direction z) of the second main body portion 321 of the conductive member 32 are rough surfaces (having fine unevenness). Even in this modification, the two conductive members 31 and 32 can be fixed together by the insulating member 60 and positioned together. Furthermore, in this modification, the anchor effect of the unevenness of the two conductive members 31 and 32 can prevent the insulating member 60 from peeling off from the conductive members 31 and 32. In the illustrated example, the upper surfaces of the first main body portion 311 and the second main body portion 321 are roughened, but the lower surfaces may also be roughened, or only the areas in contact with the insulating member 60 may be roughened.

[0130] In a configuration different from the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments, the insulating member 60 may be, for example, an insulating adhesive sheet rather than a molded resin material. For example, FIGS. 40 and 41 show a configuration example in which the insulating member 60 in the semiconductor device A20 is an insulating adhesive sheet. In the semiconductor device shown in FIGS. 40 and 41, the top surfaces of the conductive members 31, 32, 41A, 42A, 41B, and 42B are positioned at the same (or approximately the same) height in the thickness direction z. As a result, the insulating member 60 contacts and adheres to portions of the top surfaces of the two conductive members 31 and 32 and the multiple conductive members 41A, 42A, 41B, and 42B. Even in this modification, the two conductive members 31 and 32 can be fixed by the insulating member 60, allowing them to be positioned together. Furthermore, in this modification, the insulating member 60 can also collectively arrange the plurality of conductive members 41A, 42A, 41B, and 42B.

[0131] In a configuration different from the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments, the semiconductor circuit unit 20 may include a plurality of first chips 21. In such a modification, the plurality of first chips 21 may all be transistors or diodes, or may include a transistor and a diode (for example, connected in anti-parallel to a transistor). Similarly, the semiconductor circuit unit 20 may include a plurality of second chips 22. In such a modification, the plurality of second chips 22 may all be transistors or diodes, or may include a transistor and a diode (for example, connected in anti-parallel to a transistor).

[0132] The package structure of the semiconductor device of the present disclosure is not limited to those exemplified in the first to third embodiments (including their variations). For example, the semiconductor device of the present disclosure can also be applied to other TO (Transistor Outline) packages. Specifically, the semiconductor devices A10 to A13 and A20 to A23 according to the first and second embodiments are extensions of a package structure called TO-247, but may also be extensions of other package structures such as TO-220, TO-252, and TO-263. In other words, the semiconductor device of the present disclosure enables packaging of multiple semiconductor elements (first chip 21 and second chip 22) using a single sealing resin 50 while maintaining an appearance similar to that of a conventional TO package.

[0133] The semiconductor device and the method for manufacturing a semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the method for manufacturing a semiconductor device according to the present disclosure can be freely designed and modified in various ways. For example, the semiconductor device and the method for manufacturing a semiconductor device according to the present disclosure include embodiments relating to the following supplementary notes. Supplementary note 1. A semiconductor device comprising: a semiconductor circuit section; a first conductive member electrically connected to the semiconductor circuit section; a second conductive member electrically connected to the semiconductor circuit section; an insulating member in contact with the first conductive member and the second conductive member; and a sealing resin covering the semiconductor circuit section, the first conductive member, the second conductive member, and a portion of the insulating member, wherein the first conductive member and the second conductive member are fixed by the insulating member. Supplementary note 2. The semiconductor device according to Supplementary note 1, wherein the semiconductor circuit section includes a first chip and a second chip; the first conductive member is bonded to the first chip; and the second conductive member is bonded to the second chip. Supplementary note 3. The semiconductor device according to Supplementary Note 2, wherein the first chip and the second chip are electrically connected in series, and the semiconductor circuit portion forms a half-bridge circuit.Supplementary Note 4. The semiconductor device according to Supplementary Note 3, comprising: a first mounting portion on which the first chip is mounted; a second mounting portion on which the second chip is mounted; and first terminal leads separated from the first mounting portion and the second mounting portion.Supplementary Note 5. the first chip has a first main surface facing one side in a thickness direction of the sealing resin, a first back surface facing the other side in the thickness direction, a first main surface electrode formed on the first main surface, and a first back surface electrode formed on the first back surface, the first back surface electrode facing the first mounting portion and conducting to the first mounting portion; the second chip has a second main surface facing the one side in the thickness direction, a second back surface facing the other side in the thickness direction, a second main surface electrode formed on the second main surface, and a second back surface electrode formed on the second back surface, the second back surface electrode facing the second mounting portion and conducting to the second mounting portion.Appendix 6. The semiconductor device according to Appendix 5, wherein the first conductive member electrically connects the first main surface electrode and the second mounting portion, and the second conductive member electrically connects the second main surface electrode and the first terminal lead. Appendix 7. The semiconductor device according to Appendix 6, wherein the first mounting portion is located on one side of the second mounting portion in a first direction perpendicular to the thickness direction. Appendix 8. The semiconductor device according to Appendix 7, further comprising: a second terminal lead extending from the first mounting portion in a second direction perpendicular to the thickness direction and the first direction; and a third terminal lead extending from the second mounting portion in the second direction, wherein the first terminal lead, the second terminal lead, and the third terminal lead are arranged in the first direction. Appendix 9. The semiconductor device according to Appendix 8, wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction. Appendix 10. Appendix 11. The semiconductor device according to Appendix 9, further comprising: a fourth terminal lead; a fifth terminal lead; a third conductive member electrically connecting the first chip and the fourth terminal lead; and a fourth conductive member electrically connecting the first chip and the fifth terminal lead, wherein the fourth terminal lead and the fifth terminal lead are positioned further on one side in the first direction than the second terminal lead and are adjacent to each other in the first direction. Appendix 11. The semiconductor device according to Appendix 10, further comprising: a first insulating member, and a second insulating member, wherein the third conductive member and the fourth conductive member are each a plate-shaped member, and the second insulating member fixes the third conductive member and the fourth conductive member. Appendix 12. 12. The semiconductor device according to claim 10, further comprising: a sixth terminal lead; a seventh terminal lead; a fifth conductive member electrically connecting the second chip and the sixth terminal lead; and a sixth conductive member electrically connecting the second chip and the seventh terminal lead, wherein the sixth terminal lead and the seventh terminal lead are located on the other side of the third terminal lead in the first direction and are adjacent to each other in the first direction.Appendix 13. The semiconductor device according to Appendix 12, further comprising a third insulating member, wherein the fifth conductive member and the sixth conductive member are each a plate-like member, and wherein the third insulating member fixes the fifth conductive member and the sixth conductive member. Appendix 14. The semiconductor device according to any of Appendix 2 to Appendix 13, wherein the first chip is either a transistor or a diode, and the second chip is either a transistor or a diode. Appendix 15. The semiconductor device according to any of Appendix 1 to Appendix 14, wherein the insulating member is formed in a portion where the first conductive member and the second conductive member are close to each other when viewed in the thickness direction of the sealing resin. Appendix 16. The semiconductor device according to any of Appendix 1 to Appendix 15, wherein the insulating member contains the same resin material as the sealing resin. Appendix 17. The semiconductor device according to any of Appendix 1 to Appendix 16, wherein a portion of the first conductive member and a portion of the second conductive member are sandwiched between the insulating members in the thickness direction. Appendix 18. A method for manufacturing a semiconductor device, comprising: a step of preparing a lead frame including a first conductive member and a second conductive member; a step of fixing the first conductive member and the second conductive member in the lead frame state with an insulating member; a step of joining the first conductive member and the second conductive member while they are fixed with the insulating member to a semiconductor circuit unit; and a step of forming a sealing resin that covers the first conductive member, the second conductive member, and the semiconductor circuit unit.

[0134] A10 to A13, A20 to A23: semiconductor device 10A: first mounting portion 10B: second mounting portion 101: main surface 102: back surface 103: first seating surface 104: first upright surface 111: first end surface 112: second end surface 113: third end surface 114: fourth end surface 13: terminal lead 14: first terminal lead 14A: covering portion 14B: exposed portion 14C: second seating surface 14D: second upright surface 15: second terminal lead 15A: covering portion 15B: exposed portion 16: third terminal lead 16A: covering portion 16B: exposed portion 171: fourth terminal lead 171A: covering portion 171B: exposed portion 172: sixth terminal lead 172A: covering portion 172B: exposed portion 181: Fifth terminal lead 181A: Covering portion 181B: Exposed portion 182: Seventh terminal lead 182A: Covering portion 182B: Exposed portion 20: Semiconductor circuit portion 21: First chip 21a: First main surface 21b: First back surface 211: First main surface electrode 212, 214: Main surface electrode 213: First back surface electrode 22: Second chip 22a: Second main surface 22b: Second back surface 221: Second main surface electrode 222, 224: Main surface electrode 223: Second back surface electrode 231, 232: Die bonding layer 30: Lead frame 301: Frame portion 302: Suspension portion 31: Conductive member 311: First main body portion 311a, 311b: Partition portion 312: First bonding portion 312a: Strip-shaped portion 313: Second bonding portion 314: First connecting portion 315: Second connecting portion 319: Through hole 32: Conductive member 321: Second main body portion 321a, 321b, 321c: Partition portion 322: Third bonding portion 323: Fourth bonding portion 323a: Strip-shaped portion 324: Third connecting portion 325: Fourth connecting portion 329: Through hole 33: First bonding layer 34: Second bonding layer 35: Third bonding layer 36: Fourth bonding layer 41A, 41B, 42A, 42B: Conductive member 50: Sealing resin 51: Resin main surface 52: Resin back surface 53: First side surface 54: Second side surface 55: Third side surface 56: Recess 57: Groove portion 581, 582: Recess 60: Insulating member 61: First insulating member 62: Second insulating member 63: Third insulating member

Claims

1. A semiconductor circuit unit; A first conductive member that is electrically connected to the semiconductor circuit portion; A second conductive member that is electrically connected to the semiconductor circuit portion; an insulating member in contact with the first conductive member and the second conductive member; a sealing resin that covers the semiconductor circuit portion, the first conductive member, the second conductive member, and a part of the insulating member; Equipped with The first conductive member and the second conductive member are fixed by the insulating member.

2. the semiconductor circuit unit includes a first chip and a second chip, the first conductive member is joined to the first chip, The semiconductor device according to claim 1 , wherein the second conductive member is joined to the second chip.

3. the first chip and the second chip are electrically connected in series; The semiconductor device according to claim 2 , wherein the semiconductor circuit portion constitutes a half-bridge circuit.

4. a first mounting portion for mounting the first chip; a second mounting portion for mounting the second chip; The semiconductor device according to claim 3 , further comprising: a first terminal lead spaced apart from said first mounting portion and said second mounting portion.

5. the first chip has a first main surface facing one side in a thickness direction of the sealing resin, a first back surface facing the other side in the thickness direction, a first main surface electrode formed on the first main surface, and a first back surface electrode formed on the first back surface; the first back surface electrode faces the first mounting portion and is electrically connected to the first mounting portion; the second chip has a second main surface facing the one side in the thickness direction, a second back surface facing the other side in the thickness direction, a second main surface electrode formed on the second main surface, and a second back surface electrode formed on the second back surface; The semiconductor device according to claim 4 , wherein the second back surface electrode faces the second mounting portion and is electrically connected to the second mounting portion.

6. the first conductive member electrically connects the first principal surface electrode and the second mounting portion; The semiconductor device according to claim 5 , wherein the second conductive member electrically connects the second main surface electrode and the first terminal lead.

7. The semiconductor device according to claim 6 , wherein the first mounting portion is located on one side of the second mounting portion in a first direction perpendicular to the thickness direction.

8. a second terminal lead extending from the first mounting portion in a second direction perpendicular to the thickness direction and the first direction; a third terminal lead extending in the second direction from the second mounting portion; Further equipped with The semiconductor device according to claim 7 , wherein the first terminal lead, the second terminal lead, and the third terminal lead are arranged in the first direction.

9. The semiconductor device according to claim 8 , wherein the first terminal lead is located between the second terminal lead and the third terminal lead in the first direction.

10. A fourth terminal lead; A fifth terminal lead; a third conductive member electrically connecting the first chip and the fourth terminal lead; a fourth conductive member electrically connecting the first chip and the fifth terminal lead; Further equipped with 10. The semiconductor device according to claim 9, wherein the fourth terminal lead and the fifth terminal lead are located on the one side in the first direction relative to the second terminal lead and are adjacent to each other in the first direction.

11. The insulating member is a first insulating member, and a second insulating member is further provided, the third conductive member and the fourth conductive member are each a plate-shaped member, The semiconductor device according to claim 10 , wherein the second insulating member fixes the third conductive member and the fourth conductive member.

12. A sixth terminal lead; A seventh terminal lead; a fifth conductive member electrically connecting the second chip and the sixth terminal lead; a sixth conductive member electrically connecting the second chip and the seventh terminal lead; Further equipped with 11 . The semiconductor device according to claim 10 , wherein the sixth terminal lead and the seventh terminal lead are located on the other side of the third terminal lead in the first direction and are adjacent to each other in the first direction.

13. Further comprising a third insulating member; each of the fifth conductive member and the sixth conductive member is a plate-shaped member; The semiconductor device according to claim 12 , wherein the third insulating member fixes the fifth conductive member and the sixth conductive member.

14. the first chip is either a transistor or a diode; 14. The semiconductor device according to claim 2, wherein the second chip is either a transistor or a diode.

15. 14. The semiconductor device according to claim 1, wherein the insulating member is formed in a portion where the first conductive member and the second conductive member are adjacent to each other as viewed in a thickness direction of the sealing resin.

16. The semiconductor device according to claim 1 , wherein the insulating member contains the same resin material as the sealing resin.

17. 14 . The semiconductor device according to claim 1 , wherein a portion of the first conductive member and a portion of the second conductive member are sandwiched between the insulating members in a thickness direction.

18. providing a lead frame including a first conductive member and a second conductive member; a step of fixing the first conductive member and the second conductive member with an insulating member in the lead frame state; a step of joining the first conductive member and the second conductive member to a semiconductor circuit portion while the first conductive member and the second conductive member are fixed by the insulating member; and forming a sealing resin that covers the first conductive member, the second conductive member, and the semiconductor circuit portion.