Simulation program, simulation method, and information processing device

Abstract

The present invention improves the efficiency of calculating the probability of occurrence of logical errors.　An information processing device (10) generates error patterns (2-4) indicating a first data qubit that generates an error among a plurality of data qubits included in a two-dimensional lattice array in which the plurality of data qubits and a plurality of auxiliary qubits are arranged alternately in each of the row and column directions. The information processing device (10) determines whether or not the first data qubit indicated in the error patterns (2-4) meets predetermined determination criteria. If the determination criteria are met, the information processing device (10) determines that no logical error occurs in the error patterns (2-4). If the determination criteria are not met, the information processing device (10) determines whether or not a logical error has occurred on the basis of error detection information with flipped states of the auxiliary qubits adjacent to the first data qubit in the row or column direction as indicated in the error patterns (2-4).

Description

Simulation program, simulation method, and information processing device

[0001] The present invention relates to a simulation program, a simulation method, and an information processing device for quantum bit error correction.

[0002] Quantum computer calculations are achieved by initializing, operating gates, and performing measurements on multiple qubits. In quantum computers, errors (physical errors) occur in qubits due to environmental noise and other factors during these qubit operations. Therefore, in quantum computers, qubit redundancy is implemented, just like in classical computers (also known as von Neumann computers), to identify error qubits and their contents.

[0003] Surface coding is one method for identifying error qubits and the nature of the error using redundant qubits. In surface coding, data qubits and auxiliary qubits are arranged alternately in a two-dimensional lattice. The state of a data qubit among multiple qubits (data qubits and auxiliary qubits) arranged in the lattice is encoded into a single logical qubit. Each column of auxiliary qubits is used for either X error detection or Z error detection. When performing surface coding, a quantum computer first appropriately initializes the logical quantum state. When detecting an error, it performs gate operations between one auxiliary qubit and four surrounding data qubits and measures the auxiliary qubit. The quantum computer detects an X error or a Z error based on the value of the auxiliary qubit. The quantum computer then performs gate operations for error correction processing on the qubit using information indicating the type of error and the position information of the data qubit identified as the error location.

[0004] For example, quantum error correction methods have been proposed that involve correcting a stream of syndrome measurements generated by a quantum computer, and techniques have also been proposed for optimizing physical parameters in fault-tolerant quantum computing to reduce frequency congestion.

[0005] Special table 2020-535690 publication Special table 2020-515970 publication

[0006] When an error occurs in a predetermined number or more of the quantum bits that make up one logical quantum bit, error correction may fail even when using a surface code. Such an error correction failure is called a logical error.

[0007] In surface codes, the probability of a logical error occurring varies depending on the number of qubits in the two-dimensional lattice array that represents one logical qubit. The probability of a logical error occurring also varies depending on the rate at which qubit errors occur due to environmental noise, etc. Therefore, in order to evaluate the performance of quantum error correction using surface codes, it is possible to simulate error correction using surface codes using a classical computer. With an actual quantum computer, it is not possible to determine whether a logical error has occurred without measuring the data qubits themselves, but with a simulation, the location of the error can be determined in advance. Therefore, by simulating error correction using surface codes under specified conditions, it is possible to determine whether a logical error will occur under those conditions.

[0008] In error correction simulations, the probability of logical errors occurring is evaluated as the performance of an error-correcting code. For example, N error patterns (N is a natural number) are generated, and each is decoded (the process of identifying the location of the error), and a determination is made as to whether a logical error has occurred based on the error pattern and the decoding results. If the total number of logical errors is m (m is an integer greater than or equal to 0), the logical error probability is calculated as m / N. N is generally a very large value, between 10,000 and 1,000,000, to minimize the influence of statistical errors. Because numerous decoding operations are required to calculate the logical error probability, the calculation time is long.

[0009] In one aspect, the present invention aims to improve the efficiency of calculating the probability of logical error occurrence.

[0010] One proposal provides a simulation program for causing a computer to execute the following processes: the computer generates an error pattern indicating a first data qubit that generates an error among multiple data qubits included in a two-dimensional lattice array in which multiple data qubits and multiple auxiliary qubits are alternately arranged in both row and column directions; the computer determines whether the first data qubit indicated in the error pattern satisfies a predetermined judgment criterion; if the judgment criterion is satisfied, the computer determines that no logical error has occurred in the error pattern; and if the judgment criterion is not satisfied, the computer determines whether a logical error has occurred based on error detection information in which the state of an auxiliary qubit adjacent in the row or column direction to the first data qubit indicated in the error pattern has been inverted.

[0011] According to one aspect, the efficiency of calculating the probability of logical error occurrence is improved. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention by way of example.

[0012] 1 is a diagram illustrating an example of a simulation method according to a first embodiment; FIG. 1 is a diagram illustrating an example of hardware for a computer that executes a surface code simulation; FIG. 1 is a diagram illustrating an example of an error occurrence situation in a quantum bit; FIG. 2 is a diagram illustrating an example of quantum bit redundancy; FIG. 2 is a diagram illustrating an example of a quantum bit configuration for performing a surface code; FIG. 3 is a diagram illustrating an example of measurement results of an auxiliary quantum bit when an error occurs; FIG. 4 is a diagram illustrating an example of error correction using a surface code; FIG. 5 is a diagram illustrating an example of a case where the location of an error cannot be uniquely identified; FIG. 6 is a diagram illustrating an example of a logical error due to miscorrection; FIG. 7 is a diagram illustrating an example of the relationship between physical error probability and logical error probability; FIG. 8 is a diagram illustrating an example of an error pattern; FIG. 9 is a block diagram illustrating functions of a computer for performing a surface code simulation; FIG. 10 is a diagram illustrating an example of a determination of whether or not decoding is omitted;

[0013] The present embodiment will be described below with reference to the drawings. Note that each embodiment can be implemented by combining multiple embodiments within a consistent range. [First Embodiment] The first embodiment is a simulation method that can efficiently determine whether or not a logical error has occurred in quantum error correction.

[0014] Fig. 1 is a diagram illustrating an example of a simulation method according to a first embodiment. Fig. 1 shows an information processing device 10 for implementing the simulation method according to the first embodiment. The information processing device 10 can implement the simulation method according to the first embodiment by, for example, executing a simulation program.

[0015] The information processing device 10 includes a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or a storage device included in the information processing device 10. The processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing device 10.

[0016] The storage unit 11 stores simulation condition 1. For example, simulation condition 1 includes a physical error probability. The physical error probability is the probability that an error occurs in a data quantum bit.

[0017] The processing unit 12 performs a simulation of quantum bit error correction based on simulation condition 1. The processing unit 12 calculates the probability of a logical error occurring in a predetermined quantum bit error correction method through the simulation.

[0018] For example, processing unit 12 determines a first data quantum bit that generates an error among a plurality of data quantum bits included in a two-dimensional lattice array in which a plurality of data quantum bits and a plurality of auxiliary quantum bits are alternately arranged in the row and column directions, and then generates error patterns 2 to 4 that represent the first data quantum bit in the two-dimensional lattice array.

[0019] For example, processing unit 12 uses a random number to determine, for each data quantum bit, whether or not to generate an error at the physical error probability indicated in simulation condition 1. Processing unit 12 then generates error patterns 2 to 4 that indicate the data quantum bits for which it has been determined that an error will be generated.

[0020] For each of the generated error patterns 2 to 4, the processing unit 12 determines whether the first data quantum bits indicated in the error patterns 2 to 4 satisfy a predetermined criterion. The predetermined criterion may be, for example, a first criterion that the number of first data quantum bits that cause errors is equal to or less than a predetermined value corresponding to the size of the two-dimensional lattice array. The predetermined value corresponding to the size of the two-dimensional lattice array in the first criterion is, for example, 1 / 2 of the code distance of the two-dimensional lattice array minus 1.

[0021] The code distance is the minimum number of data qubits included on one side of a two-dimensional lattice array. For example, error patterns 2 to 4 include three data qubits on the vertical side and four data qubits on the horizontal side. Therefore, the code distance for error patterns 2 to 4 is "3." When the code distance is "3," half of the value obtained by subtracting 1 from the code distance is "1."

[0022] Furthermore, a second predetermined criterion may be applied, which is that the maximum number of first data quantum bits included in the same row or column of the two-dimensional lattice array is less than or equal to a predetermined value (e.g., "1").

[0023] If the error pattern satisfies the judgment criterion, the processing unit 12 determines that no logical error will occur in that error pattern. For example, error pattern 2 has only one first data quantum bit that generates an error. In this case, the first judgment criterion is satisfied. Therefore, when the first judgment criterion is applied as the judgment criterion, it is determined that no logical error will occur in quantum error correction for error pattern 2.

[0024] Error pattern 3 has three first data qubits that generate errors. Therefore, the first criterion is not met. On the other hand, the first data qubits included in error pattern 3 are all in different rows and columns. Therefore, the maximum number of first data qubits in the same row or column is "1," and the second criterion is met. When the second criterion is applied as the criterion, it is determined that no logical error occurs in quantum error correction for error pattern 3.

[0025] Error pattern 4 has two first data qubits that generate errors. Therefore, the first judgment criterion is not satisfied. Furthermore, the first data qubits included in error pattern 4 are included in the same row. Therefore, the maximum number of first data qubits in the same row or column is "2", and the second judgment criterion is not satisfied. Even if both the first judgment criterion and the second judgment criterion are applied as judgment criteria, error pattern 4 does not satisfy the judgment criterion. In this case, it is determined that there is a possibility that a logical error will occur in quantum error correction for error pattern 4.

[0026] If the judgment criterion is not met, the processing unit 12 determines whether a logical error has occurred based on error detection information in which the state of an auxiliary quantum bit adjacent to the first data quantum bit in the row or column direction indicated by the corresponding error pattern is inverted. For example, the processing unit 12 searches for a data quantum bit error pattern that inverts the inverted auxiliary quantum bit according to a predetermined quantum error correction method, and identifies the data quantum bit in which the error has occurred. The processing unit 12 determines whether a logical error has occurred based on the identified data quantum bit and the first data quantum bit. For example, the processing unit 12 determines that a logical error has occurred if the identified data quantum bit and the first data quantum bit are continuous from one side of the two-dimensional lattice array to the opposite side.

[0027] For example, when an ancillary quantum bit is inverted based on error pattern 4, if the data quantum bit whose state is inverted as an error in error pattern 4 is identified as the erroneous data quantum bit, no logical error will occur. However, if another data quantum bit that inverts the ancillary quantum bit based on error pattern 4 is identified, a logical error may occur.

[0028] In this way, by determining whether or not a logical error has occurred for the generated error patterns 2 to 4, the probability of a logical error occurring according to a predetermined quantum error correction method can be calculated. Moreover, if error patterns 2 to 4 satisfy predetermined criteria, the process of identifying the location of an error occurring based on the inverted auxiliary quantum bit for that error pattern is omitted. As a result, the number of times the process of identifying the location of an error occurring is reduced. This improves the efficiency of calculating the probability of a logical error occurring when quantum error correction is performed according to a predetermined method.

[0029] Second Embodiment Next, a second embodiment will be described. The second embodiment is a computer that executes a simulation of error correction using a surface code for errors that occur randomly in a quantum computer (hereinafter referred to as a surface code simulation) and efficiently determines whether or not a logical error has occurred.

[0030] 2 is a diagram illustrating an example of hardware of a computer that executes a surface code simulation. The computer 100 is entirely controlled by a processor 101. A memory 102 and multiple peripheral devices are connected to the processor 101 via a bus 109. The processor 101 may be a multiprocessor. The processor 101 is, for example, a central processing unit (CPU), a micro processing unit (MPU), or a digital signal processor (DSP). At least some of the functions realized by the processor 101 executing a program may be realized by an electronic circuit such as an application specific integrated circuit (ASIC) or a programmable logic device (PLD).

[0031] The memory 102 is used as a main storage device of the computer 100. The memory 102 temporarily stores at least a portion of the OS (Operating System) programs and application programs to be executed by the processor 101. The memory 102 also stores various data used in processing by the processor 101. The memory 102 may be, for example, a volatile semiconductor storage device such as a RAM (Random Access Memory).

[0032] The peripheral devices connected to the bus 109 include a storage device 103 , a GPU (Graphics Processing Unit) 104 , an input interface 105 , an optical drive device 106 , a device connection interface 107 , and a network interface 108 .

[0033] The storage device 103 electrically or magnetically writes and reads data to and from a built-in recording medium. The storage device 103 is used as an auxiliary storage device for the computer 100. The storage device 103 stores an OS program, application programs, and various data. Note that the storage device 103 may be, for example, a hard disk drive (HDD) or a solid state drive (SSD).

[0034] The GPU 104 is an arithmetic unit that performs image processing and is also called a graphics controller. A monitor 21 is connected to the GPU 104. The GPU 104 displays images on the screen of the monitor 21 in accordance with commands from the processor 101. The monitor 21 may be a display device using organic electroluminescence (EL) or a liquid crystal display device.

[0035] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals sent from the keyboard 22 and the mouse 23 to the processor 101. The mouse 23 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

[0036] The optical drive device 106 uses a laser beam or the like to read data recorded on an optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded so that it can be read by reflected light. Examples of the optical disc 24 include a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (Rewritable).

[0037] The device connection interface 107 is a communication interface for connecting peripheral devices to the computer 100. For example, a memory device 25 or a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a function for communicating with the device connection interface 107. The memory reader / writer 26 is a device for writing data to a memory card 27 or reading data from the memory card 27. The memory card 27 is a card-type recording medium.

[0038] The network interface 108 is connected to the network 20. The network interface 108 transmits and receives data to and from other computers or communication devices via the network 20. The network interface 108 is a wired communication interface that is connected by a cable to a wired communication device such as a switch or a router. The network interface 108 may also be a wireless communication interface that is connected by radio waves to a wireless communication device such as a base station or an access point.

[0039] The computer 100 can realize the processing functions of the second embodiment by using the hardware described above. Note that the information processing device 10 shown in the first embodiment can also be realized by using hardware similar to that of the computer 100 shown in FIG. 2.

[0040] The computer 100 realizes the processing functions of the second embodiment by executing a program recorded on, for example, a computer-readable recording medium. The program describing the processing to be executed by the computer 100 can be recorded on various recording media. For example, the program to be executed by the computer 100 can be stored in the storage device 103. The processor 101 loads at least a portion of the program from the storage device 103 into the memory 102 and executes the program. The program to be executed by the computer 100 can also be recorded on a portable recording medium such as the optical disk 24, the memory device 25, or the memory card 27. The program stored on the portable recording medium becomes executable after being installed on the storage device 103 under the control of, for example, the processor 101. The processor 101 can also read and execute the program directly from the portable recording medium.

[0041] Before describing the surface code simulation, we will now explain error correction by surface codes in quantum computers and the causes of logical errors with reference to FIGS. 3 to 9. FIG. 3 is a diagram showing an example of an error occurrence situation in a quantum bit. The quantum bit 31 is affected by various noises. Types of noise include environmental noise, noise during quantum bit operation, and interference from other quantum bits. The quantum bit 31 may unintentionally change state due to the influence of noise. Such unintentional state changes are quantum bit errors. Errors that occur in quantum bits include bit inversion errors (X errors) and phase inversion errors (Z errors).

[0042] Current quantum computers have a high probability of quantum bit errors due to environmental noise, making it difficult to accurately perform large-scale calculations. Therefore, in order to put quantum computers into practical use, it is necessary to be able to perform calculations while repairing errors (quantum error correction). Quantum error correction is a process that maintains the correct state by, for example, making quantum bits redundant and detecting and correcting errors.

[0043] 4 is a diagram showing an example of quantum bit redundancy. When one quantum bit 31 is made redundant, the quantum state represented by the quantum bit 31 is represented by a logical quantum state by a logical quantum bit 32. The logical quantum bit 32 is made up of a plurality of quantum bits 32a to 32h, ...

[0044] Here, it is assumed that an error occurs in one quantum bit 32h that constitutes the logical quantum bit 32. In this case, the error quantum bit and the error content are identified by a process for identifying the error quantum bit and the error content.

[0045] If quantum bit 32 h is correctly identified as an error quantum bit and the error content is also correctly identified, an error correction gate operation is performed on quantum bit 32 h. The error correction corrects the state of logical quantum bit 32 to the state it would be in if no error had occurred.

[0046] 4, it is assumed that the error quantum bit has been correctly identified, but identifying the error quantum bit is not easy. Information about the states of the quantum bits 32a-32h, ... that make up the logical quantum bit 32 is used to identify the error quantum bit, but if the quantum bit is measured directly, the quantum state will be destroyed and the calculation will not be able to continue. For this reason, auxiliary quantum bits are introduced, and by measuring the state of the auxiliary quantum bits, information about the states of the quantum bits 32a-32h, ... that make up the logical quantum bit 32 can be obtained.

[0047] Surface coding is a technique for identifying error qubits based on the qubit state obtained using an auxiliary qubit. Surface coding is a typical coding (redundancy) technique in quantum error correction.

[0048] Fig. 5 is a diagram showing an example of a quantum bit configuration for performing surface coding. In the example of Fig. 5, quantum bits are arranged in a two-dimensional lattice. Data quantum bits 40 and auxiliary quantum bits 41, 42 are arranged alternately in both the row direction and the column direction. The auxiliary quantum bits 41, 42 are divided into auxiliary quantum bits 41 for X error detection and auxiliary quantum bits 42 for Z error detection. The auxiliary quantum bits 41 for X error detection and the auxiliary quantum bits 42 for Z error detection are arranged alternately in each column.

[0049] All of the data qubits 40 are used to form one logical qubit. The state of a logical qubit is called a logical quantum state. The number of data qubits on the shorter side of the two-dimensional lattice arrangement of qubits that make up the logical qubit is called the code distance.

[0050] The quantum bits shown in Figure 5 are part of the quantum bits used for error correction using surface codes. When performing error correction using surface codes, the quantum number of one side of the two-dimensional lattice array including all the quantum bits used for error correction (the sum of data quantum bits and auxiliary quantum bits) is odd, and the data quantum bits are arranged at the four corners (see Figure 9, etc.).

[0051] First, the logical quantum state is properly initialized, and then, in error detection, a gate operation (two-qubit operation) is performed between one auxiliary quantum bit and four surrounding data quantum bits, and the presence or absence of an error can be detected by measuring the auxiliary quantum bit. Error detection is divided into X error detection using auxiliary quantum bit 41 for X error detection and Z error detection using auxiliary quantum bit 42 for Z error detection.

[0052] 6 is a diagram showing an example of the measurement results of the auxiliary quantum bits when an error occurs. In the error occurrence pattern 43 shown in FIG. 6, a Z error occurs in two data quantum bits 40a and 40b. The Z error is detected by the auxiliary quantum bit for Z error detection. The auxiliary quantum bit for X error detection is omitted in FIG. 6.

[0053] In quantum error correction using surface codes, a predetermined two-qubit operation is first performed between adjacent data qubits and auxiliary qubits: a two-qubit operation for Z error detection is performed between the data qubit and the auxiliary qubit for Z error detection, and a two-qubit operation for X error detection is performed between the data qubit and the auxiliary qubit for X error detection.

[0054] The two-qubit operation inverts the states of the auxiliary qubits 42a-42d for Z error detection that are adjacent to the data qubits 40a, 40b in which the Z error occurred. By measuring the states of all the auxiliary qubits after the two-qubit operation, the inversion of the auxiliary qubits 42a-42d can be detected. Data indicating the measurement results of the auxiliary qubits is called syndrome 44. Syndrome 44 is an example of the error detection information shown in the first embodiment.

[0055] In the error correction process, the position of the data quantum bit in which an error has occurred is identified based on the syndrome 44. Fig. 7 is a diagram showing an example of error correction using a surface code. When performing error correction using a surface code, first, matching of inverted ancillary quantum bits is performed based on the syndrome 44. In the matching, pairs of inverted ancillary quantum bits 42a to 42d are generated. In the example of Fig. 7, pairs of ancillary quantum bit 42a and ancillary quantum bit 42b, and pairs of ancillary quantum bit 42c and ancillary quantum bit 42d are generated.

[0056] Then, the location of the error is identified based on the pair of ancillary quantum bits generated by matching. That is, for each pair of inverted ancillary quantum bits, one or more data quantum bits are identified that will simultaneously invert the pair if an error occurs in the corresponding data quantum bit. In the example of Figure 7, data quantum bit 40a is identified as the location of the error based on the pair of ancillary quantum bits 42a and 42b. Data quantum bit 40b is identified as the location of the error based on the pair of ancillary quantum bits 42c and 42d.

[0057] In this way, the data quantum bit where the error occurred is identified based on syndrome 44. The process of identifying such a data quantum bit where an error occurred is called decoding.

[0058] However, surface codes have the property that they cannot uniquely identify the location of an error. For example, a different error location is identified for each matching candidate of the inverted ancillary quantum bit. Therefore, during decoding, for example, the solution with the fewest error locations (candidate error locations) is identified as the location of the error.

[0059] 8 is a diagram showing an example of a case where the location of an error cannot be uniquely identified. In syndrome 44, the states of four ancillary quantum bits 42a to 42d are inverted. Therefore, matching of the four inverted ancillary quantum bits 42a to 42d is performed.

[0060] The first matching candidate 51 generates a pair of ancillary quantum bits 42 a and 42 b, and a pair of ancillary quantum bits 42 c and 42 d. When the location of an error is identified based on these pairs, for example, two data quantum bits are identified as the location of the error.

[0061] The second matching candidate 52 generates a pair of ancillary quantum bit 42 a and ancillary quantum bit 42 c, and a pair of ancillary quantum bit 42 b and ancillary quantum bit 42 d. When the error occurrence location is identified based on these pairs, for example, six data quantum bits are identified as the error occurrence location.

[0062] The third matching candidate 53 generates a pair of ancillary quantum bit 42 a and ancillary quantum bit 42 d, and a pair of ancillary quantum bit 42 b and ancillary quantum bit 42 c. When the error occurrence location is identified based on these pairs, for example, four data quantum bits are identified as the error occurrence location.

[0063] In this case, the number of error locations identified based on the first matching candidate 51 is the smallest. In other words, it is determined that the error locations identified based on the first matching candidate 51 are most likely to indicate the correct error locations.

[0064] In this way, the locations where errors occur are identified so as to minimize the number of error occurrences. Quantum error correction is then performed by inverting the state of the data qubits at the identified error locations.

[0065] However, the error location identified during decoding is only a high probability, and does not guarantee that an error actually occurred at that location. Therefore, in quantum error correction, an error correction process (state reversal) may be performed on an incorrect data qubit.

[0066] 9 is a diagram showing an example of a logical error due to miscorrection. In the error pattern 61 shown in FIG. 9, a Z error occurs in multiple data qubits 61a-61c on the same row. In this case, the states of auxiliary qubits 61d-61h adjacent to any of data qubits 61a-61c on the same row are inverted.

[0067] When a syndrome in which ancillary quantum bits 61d to 61h are inverted is obtained, decoding shown in a first decoding example 61-1 and decoding shown in a second decoding example 61-2 are possible.

[0068] In the first decoding example 61-1, the data quantum bits 61a to 61c in which the error occurred are correctly identified. If quantum error correction is performed on the data quantum bits 61a to 61c identified in the first decoding example 61-1, the quantum error correction will be successful.

[0069] On the other hand, in the second decoding example 61-2, data quantum bits 61i-61k different from the data quantum bits 61a-61c in which an error occurred are identified. When error correction processing is performed on the data quantum bits 61i-61k identified in the second decoding example 61-2, the data quantum bits 61a-61c and 61i-61k are ultimately inverted from their correct states. That is, in the second decoding example 61-2, the uncorrected data quantum bits 61a-61c and the incorrectly corrected data quantum bits 61i-61k are connected from one boundary to the opposite boundary of the two-dimensional lattice array representing one logical quantum bit. This state is called a logical error.

[0070] Logical errors change the logical quantum state. Therefore, if the calculation continues as is, the correct result will not be obtained. In other words, if a logical error occurs, quantum error correction will fail. Therefore, it is important to correctly evaluate logical errors when evaluating the performance of quantum error correction. For example, when a new quantum error correction method or a new decoding method is developed, the logical error probability is used as a performance evaluation value for that quantum error correction.

[0071] The probability of a logical error can be calculated through computer simulation. In other words, with an actual quantum computer, it is not possible to determine whether a logical error has occurred or how often it occurs without measuring the data qubits themselves. However, if a simulation of error correction using surface codes is performed using a classical computer, the location of the error can be determined in advance, making it possible to determine whether a logical error has occurred.

[0072] The logical error probability depends on the code distance, the frequency of error occurrence of data quantum bits (physical error probability), etc. Fig. 10 is a diagram showing an example of the relationship between the physical error probability and the logical error probability. In a computer simulation of quantum error correction, a physical error is generated with an arbitrary physical error probability, and the logical error probability at that time can be calculated.

[0073] For example, in a computer simulation, N error patterns (N is a natural number) are generated, and each of them is decoded to determine the number m of logical errors (an integer equal to or greater than 0). In this case, the logical error probability P L is "P L = m / N".

[0074] In the graph 62, the horizontal axis represents the physical error probability p and the vertical axis represents the logical error probability P L Graph 62 shows broken lines 62a, 62b, and 62c indicating the logical error probability according to the physical error probability for each code distance. Line 62a shows the logical error probability according to the physical error probability when a logical quantum bit with a code distance d of "11" is used. Line 62b shows the logical error probability according to the physical error probability when a logical quantum bit with a code distance d of "21" is used. Line 62c shows the logical error probability according to the physical error probability when a logical quantum bit with a code distance d of "31" is used.

[0075] The dashed line 62d in the graph 62 indicates the position where the physical error probability and the logical error probability are equal. The further the logical error probability is below the dashed line 62d, the higher the performance of quantum error correction.

[0076] In a particular quantum error correction method, the higher the physical error probability, the higher the logical error probability. Furthermore, the longer the code distance, the higher the quantum error correction performance. Different quantum error correction methods produce different broken lines showing the logical error probability corresponding to the physical error probability. Therefore, computer simulations are used to calculate the logical error probability corresponding to the physical error probability for each quantum error correction method, and the performance of quantum error correction is evaluated. To accurately evaluate performance, it is necessary to generate a sufficiently large number of error patterns. For example, the number N of error patterns used when evaluating the performance of quantum error correction using computer simulations is generally between 10,000 and 1,000,000.

[0077] When calculating the logical error probability using computer simulation, decoding calculations are performed for each physical error occurrence pattern, resulting in numerous decoding operations. In particular, when the physical error probability is small and the code distance is large, logical errors are rare events, so the number of error pattern samples required for accurate performance evaluation becomes enormous, and the time required to calculate the logical error probability becomes extremely long.

[0078] Therefore, a technology to reduce the amount of calculation is required. In the calculation of the logical error probability of quantum error correction, the calculation for decoding accounts for a large proportion. In decoding, all matching candidates as shown in Figure 8 are searched based on the syndrome corresponding to the error pattern, and then the location of the error in each matching candidate is searched. In such a search, the search space becomes wider as the code distance increases, and the amount of calculation increases.

[0079] Therefore, the computer 100 omits decoding of generated error patterns that are estimated to cause no logical errors. For example, if the number of physical errors is very small compared to the code distance, logical errors will hardly occur.

[0080] 11 is a diagram showing an example of an error pattern. Error pattern 71 shows the positions in a two-dimensional array of physical quantum bits that have been inverted by a Z error, among the physical quantum bits that make up a logical quantum bit with a code distance of 11 (d=11). In error pattern 71, there are two inverted data quantum bits. In other words, the number of errors is "2." The state of the auxiliary quantum bit adjacent to the inverted data quantum bit is also inverted. In a case like error pattern 71, the probability that a logical error will occur during decoding is extremely low.

[0081] The computer 100 improves the efficiency of calculating the logical error probability by omitting decoding when it can be estimated that a logical error such as that shown in the error pattern 71 will not occur. Specifically, the computer 100 defines a criterion for omitting decoding, determines that an error pattern that satisfies the criterion has an extremely low probability of causing a logical error, and omits the decoding calculation for that error pattern.

[0082] 12 is a block diagram showing the functions of a computer for performing a surface code simulation. The computer 100 has a storage unit 110, a simulation control unit 120, an error pattern generation unit 130, a decoding omission determination unit 140, a decoding unit 150, and a logical error determination unit 160.

[0083] The storage unit 110 stores simulation conditions 111 and simulation results 112. The simulation conditions 111 include conditions such as the number of error patterns to be generated, the code distance, and the physical error probability. If a quantum error correction method (program) is prepared, the simulation conditions 111 also include a designation of the method to be applied. The simulation results 112 are information indicating the results of a quantum error correction simulation. For example, the simulation results 112 include the logical error probability when quantum error correction is performed under the corresponding conditions, in association with information such as the quantum error correction method, the code distance, and the physical error probability.

[0084] The simulation manager 120 manages the simulation of quantum error correction using surface codes. For example, the simulation manager 120 instructs the error pattern generator 130 to generate an error pattern in accordance with the simulation conditions 111. The simulation manager 120 also obtains the logical error determination results for each error pattern from the logical error determination unit 160 and calculates the logical error probability. The simulation manager 120 then stores the calculated logical error probability in the storage unit 110 as the simulation result 112.

[0085] The error pattern generation unit 130 generates an error pattern by generating errors for data quantum bits of the code distance indicated in the simulation conditions at the physical error probability indicated in the simulation conditions. The error pattern generation unit 130 transmits the generated error pattern to the decoding omission determination unit 140.

[0086] The decoding skip determination unit 140 determines whether or not to skip decoding for the error pattern generated by the error pattern generation unit 130. For example, the decoding skip determination unit 140 compares the error pattern with a predetermined determination criterion, and determines to skip decoding if the criterion is met. If the decoding skip determination unit 140 determines to skip decoding, it notifies the logical error determination unit 160 that decoding has been skipped. If the decoding skip determination unit 140 determines not to skip decoding, it instructs the decoding unit 150 to perform decoding.

[0087] In response to a decoding instruction, the decoding unit 150 performs decoding based on a syndrome corresponding to the generated error pattern. The decoding includes, for example, generating a syndrome, matching ancillary quantum bits whose states have been inverted, generating a solution indicating the error location according to the matching result, and identifying the most likely solution. The finally identified solution becomes the decoding result indicating the data quantum bit estimated as the error location.

[0088] The logical error determination unit 160 determines whether a logical error has occurred based on the error pattern and the decoding result, and notifies the simulation control unit 120 of the determination result on whether a logical error has occurred.

[0089] The function of each element shown in FIG. 12 can be realized, for example, by having a computer execute a program module corresponding to that element. In this way, the decoding omission determination unit 140 determines whether to omit decoding, and performs decoding only if it determines not to omit, thereby making it possible to efficiently calculate the quantum error probability. The following criteria can be considered as criteria for determining whether to omit decoding: First criterion: The number of errors n1 is (d-1) / 2 or less; Second criterion: The maximum number of errors n2 in the same row or column of the lattice is 1 or less. The first criterion is based on the presence of more than (d-1) / 2 physical errors for incorrect decoding to result in a logical error. For example, in the example shown in FIG. 9, the number of data qubits in the row direction is "6." If the number of data qubits in the column direction is also "6," the code distance d is "6." A logical error occurs when data qubits that remain inverted even after quantum error correction (error-indeterminate data qubits and miscorrected data qubits) continue from one side to the opposite side, as in the second decoding example 61-2 shown in Figure 9. Therefore, to cause a logical error, at least six data qubits that remain inverted even after quantum error correction are required. If the number of data qubits inverted due to errors is "2.5" (= (6 - 1) / 2) or less, the likelihood that four or more data qubits will be identified as errors by decoding is extremely low. Therefore, if the first judgment criterion is met, it can be determined that the possibility of a logical error is low.

[0090] The second criterion is based on the fact that even if the number of errors n exceeds (d−1) / 2, the likelihood of a logical error occurring is low if the error locations are dispersed. In other words, if there is one or fewer erroneous data qubits in each row or column of the two-dimensional lattice array, the likelihood of data qubits remaining inverted after quantum error correction becoming so continuous as to cause a logical error is extremely low.

[0091] 13 is a diagram showing an example of determining whether or not to omit decoding. In the example of FIG. 13, the code distance d is "11." In this case, "(d-1) / 2" in the first determination criterion is "5."

[0092] The number of errors n1 in error pattern 72 is "2." Because the number of errors n1 is equal to or less than "(d-1) / 2," error pattern 72 satisfies the first criterion. Furthermore, the maximum number of errors n2 in the same row or column of a data quantum bit in which an error has occurred in error pattern 72 is "1." Therefore, error pattern 72 also satisfies the second criterion. Because error pattern 72 satisfies both the first and second criterion, the decoding process for error pattern 72 is omitted.

[0093] The number of errors n1 in error pattern 73 is "10." Because the number of errors n1 is greater than "(d-1) / 2," error pattern 73 does not satisfy the first criterion. Furthermore, the maximum number of errors n2 in the same row or column of a data quantum bit in which an error has occurred in error pattern 73 is "1." Therefore, error pattern 73 satisfies the second criterion. Because error pattern 73 does not satisfy the first criterion but satisfies the second criterion, the decoding process for error pattern 73 is omitted.

[0094] The number of errors n1 in error pattern 74 is "6." Because the number of errors n1 is greater than "(d-1) / 2," error pattern 74 does not satisfy the first criterion. Furthermore, the maximum number of errors n2 in the same row or column of a data quantum bit in which an error has occurred in error pattern 74 is "6." Therefore, error pattern 74 does not satisfy the second criterion either. Because error pattern 74 satisfies neither the first nor the second criterion, a decoding process is performed on error pattern 74.

[0095] Next, the procedure for calculating the logical error probability of a Z error will be described. Fig. 14 is a flowchart showing an example of the procedure for the logical error (Z error) probability calculation process. The process shown in Fig. 14 will be described below in order of step number.

[0096] [Step S101] Upon receiving an instruction to calculate the quantum error probability for a predetermined quantum error correction method, the simulation control unit 120 initializes the number of logical error occurrences m to "0" (m=0).

[0097] [Step S102] The simulation controller 120 creates row number data R for the data quantum bits. The row number data R is an array of size Nd, where Nd is the number of data quantum bits. For example, the row number of the kth (k is an integer from 1 to Nd) data quantum bit is set as the value of the array of subscript k in the row number data R.

[0098] [Step S103] The error pattern generation unit 130 repeats the processes of steps S104 and S105 until the variable i indicating the number of loops is 1 to N, where N is an integer indicating the number of error patterns to be generated.

[0099] [Step S104] The error pattern generation unit 130 uses random numbers to create error pattern data EZ for Z errors in the data quantum bits. The error pattern data EZ is an array of size Nd. If a Z error is to be generated in the kth data quantum bit, the value of the array with subscript k is set to "1." If no error is to be generated in the kth data quantum bit (k is an integer from 1 to Nd), the value of the array with subscript k is set to "0."

[0100] For example, the error pattern generation unit 130 generates a random number (a real number between 0 and 1) for each data quantum bit. When the physical error probability is "a" (a is a real number between 0 and 1), the error pattern generation unit 130 determines to generate an error in the corresponding data quantum bit if the generated random number is less than or equal to a.

[0101] [Step S105] The decoding skip determination unit 140, the decoding unit 150, and the logical error determination unit 160 work together to execute a logical error occurrence determination process. If a logical error occurs in the error pattern indicated in the generated error pattern data EZ as a result of the logical error occurrence determination process, the number of logical errors m is counted up. The logical error occurrence determination process will be described in detail later (see FIG. 15).

[0102] [Step S106] If the loop variable i has reached N, the error pattern generation unit 130 proceeds to step S107. [Step S107] The simulation control unit 120 calculates the logical error probability. The logical error probability is obtained by dividing the number of logical errors m by the number of generated error patterns N.

[0103] In this way, the logical error probability can be calculated. Next, the logical error occurrence determination process will be described in detail. Figure 15 is a flowchart showing the details of the procedure for the logical error (Z error) occurrence determination process. The process shown in Figure 15 will be described below in order of step number.

[0104] [Step S121] The decoding skip determination unit 140 sums the values ​​of the error pattern data EZ. The decoding skip determination unit 140 defines the sum as n1. [Step S122] The decoding skip determination unit 140 uses the row number data R to sum the values ​​of the error pattern data EZ for each row. For example, the decoding skip determination unit 140 counts the number of data quantum bits for which the value "1" indicating an error is set in the error pattern data EZ, among the data quantum bits having the same row number set in the row number data R. The decoding skip determination unit 140 defines the maximum number of data quantum bits counted for each row as n2.

[0105] [Step S123] The decoding skip determination unit 140 determines whether either the first or second criterion is satisfied. For example, if "n1 ≦ (d−1) / 2", the decoding skip determination unit 140 determines that the first criterion is satisfied. Furthermore, if "n2 ≦ 1", the decoding skip determination unit 140 determines that the second criterion is satisfied. If at least one of the criteria is satisfied, the decoding skip determination unit 140 determines that no logical error has occurred and terminates the logical error occurrence determination process. If neither criterion is satisfied, the decoding skip determination unit 140 proceeds to step S124.

[0106] [Step S124] The decoding unit 150 decodes the generated error pattern. For example, the decoding unit 150 inverts the states of the auxiliary quantum bits adjacent to the data quantum bit in which the Z error occurred, based on the error pattern data EZ. Next, the decoding unit 150 identifies the data quantum bit to be identified as having an error based on the configuration (syndrome) of the inverted auxiliary quantum bits and a predetermined quantum error correction method.

[0107] [Step S125] The logical error determination unit 160 determines whether a logical error has occurred. For example, the logical error determination unit 160 identifies data qubits whose state is inverted from the correct state when error correction (state inversion) is performed on a data qubit identified as an error. Data qubits whose state is inverted from the correct state include data qubits in which an error occurred but was not corrected, and data qubits in which no error occurred but was corrected as an error. The logical error determination unit 160 determines that a logical error has occurred when data qubits whose state is inverted from the correct state continue from one side to the opposite side of the two-dimensional array of qubits that make up the logical qubit.

[0108] If a logical error occurs, the logical error determination section 160 advances the process to step S126. If a logical error does not occur, the logical error determination section 160 ends the logical error occurrence determination process.

[0109] [Step S126] The logical error determination unit 160 adds "1" to the number m of logical errors. In this way, the logical error probability for the Z error can be calculated. Similarly, the logical error probability for the X error can be calculated.

[0110] 16 is a flowchart showing an example of the procedure for calculating the probability of a logical error (X error). The process shown in FIG. 16 will be explained below in order of step number. [Step S201] When the simulation control unit 120 receives an instruction to calculate the quantum error probability for a predetermined quantum error correction method, it initializes the number of logical error occurrences m to "0" (m=0).

[0111] [Step S202] The simulation controller 120 creates column number data C for the data quantum bits. The column number data C is an array of size Nd. For example, the column number of the kth (k is an integer from 1 to Nd) data quantum bit is set as the value of the array with subscript k in the column number data C.

[0112] [Step S203] The error pattern generation unit 130 repeats the processes of steps S204 and S205 until the variable i, which indicates the number of loops, is 1 to N. [Step S204] The error pattern generation unit 130 uses random numbers to create error pattern data EX for X errors in the data quantum bits. The error pattern data EX is an array of size Nd. When an X error is to occur in the k-th data quantum bit, the value of the array with subscript k is set to "1".

[0113] [Step S205] The decoding skip determination unit 140, the decoding unit 150, and the logical error determination unit 160 work together to execute a logical error occurrence determination process. If a logical error occurs in the error pattern indicated in the generated error pattern data EX as a result of the logical error occurrence determination process, the number of logical errors m is counted up. The logical error occurrence determination process will be described in detail later (see FIG. 17).

[0114] [Step S206] If the loop variable i has reached N, the error pattern generation unit 130 proceeds to step S207. [Step S207] The simulation control unit 120 calculates the logical error probability. The logical error probability is obtained by dividing the number of logical errors m by the number of generated error patterns N.

[0115] In this way, the logical error probability can be calculated. Next, the logical error occurrence determination process for X errors will be described in detail. Figure 17 is a flowchart showing the details of the procedure for the logical error (X error) occurrence determination process. The process shown in Figure 17 will be described below in order of step number.

[0116] [Step S221] The decoding skip determination unit 140 sums the values ​​of the error pattern data EX. The decoding skip determination unit 140 defines the sum as n1. [Step S222] The decoding skip determination unit 140 uses the column number data C to sum the values ​​of the error pattern data EX for each column. For example, the decoding skip determination unit 140 counts the number of data quantum bits for which the value "1" indicating an error is set in the error pattern data EX, among the data quantum bits having the same column number set in the column number data C. The decoding skip determination unit 140 defines the maximum number of data quantum bits counted for each column as n2.

[0117] [Step S223] The decoding skip determination unit 140 determines whether either the first or second criterion is satisfied. If at least one of the criteria is satisfied, the decoding skip determination unit 140 determines that no logical error has occurred and terminates the logical error occurrence determination process. If neither criterion is satisfied, the decoding skip determination unit 140 proceeds to step S224.

[0118] [Step S224] The decoding unit 150 decodes the generated error pattern. For example, the decoding unit 150 inverts the states of the auxiliary quantum bits adjacent to the data quantum bit in which the X error occurred, based on the error pattern data EX. Next, the decoding unit 150 identifies the data quantum bit to be identified as having an error based on the configuration (syndrome) of the inverted auxiliary quantum bits and a predetermined quantum error correction method.

[0119] [Step S225] The logical error determination unit 160 determines whether a logical error has occurred. If a logical error has occurred, the logical error determination unit 160 proceeds to step S226. If a logical error has not occurred, the logical error determination unit 160 ends the logical error occurrence determination process.

[0120] [Step S226] The logical error determination unit 160 adds "1" to the number m of logical errors. In this way, the quantum error probability can also be calculated for X errors. By being able to calculate the quantum error probabilities for Z errors and X errors, it is possible to quantitatively evaluate the accuracy of the quantum error correction method applied to decoding. Moreover, since decoding is omitted for error patterns that are unlikely to result in quantum errors, the logical error probability can be calculated efficiently.

[0121] Below, we will specifically explain the difference in calculation time between the quantum error probability calculation method that omits decoding based on the first and second judgment criteria (partial decoding omission method) and other quantum error probability calculation methods.

[0122] The three quantum error probability calculation methods compared are as follows: Brute Force (BF): naive sampling Importance Sampling (ISA) Importance Splitting (ISP) BF generates a predetermined number of error patterns without considering processing efficiency, performs decoding for all error patterns, and calculates the logical error probability based on the decoding results. ISA is a method that prioritizes sampling for rare events.

[0123] The ISA generates a model with a focus on error patterns that rarely occur. Details of the ISA are described in J. Geweke, "Bayesian Inference in Econometric Models Using Monte Carlo Integration," Econometrica, Vol. 57, No. 6, November 1989, pp. 1317-1339.

[0124] ISP is a method for extrapolating probabilities in ranges that are difficult to sample. Details of ISP are described in "M. Garvels and D. Kroese, "A comparison of RESTART implementations," WSC '98: Proceedings of the 30th conference on Winter simulation, December 1998, Pages 601-608."

[0125] The results of measuring the calculation time and number of decoding attempts required to calculate the logical error probability with a certain degree of accuracy using each logical error probability calculation method are shown in Figures 18 and 19. The accuracy standard is set to be within the 95% confidence interval of the logical error probability calculated using BF. The minimum weight perfect matching (MWPM) algorithm is used as the decoding method.

[0126] Other simulation conditions are code distance d = 11, physical error probability p = 1, 2, 4, 6, 8%, and the number of BF samples is 10 million. The number of samples in the partial decoding omission method is the number required to satisfy the above accuracy standard, and varies depending on the physical error probability p.

[0127] 18 is a diagram showing an example of the results of calculation time measurements. Calculation time comparison table 81 shows the calculation time for each physical error probability for the partial decryption omission method, BF, and ISA. ISA can calculate the logical error probability for any physical error probability with one set of calculations, so the calculation time is for that one set. Note that ISP does not achieve sufficient calculation accuracy when the physical error probability is p≧1, so it is excluded from the calculation time comparison.

[0128] As shown in the calculation time comparison table 81, the calculation time of the partial decryption omission method is reduced to 1 / 6 when p = 1% and to 1 / 10 when p = 2% compared to BF. Furthermore, the calculation time of the partial decryption omission method is reduced to 1 / 4 or less compared to ISA.

[0129] 19 is a diagram showing an example of the results of counting the number of decryption attempts. A decryption attempt comparison table 82 shows the calculation time for each physical error probability for the partial decryption omission method, BF, and ISA. ISA can calculate the logical error probability for any physical error probability with one set of calculations, so the number of decryption attempts is the number of decryption attempts for that one set. Note that ISP does not achieve sufficient calculation accuracy when the physical error probability is p≧1, so it is excluded from the comparison of the number of decryption attempts.

[0130] According to the decoding count comparison table 82, the number of decoding times for the partial decoding omission method is 1 / 10 or less compared to BF for all physical error probabilities p. Also, the number of decoding times for the partial decoding omission method is 1 / 3 or less compared to ISA.

[0131] By applying this partial decoding omission method, the amount of calculation is reduced, and as a result, the calculation time is shortened. Furthermore, even if decoding is omitted for error patterns that are unlikely to result in quantum errors, the decrease in the calculation accuracy of the logical error probability is minimal.

[0132] 20 is a diagram showing an example of the calculation results of the logical error probability. A logical error probability comparison table 83 shows the logical error probability for each physical error probability for the partial decryption omission method and BF. The logical error probability shown in the logical error probability comparison table 83 is the average value of the logical error probability when 10 million sample calculations are performed three times. As shown in the logical error probability comparison table 83, when the logical error probability of BF is assumed to be correct, the error in the logical error probability of the partial decryption omission method is minimal.

[0133] In the partial decoding omission method, decoding is omitted if the error pattern satisfies a predetermined criterion. However, for some criterion, even if the criterion is satisfied, there remains a slight possibility that a logical error will occur as a result of decoding.

[0134] 21 is a diagram showing an example of the probability of logical errors occurring when the criteria are satisfied. A logical error occurrence count table 84 shows the number of occurrences of error patterns that satisfy each criterion, and the number m of logical errors that occur when the criterion is satisfied. The number m of logical errors that occur when the criterion is satisfied is a value that is counted by determining whether or not a logical error has occurred without skipping decoding even when the criterion is satisfied.

[0135] If the first criterion is satisfied, no logical errors will occur even if decryption is performed. If the second criterion is satisfied, some logical errors will occur if the physical error probability is 4% or more. Furthermore, the number m of logical errors that occurs when only one of the first and second criterion is satisfied is the same as the value when the second criterion is satisfied.

[0136] The "total" occurrence count in the logical error occurrence count table 84 is the total number of error patterns generated as targets for quantum error correction. The "total" logical error occurrence count m is the number of logical errors that occurred among all error patterns, including those that do not satisfy the criteria.

[0137] In this way, even if the first criterion is applied to omit decoding, the occurrence of a logical error will not be overlooked. Furthermore, if the second criterion is applied to omit decoding, a logical error may be overlooked if the physical error probability p is 4% or more, but this is extremely small compared to the total number of logical error occurrences. Therefore, the application of the second criterion does not significantly reduce the accuracy of the calculation of the logical error probability.

[0138] Other Embodiments In the second embodiment, the calculation of the logical error probability of a Z error and the calculation of the logical error probability of an X error are described separately, but these calculation processes may be performed consecutively.

[0139] Depending on the required accuracy of calculation for the logical error probability, the first or second criterion may be relaxed. For example, if the code distance is sufficiently large and the required accuracy is not strict, the upper limit of the maximum number of errors in the same row or column in the second criterion may be relaxed from "1" to "2".

[0140] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0141] 1 Simulation conditions 2 to 4 Error patterns 10 Information processing device 11 Storage unit 12 Processing unit

Claims

1. A simulation program that causes a computer to execute the following processes: generate an error pattern indicating a first data quantum bit that generates an error among a plurality of data quantum bits included in a two-dimensional lattice array in which the plurality of data quantum bits and a plurality of auxiliary quantum bits are arranged alternately in both the row and column directions; determine whether the first data quantum bit indicated in the error pattern satisfies a predetermined judgment criterion; if the criterion is satisfied, determine that no logical error has occurred in the error pattern; and if the criterion is not satisfied, determine whether a logical error has occurred based on error detection information in which the state of the auxiliary quantum bit adjacent to the first data quantum bit indicated in the error pattern in the row direction or the column direction is inverted.

2. The simulation program according to claim 1, wherein the process of determining whether the criterion is met determines whether a first criterion is met, that is, whether the number of the first data quantum bits is equal to or less than a value according to the size of the two-dimensional lattice array.

3. The simulation program according to claim 2, wherein in the process of determining whether the criteria are met, half of the value obtained by subtracting 1 from the minimum number of data quantum bits included on one side of the two-dimensional lattice array is set as a value according to the size of the two-dimensional lattice array.

4. A simulation program according to any one of claims 1 to 3, wherein the process of determining whether the criterion is met determines whether a second criterion is met, that is, whether the maximum number of first data quantum bits included in the same row or column of the two-dimensional lattice is equal to or less than a predetermined value.

5. A simulation method in which a computer performs the following steps: generating an error pattern indicating a first data quantum bit that generates an error among a plurality of data quantum bits included in a two-dimensional lattice array in which a plurality of data quantum bits and a plurality of auxiliary quantum bits are arranged alternately in each of the row and column directions; determining whether the first data quantum bit indicated in the error pattern satisfies a predetermined judgment criterion; if the judgment criterion is satisfied, determining that no logical error has occurred in the error pattern; and if the judgment criterion is not satisfied, determining whether or not a logical error has occurred based on error detection information in which the state of the auxiliary quantum bit adjacent to the first data quantum bit in the row direction or the column direction is inverted.

6. An information processing device having a processing unit that generates an error pattern indicating a first data quantum bit that generates an error among a plurality of data quantum bits included in a two-dimensional lattice array in which a plurality of data quantum bits and a plurality of auxiliary quantum bits are arranged alternately in each of the row and column directions, determines whether the first data quantum bit indicated in the error pattern satisfies a predetermined judgment criterion, and if the criterion is satisfied, determines that no logical error has occurred in the error pattern, and if the criterion is not satisfied, determines whether a logical error has occurred based on error detection information in which the state of an auxiliary quantum bit adjacent to the first data quantum bit indicated in the error pattern in the row direction or the column direction is inverted.

Images