Semiconductor device manufacturing method

Abstract

This semiconductor device manufacturing method comprises: a step of preparing a laminate in which multiple semiconductor chips are respectively fixed on a carrier by an adhesive layer, with respective connection terminals of the multiple semiconductor chips being fixed to a first carrier surface so as to face a side opposite from the carrier; a step of forming a redistribution layer to be connected to the respective connection terminals of the multiple semiconductor chips; and a step of grinding the carrier of the laminate from a second carrier surface, which is opposite from the first carrier surface, toward the first carrier surface. In the grinding step, a second chip surface, which is opposite from a first chip surface on which the redistribution layer for the multiple semiconductor chips is disposed, is exposed by shaving off the carrier and the adhesive layer.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to methods for manufacturing semiconductor devices.

[0002] Patent Document 1 discloses an example of a fan-out type semiconductor device, in which a rewiring layer is provided between a semiconductor chip and an external connection terminal, and the rewiring layer widens the spacing between the terminals of the semiconductor chip for connection to the external connection terminal.

[0003] Japanese Patent Application Laid-Open No. 2019-029557

[0004] In a conventional semiconductor device manufacturing method, as shown in FIG. 5A, for example, multiple semiconductor chips 110 are temporarily fixed to a glass carrier 120 with a temporary fixing material 112 and then sealed with an encapsulant 130. The encapsulant 130 is then polished until the connection terminals of the semiconductor chips 110 are exposed, and a redistribution layer 140 (see FIG. 5B) is formed thereon. However, in this semiconductor device manufacturing method, because the semiconductor chips 110 are temporarily fixed to the carrier 120 with the temporary fixing material 112, when the encapsulant 130 is molded using a molding machine, the pressure can cause the semiconductor chips 110 to move from their original positions, resulting in a so-called die shift S1. If die shift occurs, a separate alignment process is required for subsequent processes (e.g., exposure processes).

[0005] Furthermore, the outer peripheral portion S2 of the temporary fixing material 112 sandwiched between the glass carrier 120 and the sealing material 130 is exposed and may be damaged by the chemicals used. This may result in the glass carrier 120 and the sealing material 130 peeling off during the process. Furthermore, as shown in FIG. 5B , when the temporary fixing material 112 is peeled off from the sealing material 130, cracks may occur between the semiconductor chip 110 and the sealing material 130 due to the force applied during the peeling. Residual resin from the temporary fixing material 112 may remain on the surface of the sealing material 130 or the semiconductor chip 110 (S3), microcracks S4 may occur in the glass carrier 120 during the process, and metal S5 used in the process may become mixed into the microcracks S4.

[0006] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can easily improve the cleanliness of the chip surface while suppressing misalignment of the semiconductor chip.

[0007] The present disclosure relates to a method for manufacturing a semiconductor device. The method includes the steps of: preparing a stack of semiconductor chips each fixed to a carrier by an adhesive layer, the semiconductor chips being fixed to a first carrier surface of the carrier so that connection terminals of the semiconductor chips face away from the carrier; forming a rewiring layer connected to the connection terminals of the semiconductor chips; and grinding the carrier in the stack from a second carrier surface opposite the first carrier surface toward the first carrier surface. In the grinding step, the carrier and the adhesive layer are removed to expose second chip surfaces of the semiconductor chips opposite the first chip surfaces on which the rewiring layers are provided.

[0008] In this semiconductor device manufacturing method, multiple semiconductor chips are fixed to the carrier by an adhesive layer. In this way, the semiconductor chips are fixed to the carrier by an adhesive layer that provides permanent fixation, not temporary fixation. In this case, misalignment of the semiconductor chips is reliably suppressed. Furthermore, in this semiconductor device manufacturing method, the carrier is scraped off in the grinding process to expose second chip surfaces opposite the first chip surfaces on which the rewiring layers of the multiple semiconductor chips are provided. In this case, scraping off the carrier makes it possible to improve the cleanliness of the chip surfaces without leaving any resin residue or the like.

[0009] In the above-described method for manufacturing a semiconductor device, the adhesive layer may be a layer of a cured thermosetting adhesive and provided for each of the plurality of semiconductor chips, in which case the adhesive layer can be easily ground in the step of grinding the carrier.

[0010] In the above-described method for manufacturing a semiconductor device, the thickness of the adhesive layer is preferably 50 μm or less. In this case, the adhesive layer can be easily ground in the step of grinding the carrier. It is more preferable that the thickness of the adhesive layer is 20 μm or less. In this case, the adhesive layer can be even more easily ground.

[0011] In the above-described semiconductor device manufacturing method, the adhesive layer contains a curable resin component and an inorganic filler, and the content of the inorganic filler is preferably 50% by mass to 95% by mass based on the total amount of adhesive before the adhesive layer is cured. In this case, the adhesive layer can be easily ground in the step of grinding the carrier. Furthermore, the content of the inorganic filler is more preferably 80% by mass to 95% by mass based on the total amount of adhesive before the adhesive layer is cured. In this case, the adhesive layer can be even more easily ground in the step of grinding the carrier.

[0012] In the semiconductor device manufacturing method described above, the step of preparing a laminate may include a step of fixing each of the semiconductor chips to a carrier with an adhesive layer, and a step of encapsulating the semiconductor chips on the carrier with an encapsulant to form an encapsulant layer. In this embodiment, the encapsulant contains a curable resin component and an inorganic filler, and the content of the inorganic filler in the encapsulant may be 50% by mass or more, preferably 80% by mass or more, based on the total amount of the encapsulant. In this case, grinding of the encapsulant layer can be performed reliably.

[0013] In the above-mentioned method for manufacturing a semiconductor device, the step of preparing a stack may further include, after the sealing step, a step of grinding off the sealing material layer covering the plurality of semiconductor chips until the first chip surfaces of the plurality of semiconductor chips are exposed.

[0014] In the semiconductor device manufacturing method described above, the carrier grinding step preferably includes a step of roughly grinding the second carrier surface of the carrier with a first grindstone and a step of finish-grinding the roughly-ground carrier with a second grindstone having a grit greater than that of the first grindstone. In this case, the rough grinding can increase the carrier grinding speed, and the finish of the ground surface can be improved by finish grinding. In this embodiment, the first grindstone may be a grindstone having a grit size of #200 to #1000, and the second grindstone may be a grindstone having a grit size of #2000 to #6000. This can more reliably improve the grinding speed and the finish accuracy of the ground surface. In this embodiment, the rough grinding step may involve grinding off at least a portion of the carrier and the adhesive layer with the first grindstone, and the finish grinding step may involve polishing the encapsulant layer and the second chip surface of the semiconductor chip with the second grindstone. This can more reliably improve the grinding speed and the finish accuracy of the ground surface.

[0015] In the above-described semiconductor device manufacturing method, the carrier may be a silicon carrier, and the grinding step may further include a step of recovering ground silicon sludge (silicon scraps) for reuse. In this case, the used silicon can be reused, making the manufacturing method environmentally friendly. For example, according to this manufacturing method, impurities can be removed from the ground silicon sludge and it can be used as recycled silicon.

[0016] According to the present disclosure, it is possible to provide a method for manufacturing a semiconductor device that can easily improve the cleanliness of the chip surface while suppressing misalignment of the semiconductor chip.

[0017] FIG. 1 is a cross-sectional view showing an example of a semiconductor device. FIGS. 2A to 2C are diagrams sequentially showing a method for manufacturing a semiconductor device. FIGS. 3A and 3B are diagrams sequentially showing a method for manufacturing a semiconductor device, showing steps performed subsequent to the step in FIG. 2. FIGS. 4A to 4C are diagrams sequentially showing a method for manufacturing a semiconductor device, showing steps performed subsequent to the step in FIG. 3. FIGS. 5A and 5B are diagrams sequentially showing a method for manufacturing a semiconductor device according to a comparative example.

[0018] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicated explanations will be omitted. Furthermore, unless otherwise specified, the positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0019] When terms such as "left," "right," "front," "back," "top," "bottom," "upper," "lower," "first," and "second" are used in this specification and claims, they are intended for descriptive purposes and do not necessarily mean that these relative positions are permanent. The term "layer" encompasses not only structures that are formed over the entire surface when viewed in a plan view, but also structures that are formed only on a portion of the surface. The term "process" includes not only independent processes but also processes that cannot be clearly distinguished from other processes, as long as the intended purpose of the process is achieved. Numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to" as minimum and maximum values, respectively. Furthermore, in numerical ranges described in stages in this specification, the upper or lower limit of a certain numerical range may be replaced with the upper or lower limit of another numerical range.

[0020] FIG. 1 is a cross-sectional view showing an example of a semiconductor device. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor chip 2, a protective portion 3, a redistribution layer 4, and bumps 5. The semiconductor chip 2 is, for example, a semiconductor chip such as a processor or memory. The protective portion 3 is a portion made of a sealing resin or the like, and protects the semiconductor chip 2. The redistribution layer 4 (RDL) is a wiring layer having an insulating portion and wiring (e.g., copper wiring) formed within the insulating portion. The redistribution layer 4 connects the connection terminals of the semiconductor chip 2 to the bumps 5. The bumps 5 are formed of, for example, a metal material such as solder.

[0021] Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 2 to 4. FIGS. 2 to 4 are diagrams sequentially illustrating the method for manufacturing the semiconductor device 1. The semiconductor device 1 is manufactured, for example, through the following steps (a) to (d). (a) A step of preparing a stack T1 in which multiple semiconductor chips 10 are fixed onto a carrier 20 by adhesive layers 12. In this step (a), the connection terminals 10c of the multiple semiconductor chips 10 are fixed to a first carrier surface 20a of the carrier 20 so that they face away from the carrier 20. (b) A step of forming a rewiring layer 40 that connects to the connection terminals 10c of the multiple semiconductor chips 10. (c) A step of grinding the carrier 20 in the stack T2 from a second carrier surface 20b opposite the first carrier surface 20a toward the first carrier surface 20a. In this step (c), the carrier 20 and the adhesive layer 12 are scraped off to expose the second chip surface 10b opposite to the first chip surface 10a on which the rewiring layer 40 of the plurality of semiconductor chips 10 is provided. (d) A step of singulating the laminate T3 from which the carrier 20 has been scraped off to obtain semiconductor devices including the semiconductor chips 10. In this step (d), a predetermined number of bumps (corresponding to the bumps 5 in FIG. 1 ) are formed on the rewiring layer 40 before singulation.

[0022] In step (a), first, as shown in FIG. 2A, a plurality of semiconductor chips 10 are prepared. An adhesive layer 12 is adhered to each semiconductor chip 10. The semiconductor chips 10 correspond to the semiconductor chip 2 in the semiconductor device 1 shown in FIG. 1. The semiconductor chip 10 has a first chip surface 10a on which connection terminals 10c are provided, and a second chip surface 10b opposite the first chip surface 10a. An adhesive layer 12 is attached to the second chip surface 10b. In other words, the adhesive layer 12 is provided corresponding to each semiconductor chip 10. The adhesive layer 12 is in an uncured state at the preparation stage.

[0023] The adhesive layer 12 is, for example, a film containing a thermosetting adhesive, such as a die attach film (DAF). The thermosetting adhesive constituting the adhesive layer 12 contains, for example, a polymer resin component and a thermosetting component. The thickness of the adhesive layer 12 is, for example, 50 μm or less. By having a thickness of the adhesive layer 12 of 50 μm or less, the adhesive layer 12 can be easily scraped off during cutting in step (c). The thickness of the adhesive layer 12 may be 20 μm or less, 10 μm or less, 9 μm or less, 8 μm or less, or 7 μm or less, or may be 1 μm or more, 2 μm or more, 3 μm or more, 4 μm or more, or 5 μm or more. Note that the thickness of the adhesive layer 12 here refers to the thickness after curing.

[0024] The high-molecular-weight resin component contained in the adhesive layer 12 may include, for example, at least one resin selected from the group consisting of acrylic rubber, polyimide, and phenoxy resin. The high-molecular-weight resin component may have a reactive group such as an epoxy group. The weight-average molecular weight (standard polystyrene equivalent value measured by GPC method) of the high-molecular-weight resin component may be 100,000 to 3,000,000. The content of the high-molecular-weight resin component may be 30 to 80 parts by mass per 10 parts by mass of the total mass of the adhesive layer 12.

[0025] The thermosetting component that can be included in the adhesive layer 12 is a compound having a reactive group that forms a crosslinked structure by self-polymerization and / or reaction with a curing agent. The thermosetting component may include, for example, at least one selected from the group consisting of an epoxy resin, a bismaleimide resin, a triazine resin, and a phenolic resin. The content of the thermosetting component may be 1 to 30 parts by mass per 100 parts by mass of the adhesive layer 12.

[0026] The thermosetting adhesive constituting the adhesive layer 12 may contain other components as needed. Examples of the other components include a curing agent that reacts with the thermosetting component, a curing accelerator that promotes the reaction between the thermosetting component and the curing agent, a coupling agent (e.g., a silane coupling agent), and a filler (e.g., silica).

[0027] The filler contained in the adhesive layer 12 may be an inorganic filler. Specific examples of inorganic fillers include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, boron nitride, crystalline silica, and amorphous silica. These may be used alone or in combination. The content of the filler contained in the adhesive layer 12 may be 50% by mass to 95% by mass, based on the total amount of the adhesive layer 12 (adhesive) before curing. The content of the filler contained in the adhesive layer 12 is preferably 60% by mass or more, more preferably 70% by mass or more, and particularly preferably 80% by mass or more, based on the total amount of the adhesive layer 12 (adhesive) before curing, and is preferably 80% by mass to 95% by mass.

[0028] In step (a), a carrier 20 is prepared. The carrier 20 may be, for example, a silicon carrier. The silicon carrier may be monocrystalline silicon or polycrystalline silicon. The carrier 20 has a thickness of, for example, 0.6 to 1.1 mm and a flatness of a calculated average roughness of 50 nm or less. The carrier 20 is, for example, wafer-shaped or panel-shaped, and is not particularly limited. For example, the carrier 20 may be a circular wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular panel with a side length of 200 to 700 mm or less. A prepreg without copper foil may be used as the carrier 20.

[0029] Next, once the preparation of the semiconductor chips 10 and the carrier 20 is complete, as shown in FIG. 2B , the semiconductor chips 10 are fixed to the first carrier surface 20a of the carrier 20 so that the connection terminals 10c of the semiconductor chips 10 face away from the carrier 20 (i.e., in a face-up state). This fixing is performed by attaching each semiconductor chip 10 to the carrier 20 with an uncured adhesive layer 12 and then curing the adhesive layer 12 attached to each semiconductor chip 10. Because this fixation is strong, the semiconductor chips 10 cannot move after being fixed to the first carrier surface 20a of the carrier 20. The surface of the carrier 20 opposite the first carrier surface 20a is the second carrier surface 20b.

[0030] Next, once the semiconductor chips 10 are fixed to the carrier 20, as shown in FIG. 2C, they are encapsulated with an encapsulant so as to cover the multiple semiconductor chips 10 on the carrier 20. This encapsulation can be performed, for example, by molding using a mold. In the manufacturing method according to this embodiment, the semiconductor chips 10 are firmly fixed to the carrier 20 by the adhesive layer 12, so that even when the encapsulant is encapsulated using a molding machine, the phenomenon of misalignment of the semiconductor chips 10 (die shift) does not occur. This forms an encapsulant layer 30 that covers the semiconductor chips 10.

[0031] The sealing material used as the sealing material layer 30 may be, for example, a sealing material containing an epoxy resin, or may contain a curable resin component and an inorganic filler. The content of the inorganic filler in the sealing material may be 50% by mass or more, based on the total amount of the sealing material before curing. The content of the inorganic filler in the sealing material is preferably 60% by mass or more, more preferably 70% by mass or more, and particularly preferably 80% by mass or more, based on the total amount of the sealing material before curing. For example, the content of the inorganic filler in the sealing material may be 60% by mass to 90% by mass, based on the total amount of the sealing material before curing. The filler contained in the sealing material layer 30 may be an inorganic filler. Specific examples of inorganic fillers include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, boron nitride, crystalline silica, and amorphous silica. These may be used alone or in combination.

[0032] Next, after the semiconductor chip 10 is encapsulated with the encapsulant, as shown in FIG. 3A, the encapsulant layer 30 is ground until the connection terminals 10c (first chip surface 10a) of the semiconductor chip 10 are exposed, forming an encapsulant layer 30A. In this grinding step, the encapsulant layer 30 may be ground to a grinding amount of, for example, 30 μm or more. The thickness of the ground encapsulant layer 30A may be 50 μm or more, 100 μm or more, or 150 μm or more. As a result, in step (a), a stack T1 is formed in which each of the multiple semiconductor chips 10 is fixed on the carrier 20 by the adhesive layer 12.

[0033] In step (b), as shown in FIG. 3B, a redistribution layer 40 is formed to connect to each connection terminal 10c of the plurality of semiconductor chips 10. In the step of forming this redistribution layer 40, the distance between the wirings, which are conductor portions, is gradually increased as it moves away from the semiconductor chip 10 (moving upward in the figure). In the example shown in FIG. 3B, the redistribution layer 40 is formed on the first chip surface 10a of the plurality of semiconductor chips 10 and on the surface of the encapsulant layer 30A. Note that the formation of the redistribution layer 40 can be performed using a conventional method, and therefore a detailed description thereof will be omitted. As a result of the above, a stacked body T2 provided with the redistribution layer 40 is formed.

[0034] In step (c), once the rewiring layer 40 is formed, the carrier 20 in the laminate T2 is ground from the second carrier surface 20b toward the first carrier surface 20a while protecting the rewiring layer 40 with a BG tape 45 (backgrinding tape) or the like. In this grinding step, as shown in FIGS. 4A and 4B , the carrier 20 is first roughly ground with a first grindstone 50 from the second carrier surface 20b toward the first carrier surface 20a. The first grindstone 50 is, for example, a grindstone with a grit size of #200 to #1000. In the rough grinding, the carrier 20 is first ground off, and then the surface portions of the adhesive layer 12 and the encapsulant layer 30A (the same layer as the adhesive layer 12) are ground off. At this time, grinding may be continued until the second chip surface 10b of the semiconductor chip 10 is exposed, or may be continued until just before the second chip surface 10b of the semiconductor chip 10 is exposed. When grinding the carrier 20 made of silicon, silicon sludge (waste) generated mainly by rough grinding may be collected and reused.

[0035] Next, just before or after the second chip surface 10b of the semiconductor chip 10 is exposed by rough grinding, the roughly ground carrier 20A is finish-ground with a second grindstone 55 having a grit size higher than that of the first grindstone 50, as shown in FIG. 4C. The second grindstone 55 has a grit size of #2000 to #6000. In the finish-grinding process, the second chip surface 10b of the semiconductor chip 10 and the surface of the encapsulant layer 30A are polished. This improves the cleanliness of the second chip surface 10b of the semiconductor chip 10 encapsulated in the encapsulant layer 30A. As a result of the above, a stack T3 is formed, including multiple semiconductor chips 10 each having a redistribution layer 40.

[0036] In step (d), the laminate T3 from which the carrier 20 has been scraped off is diced into individual semiconductor devices each including a semiconductor chip 10. Note that bumps may be attached to the redistribution layer 40 before dicing. In this manner, a plurality of semiconductor devices 1 shown in FIG. 1 can be obtained.

[0037] As described above, in the semiconductor device manufacturing method according to this embodiment, multiple semiconductor chips 10 are fixed to the carrier 20 by the adhesive layer 12. In this manner, the semiconductor chips 10 are firmly fixed to the carrier 20 by the adhesive layer 12, which provides not temporary fixation but permanent fixation. In this case, misalignment of the semiconductor chips 10 is reliably suppressed. Furthermore, in this semiconductor device manufacturing method, the carrier 20 is scraped away in the grinding step to expose the second chip surface 10b opposite the first chip surface 10a on which the rewiring layer 40 of the multiple semiconductor chips 10 is provided. In this case, because the carrier 20 is scraped away, no resin residue or the like remains, making it possible to improve the cleanliness of the chip surface.

[0038] In the semiconductor device manufacturing method according to this embodiment, the adhesive layer 12 is a layer of hardened thermosetting adhesive, and may be provided for each of the plurality of semiconductor chips 10. This allows the adhesive layer 12 to be easily ground when the carrier 20 is ground.

[0039] In the method for manufacturing a semiconductor device according to this embodiment, the thickness of the adhesive layer 12 can be set to 50 μm or less. In this case, the adhesive layer 12 can be easily ground when the carrier 20 is ground.

[0040] In the semiconductor device manufacturing method according to this embodiment, the adhesive layer 12 contains a curable resin component and an inorganic filler, and the content of the inorganic filler can be 50% by mass to 95% by mass based on the total amount of adhesive before curing the adhesive layer 12. In this case, the adhesive layer 12 can be easily ground when the carrier 20 is ground.

[0041] In the semiconductor device manufacturing method according to this embodiment, the step of preparing the laminate T1 includes a step of fixing each of the plurality of semiconductor chips 10 to the carrier 20 with an adhesive layer 12, and a step of encapsulating the plurality of semiconductor chips 10 on the carrier 20 with an encapsulant to cover them, thereby forming an encapsulant layer 30. The encapsulant contains a curable resin component and an inorganic filler, and the content of the inorganic filler in the encapsulant may be 50 mass% or more based on the total amount of the encapsulant before hardening. In this case, grinding of the encapsulant layer 30 can be performed reliably.

[0042] In the semiconductor device manufacturing method of this embodiment, the process of preparing the laminate T1 may further include, after the sealing process, a process of grinding the sealing material layer 30 covering the multiple semiconductor chips 10 until the first chip surfaces 10a of the multiple semiconductor chips 10 are exposed.

[0043] In the semiconductor device manufacturing method according to this embodiment, the step of grinding the carrier 20 includes a step of roughly grinding the second carrier surface 20b of the carrier 20 with a first grindstone 50 and a step of finish-grinding the roughly-ground carrier 20A with a second grindstone 55 having a grit size higher than that of the first grindstone 50. Rough grinding can increase the grinding speed of the carrier 20, while finish grinding can improve the finish of the ground surface. The first grindstone may be a grindstone having a grit size of #200 to #1000, and the second grindstone may be a grindstone having a grit size of #2000 to #6000. This can more reliably improve the grinding speed and the finish accuracy of the ground surface. Furthermore, in the rough grinding step, the carrier 20 and at least a portion of the adhesive layer 12 may be scraped off with the first grindstone 50. In the finish grinding step, the encapsulant layer 30A and the second chip surface 10b of the semiconductor chip 10 may be polished by a second grindstone 55. This makes it possible to more reliably improve the grinding speed and the finishing accuracy of the ground surface.

[0044] In the semiconductor device manufacturing method according to this embodiment, the carrier 20 may be a silicon carrier. The grinding step may further include a step of recovering the ground silicon sludge for reuse. In this case, the used silicon can be reused, making the manufacturing method environmentally friendly.

[0045] The above describes a method for manufacturing a semiconductor device according to one embodiment of the present disclosure, but the present disclosure is not limited to the above-described embodiment and can be modified as appropriate without departing from the spirit of the present disclosure.

[0046] 1...semiconductor device, 10...semiconductor chip, 10a...first chip surface, 10b...second chip surface, 10c...connection terminal, 12...adhesive layer, 20, 20A...carrier, 20a...first carrier surface, 20b...second carrier surface, 30, 30A...sealing material layer, 40...rewiring layer, 50...first grinding stone, 55...second grinding stone, T1, T2...laminated body.

Claims

1. A step of preparing a laminate in which each of a plurality of semiconductor chips is fixed on a carrier by an adhesive layer, wherein each connection terminal of the plurality of semiconductor chips is fixed on a first carrier surface of the carrier so as to face the side opposite to the carrier, A step of forming a rewiring layer connected to each of the connection terminals of the plurality of semiconductor chips, A step of grinding the carrier in the laminate from a second carrier surface opposite to the first carrier surface toward the first carrier surface, and In the grinding step, the carrier and the adhesive layer are scraped off to expose a second chip surface opposite to a first chip surface provided with the rewiring layer of the plurality of semiconductor chips, a method for manufacturing a semiconductor device.

2. The adhesive layer is a layer obtained by curing a thermosetting adhesive, and is provided corresponding to each of the plurality of semiconductor chips, The method for manufacturing a semiconductor device according to claim 1.

3. The thickness of the adhesive layer is 50 μm or less, The method for manufacturing a semiconductor device according to claim 1 or 2.

4. The thickness of the adhesive layer is 20 μm or less, The method for manufacturing a semiconductor device according to claim 3.

5. The adhesive layer contains a curable resin component and an inorganic filler, The content of the inorganic filler is 50% by mass to 95% by mass based on the total amount of the adhesive before the adhesive layer is cured, The method for manufacturing a semiconductor device according to claim 1 or 2.

6. The content of the inorganic filler is 80% by mass to 95% by mass based on the total amount of the adhesive before the adhesive layer is cured, The method for manufacturing a semiconductor device according to claim 5.

7. The step of preparing the laminate includes A step of fixing each of the plurality of semiconductor chips to the carrier with the adhesive layer, and A step of sealing with a sealing material so as to cover the plurality of semiconductor chips on the carrier to form a sealing material layer, The method for manufacturing a semiconductor device according to claim 1 or 2.

8. The sealing material contains a curable resin component and an inorganic filler, The content of the inorganic filler in the sealing material is 50% by mass or more based on the total amount of the sealing material, The method for manufacturing a semiconductor device according to claim 7.

9. The step of preparing the laminate is After the step of forming the encapsulant layer, the method further includes a step of grinding the encapsulant layer covering the plurality of semiconductor chips until the first chip surface of the plurality of semiconductor chips is exposed. The method of manufacturing a semiconductor device according to claim 7.

10. The step of grinding the carrier includes: a step of roughly grinding the second carrier surface of the carrier with a first grinding wheel; a step of finish-grinding the roughly ground carrier with a second grinding wheel having a higher mesh number than the first grinding wheel. The method of manufacturing a semiconductor device according to claim 1 or 2.

11. The first grinding wheel is a grinding wheel having a mesh number of #200 to #1000. The second grinding wheel is a grinding wheel having a mesh number of #2000 to #6000. The method of manufacturing a semiconductor device according to claim 10.

12. In the step of rough grinding, at least a part of the carrier and the adhesive layer are scraped off by the first grinding wheel. The method of manufacturing a semiconductor device according to claim 10.

13. In the step of finish grinding, the encapsulant layer and the second chip surface of the semiconductor chip are polished by the second grinding wheel. The method of manufacturing a semiconductor device according to claim 10.

14. The carrier is a silicon carrier. The step of grinding further includes a step of collecting the ground silicon sludge for reuse. The method of manufacturing a semiconductor device according to claim 1 or 2.