Semiconductor device

Abstract

This semiconductor device comprises: a substrate; a device region provided to the substrate; a terminal covering the device region in a planar view; and at least three pseudo bumps disposed densely in a layout so as to be positioned at vertexes of a triangle in a planar view, on the terminal. From a bottom portion and along a side portion of each of the three pseudo bumps, excluded portions are formed due to a protrusion of part of the terminal. The excluded portions of each pseudo bump are formed in a pair on a first side and a second side of each pseudo bump in a first direction, so as to have a directionality along the first direction in a planar view. The excluded portions of the three pseudo bumps are arranged along a second direction with an interval therebetween.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Patent Application No. 2022-178205 filed with the Japan Patent Office on November 7, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Japanese Patent Application Laid-Open No. 2003-122222 discloses a semiconductor device including an electrode for wire bonding formed in the vicinity of an active element such as a microcomputer or a power transistor.

[0004] International Publication No. 2012-005073

[0005] An embodiment of the present disclosure provides a semiconductor device that can prevent interference between rejects of multiple pseudo bumps and that can arrange multiple pseudo bumps in a dense layout.

[0006] A semiconductor device according to one embodiment of the present disclosure comprises a substrate, a device region provided on the substrate, terminals covering the device region in a planar view, and a plurality of pseudo-bumps arranged on the terminals, the plurality of pseudo-bumps including at least three pseudo-bumps densely arranged in a layout positioned at the vertices of a triangle in a planar view, with exclusions formed by protruding portions of the terminals from the bottom to the sides of each of the three pseudo-bumps, the exclusions of each pseudo-bump being formed in pairs on both sides of each pseudo-bump in the first direction so as to have directionality along the first direction in a planar view, and the exclusions of the three pseudo-bumps being arranged at intervals from each other along a second direction perpendicular to the first direction.

[0007] According to a semiconductor device according to an embodiment of the present disclosure, at least three pseudo-bump rejects are arranged at intervals from one another along the second direction. Therefore, although each of the rejects is formed to have directivity in the first direction, the rejects can be prevented from interfering with one another. As a result, the pseudo-bumps can be arranged in a dense layout, thereby increasing the number of pseudo-bumps and improving heat dissipation.

[0008] FIG. 1 is a plan view showing a semiconductor chip according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a circuit diagram showing an example of the electrical configuration of the semiconductor chip shown in FIG. 1. FIG. 4 is a plan view showing the layout of an output region. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a perspective view showing a semiconductor device on which the semiconductor chip shown in FIG. 1 is mounted. FIG. 9 is a plan view showing the internal structure of the semiconductor device shown in FIG. 8. FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 9. FIG. 12 is an enlarged plan view showing a portion of FIG. 9. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 12. FIG. 15A is an enlarged view of a portion surrounded by a two-dot chain line XV in FIG. 13. Fig. 15B is a cross-sectional view of the pseudo-bumps cut along the second direction. Fig. 16 is a diagram showing a method of joining the pseudo-bumps to the terminals. Fig. 17 is an enlarged plan view of the pseudo-bumps. Fig. 18 is a plan view showing a first layout of the pseudo-bumps. Fig. 19 is a plan view showing a second layout of the pseudo-bumps. Fig. 20 is a plan view showing a modified example of the layout of Fig. 12. Fig. 21 is a plan view showing a semiconductor chip according to a second embodiment.

[0009] First, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When a term such as "substantially equal" is used in a description in which a comparison target is present, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0011] Fig. 1 is a plan view showing a semiconductor chip 1. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a circuit diagram showing an example of the electrical configuration of the semiconductor chip 1 shown in Fig. 1. Fig. 3 shows an example in which an inductive load L is connected to the output end (source terminal 26).

[0012] 1 and 2, in this embodiment, a semiconductor chip 1 includes a substrate 2 formed in a rectangular parallelepiped shape. The substrate 2 is made of a Si single crystal substrate. The substrate 2 may also be made of a single crystal substrate of a wide bandgap semiconductor (e.g., a SiC single crystal substrate). The substrate 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.

[0013] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z. The first main surface 3 is a device surface on which functional devices are formed. The second main surface 4 is a non-device surface. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0014] The first to fourth side surfaces 5A to 5D may each have a length of 0.1 mm to 10 mm in plan view. The length of the first to fourth side surfaces 5A to 5D may be 0.1 mm to 0.5 mm, 0.5 mm to 1 mm, 1 mm to 2.5 mm, 2.5 mm to 5 mm, 5 mm to 7.5 mm, or 7.5 mm to 10 mm.

[0015] The semiconductor chip 1 includes an output region 6, a current detection region 7, a control region 8, a first temperature detection region 9, and a second temperature detection region 10 provided on the first main surface 3. The output region 6, the current detection region 7, the control region 8, the first temperature detection region 9, and the second temperature detection region 10 may be referred to as a "first device region," a "second device region," a "third device region," a "fourth device region," and a "fifth device region," respectively.

[0016] The output region 6 is a region having a functional device configured to generate an output signal that is output externally (outside the semiconductor chip 1). In this embodiment, the output region 6 is partitioned into an L-shape in a planar view. Specifically, the output region 6 has a first region 6A extending in a strip-like shape along the first direction X in the region on the first side surface 5A side, and a second region 6B extending in a strip-like shape along the second direction Y in the region on the third side surface 5C side. The output region 6 is partitioned in the region on the first side surface 5A side of the first main surface 3. The output region 6 may be partitioned into a rectangular shape in a planar view, or into a polygonal shape other than a rectangular shape. The position, size, and planar shape of the output region 6 are arbitrary and are not limited to a specific shape.

[0017] The current detection region 7 is a region having a functional device configured to generate a monitor signal for monitoring the output signal. The current detection region 7 is preferably adjacent to the output region 6. In this embodiment, the current detection region 7 has a planar area smaller than the planar area of ​​the output region 6 and is provided inside the output region 6.

[0018] In other words, the current detection region 7 is provided so as to be surrounded by the output region 6. Here, "surrounded" includes a form in which the current detection region 7 is surrounded by the output region 6 all around, as well as a form in which the current detection region 7 is adjacent to the output region 6 in at least two directions. In this form, the functional device of the current detection region 7 is formed by utilizing a part of the functional device of the output region 6.

[0019] The control area 8 is an area having multiple types of functional devices configured to generate control signals that control the functional devices in the output area 6. In this embodiment, the control area 8 is defined as an area on the second side surface 5B side of the output area 6, and faces the output area 6 in the second direction Y. The control area 8 may be defined in a rectangular shape in a plan view, or in a polygonal shape other than a rectangular shape. The position, size, and planar shape of the control area 8 are arbitrary and are not limited to a specific shape.

[0020] The control region 8 preferably has a planar area equal to or smaller than the planar area of ​​the output region 6. The area ratio of the planar area of ​​the control region 8 to the planar area of ​​the output region 6 may be 0.1 or greater and 2 or less. The area ratio of the planar area of ​​the control region 8 to the planar area of ​​the output region 6 may be 0.1 or greater and 0.25 or less, 0.25 or greater and 0.5 or less, 0.5 or greater and 0.75 or less, 0.75 or greater and 1 or less, 1 or greater and 1.25 or less, 1.25 or greater and 1.5 or less, 1.5 or greater and 1.75 or less, or 1.75 or greater and 2 or less. The area ratio is preferably less than 1.

[0021] The first temperature detection area 9 is an area having a functional device configured to generate a temperature detection signal for monitoring the temperature of the output area 6. The first temperature detection area 9 is preferably adjacent to the output area 6. The first temperature detection area 9 has a planar area smaller than the planar area of ​​the output area 6 and is provided inside the output area 6.

[0022] In other words, the first temperature detection area 9 is surrounded by the output area 6. The term "surrounded" here includes a configuration in which the first temperature detection area 9 is surrounded by the output area 6 all around, as well as a configuration in which the first temperature detection area 9 is adjacent to the output area 6 in at least two directions.

[0023] The second temperature detection area 10 is an area having a functional device configured to generate a temperature detection signal for monitoring the temperature of the control area 8. The second temperature detection area 10 is preferably adjacent to the control area 8. In this embodiment, the second temperature detection area 10 has a planar area smaller than the planar area of ​​the control area 8 and is provided inside the control area 8.

[0024] In other words, the second temperature detection area 10 is surrounded by the control area 8. The term "surrounded" here includes a configuration in which the second temperature detection area 10 is surrounded by the control area 8 all around, as well as a configuration in which the second temperature detection area 10 is adjacent to the control area 8 in at least two directions.

[0025] 1 and 3, the semiconductor chip 1 includes n-system insulated gate main transistors 11 formed in the output region 6. "n" is 2 or more (n≧2). FIG. 3 illustrates two systems of main transistors 11. The main transistors 11 may be referred to as "gate split transistors." The main transistors 11 include n-number first gates FG, one first drain FD, and one first source FS.

[0026] The main transistor 11 is configured so that n gate signals (gate voltages), which may be the same or different, are input to n first gates FG at any timing. Each gate signal includes an ON signal that controls part of the main transistor 11 to an ON state and an OFF signal that controls part of the main transistor 11 to an OFF state.

[0027] The main transistor 11 generates a single output current IO (output signal) in response to n gate signals. In other words, the main transistor 11 is a multi-input single-output switching device. The output current IO is a drain-source current that flows between the first drain FD and the first source FS. The output current IO is output to the outside of the substrate 2.

[0028] The main transistor 11 includes n system transistors 12. In Fig. 3, a first system transistor 12A and a second system transistor 12B are illustrated. The n system transistors 12 are formed together in a single output region 6 and are configured to be controlled to be turned on or off electrically independent of each other.

[0029] Specifically, the n system transistors 12 are connected in parallel to one another so that n gate signals are individually input to the n system transistors 12. In other words, the n system main transistors 11 are configured so that the system transistors 12 in the ON state and the system transistors 12 in the OFF state coexist at any timing.

[0030] Each of the n system transistors 12 includes a second gate SG, a second drain SD, and a second source SS. The n second gates SG constitute n first gates FG, respectively. The n second drains SD constitute one first drain FD. The n second sources SS constitute one first source FS.

[0031] The n system transistors 12 each generate a system current IS in response to a corresponding gate signal. The system current IS is a drain-source current flowing between the second drain SD and the second source SS of the system transistor 12. The n system currents IS may have different values ​​or may be equal to each other. The n system currents IS are added between the first drain FD and the first source FS. As a result, a single output current IO consisting of the sum of the n system currents IS is generated.

[0032] 1 and 3, the semiconductor chip 1 includes m-system insulated gate type monitor transistors 13 formed in the current detection region 7. "m" is 1 or greater (m≧1). FIG. 3 illustrates two systems of monitor transistors 13. The monitor transistors 13 are connected in parallel to the main transistor 11 and are configured to monitor part or all of the output current IO. That is, the monitor transistor 13 is connected in parallel to at least one system transistor 12 and monitors at least one system current IS.

[0033] The monitor transistor 13 is preferably connected in parallel to the plurality of system transistors 12 and configured to monitor the plurality of system currents IS. In this embodiment, the monitor transistor 13 is made up of n systems (m=n) of monitor transistors 13 connected in parallel to n system transistors 12 so as to monitor n system currents IS. In the following description, "m systems" will be replaced with "n systems" and "m pieces" will be replaced with "n pieces" as necessary.

[0034] In this embodiment, the monitor transistor 13 includes n first monitor gates FMG, one first monitor drain FMD, and one first monitor source FMS. The n first monitor gates FMG are configured to receive n monitor gate signals (monitor gate voltages) individually.

[0035] The first monitor drain FMD is electrically connected to the first drain FD. The first monitor source FMS is electrically isolated from the first source FS. The n first monitor gates FMG receive n identical or different monitor gate signals at any timing. Each monitor gate signal includes an ON signal that controls a portion of the monitor transistors 13 to an ON state and an OFF signal that controls a portion of the monitor transistors 13 to an OFF state.

[0036] In this embodiment, the monitor transistor 13 generates a single monitor current IM (monitor signal) that monitors n system currents IS (output currents IO) in response to n monitor gate signals. That is, the monitor transistor 13 is a multiple-input, single-output switching device. The monitor current IM is a drain-source current that flows between the first monitor drain FMD and the first monitor source FMS.

[0037] In this configuration, the n first monitor gates FMG are electrically connected to the n corresponding first gates FG in a one-to-one correspondence. Therefore, the n first monitor gates FMG are configured so that monitor gate signals, which are gate signals, are individually input to each of them. In other words, the monitor transistor 13 is controlled to be turned on and off at the same timing as the main transistor 11, and generates a monitor current IM that increases and decreases in conjunction with the increase and decrease of the output current IO.

[0038] The monitor current IM is output to the outside of the output region 6 via a current path electrically independent from the current path of the output current IO. The monitor current IM is equal to or less than the output current IO (IM≦IO). The monitor current IM is preferably less than the output current IO (IM<IO). The current ratio IM / IO of the monitor current IM to the output current IO is arbitrary. The current ratio IM / IO may be 1 / 10,000 or more and 1 or less (preferably less than 1).

[0039] The monitor transistor 13 includes m (n in this embodiment) system monitor transistors 14. In FIG. 3, a first system monitor transistor 14A and a second system monitor transistor 14B are illustrated. The number of systems of the monitor transistor 13 is adjusted by the number of system monitor transistors 14.

[0040] That is, when m monitor transistors 13 monitor at least one system current IS, at least one system monitor transistor 14 is electrically connected (specifically, connected in parallel) to at least one system transistor 12. When m monitor transistors 13 monitor multiple system currents IS, multiple system monitor transistors 14 are electrically connected to multiple system transistors 12. In this configuration, n system monitor transistors 14 are electrically connected to n system transistors 12.

[0041] The n system monitor transistors 14 are configured to be controlled to be in an on state or an off state electrically independent of one another. Specifically, the n system monitor transistors 14 are connected in parallel to one another so that n monitor gate signals are individually input thereto. In other words, the monitor transistor 13 is configured so that the system monitor transistor 14 in the on state and the system monitor transistor 14 in the off state coexist at any timing.

[0042] Each of the n system monitor transistors 14 includes a second monitor gate SMG, a second monitor drain SMD, and a second monitor source SMS. The n second monitor gates SMG constitute n first monitor gates FMG. The n second monitor drains SMD constitute one first monitor drain FMD. The n second monitor sources SMS constitute one first monitor source FMS.

[0043] The n second monitor gates SMG are supplied with n identical or different monitor gate signals at any timing. In response to the corresponding monitor gate signals, the n system monitor transistors 14 each generate a system monitor current ISM (system monitor signal) for monitoring the system current IS of the corresponding system transistor 12.

[0044] The grid monitor current ISM is a drain-source current flowing between the second monitor drain SMD and the second monitor source SMS of the grid monitor transistor 14. The n grid monitor currents ISM are summed between the first monitor drain FMD and the first monitor source FMS, thereby generating a single monitor current IM consisting of the sum of the n grid monitor currents ISM.

[0045] In this embodiment, the n system monitor transistors 14 are electrically connected to the corresponding system transistors 12 in a one-to-one correspondence and are controlled in conjunction with the corresponding system transistors 12. Specifically, the n system monitor transistors 14 are each connected in parallel to the corresponding system transistor 12 so that the system monitor current ISM is output to a current path that is electrically independent from the current path of the system current IS.

[0046] The n second monitor gates SMG are electrically connected to the corresponding first gates FG in a one-to-one correspondence. That is, in this configuration, a monitor gate signal consisting of a gate signal is input to each of the n second monitor gates SMG. The second monitor drain SMD is electrically connected to the first drain FD. The second monitor source SMS is electrically isolated from the first source FS.

[0047] As a result, the n grid monitor transistors 14 are controlled to turn on and off at the same timing as the corresponding grid transistors 12, and each generates a grid monitor current ISM that increases or decreases in conjunction with an increase or decrease in the corresponding grid current IS. The grid monitor current ISM is extracted from the second monitor source SMS electrically independent from the grid current IS.

[0048] Each grid monitor current ISM is equal to or less than the corresponding grid current IS (ISM≦IS). Preferably, each grid monitor current ISM is less than the corresponding grid current IS (ISM<IS). The current ratio ISM / IS of the grid monitor current ISM to the grid current IS is arbitrary. The current ratio ISM / IS may be 1 / 10,000 or more and 1 or less (preferably less than 1).

[0049] An example of control of the two systems of main transistors 11 and the two systems of monitor transistors 13 will be described below. When gate signals (i.e., off signals) lower than the gate threshold voltage are input to all of the n first gates FG, the first system transistors 12A and the second system transistors 12B are turned off. This control is applied when the main transistor 11 is turned off. Meanwhile, in the monitor transistor 13, the first system monitor transistor 14A and the second system monitor transistor 14B are turned off in conjunction with the main transistor 11.

[0050] When gate signals (i.e., ON signals) equal to or greater than the gate threshold voltage are input to all of the n first gates FG, the first system transistor 12A and the second system transistor 12B are turned ON. As a result, the main transistor 11 generates an output current IO including the system current IS of the first system transistor 12A and the system current IS of the second system transistor 12B. In this case, the channel utilization rate of the main transistor 11 increases relatively, and the ON resistance decreases relatively. This control is applied during normal operation of the main transistor 11.

[0051] Meanwhile, in the monitor transistor 13, the first system monitor transistor 14A and the second system monitor transistor 14B are turned on in conjunction with the main transistor 11. The monitor transistor 13 generates a monitor current IM including the system monitor current ISM of the first system monitor transistor 14A and the system monitor current ISM of the second system monitor transistor 14B. In this case, the channel utilization rate of the monitor transistor 13 increases relatively, and the on-resistance decreases relatively.

[0052] When a gate signal (i.e., an ON signal) equal to or greater than the gate threshold voltage is input to the first gate FG of the first system transistor 12A, and a gate signal (i.e., an OFF signal) less than the gate threshold voltage is input to the first gate FG of the second system monitor transistor 14B, the first system transistor 12A is turned ON and the second system monitor transistor 14B is turned OFF.

[0053] As a result, the main transistor 11 generates an output current IO that includes the system current IS of the first system transistor 12A. In this case, the channel utilization rate of the main transistor 11 relatively decreases, and the on-resistance relatively increases. This control is applied when the main transistor 11 operates in active clamp mode.

[0054] Meanwhile, in the monitor transistor 13, the first system monitor transistor 14A is turned on and the second system monitor transistor 14B is turned off in conjunction with the main transistor 11. The monitor transistor 13 generates a monitor current IM including the system monitor current ISM of the first system monitor transistor 14A. In this case, the channel utilization rate of the monitor transistor 13 relatively decreases, and the on-resistance relatively increases.

[0055] 1 and 3, the semiconductor chip 1 includes a first temperature sensing diode 15 as an example of a first temperature sensor formed in the first temperature sensing region 9. The first temperature sensing diode 15 has a temperature characteristic with respect to its forward voltage that varies in accordance with the temperature T1 of the output region 6, and generates a first temperature sensing signal ST1 that detects the temperature of the output region 6. The forward voltage may have a negative temperature characteristic that decreases linearly as the temperature of the output region 6 increases.

[0056] 1 and 3, the semiconductor chip 1 includes a second temperature sensing diode 16 as an example of a second temperature sensor formed in the second temperature sensing region 10. The second temperature sensing diode 16 has a temperature characteristic with respect to its forward voltage that varies in accordance with the temperature T2 of the control region 8, and generates a second temperature sensing signal ST2 that detects the temperature of the control region 8. The forward voltage may have a negative temperature characteristic that decreases linearly as the temperature of the control region 8 increases.

[0057] The second temperature sensitive diode 16 preferably has substantially the same configuration as the first temperature sensitive diode 15 and preferably has substantially the same electrical characteristics as the first temperature sensitive diode 15. When the main transistor 11 generates the output current IO, the temperature T2 of the control region 8 is less than the temperature T1 of the output region 6 (T2<T1). Therefore, when the output current IO is generated, the forward voltage of the second temperature sensitive diode 16 is greater than the forward voltage of the first temperature sensitive diode 15.

[0058] The semiconductor chip 1 includes a control circuit 17 formed in the control region 8. The control circuit 17 may be referred to as a "control integrated circuit (control IC)." The control circuit 17, together with the main transistor 11, constitutes an intelligent power device (IPD). The IPD may be referred to as an intelligent power module (IPM). The control circuit 17 includes multiple types of functional circuits that realize various functions in response to electrical signals input from the outside.

[0059] In this embodiment, the control circuit 17 includes a gate drive circuit 18, an active clamp circuit 19, an overcurrent protection circuit 20, and an overheat protection circuit 21. The overcurrent protection circuit 20 may be called an "OCP (Over Current Protection) circuit," and the overheat protection circuit 21 may be called a "TSD (Thermal Shutdown) circuit." The monitor transistor 13, the first temperature sensing diode 15, and the second temperature sensing diode 16 described above constitute part of the control circuit 17.

[0060] The gate drive circuit 18 is electrically connected to the first gate FG of the main transistor 11 and the first monitor gate FMG of the monitor transistor 13, and generates gate signals that control the main transistor 11 and the monitor transistor 13 in response to external electrical signals.

[0061] The active clamp circuit 19 is electrically connected to the main transistor 11 and the gate drive circuit 18. Specifically, the active clamp circuit 19 is electrically connected to some (but not all) of the first gate FG, the first drain FD, and the gate drive circuit 18.

[0062] The active clamp circuit 19 may include a first diode stage 19 a, a second diode stage 19 b, and an n-channel MISFET 19 c. The first diode stage 19 a includes one or more Zener diodes forming a forward series circuit. The cathode of the first diode stage 19 a is electrically connected to the first drain FD.

[0063] The second diode stage 19b includes one or more pn junction diodes forming a forward series circuit. The anode of the second diode stage 19b is reverse-bias connected to the anode of the first diode stage 19a. The cathode of the second diode stage 19b is electrically connected to the gate drive circuit 18.

[0064] The gate of the MISFET 19c is electrically connected to the cathode of the second diode stage 19b. The back gate of the MISFET 19c is electrically connected to the first source FS. The drain of the MISFET 19c is connected to the first drain FD. The source of the MISFET 19c is electrically connected to part (but not all) of the first gate FG.

[0065] The active clamp circuit 19 cooperates with the gate drive circuit 18 to limit (clamp) the output voltage and protect the main transistor 11 from the back electromotive force when the back electromotive force is input to the main transistor 11 due to the energy stored in the inductive load L. In other words, the active clamp circuit 19 is configured to limit the output voltage until the back electromotive force is consumed by causing the main transistor 11 to perform an active clamp operation when the back electromotive force is input.

[0066] Specifically, during active clamp operation, the active clamp circuit 19 cooperates with the gate drive circuit 18 to control a portion of the main transistors 11 (for example, the first system transistor 12A) to an on state and a portion of the main transistors 11 (for example, the second system transistor 12B) to an off state.

[0067] During active clamp operation, the active clamp circuit 19 cooperates with the gate drive circuit 18 to control a portion of the monitor transistors 13 (for example, the first system monitor transistor 14A) to an ON state and a portion of the monitor transistors 13 (for example, the second system monitor transistor 14B) to an OFF state.

[0068] The active clamp circuit 19 may be configured to control the on / off of the n system transistors 12 (system monitor transistors 14) when the first source FS of the main transistor 11 becomes equal to or lower than a predetermined voltage (for example, a predetermined negative voltage).

[0069] The overcurrent protection circuit 20 is electrically connected to the monitor transistor 13 and the gate drive circuit 18. The overcurrent protection circuit 20 is electrically connected to the first monitor source FMS of the monitor transistor 13, and is configured to receive a part or all (all in this embodiment) of the monitor current IM. The overcurrent protection circuit 20 cooperates with the gate drive circuit 18 to control the gate signal and protect the main transistor 11 from overcurrent.

[0070] The overcurrent protection circuit 20 may be configured to generate an overcurrent detection signal SC when the monitor current IM exceeds a predetermined threshold, and output the overcurrent detection signal SC to the gate drive circuit 18. The overcurrent detection signal SC is a signal for limiting some or all of the n gate signals generated in the gate drive circuit 18 to a predetermined value or less (for example, OFF).

[0071] The gate drive circuit 18 limits some or all of the n gate signals in response to the overcurrent detection signal SC, thereby suppressing the overcurrent flowing through the main transistor 11. When the monitor current IM falls below a predetermined threshold, the overcurrent protection circuit 20 switches the gate drive circuit 18 (main transistor 11) to normal control.

[0072] The overheat protection circuit 21 is electrically connected to the first temperature sensing diode 15, the second temperature sensing diode 16, and the gate drive circuit 18. The overheat protection circuit 21 is configured to cooperate with the gate drive circuit 18 to control the gate signal and protect the main transistor 11 from overheating. The overheat protection circuit 21 receives a first temperature detection signal ST1 from the first temperature sensing diode 15 and a second temperature detection signal ST2 from the second temperature sensing diode 16.

[0073] The overheat protection circuit 21 may be configured to generate an overheat detection signal SH when the difference between the first temperature detection signal ST1 and the second temperature detection signal ST2 exceeds a predetermined threshold, and output the overheat detection signal SH to the gate drive circuit 18. The overheat detection signal SH is a signal for limiting some or all of the n gate signals generated in the gate drive circuit 18 to OFF.

[0074] In response to the overheat detection signal SH, the gate drive circuit 18 controls some or all of the main transistors 11 to an off state, thereby suppressing a temperature rise in the output region 6. In addition, in response to the overheat detection signal SH, the gate drive circuit 18 controls some or all of the monitor transistors 13 to an off state, thereby suppressing a temperature rise in the current detection region 7 (output region 6). When the difference value becomes equal to or less than a threshold value, the overheat protection circuit 21 switches the gate drive circuit 18 to normal control.

[0075] 2, the semiconductor chip 1 includes an interlayer insulating film 24 that covers the first main surface 3. The interlayer insulating film 24 collectively covers the output region 6, the current detection region 7, the control region 8, the first temperature detection region 9, and the second temperature detection region 10. In this embodiment, the interlayer insulating film 24 has a multilayer wiring structure that includes a plurality of insulating films stacked on the first main surface 3 and a plurality of wirings arranged on any of the insulating films.

[0076] Each insulating film may include at least one of a silicon oxide film and a silicon nitride film. Each wiring may include at least one of a pure Al layer (an Al layer having a purity of 99% or more), a Cu layer (a Cu layer having a purity of 99% or more), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0077] 1 and 2, semiconductor chip 1 includes a plurality of terminals 25 to 30. The number, layout, etc. of the plurality of terminals 25 to 30 are adjusted as appropriate according to the specifications of main transistor 11 and control circuit 17. In this embodiment, the plurality of terminals 25 to 30 include a drain terminal 25 (power supply terminal), a source terminal 26 (output terminal), a first control terminal 27, a second control terminal 28, a third control terminal 29, and a fourth control terminal 30.

[0078] The drain terminal 25 covers the second main surface 4 of the substrate 2 and is electrically connected to the second main surface 4. The drain terminal 25 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain terminal 25 may have a layered structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are layered in any manner. The drain terminal 25 is electrically connected to the first drain FD of the main transistor 11 and transmits the power supply potential.

[0079] The source terminal 26 is disposed on the interlayer insulating film 24. The source terminal 26 covers the output region 6 so as to expose the control region 8 in a plan view. The layout of the source terminal 26 is adjusted depending on the layout of the output region 6 and is not limited to a specific form. In this form, the source terminal 26 is formed in a quadrangular shape (specifically, a rectangular shape extending in the first direction X) in a plan view. Of course, the source terminal 26 may be formed in a polygonal shape other than a quadrangular shape in a plan view.

[0080] In this embodiment, the source terminal 26 has a rectangular cutout portion 26a that exposes the first temperature detection region 9 (first temperature sensing diode 15). The source terminal 26 is electrically connected to the first source FS of the main transistor 11 and transmits the output current IO to the outside. The source terminal 26 may include either or both of an Al-based metal layer and a Cu-based metal layer. The source terminal 26 may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0081] The first to fourth control terminals 27 to 30 are disposed on the interlayer insulating film 24. The first to fourth control terminals 27 to 30 may be, for example, an input terminal that applies an input signal to the control circuit 17, an enable terminal that applies an enable signal to the control circuit 17, a self-diagnosis output terminal that outputs an electrical signal for diagnosing the state of the control circuit 17, and a ground terminal that applies a ground potential to the control circuit 17.

[0082] The first to fourth control terminals 27 to 30 each cover an area outside the output area 6 (specifically, the control area 8) in a plan view. Each of the first to fourth control terminals 27 to 30 has a planar area smaller than the planar area of ​​the source terminal 26. The first to fourth control terminals 27 to 30 may include at least one of a pure Al layer, a pure Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0083] The configuration of the output region 6 will be described below with reference to FIGS. 4 to 7. FIG. 4 is a plan view showing the layout of the output region 6. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4.

[0084] The semiconductor chip 1 includes a first semiconductor region 31 of n-type (first conductivity type) formed in a surface layer portion of the first main surface 3 of the substrate 2. The first semiconductor region 31 forms a first drain FD of the main transistor 11 and a first monitor drain FMD of the monitor transistor 13. The first semiconductor region 31 may also be referred to as a "drift region."

[0085] The first semiconductor region 31 is formed over the entire surface layer of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The thickness of the first semiconductor region 31 may be 5 μm or more and 30 μm or less. The thickness of the first semiconductor region 31 is preferably 10 μm or more and 20 μm or less. In this embodiment, the first semiconductor region 31 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0086] The semiconductor chip 1 includes an n-type second semiconductor region 32 formed in a surface layer portion of the second main surface 4 of the substrate 2. The second semiconductor region 32, together with the first semiconductor region 31, forms a first drain FD of the main transistor 11 and a first monitor drain FMD of the monitor transistor 13. The second semiconductor region 32 may also be referred to as a "drain region."

[0087] The second semiconductor region 32 is formed over the entire surface layer of the second main surface 4 so as to be electrically connected to the first semiconductor region 31, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 32 is thicker than the first semiconductor region 31. The thickness of the second semiconductor region 32 may be 10 μm or more and 450 μm or less. The thickness of the second semiconductor region 32 is preferably 50 μm or more and 150 μm or less. In this embodiment, the second semiconductor region 32 is formed of an n-type semiconductor substrate (Si semiconductor substrate).

[0088] The semiconductor chip 1 includes a p-type (second conductivity type) body region 33 formed in a surface layer portion of the first semiconductor region 31 in the output region 6 and the current detection region 7. The body region 33 is formed at a distance from the bottom of the first semiconductor region 31 toward the first main surface 3, and faces the second semiconductor region 32 with a part of the first semiconductor region 31 in between.

[0089] The semiconductor chip 1 includes a plurality of trench structures 35 formed on the first main surface 3 in the output region 6. The trench structures 35 may also be referred to as "trench gate structures." The plurality of trench structures 35 includes a plurality of trench structures 35 for the main transistors 11 formed in the output region 6 and a plurality of trench structures 35 for the monitor transistors 13 formed in the current detection region 7. The number of the plurality of trench structures 35 for the monitor transistors 13 is less than the number of the plurality of trench structures 35 for the main transistors 11.

[0090] The multiple trench structures 35 are arranged at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. The multiple trench structures 35 penetrate the body region 33 to reach the first semiconductor region 31. The multiple trench structures 35 are formed at intervals from the bottom of the first semiconductor region 31 toward the first main surface 3, and face the second semiconductor region 32 with a part of the first semiconductor region 31 in between.

[0091] Each trench structure 35 has a first width W1 and a first depth D1. The first width W1 is the width in a direction perpendicular to the extension direction of the trench structure 35. The first width W1 may be 0.5 μm or more and 2 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less. The first depth D1 may be 1 μm or more and 10 μm or less. The first depth D1 is preferably 2 μm or more and 6 μm or less. The bottom wall of each trench structure 35 is preferably spaced 1 μm or more and 5 μm or less from the bottom of the first semiconductor region 31.

[0092] The multiple trench structures 35 are arranged at a trench interval IT in the first direction X. The trench interval IT may be 0.25 to 1.5 times the first width W1. The trench interval IT is preferably equal to or smaller than the first width W1. The trench interval IT may be 0.5 μm to 2 μm.

[0093] The configuration of one trench structure 35 will be described below. The trench structure 35 has a multi-electrode structure including a trench 36, a first insulating film 37, a second insulating film 38, a first electrode 39, a second electrode 40, and a third insulating film 41. In other words, the trench structure 35 includes an electrode (gate electrode) buried in the trench 36 with an insulator (gate insulator) sandwiched between them. The insulator is composed of the first insulating film 37, the second insulating film 38, and the third insulating film 41. The electrode is composed of the first electrode 39 and the second electrode 40.

[0094] The trench 36 is dug down from the first main surface 3 toward the second main surface 4, and defines the wall surface of the trench structure 35. The first insulating film 37 coats the upper wall surface of the trench 36 in a film-like manner. Specifically, the first insulating film 37 coats the upper wall surface located in a region on the opening side of the trench 36 relative to the bottom of the body region 33.

[0095] The first insulating film 37 crosses the boundary between the first semiconductor region 31 and the body region 33 and has a portion covering the first semiconductor region 31. The first insulating film 37 may include a silicon oxide film. The first insulating film 37 preferably includes a silicon oxide film made of an oxide of the substrate 2. The first insulating film 37 is formed as a gate insulating film.

[0096] The second insulating film 38 covers the lower wall surface of the trench 36 in a film-like manner. Specifically, the second insulating film 38 covers the lower wall surface located in a region closer to the bottom wall of the trench 36 than the bottom of the body region 33. The second insulating film 38 covers the first semiconductor region 31. The second insulating film 38 may include a silicon oxide film. The second insulating film 38 preferably includes a silicon oxide film made of an oxide of the substrate 2. The second insulating film 38 is preferably thicker than the first insulating film 37.

[0097] The first electrode 39 is embedded in the upper side (opening side) of the trench 36 with the first insulating film 37 sandwiched therebetween. The first electrode 39 is embedded in a strip shape extending in the second direction Y in a plan view. The first electrode 39 faces the body region 33 and the first semiconductor region 31 with the first insulating film 37 sandwiched therebetween. The first electrode 39 may include conductive polysilicon. The first electrode 39 is formed as a gate electrode. A gate signal is input to the first electrode 39.

[0098] The second electrode 40 is embedded in the lower side (bottom wall side) of the trench 36 with the second insulating film 38 sandwiched therebetween. The second electrode 40 is embedded in a strip shape extending in the second direction Y in a plan view. The second electrode 40 may have a thickness (length) in the depth direction of the trench 36 that exceeds the thickness (length) of the first electrode 39.

[0099] The second electrode 40 faces the first semiconductor region 31 with the second insulating film 38 interposed therebetween. The second electrode 40 has an upper end that protrudes from the second insulating film 38 toward the first main surface 3. The upper end of the second electrode 40 engages with the bottom of the second electrode 40 and faces the first insulating film 37 in the lateral direction along the first main surface 3 with the bottom of the second electrode 40 interposed therebetween.

[0100] The second electrode 40 may include conductive polysilicon. In this embodiment, the second electrode 40 is formed as a gate electrode and is fixed at the same potential as the first electrode 39. That is, the same gate signal is applied to the second electrode 40 simultaneously with the first electrode 39. This reduces the voltage drop between the first electrode 39 and the second electrode 40, thereby reducing electric field concentration between the first electrode 39 and the second electrode 40. Furthermore, the carrier density in the vicinity of the trench 36 increases, resulting in a decrease in the on-resistance of the substrate 2 (particularly the first semiconductor region 31).

[0101] The third insulating film 41 is interposed between the first electrode 39 and the second electrode 40, and electrically insulates the first electrode 39 and the second electrode 40. The third insulating film 41 covers a portion of the second electrode 40 that is exposed from the second insulating film 38, and is continuous with the first insulating film 37 and the second insulating film 38. The third insulating film 41 may include a silicon oxide film. The third insulating film 41 preferably includes a silicon oxide film made of an oxide of the second electrode 40. The third insulating film 41 is preferably thinner than the second insulating film 38.

[0102] The semiconductor chip 1 includes a plurality of trench connection structures 45 formed on the first main surface 3 in the output region 6. The plurality of trench connection structures 45 are formed in a region on one end side of the plurality of trench structures 35 and a region on the other end side of the plurality of trench structures 35. In FIG. 4, the region on one end side of the plurality of trench structures 35 is shown.

[0103] The plurality of trench connection structures 45 are each formed in a strip shape extending in the second direction Y so as to connect one end of at least two (two in this embodiment) trench structures 35 adjacent to each other in the first direction X. The plurality of trench connection structures 45 are each formed in a strip shape extending in the second direction Y so as to connect the other end of at least two (two in this embodiment) trench structures 35 adjacent to each other in the first direction X.

[0104] In plan view, each of the plurality of trench connection structures 45 constitutes a single annular or ladder-shaped unit trench structure together with the plurality of trench structures 35. The plurality of trench connection structures 45 are formed at intervals from the bottom of the first semiconductor region 31 toward the first main surface 3, and face the second semiconductor region 32 with a part of the first semiconductor region 31 in between.

[0105] The trench connection structure 45 on the other side has the same structure as the trench connection structure 45 on one side, except that it is connected to the other ends of the multiple trench structures 35. Below, the configuration of one trench connection structure 45 on one side will be described, and a description of the trench connection structure 45 on the other side will be omitted.

[0106] The trench connection structure 45 has a first trench portion 45a extending in the first direction X and a plurality of (two in this embodiment) second trench portions 45b extending in the second direction Y. The first trench portion 45a faces one end of the plurality of trench structures 35 in a plan view. The plurality of second trench portions 45b extend from the first trench portion 45a toward one end of the plurality of trench structures 35 and are connected to the one end of the plurality of trench structures 35.

[0107] The trench connection structure 45 has a second width W2 and a second depth D2. The second width W2 is the width in a direction perpendicular to the extension direction of the trench connection structure 45. The second width W2 is preferably approximately equal to the first width W1 of the trench structure 35. The second depth D2 is preferably approximately equal to the first depth D1 of the trench structure 35. The bottom wall of the trench connection structure 45 is preferably spaced at a distance of 1 μm to 5 μm from the bottom of the first semiconductor region 31.

[0108] The trench connection structure 45 has a single electrode structure including a connection trench 46, a connection insulating film 47, and a connection electrode 48. The connection trench 46 is dug down from the first main surface 3 toward the second main surface 4, and defines the wall surface of the trench connection structure 45. The sidewalls and bottom wall of the connection trench 46 are connected to the sidewalls and bottom wall of the trench 36 of the trench structure 35.

[0109] The connection insulating film 47 coats the wall surface of the connection trench 46 in a film-like manner. The connection insulating film 47 is connected to the first insulating film 37 and the second insulating film 38 at the communicating portion between the trench 36 and the connection trench 46. The connection insulating film 47 may include a silicon oxide film. The connection insulating film 47 preferably includes a silicon oxide film made of an oxide of the substrate 2. The connection insulating film 47 is preferably thicker than the first insulating film 37. The thickness of the connection insulating film 47 may be approximately equal to the thickness of the second insulating film 38.

[0110] The connection electrode 48 is buried in the connection trench 46 with a connection insulating film 47 sandwiched therebetween. The connection electrode 48 may include conductive polysilicon. The connection electrode 48 extends in the first direction X in the first trench portion 45 a and extends in the second direction Y in the second trench portion 45 b. The connection electrode 48 is connected to the second electrode 40 at the communicating portion between the trench 36 and the connection trench 46, and faces the first electrode 39 with the third insulating film 41 sandwiched therebetween. The same gate signal is applied to the connection electrode 48 simultaneously with the first electrode 39 and the second electrode 40.

[0111] The semiconductor chip 1 includes a plurality of n-type source regions 51 formed in regions along the plurality of trench structures 35 in the surface layer portion of the body region 33 of the output region 6 and the current detection region 7. The n-type impurity concentration of the plurality of source regions 51 is higher than that of the first semiconductor region 31. The plurality of source regions 51 are disposed on both sides of each trench structure 35 and are arranged at intervals along each trench structure 35. The plurality of source regions 51 are formed at intervals from the bottom of the body region 33 toward the first main surface 3 and face the first electrodes 39 with the corresponding first insulating films 37 sandwiched therebetween.

[0112] The plurality of source regions 51 along one trench structure 35 are preferably arranged so as to be shifted in the second direction Y relative to the plurality of source regions 51 along the other trench structure 35. In other words, the plurality of source regions 51 along one trench structure 35 are preferably opposed in the first direction X to regions between the plurality of source regions 51 along the other trench structure 35.

[0113] The semiconductor chip 1 includes a plurality of p-type contact regions 52 formed in regions along the plurality of trench structures 35 in the surface layer portion of the body region 33 of the output region 6 and the current detection region 7. The p-type impurity concentration of the plurality of contact regions 52 is higher than that of the body region 33.

[0114] The plurality of contact regions 52 are disposed on both sides of each trench structure 35, and are arranged at intervals along each trench structure 35. The plurality of contact regions 52 are formed at intervals from the bottom of the body region 33 toward the first main surface 3, and face the first electrodes 39 with the corresponding first insulating films 37 interposed therebetween.

[0115] The contact regions 52 are arranged alternately with the source regions 51 on both sides of each trench structure 35. The contact regions 52 along one trench structure 35 are preferably arranged offset in the second direction Y with respect to the contact regions 52 along the other trench structure 35. In other words, the contact regions 52 along one trench structure 35 are preferably opposed in the first direction X to the regions between the contact regions 52 along the other trench structure 35 (i.e., the source regions 51).

[0116] The semiconductor chip 1 includes n gate wirings 53 arranged electrically independent from one another in the interlayer insulating film 24. The n gate wirings 53 include n gate wirings 53 for the main transistor 11 and n gate wirings 53 for the monitor transistor 13. The n gate wirings 53 are selectively electrically connected to at least one corresponding trench structure 35 through a plurality of first via electrodes 54 in the output region 6 and the current detection region 7, and are electrically connected to the control circuit 17 (gate drive circuit 18) in the control region 8. The plurality of first via electrodes 54 may contain tungsten.

[0117] Specifically, the n gate wirings 53 for the main transistor 11 are electrically connected to at least one (multiple in this embodiment) trench structure 35 and at least one (multiple in this embodiment) trench connection structure 45 to be systemized (grouped) as system transistors 12 in the output region 6 via multiple first via electrodes 54.

[0118] Here, an example will be described in which the n gate wirings 53 for the main transistors 11 include a first gate wiring 53A for the first system transistors 12A and a second gate wiring 53B for the second system transistors 12B. The first gate wiring 53A is electrically connected to a plurality of unit trench structures (a plurality of trench structures 35 and a plurality of trench connection structures 45) to be organized (grouped) as the first system transistors 12A through a plurality of first via electrodes 54 in the output region 6.

[0119] The second gate wiring 53B is disposed in the interlayer insulating film 24 while being electrically independent from the first gate wiring 53A. The second gate wiring 53B is electrically connected to a plurality of unit trench structures (a plurality of trench structures 35 and a plurality of trench connection structures 45) to be organized (grouped) as the second system transistors 12B in the output region 6 through a plurality of first via electrodes 54. In this configuration, a plurality of unit trench structures for the second system transistors 12B are organized alternately with a plurality of unit trench structures for the first system transistors 12A.

[0120] On the other hand, the n gate wirings 53 for the monitor transistors 13 are electrically connected to at least one (plurality in this embodiment) trench structure 35 and at least one (plurality in this embodiment) trench connection structure 45 to be systemized (grouped) as the system monitor transistor 14 via a plurality of first via electrodes 54 in the current detection region 7. The number of trench structures 35 (the number of trench connection structures 45) constituting the system monitor transistor 14 is less than the number of trench structures 35 (the number of trench connection structures 45) constituting the system transistor 12.

[0121] Here, an example will be described in which the n gate wirings 53 for the monitor transistors 13 include a first gate wiring 53A for the first system monitor transistor 14A and a second gate wiring 53B for the second system monitor transistor 14B. The first gate wiring 53A is electrically connected to at least one trench structure 35 and at least one trench connection structure 45 to be organized as the first system monitor transistor 14A through a plurality of first via electrodes 54 in the current detection region 7.

[0122] The second gate wiring 53B is disposed in the interlayer insulating film 24 while being electrically independent from the first gate wiring 53A. The second gate wiring 53B is electrically connected to at least one trench structure 35 and at least one trench connection structure 45 to be integrated into the second system monitor transistor 14B through a plurality of first via electrodes 54 in the current detection region 7. The trench structure 35 for the second system monitor transistor 14B may be adjacent to the trench structure 35 for the first system monitor transistor 14A.

[0123] The first gate wiring 53A for the monitor transistor 13 may be formed integrally with the first gate wiring 53A for the main transistor 11. Furthermore, the second gate wiring 53B for the monitor transistor 13 may be formed integrally with the second gate wiring 53B for the main transistor 11.

[0124] The semiconductor chip 1 includes a plurality of source wirings 55 arranged in the interlayer insulating film 24. The plurality of source wirings 55 includes a first source wiring 55A for the main transistor 11 and a second source wiring 55B for the monitor transistor 13. The first source wiring 55A covers the output region 6 in the interlayer insulating film 24 and is electrically connected to the plurality of source regions 51 and the plurality of contact regions 52 via a plurality of second via electrodes 56. The plurality of second via electrodes 56 may contain tungsten.

[0125] The second source wiring 55B is selectively routed in the region between the current detection region 7 and the control region 8 within the interlayer insulating film 24. The second source wiring 55B is electrically connected to the plurality of source regions 51 and the plurality of contact regions 52 through the plurality of second via electrodes 56 in the current detection region 7, and is electrically connected to the control circuit 17 (overcurrent protection circuit 20) in the control region 8.

[0126] The semiconductor chip 1 includes the aforementioned source terminal 26 disposed on the interlayer insulating film 24. In this embodiment, the source terminal 26 overlaps the multiple source wirings 55 (first source wiring 55A and second source wiring 55B) in plan view, and covers all of the trench structures 35 and all of the trench connection structures 45.

[0127] The source terminal 26 is electrically connected to the first source wiring 55A via a plurality of third via electrodes 57 arranged in the interlayer insulating film 24. The plurality of third via electrodes 57 are arranged in regions between the plurality of second via electrodes 56 in plan view and cross-sectional view. That is, in this embodiment, the plurality of third via electrodes 57 do not face the second via electrode 56 across the first source wiring 55A. Of course, the plurality of third via electrodes 57 may face the second via electrode 56 across the first source wiring 55A.

[0128] The source terminal 26 preferably has a thickness greater than that of the source wiring 55. The thickness of the source terminal 26 is preferably greater than the first depth D1 of the plurality of trench structures 35 (the second depth D2 of the trench connection structure 45). The thickness of the source terminal 26 is preferably greater than the thickness of the interlayer insulating film 24. The thickness of the source terminal 26 may be 1 μm or more and 25 μm or less.

[0129] The thickness of the source terminal 26 may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less. When the source terminal 26 contains an Al-based metal as a main component, the thickness of the source terminal 26 may be 1 μm or more and 10 μm or less. When the source terminal 26 contains a Cu-based metal as a main component, the thickness of the source terminal 26 may be 10 μm or more and 25 μm or less.

[0130] FIG. 8 is a perspective view showing a semiconductor device 61 on which the semiconductor chip 1 shown in FIG. 1 is mounted. FIG. 9 is a plan view showing the internal structure of the semiconductor device 61 shown in FIG. 8. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 9. FIG. 12 is an enlarged plan view showing a portion of FIG. 9. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 12. FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. 12.

[0131] 8 to 14, the semiconductor device 61 may be referred to as a "semiconductor package" or a "semiconductor module." The package type of the semiconductor device 61 may take various forms depending on the use environment, the mounting target, the form of the semiconductor chip 1, etc. In this example, the semiconductor device 61 is an eight-terminal SOP (Small Outline Package).

[0132] The semiconductor device 61 includes a rectangular parallelepiped package body 62. The package body 62 includes a matrix resin and a plurality of fillers. The matrix resin may be a thermosetting resin (e.g., epoxy resin). The plurality of fillers may be insulating spherical particles (e.g., silica particles).

[0133] The package body 62 has a first surface 63 on one side, a second surface 64 on the other side, and first to fourth side walls 65A to 65D connecting the first surface 63 and the second surface 64. The first surface 63 is a mounting surface, and the second surface 64 is a non-mounting surface. The first surface 63 and the second surface 64 are formed in a quadrangular shape (in this embodiment, a rectangular shape extending in the first direction X) in a plan view.

[0134] The first side wall 65A and the second side wall 65B extend in the first direction X along the first main surface 3 and face each other in the second direction Y. The first side wall 65A and the second side wall 65B form long sides of the package body 62. The third side wall 65C and the fourth side wall 65D extend in the second direction Y and face each other in the first direction X. The third side wall 65C and the fourth side wall 65D form short sides of the package body 62.

[0135] The semiconductor device 61 includes a rectangular parallelepiped metal plate 66 disposed within a package body 62. The metal plate 66 may also be referred to as a metal "die pad." The metal plate 66 has a first plate surface 67 on one side, a second plate surface 68 on the other side, and first to fourth plate side walls 69A to 69D connecting the first plate surface 67 and the second plate surface 68.

[0136] The first plate surface 67 and the second plate surface 68 are formed in a quadrangular shape (in this embodiment, a rectangular shape extending in the first direction X) in a plan view. The second plate surface 68 is exposed from the second surface 64 of the package body 62. Of course, the metal plate 66 may be arranged inside the package body 62 so that the second plate surface 68 is not exposed from the second surface 64.

[0137] The first plate side wall 69A and the second plate side wall 69B extend in the first direction X along the first main surface 3 and face each other in the second direction Y. The first plate side wall 69A and the second plate side wall 69B form long sides of the metal plate 66. The third plate side wall 69C and the fourth plate side wall 69D extend in the second direction Y and face each other in the first direction X. The third plate side wall 69C and the fourth plate side wall 69D form short sides of the metal plate 66.

[0138] The semiconductor device 61 includes at least one (in this embodiment, multiple) extension portion 70 that is drawn out from the metal plate 66 toward at least one of the first to fourth side walls 65A to 65D within the package body 62. The multiple extension portions 70 include a first extension portion 70A and a second extension portion 70B.

[0139] The first extending portion 70A extends in a strip-like shape from the third plate sidewall 69C toward the third sidewall 65C. In this embodiment, the first extending portion 70A has a bent portion that bends toward the first surface 63 and is exposed at the third sidewall 65C from a portion intermediate the thickness range of the package body 62. The second extending portion 70B extends in a strip-like shape from the fourth plate sidewall 69D toward the fourth sidewall 65D. In this embodiment, the second extending portion 70B has a bent portion that bends toward the first surface 63 and is exposed at the fourth sidewall 65D from a portion intermediate the thickness range of the package body 62.

[0140] The semiconductor device 61 includes first to eighth metallic lead terminals 71A to 71H arranged within the package body 62 at intervals from the metal plate 66 so as to extend from the inside to the outside of the package body 62. The first to fourth lead terminals 71A to 71D are arranged at intervals in the first direction X on the first sidewall 65A side, and each is formed in a strip shape extending in the second direction Y. The fifth to eighth lead terminals 71E to 71H are arranged at intervals in the first direction X on the second sidewall 65B side, and each is formed in a strip shape extending in the second direction Y.

[0141] The first to eighth lead terminals 71A to 71H each have an inner end, a band portion, and an outer end. The inner end is disposed midway through the thickness range of the package body 62 so as to be located closer to the first surface 63 than the height position of the metal plate 66. The planar shape of the inner end is arbitrary. The band portion is drawn out from the inner end to the outside of the package body 62 and bent toward the second surface 64 outside the package body 62. The band portion extends to a height position that crosses the second surface 64 of the package body 62. The outer end extends substantially parallel to the second surface 64 at a height position lower than the second surface 64 of the package body 62.

[0142] The semiconductor device 61 includes a semiconductor chip 1 disposed on a metal plate 66 (first plate surface 67) within a package body 62. The semiconductor chip 1 is disposed on the metal plate 66 with the drain terminal 25 facing the metal plate 66 (first plate surface 67).

[0143] The semiconductor device 61 includes a conductive bonding material 72 interposed between the semiconductor chip 1 and a metal plate 66 in a package body 62. Specifically, the conductive bonding material 72 is interposed between the drain terminal 25 and the metal plate 66, electrically and mechanically connecting the drain terminal 25 and the metal plate 66. The conductive bonding material 72 may include solder or a metal paste. The solder may be lead-free solder. The metal paste may include at least one of Au, Ag, and Cu. The Ag paste may be an Ag sintering paste.

[0144] The semiconductor device 61 includes a plurality of pseudo bumps 75 disposed on the source terminal 26 in a state free from wires within the package body 62. Each of the pseudo bumps 75 is made of a metal mass formed using a wire bonding process for the source terminal 26. The wire bonding process is performed using a capillary (wire feeder) of a bonding device.

[0145] The plurality of pseudo bumps 75 are arranged on the source terminal 26 more densely than the true bumps 90 described below. "Denser than the true bumps 90" means that the area occupied by the plurality of pseudo bumps 75 relative to the source terminal 26 is larger than that of other structures (true bumps 90 described below) connected to the source terminal 26. The plurality of pseudo bumps 75 are arranged on the source terminal 26 with a first occupation area per unit planar area.

[0146] 12 , each of the pseudo-bumps 75 has a first size S1 in plan view. The first size S1 is defined by the length of the widest portion of the pseudo-bump 75 in plan view. The first size S1 may be 50 μm or more and 250 μm or less.

[0147] The first size S1 may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or more and 250 μm or less. The first size S1 is preferably 75 μm or more and 200 μm or less. The first size S1 is particularly preferably 100 μm or more and 180 μm or less.

[0148] The multiple pseudo bumps 75 are arranged on the source terminal 26 at a first pitch P1 in a plan view. The first pitch P1 is defined by the distance between the centers of the multiple pseudo bumps 75. The multiple pseudo bumps 75 may be arranged so as to be in contact with each other at the first pitch P1, or may be arranged at intervals from each other at the first pitch P1. It is preferable that the multiple pseudo bumps 75 are arranged at intervals from each other.

[0149] The first pitch P1 is preferably 1 to 2.5 times the first size S1. The ratio P1 / S1 of the first pitch P1 to the first size S1 may be 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, or 2.25 to 2.5. The ratio P1 / S1 is preferably greater than 1. It is particularly preferable that the ratio P1 / S1 be 1.25 to 1.75.

[0150] The first pitch P1 may be 50 μm or more and 250 μm or less. The first pitch P1 may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or more and 250 μm or less. The first pitch P1 is preferably 75 μm or more and 200 μm or less. The first pitch P1 is particularly preferably 100 μm or more and 180 μm or less.

[0151] The spacing I between the multiple pseudo bumps 75 may be 0 μm or more and 100 μm or less. The spacing I may be 0 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, or 90 μm or more and 100 μm or less. The spacing I is preferably 10 μm or more. The spacing I is particularly preferably 30 μm or more and 60 μm or less.

[0152] 13 , the plurality of pseudo bumps 75 each have a first thickness T1. The first thickness T1 is defined by the thickness of the thickest portion of the pseudo bump 75 in a cross-sectional view. The first thickness T1 is preferably greater than the first depth D1 of the plurality of trench structures 35. The first thickness T1 is preferably greater than the thickness of the source terminal 26. The first thickness T1 is preferably greater than the thickness of the first semiconductor region 31. The first thickness T1 may be greater than the thickness of the substrate 2. Of course, the first thickness T1 may also be less than the thickness of the substrate 2.

[0153] The first thickness T1 may be 10 μm or more and 150 μm or less. The first thickness T1 may be 10 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, or 125 μm or more and 150 μm or less. The first thickness T1 is preferably 25 μm or more and 100 μm or less. It is particularly preferable that the first thickness T1 be 50 μm or more.

[0154] It is preferable that at least three pseudo bumps 75 are arranged on the source terminal 26 as a pseudo bump group 76. In this case, it is preferable that the at least three pseudo bumps 75 are arranged in a layout where they are located at the vertices of an isosceles triangle in a plan view. It is particularly preferable that the isosceles triangle is an equilateral triangle. In other words, a plurality of pseudo bumps 75 are arranged in a layout where they are located at the vertices of a triangle in a plan view, and no fourth bump is arranged in the space surrounded by three pseudo bumps 75. This configuration may be defined as "a plurality of pseudo bumps 75 densely arranged."

[0155] At least seven pseudo bumps 75 are preferably arranged on the source terminal 26 as a pseudo bump group 76. In this case, six pseudo bumps 75 are preferably arranged around one pseudo bump 75 in plan view. The seven pseudo bumps 75 may include one central bump 73 and six surrounding bumps 74 arranged on concentric circles centered on the center of the central bump 73 in plan view.

[0156] It is preferable that the six peripheral bumps 74 are arranged in a layout in which they are located at the vertices of a hexagon in a plan view, and the one central bump 73 is arranged in a layout in which they are located at the center of the hexagon in a plan view. In other words, it is preferable that the multiple pseudo bumps 75 are bonded to the source terminal 26 in a layout that forms a hexagonal close-packed array (i.e., a honeycomb array) in a plan view. In this case, it is most preferable that the hexagon is a regular hexagon.

[0157] 9, a pseudo-bump group 76 including 28 pseudo-bumps 75 arranged in a hexagonal close-packed layout is bonded to the source terminal 26. The number of pseudo-bumps 75 bonded to the source terminal 26 is arbitrary, but it is preferable that a pseudo-bump group 76 including at least three pseudo-bumps 75 and / or a pseudo-bump group 76 including at least seven pseudo-bumps 75 be bonded to the source terminal 26. Of course, multiple pseudo-bump groups 76 may be bonded to the source terminal 26 at a distance greater than the first pitch P1 (interval I).

[0158] The bonding locations of the plurality of pseudo bumps 75 (pseudo bump group 76) to the source terminal 26 may be set based on the temperature distribution of the semiconductor chip 1. For example, the high temperature region and the low temperature region of the output region 6 may be analyzed using thermography, a simulation tool, or the like, and the plurality of pseudo bumps 75 (pseudo bump group 76) may be bonded to the portion of the source terminal 26 that covers the high temperature region of the output region 6.

[0159] For example, the temperature is more likely to rise in the inner part (e.g., the center) of the output region 6 than in the peripheral part of the output region 6. Therefore, the multiple pseudo bumps 75 (pseudo bump group 76) may be bonded to the source terminal 26 in a layout in which they are densely packed in the inner part (e.g., the center) of the source terminal 26 and sparsely packed in the peripheral part of the source terminal 26. A configuration in which the multiple pseudo bumps 75 are "sparse" includes a configuration in which no pseudo bumps 75 are present. In this configuration, one pseudo bump 75 is arranged along each of the three sides of the peripheral part of the source terminal 26.

[0160] The temperature of the control region 8 is lower than the temperature of the output region 6. In this embodiment, the source terminal 26 covers the output region 6 so as to expose the control region 8, and the multiple pseudo bumps 75 (pseudo bump group 76) are arranged in a region overlapping the output region 6 in a planar view. In other words, the multiple pseudo bumps 75 (pseudo bump group 76) are arranged in positions overlapping the main transistor 11 in a planar view, and are not arranged in a region overlapping the control region 8 in a planar view.

[0161] Some of the multiple pseudo bumps 75 (pseudo bump group 76) may face the monitor transistor 13 in plan view. That is, the multiple pseudo bumps 75 (pseudo bump group 76) may face the multiple trench structures 35 for the main transistor 11 and the multiple trench structures 35 for the monitor transistor 13. Of course, the multiple pseudo bumps 75 (pseudo bump group 76) may be arranged on the source terminal 26 so as not to face the multiple trench structures 35 for the monitor transistor 13.

[0162] Each pseudo-bump 75 may face 10 to 200 trench structures 35. The number of facing trench structures 35 for each pseudo-bump 75 may be 10 to 25, 25 to 50, 50 to 75, 75 to 100, 100 to 125, 125 to 150, 150 to 175, or 175 to 200. The number of facing trench structures 35 for each pseudo-bump 75 is preferably 25 to 100.

[0163] 12 and 13, a specific shape of one pseudo-bump 75 will be described. In this form, the pseudo-bump 75 includes a first bump body 77 and a first bump metal film 78. The first bump body 77 includes a first metal. The first metal is made of a material different from that of the source terminal 26, and is preferably made of a metal harder than the source terminal 26. The first metal includes, for example, at least one of a Cu-based metal, an Al-based metal, an Au-based metal, and an Ag-based metal.

[0164] The Cu-based metal may include pure Cu or a Cu alloy. The Al-based metal may include pure Al or an Al alloy. The Au-based metal may include pure Au or an Au alloy. The Ag-based metal may include pure Ag or an Ag alloy. In this embodiment, the first bump body 77 includes pure Cu. In this case, the source terminal 26 is preferably an Al-based metal layer.

[0165] The first bump main body 77 includes a first body portion 79 and a first neck portion 80. The first body portion 79 is made up of a wide portion connected to the source terminal 26. The first body portion 79 is formed in a generally cylindrical shape with outwardly curved sidewalls in a cross-sectional view. The first body portion 79 has a first body size SB1 that forms the first size S1 of the pseudo bump 75 in a plan view.

[0166] The first body portion 79 may have a first body thickness TB1 that is 0.1 to 0.9 times the first thickness T1 of the pseudo bump 75. The first body thickness TB1 is preferably greater than the thickness of the first semiconductor region 31. The first body thickness TB1 may be greater than the thickness of the substrate 2. Of course, the first body thickness TB1 may also be smaller than the thickness of the substrate 2.

[0167] The thickness ratio T1 / TB1 of the first body thickness TB1 to the first thickness T1 may be 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. The thickness ratio T1 / TB1 is preferably 0.4 to 0.7. It is particularly preferable that the thickness ratio T1 / TB1 be 0.5 or greater.

[0168] The first neck portion 80 is a portion that protrudes from the first body portion 79 toward the opposite side from the source terminal 26 and has a width narrower than that of the first body portion 79. The first neck portion 80 is formed in a generally cylindrical shape in cross section. In this embodiment, the first neck portion 80 has a first upper end portion 81 that slopes obliquely downward. Specifically, the first upper end portion 81 may have an upper apex portion 82, an upper base portion 83, and an inclined portion 84 in cross section.

[0169] The upper apex 82 is formed on one side of the periphery of the first upper end 81 in a cross-sectional view. The upper base 83 is formed on the other side of the periphery of the first upper end 81 in a cross-sectional view, and is located closer to the first body portion 79 than the height position of the upper apex 82. The inclined portion 84 slopes obliquely downward from the upper apex 82 to the upper base 83 in a cross-sectional view. The first upper end 81 may have an upper protrusion 85 that protrudes from the upper base 83 toward the opposite side from the first body portion 79. The tip of the upper protrusion 85 may be formed at a height position closer to the first body portion 79 than the height position of the tip of the upper apex 82.

[0170] The first neck portion 80 has a first neck size SN1 that is smaller than the first body size SB1 in a plan view. The first neck size SN1 may be 0.1 to 0.9 times the first body size SB1 (first size S1).

[0171] The size ratio SN1 / SB1 of the first neck size SN1 to the first body size SB1 may be 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0.6, 0.6 to 0.7, 0.7 to 0.8, or 0.8 to 0.9. The size ratio SN1 / SB1 is preferably 0.5 to 0.7. It is particularly preferable that the size ratio SN1 / SB1 be greater than 0.5.

[0172] The first bump metal film 78 includes a second metal different from the first metal of the first bump body 77, and covers at least a portion of the outer surface of the first bump body 77. The first bump metal film 78 covers the area of ​​the outer surface of the first bump body 77 outside the upper end apex 82 so as to expose the upper end apex 82.

[0173] 13 shows a configuration in which the first bump metal film 78 covers the entire area outside the top end 82, but the first bump metal film 78 does not necessarily have to have such a configuration. In addition, the configuration of the first bump metal film 78 between the multiple pseudo bumps 75 is indefinite and is not determined to be a fixed configuration.

[0174] For example, the first bump metal film 78 may cover at least a portion of the outer surface of the first bump body 77 so as to partially expose the first bump body 77 (first metal) in the area outside the upper end apex 82, and a portion of the first bump metal film 78 may be located inside the first bump body 77.

[0175] For example, a portion of the first bump metal film 78 may melt into the inside of the first bump body 77. For example, the area covered by the first bump metal film 78 with respect to the first bump body 77 may be less than the area of ​​the first bump body 77 exposed to the first bump metal film 78. Of course, the area covered by the first bump metal film 78 with respect to the first bump body 77 may be equal to or greater than the area of ​​the first bump body 77 exposed to the first bump metal film 78.

[0176] The first bump metal film 78 is preferably made of a plating film and includes at least one of a Ni plating film, a Pd plating film, and an Au plating film. For example, the first bump metal film 78 may have a layered structure including a Ni plating film, a Pd plating film, and an Au plating film stacked in this order on the first bump body 77.

[0177] For example, the first bump metal film 78 may have a layered structure including a Ni plating film and a Pd plating film stacked in this order on the first bump body 77. For example, the first bump metal film 78 may have a single-layer structure made of a Ni plating film, a Pd plating film, or an Au plating film.

[0178] The semiconductor device 61 includes at least one (in this embodiment, multiple) first bonding wire 89 disposed within the package body 62. The multiple first bonding wires 89 electrically connect the source terminal 26 to at least one connection target (in this embodiment, the first to fourth lead terminals 71A to 71D) selected from the first to eighth lead terminals 71A to 71H. The number of first bonding wires 89 is not limited to a specific number as long as it is one or more.

[0179] In this embodiment, four first bonding wires 89 are connected to the source terminal 26 and the first lead terminal 71A, four first bonding wires 89 are connected to the source terminal 26 and the second lead terminal 71B, four first bonding wires 89 are connected to the source terminal 26 and the third lead terminal 71C, and four first bonding wires 89 are connected to the source terminal 26 and the fourth lead terminal 71D.

[0180] The plurality of first bonding wires 89 each include a true bump 90, a wire loop 91, and a wire tail 92. The true bump 90 is a metal mass connected to a wire (wire loop 91) and bonded to the source terminal 26. The wire loop 91 is a wire portion that extends in an arch shape in the region between the true bump 90 and the connection target. The wire tail 92 is an end of the wire bonded to the connection target. The plurality of first bonding wires 89 are formed through a wire bonding process using a capillary (wire supply device) of a bonding device.

[0181] The following describes the configuration of the multiple true bumps 90. The multiple true bumps 90 are arranged on the source terminal 26 at intervals from the multiple pseudo bumps 75 (pseudo bump group 76). In this configuration, the multiple true bumps 90 are arranged on the peripheral portion of the source terminal 26 at intervals along the peripheral edge of the source terminal 26. The locations where the multiple true bumps 90 are arranged may be any empty space between the peripheral edge of the source terminal 26 and the multiple pseudo bumps 75 (pseudo bump group 76), and are not limited to any specific location.

[0182] The multiple true bumps 90 are arranged more sparsely on the source terminal 26 than the multiple pseudo bumps 75. "Sparsely" here means that the area occupied by the multiple true bumps 90 on the source terminal 26 is smaller than the area occupied by the multiple pseudo bumps 75 on the source terminal 26.

[0183] The form in which the true bumps 90 are "sparsely" arranged also includes a case in which only a single true bump 90 is arranged on the source terminal 26 and the occupation area of ​​the single true bump 90 is smaller than the occupation area of ​​the multiple pseudo bumps 75. In other words, it is sufficient that one or more true bumps 90 are arranged on the source terminal 26 with a second occupation area that is less than the first occupation area of ​​the multiple pseudo bumps 75 per unit planar area.

[0184] Each of the true bumps 90 has a second size S2 in plan view. The second size S2 is defined by the length of the widest portion of the true bump 90 in plan view. The second size S2 may be 50 μm or more and 250 μm or less.

[0185] The second size S2 may be 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, 175 μm or more and 200 μm or less, 200 μm or more and 225 μm or less, or 225 μm or more and 250 μm or less. The second size S2 is preferably 75 μm or more and 200 μm or less. The second size S2 is particularly preferably 100 μm or more and 180 μm or less.

[0186] The second size S2 may be equal to or greater than the first size S1 of the pseudo bump 75, or may be less than the first size S1. The second size S2 is preferably approximately equal to the first size S1. This configuration allows the pseudo bump 75 and the true bump 90 to be formed under the same manufacturing conditions with respect to size.

[0187] The true bumps 90 are arranged on the source terminal 26 at a second pitch P2 that is equal to or greater than the first pitch P1 of the pseudo bumps 75 in a plan view. The second pitch P2 is defined by the distance between the centers of two adjacent true bumps 90. The true bumps 90 are preferably arranged at intervals at the second pitch P2 so as not to come into contact with each other.

[0188] The second pitch P2 may take any value as long as the entire true bump 90 is located within the area surrounded by the periphery of the source terminal 26 and the second pitch P2 is equal to or greater than the first pitch P1. As an example, the pitch ratio P2 / P1 of the second pitch P2 to the first pitch P1 may be 1 or greater and 20 or less. The pitch ratio P2 / P1 may be 1 or greater and 2 or less, 2 or greater and 5 or less, 5 or greater and 10 or less, 10 or greater and 15 or less, or 15 or greater and 20 or less. It is preferable that the pitch ratio P2 / P1 be greater than 1.

[0189] The multiple true bumps 90 are arranged on the source terminal 26 at a third pitch P3 based on one adjacent pseudo bump 75. The third pitch P3 is defined by the distance between the centers of the pseudo bumps 75 and true bumps 90 that are adjacent to each other. The third pitch P3 is preferably equal to or greater than the first pitch P1 of the pseudo bumps 75. It is preferable that at least one true bump 90 is arranged at a third pitch P3 that is larger than the first pitch P1. In this embodiment, all true bumps 90 are arranged at a third pitch P3 that is larger than the first pitch P1.

[0190] The third pitch P3 can take any value as long as the entire true bump 90 is located within the area surrounded by the periphery of the source terminal 26 and is equal to or greater than the first pitch P1. As an example, the pitch ratio P3 / P1 of the third pitch P3 to the first pitch P1 may be 1 or greater and 20 or less. The pitch ratio P2 / P1 may be 1 or greater and 2 or less, 2 or greater and 5 or less, 5 or greater and 10 or less, 10 or greater and 15 or less, or 15 or greater and 20 or less.

[0191] Each of the multiple true bumps 90 has a second thickness T2. The second thickness T2 is defined by the thickness of the thickest portion of the true bump 90 in a cross-sectional view. The second thickness T2 is preferably greater than the first depth D1 of the multiple trench structures 35. The second thickness T2 is preferably greater than the thickness of the source terminal 26. The second thickness T2 is preferably greater than the thickness of the first semiconductor region 31. The second thickness T2 may be greater than the thickness of the substrate 2. Of course, the second thickness T2 may also be smaller than the thickness of the substrate 2.

[0192] The second thickness T2 may be 10 μm or more and 150 μm or less. The second thickness T2 may be 10 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, or 125 μm or more and 150 μm or less. The second thickness T2 is preferably 25 μm or more and 100 μm or less. It is particularly preferable that the second thickness T2 be 50 μm or more.

[0193] The second thickness T2 may be equal to or greater than the first thickness T1 of the pseudo bump 75, or may be less than the first thickness T1. The second thickness T2 is preferably approximately equal to the first thickness T1. This configuration allows the pseudo bump 75 and the true bump 90 to be formed under the same manufacturing conditions with respect to thickness.

[0194] The multiple true bumps 90 are arranged in a region overlapping the output region 6 in a plan view. In other words, the multiple true bumps 90 are arranged in a position overlapping the main transistor 11 in a plan view, and are not arranged in a region overlapping the control region 8 in a plan view. Some of the multiple true bumps 90 may face the monitor transistor 13 in a plan view.

[0195] That is, the multiple true bumps 90 may face the multiple trench structures 35 for the main transistor 11 and the multiple trench structures 35 for the monitor transistor 13. Of course, the multiple true bumps 90 may be arranged on the source terminal 26 so as not to face the multiple trench structures 35 for the monitor transistor 13.

[0196] Each true bump 90 may face 10 to 200 trench structures 35. The number of facing trench structures 35 for each true bump 90 may be 10 to 25, 25 to 50, 50 to 75, 75 to 100, 100 to 125, 125 to 150, 150 to 175, or 175 to 200. The number of facing trench structures 35 for each true bump 90 is preferably 25 to 100.

[0197] 12 and 14, a specific shape of one true bump 90 will be described. In this form, the true bump 90 includes a second bump body 97 and a second bump metal film 98. The second bump body 97 includes a first metal. The first metal is made of a material different from that of the source terminal 26 and is preferably made of a metal harder than the source terminal 26. The first metal includes, for example, at least one of a Cu-based metal, an Al-based metal, an Au-based metal, and an Ag-based metal.

[0198] The Cu-based metal may include pure Cu or a Cu alloy. The Al-based metal may include pure Al or an Al alloy. The Au-based metal may include pure Au or an Au alloy. The Ag-based metal may include pure Ag or an Ag alloy. In this embodiment, the second bump body 97 includes pure Cu. In this case, the source terminal 26 is preferably an Al-based metal layer. The second bump body 97 preferably includes the same metal as the first bump body 77 of the pseudo-bump 75. Of course, the second bump body 97 may include a metal different from that of the first bump body 77.

[0199] The second bump body 97 includes a second body portion 99 and a second neck portion 100. The second body portion 99 is made up of a wide portion connected to the source terminal 26. The second body portion 99 is formed in a generally cylindrical shape with outwardly curved sidewalls in a cross-sectional view. The second body portion 99 has a second body size SB2 that forms the second size S2 of the true bump 90 in a plan view.

[0200] The second body portion 99 may have a second body thickness TB2 that is 0.1 to 0.9 times the second thickness T2 of the true bump 90. The second body thickness TB2 is preferably greater than the thickness of the first semiconductor region 31. The second body thickness TB2 may be greater than the thickness of the substrate 2. Of course, the second body thickness TB2 may be smaller than the thickness of the substrate 2.

[0201] The thickness ratio T2 / TB2 of the second body thickness TB2 to the second thickness T2 may be 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, or 0.8 or more and 0.9 or less. The thickness ratio T2 / TB2 is preferably 0.4 or more and 0.7 or less. The thickness ratio T2 / TB2 is particularly preferably 0.5 or more. The second body thickness TB2 may be approximately equal to the first body thickness TB1 of the pseudo-bump 75.

[0202] The second neck portion 100 is a portion that protrudes from the second body portion 99 toward the opposite side from the source terminal 26 and has a narrower width than the second body portion 99. The second neck portion 100 is formed in a generally cylindrical shape in cross section. The second neck portion 100 has a second upper end portion 101 connected to the wire loop 91. Unlike the first upper end portion 81 of the first neck portion 80, the second upper end portion 101 does not have the upper apex portion 82, the upper base portion 83, or the inclined portion 84.

[0203] The second neck portion 100 has a second neck size SN2 that is smaller than the second body size SB2 in a plan view. The second neck size SN2 may be 0.1 to 0.9 times the second body size SB2 (first size S1).

[0204] The size ratio SN2 / SB2 of the second neck size SN2 to the second body size SB2 may be 0.1 or greater and 0.2 or less, 0.2 or greater and 0.3 or less, 0.3 or greater and 0.4 or less, 0.4 or greater and 0.5 or less, 0.5 or greater and 0.6 or less, 0.6 or greater and 0.7 or less, 0.7 or greater and 0.8 or less, or 0.8 or greater and 0.9 or less. The size ratio SN2 / SB2 is preferably 0.5 or greater and 0.7 or less. It is particularly preferable that the size ratio SN2 / SB2 be greater than 0.5. The second neck size SN2 may be approximately equal to the first neck size SN1 of the pseudo bump 75.

[0205] The second bump metal film 98 includes a second metal different from the first metal of the second bump body 97, and covers at least a portion of the outer surface of the second bump body 97. The second bump metal film 98 also covers at least a portion of the outer surface of the wire loop 91 and at least a portion of the outer surface of the wire tail 92.

[0206] 14 shows a configuration in which the second bump metal film 98 covers the entire outer surface of the second bump body 97, but the second bump metal film 98 does not necessarily have to have such a configuration. In addition, the configuration of the second bump metal film 98 between the multiple true bumps 90 is indefinite and is not determined to be a fixed configuration.

[0207] For example, the second bump metal film 98 may cover at least a portion of the outer surface of the second bump body 97 so as to partially expose the second bump body 97 (first metal), and a portion of the second bump metal film 98 may be located inside the second bump body 97.

[0208] For example, a portion of the second bump metal film 98 may melt into the second bump body 97. For example, the area of ​​the second bump body 97 covered by the second bump metal film 98 may be less than the area of ​​the second bump body 97 exposed to the second bump metal film 98. Of course, the area of ​​the second bump body 97 covered by the second bump metal film 98 may be equal to or greater than the area of ​​the second bump body 97 exposed to the second bump metal film 98.

[0209] The second bump metal film 98 is preferably made of a plating film and includes at least one of a Ni plating film, a Pd plating film, and an Au plating film. For example, the second bump metal film 98 may have a layered structure including a Ni plating film, a Pd plating film, and an Au plating film stacked in this order on the second bump body 97.

[0210] For example, the second bump metal film 98 may have a layered structure including a Ni-plated film and a Pd-plated film stacked in this order on the second bump body 97. For example, the second bump metal film 98 may have a single-layer structure made of a Ni-plated film, a Pd-plated film, or an Au-plated film. The second bump metal film 98 preferably has the same configuration as the first bump metal film 78 of the pseudo-bump 75.

[0211] 13 and 14 , semiconductor device 61 includes a plurality of first thin film portions 111, a plurality of second thin film portions 112, and a thick film portion 113 formed on source terminal 26. Each of the plurality of first thin film portions 111 is formed from a portion of source terminal 26 that is sunken due to the bonding of a plurality of pseudo bumps 75, and is formed at each of the bonding portions of source terminal 26 where the plurality of pseudo bumps 75 are bonded.

[0212] The plurality of second thin film portions 112 are each formed from a portion of the source terminal 26 that has been sunken due to the bonding of the plurality of true bumps 90, and are formed at the respective bonding portions of the plurality of true bumps 90 in the source terminal 26. The thick film portions 113 are formed from portions that have avoided the sunken portion caused by the bonding of the plurality of pseudo bumps 75 and the plurality of true bumps 90, and are formed in regions of the source terminal 26 outside the bonding portions of the plurality of pseudo bumps 75 and the bonding portions of the plurality of true bumps 90.

[0213] The maximum thickness of the thick film portion 113 may be greater than the minimum thickness of the first thin film portion 111 (second thin film portion 112) and may be not more than 2.5 times the minimum thickness of the first thin film portion 111 (second thin film portion 112). The thickness ratio of the maximum thickness to the minimum thickness may be greater than 1 and not more than 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, or 2.25 to 2.5.

[0214] The semiconductor device 61 includes a plurality of first raised portions 114 formed on the source terminal 26. The plurality of first raised portions 114 are formed on the bonding edges of the plurality of pseudo bumps 75 on the source terminal 26, and are portions of the source terminal 26 that are thicker than the thick film portion 113. Each first raised portion 114 extends in a ring shape along the edge (bonding edge) of each pseudo bump 75 in a plan view. At least a portion of each first raised portion 114 faces the peripheral edge of each pseudo bump 75 in the thickness direction.

[0215] Portions of the source terminal 26 along the edges of each pseudo-bump 75 are made thicker than the first thin-film portions 111 by the thick film portions 113 and the plurality of first raised portions 114. In addition, portions of the source terminal 26 located between the plurality of pseudo-bumps 75 are made thicker than the plurality of first thin-film portions 111 by the thick film portions 113 and the first raised portions 114.

[0216] It is preferable that the portions of the source terminal 26 located between the plurality of pseudo bumps 75 face the plurality of trench structures 35. In other words, in the regions between the plurality of pseudo bumps 75, it is preferable that the thick film portion 113 and the plurality of first protrusions 114 face the plurality of trench structures 35.

[0217] The semiconductor device 61 includes a plurality of second raised portions 115 formed on the source terminal 26. The second raised portions 115 are formed on the bonding edges of the plurality of true bumps 90 on the source terminal 26, and are portions of the source terminal 26 that are thicker than the thick film portion 113. Each second raised portion 115 extends annularly along the edge (bonding edge) of each true bump 90 in a plan view. At least a portion of each second raised portion 115 faces the peripheral edge of each true bump 90 in the thickness direction.

[0218] The portions of the source terminal 26 along the edges of each true bump 90 are made thicker than the second thin film portions 112 by the thick film portions 113 and the second raised portions 115. Furthermore, the portions of the source terminal 26 located between the multiple true bumps 90 are made thicker than the second thin film portions 112 by the thick film portions 113 and the multiple second raised portions 115. Furthermore, the portions of the source terminal 26 located between the pseudo bumps 75 and the true bumps 90 are made thicker by the thick film portions 113 and the multiple second raised portions 115. At least a portion of each second raised portion 115 faces the peripheral edge of each true bump 90 in the thickness direction.

[0219] The semiconductor device 61 includes at least one (a plurality of, in this embodiment) second bonding wire 119 disposed within the package body 62. The plurality of second bonding wires 119 electrically connect the first to fourth control terminals 27 to 30 to at least one connection target (the fifth to eighth lead terminals 71E to 71H in this embodiment) selected from the first to eighth lead terminals 71A to 71H.

[0220] The number of second bonding wires 119 for the first to fourth control terminals 27 to 30 is not limited to a specific number as long as it is at least 1. In this embodiment, one second bonding wire 119 is connected to the first control terminal 27 and the fifth lead terminal 71E, one second bonding wire 119 is connected to the second control terminal 28 and the sixth lead terminal 71F, one second bonding wire 119 is connected to the third control terminal 29 and the seventh lead terminal 71G, and one second bonding wire 119 is connected to the fourth control terminal 30 and the eighth lead terminal 71H.

[0221] Similar to the first bonding wire 89, the second bonding wires 119 each include a true bump 90, a wire loop 91, and a wire tail 92. Similarly to the first bonding wire 89, the second bonding wires 119 also include a second bump body 97 and a second bump metal film 98 in the true bump 90.

[0222] It is preferable that the true bump 90 is bonded to the first to fourth control terminals 27 to 30, and the wire tail 92 is bonded to the fifth to eighth lead terminals 71E to 71H. Of course, the true bump 90 may be bonded to the fifth to eighth lead terminals 71E to 71H, and the wire tail 92 may be bonded to the first to fourth control terminals 27 to 30. Other explanations of the second bonding wire 119 will be omitted, as the explanation of the first bonding wire 89 applies.

[0223] As described above, the semiconductor device 61 includes the substrate 2, the output region 6 (device region), the source terminal 26 (terminal), a plurality of pseudo bumps 75, and at least one true bump 90. The output region 6 is provided on the substrate 2. The source terminal 26 covers the output region 6 in a plan view. The plurality of pseudo bumps 75 are densely arranged on the source terminal 26 in a state where they are released from the wires. The at least one true bump 90 is sparsely arranged on the source terminal 26 compared to the plurality of pseudo bumps 75 in a state where they are connected to the wires.

[0224] That is, the plurality of pseudo bumps 75 are arranged on the source terminal 26 with a first occupation area per unit planar area, and at least one true bump 90 is arranged on the source terminal 26 with a second occupation area per unit planar area that is less than the first occupation area. With this configuration, the plurality of pseudo bumps 75 can absorb heat generated in the output region 6. This makes it possible to suppress a temperature rise in the output region 6 and a deterioration in the electrical characteristics of the output region 6 due to the temperature rise. Therefore, it is possible to provide a semiconductor device 61 that can improve electrical characteristics.

[0225] The locations of the multiple pseudo bumps 75 relative to the source terminal 26 may be set based on the temperature distribution of the semiconductor chip 1. For example, the high temperature region and the low temperature region of the output region 6 may be analyzed using thermography, a simulation tool, or the like, and the multiple pseudo bumps 75 may be densely arranged in the portion of the source terminal 26 that covers the high temperature region of the output region 6, and the multiple pseudo bumps 75 may be sparsely arranged in the portion of the source terminal 26 that covers the low temperature region of the output region 6. At least one true bump 90 is arranged in the portion where the multiple pseudo bumps 75 are sparsely arranged.

[0226] For example, the temperature is more likely to rise in the inner part of the output region 6 than in the peripheral part of the output region 6. Therefore, the multiple pseudo-bumps 75 may be bonded to the source terminal 26 in a layout in which they are densely packed in the inner part of the source terminal 26 and sparsely packed in the peripheral part of the source terminal 26. A form in which the multiple pseudo-bumps 75 are "sparse" also includes a form in which no pseudo-bumps 75 are present.

[0227] Another possible means of absorbing heat generated in the device region is to form a relatively thick plated terminal film (e.g., a Cu plated film of 10 μm or more and 25 μm or less) on or as the source terminal 26 at the wafer stage.

[0228] In this case, not only does the equipment required for forming the plating terminal film (such as film formation equipment and plating solution) increase costs, but the plating terminal film also causes wafer warpage. The electrical and physical properties of the wafer are degraded by the wafer warpage. For example, if cracks or crystal defects occur in the wafer due to the wafer warpage, the electrical properties of the device region fluctuate. Furthermore, the wafer warpage can also hinder the dicing process, etc.

[0229] In contrast, in the semiconductor device 61, multiple pseudo bumps 75 can be bonded to the semiconductor chip 1 during the packaging process of the semiconductor chip 1 after it has been diced from the wafer. Therefore, no equipment is required for forming a plating terminal film. Also, because wafer warpage can be suppressed at the wafer stage, semiconductor chips 1 with reduced cracks and crystal defects can be obtained. Furthermore, relatively thick pseudo bumps 75 can be formed using the relatively inexpensive wire bonding process used in the process of forming the true bumps 90. Therefore, electrical characteristics can be improved while keeping costs down.

[0230] Of course, the pseudo bumps 75 may be bonded to a plated terminal film formed on a terminal (source terminal 26) or to a plated terminal film formed as a terminal (source terminal 26). In this case, the heat absorption effect of the multiple pseudo bumps 75 can be added to the heat absorption effect of the plated terminal film. However, it should be noted that if the amount of heat that can be absorbed by the plated terminal film is already saturated, there is little benefit in bonding multiple pseudo bumps 75 to the plated terminal film.

[0231] The plurality of pseudo-bumps 75 are preferably thicker than the source terminal 26. According to this configuration, the source terminal 26 can be thinned by forming the plurality of relatively thick pseudo-bumps 75. Therefore, heat can be transferred to the plurality of pseudo-bumps 75 via the relatively thin source terminal 26, and at the same time, the cost of forming the source terminal 26 can be reduced.

[0232] For example, the source terminal 26 can include a Cu-based metal film or an Al-based metal film and have a thickness of 1 μm or more and 10 μm or less by employing a plurality of relatively thick pseudo-bumps 75. Since such a source terminal 26 can be formed by a sputtering method, it can be made of an electrode film other than a plating film.

[0233] It is preferable that the multiple true bumps 90 are sparsely arranged on the source terminal 26. In other words, it is preferable that a design rule requiring dense arrangement is not imposed on the multiple true bumps 90. This configuration allows the multiple true bumps 90 to be connected to appropriate positions on the source terminal 26. The multiple pseudo bumps 75 may be arranged on the source terminal 26 at a first pitch P1. In this case, it is preferable that the multiple true bumps 90 are arranged on the source terminal 26 at a second pitch P2 that is equal to or greater than the first pitch P1.

[0234] It is preferable that at least three pseudo bumps 75 are densely arranged on the source terminal 26. It is preferable that the at least three pseudo bumps 75 are arranged in a layout in which they are located at the vertices of an isosceles triangle in a plan view. In this case, it is particularly preferable that the isosceles triangle is an equilateral triangle. With these configurations, the multiple pseudo bumps 75 can be appropriately densely arranged. Furthermore, the pseudo bump group 76 including the multiple pseudo bumps 75 can absorb heat generated in the output region 6.

[0235] It is preferable that at least seven pseudo bumps 75 are densely arranged on the source terminal 26. In this case, it is preferable that six pseudo bumps 75 (peripheral bumps 74) are arranged around one pseudo bump 75 (central bump 73). It is preferable that the six peripheral bumps 74 are arranged on concentric circles centered on the central portion of one central bump 73 in a plan view. It is preferable that the six peripheral bumps 74 are arranged in a layout where they are located at the vertices of a hexagon in a plan view, and the one central bump 73 is arranged in a layout where they are located at the center of the hexagon in a plan view.

[0236] In other words, it is preferable that the multiple pseudo-bumps 75 are bonded to the source terminal 26 in a layout that forms a hexagonal close-packed array (i.e., a honeycomb array) in a plan view. In this case, it is particularly preferable that the hexagon is a regular hexagon. With these configurations, the multiple pseudo-bumps 75 can be appropriately densely arranged. Furthermore, the pseudo-bump group 76 including the multiple pseudo-bumps 75 can absorb heat generated in the output region 6.

[0237] The semiconductor device 61 preferably includes a first thin film portion 111 formed at the bonding portion of the pseudo bump 75 in the source terminal 26. With this configuration, heat generated in the output region 6 can be transferred to the pseudo bump 75 via the first thin film portion 111. The semiconductor device 61 preferably includes a thick film portion 113 formed in an area outside the bonding portion of the pseudo bump 75 in the source terminal 26. With this configuration, heat generated in the output region 6 can be absorbed by the thick film portion 113 in an area outside the bonding portion of the pseudo bump 75. The heat absorbed by the thick film portion 113 is transferred to the pseudo bump 75.

[0238] Furthermore, the portions of the source terminal 26 located between the plurality of pseudo-bumps 75 are made thicker than the plurality of first thin-film portions 111 by the thick-film portions 113. With this configuration, the heat generated in the output region 6 can be absorbed by the thick-film portions 113 in the regions outside the joints of the pseudo-bumps 75.

[0239] The pseudo-bump 75 may include a first bump body 77 containing a first metal, and a first bump metal film 78 containing a second metal different from the first metal and covering at least a portion of the outer surface of the first bump body 77. The pseudo-bump 75 may include a wide first body portion 79 connected to the source terminal 26, and a first neck portion 80 that protrudes from the first body portion 79 toward the opposite side from the source terminal 26 and is narrower than the first body portion 79.

[0240] The semiconductor device 61 may include a plurality of trench structures 35 formed on the first main surface 3 of the output region 6. In this case, the pseudo-bumps 75 preferably overlap the plurality of trench structures 35 in a plan view. With this configuration, heat generated in the plurality of trench structures 35 and / or in the vicinity of the plurality of trench structures 35 can be absorbed by the pseudo-bumps 75 directly above them.

[0241] The pseudo bumps 75 preferably have a thickness greater than the depth of each trench structure 35 .

[0242] The semiconductor device 61 preferably has an insulated gate type main transistor 11 including a plurality of trench structures 35 in the output region 6. With this configuration, the plurality of pseudo bumps 75 can suppress a temperature rise caused by the back electromotive force of the inductive load L during active clamp operation of the main transistor 11. This improves the active clamp resistance.

[0243] The main transistor 11 is preferably a gate-divided transistor with n systems including n first gates FG to which n gate signals are individually input. According to this configuration, the main transistor 11 is controlled to switch between a full-on state in which all of the first gates FG are on, a part-on state in which some of the first gates FG are on (some of the gates are off), and a full-off state in which all of the first gates FG are off. The on-resistance of the main transistor 11 in the part-on state is higher than that in the full-on state.

[0244] With n main transistors 11, during active clamp operation, the output voltage of the main transistor 11 can be clamped by controlling the first gates FG of some of the main transistors 11 to the on state and controlling the first gates FG of some of the main transistors 11 to the off state. This makes it possible to protect the main transistor 11 from the back electromotive force of the inductive load L and improve the active clamp withstand capability.

[0245] The semiconductor device 61 preferably includes a control region 8 provided on the first main surface 3. The semiconductor device 61 preferably includes a control circuit 17 formed in the control region 8 to generate gate signals to be applied to the plurality of trench structures 35. In this case, the source terminal 26 preferably covers the output region 6 so as to expose the control region 8 in a plan view.

[0246] The semiconductor device 61 preferably includes a first temperature detection region 9 provided on the first main surface 3 adjacent to the output region 6, and a second temperature detection region 10 provided on the first main surface 3 adjacent to the control region 8. The semiconductor device 61 preferably includes a first temperature sensing diode 15 (first temperature sensor) formed in the first temperature detection region 9 to detect the temperature of the output region 6, and a second temperature sensing diode 16 (second temperature sensor) formed in the second temperature detection region 10 to detect the temperature of the control region 8.

[0247] In this case, the control circuit 17 may be configured to generate a gate signal based on the first temperature detection signal ST1 (electrical signal) from the first temperature sensing diode 15 and the second temperature detection signal ST2 (electrical signal) from the second temperature sensing diode 16. With this configuration, the temperature rise in the output region 6 can be suppressed by the multiple pseudo bumps 75, and at the same time, the temperature rise in the output region 6 can be suppressed by utilizing the control of the control circuit 17.

[0248] Fig. 15A is an enlarged view of the portion surrounded by the two-dot chain line XV in Fig. 13. Fig. 15B is a cross-sectional view of the pseudo bump 75 when cut along the second direction Y. Fig. 16 is a diagram showing a method of joining the pseudo bump 75 to the source terminal 26. Fig. 17 is an enlarged plan view of the pseudo bump 75. Although Figs. 15A and 15B to 17 show the structure of the first raised portion 114 of the pseudo bump 75, the second raised portion 115 of the true bump 90 also has a similar structure.

[0249] 15A and 15B , as described above, a first raised portion 114 is formed on the source terminal 26. The first raised portion 114 is a portion of the source terminal 26 at the joining edge of the pseudo-bump 75 that is thicker than the thick film portion 113. The first raised portion 114 is formed by a portion of the source terminal 26 being expelled from the bottom to the side of each pseudo-bump 75 when the pseudo-bumps 75 are joined. Therefore, the first raised portion 114 may be referred to as an expelled object 86 of the source terminal 26. The first raised portion 114 may be referred to as a splash because it has a shape in which a portion of the source terminal 26 splashes up around the pseudo-bump 75 in a splash-like shape.

[0250] The process of forming the rejection object 86 will be described with reference to FIG. 16 . A wire 95 is fed into the inner bore 94 of the capillary 93, and an initial ball is formed at the tip of the capillary 93 by electrical discharge machining of the wire 95. Next, the initial ball is brought into contact with the source terminal 26. A load is applied to the initial ball toward the source terminal 26, and ultrasonic vibrations are simultaneously applied to the initial ball. The ultrasonic vibrations are applied so as to have directionality in a specific direction. In this form, the ultrasonic vibrations are selectively applied along the first direction X. As a result, the initial ball is crushed and simultaneously crimped to the source terminal 26. The portion of the source terminal 26 pressed against the initial ball is pushed outward from below the initial ball by the ultrasonic vibrations along the first direction X, thereby forming the rejection object 86. The wire is then cut off from the crushed initial ball, and the pseudo bump 75 is formed.

[0251] In this way, the rejection material 86 is a structure formed by extruding a portion of the source terminal 26 by ultrasonic vibration, and does not have a fixed shape. Therefore, the rejection material 86 around each pseudo bump 75 may have various shapes. For example, the rejection material 86 may include a first rejection material 861 and a second rejection material 862 having different shapes.

[0252] 15A , the first rejection object 861 may have a mountain-like shape that protrudes from a base surface 87 set along the surface of the thick film portion 113. In a cross-sectional view, the first rejection object 861 may include a top portion 863, and a first inclined portion 864 (inner inclined portion) and a second inclined portion 865 (outer inclined portion) that slope downward at approximately the same angle from the top portion 863 toward the underside of the pseudo-bump 75 and the opposite side thereof. The second inclined portion 865 of the first rejection object 861 extends toward the side of the pseudo-bump 75 so as to move away from the thick film portion 113. As a result, the first rejection object 861 is formed so as not to overlap above the thick film portion 113. Recesses 869 may be selectively formed on the surfaces of the first inclined portion 864 and the second inclined portion 865.

[0253] The second reject object 862 may have a shape that is warped upward relative to the base surface 87. In a cross-sectional view, the second reject object 862 may include a first inclined portion 866 that extends from below the pseudo bump 75 to a position above the thick film portion 113, and a second inclined portion 868 that folds back at a tip end 867 of the first inclined portion 866 and extends toward the below of the pseudo bump 75. Since the tip end 867 of the second reject object 862 is located above the thick film portion 113, the second reject object 862 is formed to be spaced above the thick film portion 113 and overlap the thick film portion 113. Recesses 870 may be selectively formed on the surfaces of the first inclined portion 866 and the second inclined portion 868.

[0254] The first reject 861 may have a first thickness TS1 that is smaller than the thickness TT1 of the thick film portion 113, and the second reject 862 may have a second thickness TS2 that is larger than the thickness TT1. The second thickness TS2 may be larger than the first thickness TS1.

[0255] The first total thickness (TT1+TS1 or TT1+TS2) of the thick film portion 113 and the reject material 86 is preferably greater than the thickness of the interlayer insulating film 24. The first total thickness may be greater than 1 time the minimum thickness of the first thin film portion 111 and not more than 10 times the minimum thickness of the first thin film portion 111. The thickness ratio of the first total thickness to the minimum thickness may be greater than 1 and not more than 2, 2 to 4, 4 to 6, 6 to 8, or 8 to 10. The thickness ratio is preferably 2 to 6.

[0256] 17 , the rejection objects 86 are formed by ultrasonic vibrations applied in the first direction X, and therefore have directivity in the same direction as the direction in which the ultrasonic vibrations are applied. In this embodiment, the rejection objects 86 of each pseudo-bump 75 are formed in pairs on both sides of each pseudo-bump 75 in the first direction X so as to have directivity along the first direction X in a plan view.

[0257] The pair of reject objects 86 may include an reject object 86A on one side in the first direction X and an reject object 86B on the other side. The reject objects 86A and 86B are each formed in a curved shape in a plan view that follows the peripheral edge portion 751 of the pseudo-bump 75, which is circular in a plan view. The reject objects 86A and 86B may be formed in a crescent shape that bulges out in opposite directions in the first direction X. The reject objects 86A and 86B are physically independent from each other. As a result, the peripheral edge portion 751 of the pseudo-bump 75 may include a pair of arc-shaped first peripheral edges 752 adjacent to the reject objects 86A and 86B in the first direction X, and a pair of arc-shaped second peripheral edges 753 between the ends of the reject objects 86A and 86B. In plan view, first peripheral portion 752 may be a region covered by rejects 86A and 86B, and second peripheral portion 753 may be a region not covered by rejects 86A and 86B. Therefore, below second peripheral portion 753, source terminal 26 has flat region 116 made of thick film portion 113, as shown in FIG. 15B .

[0258] As described above, exclusion objects 86 are formed around the pseudo bumps 75. The exclusion objects 86 are formed outside the peripheral edge 751 of the pseudo bumps 75. Therefore, when multiple pseudo bumps 75 are densely arranged as in the present disclosure and the distance between adjacent pseudo bumps 75 becomes small, the adjacent exclusion objects 86 may interfere with each other. Therefore, a layout that can avoid interference of the exclusion objects 86 will be described below with reference to FIGS. 18 and 19 .

[0259] Fig. 18 is a plan view showing a first layout of the pseudo bumps 75. Fig. 19 is a plan view showing a second layout of the pseudo bumps 75.

[0260] 18 and 19, in both the first layout and the second layout, at least three pseudo bumps 75 are arranged in a layout that is located at the vertices of a triangle in a plan view. Furthermore, if attention is focused on seven pseudo bumps 75 that are close to each other, the seven pseudo bumps 75 include one central bump 73 and six peripheral bumps 74 arranged on concentric circles centered on the center of the central bump 73 in a plan view. As a result, the multiple pseudo bumps 75 are arranged in a hexagonal close-packed array (i.e., honeycomb array) in a plan view.

[0261] The first layout will be described in detail with reference to Fig. 18. The first layout may conceptually include at least two patterns of arrangement.

[0262] The first pattern is a honeycomb structure layout 88. The honeycomb structure layout 88 includes one central bump 73 and six peripheral bumps 74 arranged on concentric circles centered on the center of the central bump 73. Furthermore, the peripheral bumps 74 may include a first peripheral bump 741 and a second peripheral bump 742.

[0263] The first peripheral bumps 741 include two first peripheral bumps 741 adjacent to the central bump 73 in the second direction Y. The second peripheral bumps 742 include four second peripheral bumps 742 adjacent to the central bump 73 in an oblique direction that is inclined with respect to both the first direction X and the second direction Y. Two second peripheral bumps 742 are arranged on one side and two on the other side of the central bump 73 in the first direction X.

[0264] The honeycomb structure layout 88 includes a plurality of triangular layouts 743 in which the central bump 73 and two second peripheral bumps 742 adjacent to each other in the second direction Y are located at the vertices of a triangle in a plan view. In this form, the layouts 743 include triangular layouts 743 that share the central bump 73 with each other. In each triangular layout 743, an equilateral triangle is formed by imaginary lines 744 connecting the vertices.

[0265] Exclusions 86 are formed on one side and the other side in the first direction X of the central bump 73 and each peripheral bump 74. For example, the exclusions 86 on one side in the first direction X of each central bump 73 and each peripheral bump 74 may be first exclusions 881, and the exclusions 86 on the other side may be second exclusions 882.

[0266] In the honeycomb structure layout 88, the rejects 86 of the central bump 73 and the rejects 86 of the two first peripheral bumps 741 are arranged at intervals from each other along the second direction Y. More specifically, the first rejects 881 of the central bump 73 and the first rejects 881 of the two first peripheral bumps 741 are arranged at intervals from each other along the second direction Y. Similarly, the second rejects 882 of the central bump 73 and the second rejects 882 of the two first peripheral bumps 741 are arranged at intervals from each other along the second direction Y. The rejects 86 of the central bump 73 face the space regions 745 between the second peripheral bumps 742 in the first direction X.

[0267] In addition, in the honeycomb structure layout 88, the first rejects 881 of the central bump 73 and the second rejects 882 of the two second peripheral bumps 742 are arranged at intervals from each other along the second direction Y. Similarly, the second rejects 882 of the central bump 73 and the first rejects 881 of the two second peripheral bumps 742 are arranged at intervals from each other along the second direction Y.

[0268] As a result, in the honeycomb structure layout 88, the first reject objects 881 of the first peripheral bump 741, the second reject objects 882 of the second peripheral bump 742, the first reject objects 881 of the central bump 73, the second reject objects 882 of the second peripheral bump 742, and the first reject objects 881 of the first peripheral bump 741 are arranged in this order along the second direction Y. In this configuration, the first reject objects 881 and the second reject objects 882 are arranged alternately on an imaginary straight line 883 indicated by a dashed line in Fig. 18 . The first reject objects 881 and the second reject objects 882 on the imaginary straight line 883 overlap each other in the second direction Y.

[0269] Similarly, the second rejects 882 of the first peripheral bump 741, the first rejects 881 of the second peripheral bump 742, the second rejects 882 of the central bump 73, the first rejects 881 of the second peripheral bump 742, and the second rejects 882 of the first peripheral bump 741 are alternately arranged on an imaginary straight line 884 shown by a dashed dotted line in Fig. 18. The first rejects 881 and the second rejects 882 on the imaginary straight line 884 overlap each other in the second direction Y.

[0270] As described above, in the honeycomb structure layout 88, the first reject objects 881 and the second reject objects 882 are arranged alternately on the imaginary straight lines 883 and 884 and overlap each other in the second direction Y. Although the reject objects 86 (the first reject objects 881 and the second reject objects 882) are formed to have directionality in the first direction X, by employing the honeycomb structure layout 88 of FIG. 18 , it is possible to prevent the multiple reject objects 86 from interfering with each other. This allows, for example, the spatial regions 745 between the pseudo-bumps 75 to be used as escape spaces for the reject objects 86 of adjacent pseudo-bumps 75. As a result, it is possible to arrange the multiple pseudo-bumps 75 in a dense layout, thereby increasing the number of pseudo-bumps 75 and improving heat dissipation.

[0271] Next, the second pattern of the first layout includes a first line bump group 120 and a second line bump group 121, each including a plurality of pseudo bumps 75 arranged along the second direction Y. In Fig. 18, the first line bump group 120 includes three pseudo bumps 75, and the second line bump group 121 includes two pseudo bumps 75. The first line bump group 120 and the second line bump group 121 are arranged alternately in the first direction X.

[0272] The multiple pseudo bumps 75 of the first line bump group 120 may be referred to as first pseudo bumps 123, and the multiple pseudo bumps 75 of the second line bump group 121 may be referred to as second pseudo bumps 124. The first pseudo bumps 123 face a space region 125 between two second pseudo bumps 124 in the first direction X. As a result, in a pair of first line bump groups 120 adjacent to each other in the first direction X with the second line bump group 121 in between, the rejection material 86 of the pseudo bump 75 of one first line bump group 120 and the rejection material 86 of the pseudo bump 75 of the other first line bump group 120 face each other across the space region 125 between the multiple pseudo bumps 75 in the second line bump group 121 in plan view.

[0273] On the other hand, the second pseudo bump 124 faces a space region 126 between the two first pseudo bumps 123 in the first direction X.

[0274] Exclusions 86 are formed on one side and the other side in the first direction X of the first pseudo bumps 123 and the second pseudo bumps 124. For example, the exclusions 86 on one side in the first direction X of each of the first pseudo bumps 123 and the second pseudo bumps 124 may be first exclusions 891, and the exclusions 86 on the other side may be second exclusions 892.

[0275] In the second pattern, the first rejects 891 of the first pseudo-bump 123 and the second rejects 892 of the second pseudo-bump 124 are alternately arranged at intervals from each other along the second direction Y. Similarly, the second rejects 892 of the first pseudo-bump 123 and the first rejects 891 of the second pseudo-bump 124 are alternately arranged at intervals from each other along the second direction Y. As a result, the first rejects 891 and the second rejects 892 are alternately arranged on imaginary straight lines 893 and 894 indicated by dashed lines in FIG. 18 . The first rejects 891 and the second rejects 892 on the imaginary straight lines 893 and 894 overlap each other in the second direction Y.

[0276] As described above, in the second pattern, the first rejects 891 and the second rejects 892 are arranged alternately on the imaginary straight lines 893 and 894 and overlap each other in the second direction Y. Although the rejects 86 (the first rejects 891 and the second rejects 892) are formed to have directionality in the first direction X, by adopting the layout of the second pattern in FIG. 18 , it is possible to prevent the multiple rejects 86 from interfering with each other. This allows, for example, the spatial regions 125 and 126 between each pseudo-bump 75 to be used as escape spaces for the rejects 86 of adjacent pseudo-bumps 75. As a result, multiple pseudo-bumps 75 can be arranged in a dense layout, which increases the number of pseudo-bumps 75 and improves heat dissipation.

[0277] 19, the pseudo bumps 75 are arranged in the same row along the direction in which ultrasonic vibrations are applied by the capillary 93 (see FIG. 16) (first direction X in this embodiment). Therefore, the rejection objects 86 may overlap and interfere with each other in the first direction X. As a result, it is more difficult to arrange multiple pseudo bumps 75 in a dense layout than in the layout of FIG. 18.

[0278] FIG. 20 is a plan view showing a modification of the layout of FIG.

[0279] In the above-described embodiment, the layout is configured in a hexagonal close-packed array (i.e., honeycomb array) using only a plurality of pseudo bumps 75. In contrast to this, as shown in Fig. 20, a layout may be configured in which a plurality of pseudo bumps 75 includes at least one true bump 90, and in which the layout is a hexagonal close-packed array (i.e., honeycomb array) in plan view.

[0280] FIG. 21 is a plan view showing a semiconductor chip 200 according to the second embodiment.

[0281] 21 , the semiconductor chip 200 has a modified layout of the output region 6 of the semiconductor chip 1. In this configuration, the output region 6 is partitioned into an L-shape in a plan view. Specifically, the output region 6 has a first region 6A extending in a strip-like manner along the first direction X in the region on the first side surface 5A side, and a second region 6B extending in a strip-like manner along the second direction Y in the region on the third side surface 5C side.

[0282] In this embodiment, the control region 8 is provided in an area on the second side surface 5B side, which is defined by the periphery of the first main surface 3 and the first and second regions 6A and 6B of the output region 6. The current detection region 7 may be provided in either or both of the first and second regions 6A and 6B of the output region 6. In this embodiment, the current detection region 7 is provided in the first region 6A.

[0283] The first temperature detection area 9 may be provided adjacent to either or both of the first area 6A of the output area 6 and the second area 6B of the output area 6. In this embodiment, the first temperature detection area 9 is provided adjacent to the first area 6A. The second temperature detection area 10 is provided adjacent to the control area 8, as in the first embodiment.

[0284] In this embodiment, the source terminal 26 is partitioned into an L-shape in a plan view. Specifically, the source terminal 26 has a first terminal portion 26A extending in a strip shape along the first direction X to cover the first region 6A of the output region 6, and a second terminal portion 26B extending in a strip shape along the second direction Y to cover the second region 6B of the output region 6. In this embodiment, the source terminal 26 has a rectangular notch portion 26a cut out in the first terminal portion 26A to expose the first temperature detection region 9.

[0285] The first to fourth control terminals 27 to 30 are arranged in an area on the second side surface 5B side, in an area partitioned by the periphery of the first main surface 3, the first terminal portion 26A of the source terminal 26, and the second terminal portion 26B of the source terminal 26.

[0286] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0287] The following characteristics can be extracted from the description of this specification and the drawings.

[0288] [Supplementary Note 1-1] A semiconductor device comprising: a substrate (2); a device region (6) provided on the substrate (2); a terminal (26) covering the device region (6) in a plan view; and a plurality of pseudo bumps (75) arranged on the terminals (26), wherein the plurality of pseudo bumps (75) include at least three pseudo bumps (75) densely arranged in a layout positioned at the vertices of a triangle in a plan view; an exclusion member (86) is formed by protruding a part of the terminal (26) from the bottom along the side of each of the three pseudo bumps (75); and the exclusion member (86) of each pseudo bump (75) is formed in pairs on both sides of each pseudo bump (75) in the first direction (X) so as to have directionality along the first direction (X) in a plan view. The exclusion members (86) of the three pseudo bumps (75) are arranged at intervals from one another along a second direction (Y) perpendicular to the first direction (X).

[0289] According to this configuration, the rejects (86) of at least three pseudo-bumps (75) are arranged at intervals from one another along the second direction (Y). Therefore, although the multiple rejects (86) are each formed to have directivity in the first direction (X), it is possible to prevent the multiple rejects (86) from interfering with one another. As a result, the multiple pseudo-bumps (75) can be arranged in a dense layout, and the number of pseudo-bumps (75) can be increased to improve heat dissipation.

[0290] [Appendix 1-2] When focusing on two adjacent pseudo bumps (75) in a diagonal direction that is inclined with respect to both the first direction (X) and the second direction (Y) in a plan view, the rejection object (86) of the pair of rejection objects (86) of one of the pseudo bumps (75) that is closer to the other pseudo bump (75) and the rejection object (86) of the pair of rejection objects (86) of the other pseudo bump (75) that is closer to the one pseudo bump (75) overlap in the second direction (Y).

[0291] [Appendix 1-3] The semiconductor device (61) according to Appendix 1-1 or Appendix 1-2, wherein the terminal (26) includes a flat region (116) in which the rejection material (86) is not formed, between the rejection material (86) on one side and the rejection material (86) on the other side in the first direction (X) of each pseudo bump (75).

[0292] [Supplementary Note 1-4] A semiconductor device comprising: a substrate (2); a device region (6) provided on the substrate (2); terminals (26) covering the device region (6) in a plan view; and a plurality of pseudo-bumps (75) arranged on the terminals (26), the plurality of pseudo-bumps (75) being arranged in a honeycomb structure layout (88) including one central bump (73) and six peripheral bumps (74) densely arranged around the central bump (73) in a layout positioned at the vertices of a hexagon in a plan view; an exclusion member (86) being formed by a protrusion of a part of the terminal (26) from the bottom along the side of each of the plurality of pseudo-bumps (75); the exclusion member (86) of each pseudo-bump (75) being formed in pairs on both sides of each pseudo-bump (75) in the first direction (X) so as to have directionality along the first direction (X) in a plan view; The semiconductor device (61) has an arrangement in which the rejection (86) of the central bump (73) and the rejection (86) of two first peripheral bumps (741) of the plurality of peripheral bumps (74) that are adjacent to the central bump (73) in a second direction (Y) perpendicular to the first direction (X) are spaced apart from each other along the second direction (Y).

[0293] According to this configuration, the rejects (86) of the central bump (73) and the rejects (86) of the two first peripheral bumps (741) are arranged at intervals from each other along the second direction (Y). Therefore, although the multiple rejects (86) are each formed to have directionality in the first direction (X), it is possible to prevent the multiple rejects (86) from interfering with each other. As a result, the multiple pseudo-bumps (75) can be arranged in a dense honeycomb structure layout (88), and the number of pseudo-bumps (75) can be increased to improve heat dissipation.

[0294] [Appendix 1-5] When focusing on the central bump (73) and two second peripheral bumps (742) adjacent to the central bump (73) in an oblique direction that is inclined with respect to both the first direction (X) and the second direction (Y) in a plan view, the exclusion object (86) of the central bump (73) faces a spatial region (745) between the second peripheral bumps (742) in the first direction (X).

[0295] [Appendix 1-6] A semiconductor device (61) according to Appendix 1-5, wherein the rejects (86) of the first peripheral bump (741), the rejects (86) of the second peripheral bump (742), the rejects (86) of the central bump (73), the rejects (86) of the second peripheral bump (742), and the rejects (86) of the first peripheral bump (741) are arranged in that order along the second direction (Y).

[0296] [Supplementary Note 1-7] The semiconductor device (61) according to any one of Supplementary Note 1-4 to Supplementary Note 1-6, wherein the honeycomb structure layout (88) includes a plurality of triangular layouts (743) in which the central bump (73) and two adjacent peripheral bumps (74) among the plurality of peripheral bumps (74) are located at vertices of a triangle in a planar view, and in each of the triangular layouts (743), an equilateral triangle is formed by imaginary lines (744) connecting the vertices.

[0297] [Supplementary Note 1-8] A semiconductor device comprising: a substrate (2); a device region (6) provided on the substrate (2); terminals (26) covering the device region (6) in a plan view; and a plurality of pseudo bumps (75) arranged on the terminals (26), wherein an exclusion member (86) is formed by a protrusion of a part of the terminal (26) from the bottom along the side of each of the plurality of pseudo bumps (75), and the exclusion member (86) of each pseudo bump (75) is formed in pairs on both sides of each of the pseudo bumps (75) in the first direction (X) so as to have directionality along the first direction (X) in a plan view; and a first line bump group (120) and a second line bump group (121) each including the plurality of pseudo bumps (75) arranged along a second direction (Y) perpendicular to the first direction (X), The first line bump group (120) and the second line bump group (121) are arranged alternately in the first direction (X), and between the first line bump group (120) and the second line bump group (121), the rejects (86) of the pseudo bumps (75) of the first line bump group (120) and the rejects (86) of the pseudo bumps (75) of the second line bump group (121) are arranged alternately at intervals from each other along the second direction (Y).

[0298] According to this configuration, the rejects (86) of the pseudo bumps (75) of the first line bump group (120) and the rejects (86) of the pseudo bumps (75) of the second line bump group (121) are arranged at intervals from each other along the second direction (Y). Therefore, although the multiple rejects (86) are each formed to have directionality in the first direction (X), it is possible to prevent the multiple rejects (86) from interfering with each other. As a result, the multiple pseudo bumps (75) can be arranged in a dense line layout, and the number of pseudo bumps (75) can be increased to improve heat dissipation.

[0299] [Appendix 1-9] In a pair of the first line bump groups (120) adjacent to each other in the first direction (X) with the second line bump group (121) sandwiched therebetween, the rejection object (86) of the pseudo bump (75) of one of the first line bump groups (120) and the rejection object (86) of the pseudo bump (75) of the other first line bump group (120) face each other in a plan view via a space region (125) between the plurality of pseudo bumps (75) in the second line bump group (121).

[0300] [Appendix 1-10] The semiconductor device (61) according to any one of Appendices 1-1 to 1-9, wherein the terminals (26) and the plurality of pseudo bumps (75) are made of different materials.

[0301] [Appendix 1-11] The semiconductor device (61) according to appendix 1-10, wherein the material of the plurality of pseudo bumps (75) is harder than the material of the terminals (26).

[0302] [Appendix 1-12] The semiconductor device (61) according to appendix 1-11, wherein the plurality of pseudo bumps (75) are made of copper, and the terminals (26) are made of aluminum.

[0303] [Appendix 1-13] The semiconductor device (61) according to any one of Appendices 1-1 to 1-12, wherein the pitch (P1) of the plurality of pseudo bumps (75) is 50 μm or more and 250 μm or less.

[0304] [Appendix 1-14] The semiconductor device (61) according to any one of Appendices 1-1 to 1-13, further comprising a true bump (90) connected to a wire (91) and disposed on the terminal (26).

[0305] [Appendix 1-15] The semiconductor device (61) according to appendix 1-14, wherein the true bumps (90) are made of the same material as the plurality of pseudo bumps (75).

[0306] [Appendix 1-16] The semiconductor device (61) according to any one of Appendices 1-1 to 1-15, further comprising a plurality of trench structures (35) formed in the device region (6) in the substrate (2), and further comprising a transistor (11) including the plurality of trench structures (35).

[0307] [Supplementary Note 1-17] The semiconductor device (61) according to Supplementary Note 1-16, wherein the transistor (11) is a gate-divided transistor that includes a plurality of individually controlled system transistors and generates a single output signal by selectively controlling the plurality of system transistors.

[0308] [Supplementary Note 1-18] The semiconductor device (61) according to Supplementary Note 1-17, wherein the transistor (11) is configured so that an on-resistance thereof is changed by individual control of the plurality of system transistors.

[0309] [Appendix 1-19] The semiconductor device (61) according to any one of Appendices 1-1 to 1-18, wherein the rejection object (86) has a shape that is warped upward relative to the surface of the terminal (26).

[0310] [Appendix 1-20] The semiconductor device (61) according to Appendix 1-19, wherein the rejection object (86, 862) includes, in a cross-sectional view, a first inclined portion (866) extending from the underside of the pseudo bump (75) to a position above the flat region (113, 116) of the terminal (26), and a second inclined portion (868) folding back at a tip end (867) of the first inclined portion (866) and extending toward the underside of the pseudo bump (75), and the rejection object (86, 862) is spaced above the flat region (113, 116) of the terminal (26) and overlaps the flat region (113, 116).

[0311] According to this configuration, the exclusion members (86, 862) are curved upward so as to overlap the flat areas (113, 116) of the terminals (26). Even with this configuration, the space between adjacent pseudo bumps (75) can be used as an overlapping area for the exclusion members (86), thereby enabling effective use of space.

[0312] 1: Semiconductor chip 2: Substrate 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: Output area 6A: First area 6B: Second area 7: Current detection area 8: Control area 9: First temperature detection area 10: Second temperature detection area 11: Main transistor 12: System transistor 12A: First system transistor 12B: Second system transistor 13: Monitor transistor 14: System monitor transistor 14A: First system monitor transistor 14B: Second system monitor transistor 15: First temperature sensing diode 16: Second temperature sensing diode 17: Control circuit 18: Gate drive circuit 19: Active clamp circuit 19a: First diode stage 19b: Second diode stage 20: Overcurrent protection circuit 21: Overheat protection circuit 24: Interlayer insulating film 25: Drain terminal 26: Source terminal 26A: First terminal portion 26B: Second terminal portion 26a: Notch portion 27: First control terminal 28: Second control terminal 29: Third control terminal 30: Fourth control terminal 31: First semiconductor region 32: Second semiconductor region 33: Body region 35: Trench structure 36: Trench 37: First insulating film 38: Second insulating film 39: First electrode 40: Second electrode 41: Third insulating film 45: Trench connection structure 45a: First trench portion 45b: Second trench portion 46: Connection trench 47: Connection insulating film 48: Connection electrode 51: Source region 52: Contact region 53: Gate wiring 53A: First gate wiring 53B: Second gate wiring 54: First via electrode 55: Source wiring 55A: First source wiring 55B: Second source wiring 56: Second via electrode 57: Third via electrode 61: Semiconductor device 62: Package body 63: First surface 64: Second surface 65A: First side wall 65B: Second side wall 65C: Third side wall 65D: Fourth side wall 66: Metal plate 67: First plate surface 68: Second plate surface 69A: First plate side wall 69B: Second plate side wall 69C: Third plate side wall 69D: Fourth plate side wall70: Extension portion 70A: First extension portion 70B: Second extension portion 71A: First lead terminal 71B: Second lead terminal 71C: Third lead terminal 71D: Fourth lead terminal 71E: Fifth lead terminal 71F: Sixth lead terminal 71G: Seventh lead terminal 71H: Eighth lead terminal 72: Conductive bonding material 73: Center bump 74: Peripheral bump 75: Pseudo bump 76: Pseudo bump group 77: First bump main body 78: First bump metal film 79: First body portion 80: First neck portion 81: First upper end portion 82: Upper end apex portion 83: Upper end base portion 84: Inclined portion 85: Upper end protrusion portion 86: Rejected object 86A: Rejected object 86B: Rejected object 87: Base surface 88: Honeycomb structure layout 89: First bonding wire 90: True bump 91: Wire loop 92: Wire tail 93: Capillary 94: Inner hole 95: Wire 97: Second bump body 98: Second bump metal film 99: Second body portion 100: Second neck portion 101: Second upper end portion 111: First thin film portion 112: Second thin film portion 113: Thick film portion 114: First raised portion 115: Second raised portion 116: Flat region 119: Second bonding wire 120: First line bump group 121: Second line bump group 123 : First pseudo bump 124 : Second pseudo bump 125 : Spatial region 126 : Spatial region 200 : Semiconductor chip 741 : First peripheral bump 742 : Second peripheral bump 743 : Triangular layout 744 : Virtual line 745 : Spatial region 751 : Peripheral edge 752 : First peripheral edge 753 : Second peripheral edge 861 : First rejection object 862 : Second rejection object 863 : Top 864 : First inclined portion 865 : Second inclined portion 866 : First inclined portion 867 : Tip 868 : Second inclined portion 869 : Recess 870 : Recess 881 : First rejection object 882 : Second rejection object 883: Imaginary straight line 884: Imaginary straight line 891: First rejection object 892: Second rejection object 893: Imaginary straight line 894: Imaginary straight line D1: First depth D2: Second depth IT: Trench spacing P1: First pitch P2: Second pitch P3: Third pitchS1: First size S2: Second size SB1: First body size SB2: Second body size SN1: First neck size SN2: Second neck size T1: First thickness T2: Second thickness TB1: First body thickness TB2: Second body thickness TS1: First thickness TS2: Second thickness TT1: Thickness W1: First width W2: Second width X: First direction Y: Second direction Z: Normal direction

Claims

1. A substrate, a device region provided on the substrate, terminals that cover the device region in a plan view, and a plurality of pseudo bumps disposed on the terminals, wherein the plurality of pseudo bumps include at least three pseudo bumps densely arranged in a layout positioned at vertices of a triangle in a plan view, repellents are formed by bulges of a part of the terminals along sides from lower parts to side parts of each of the three pseudo bumps, a pair of the repellents of each pseudo bump are formed on both sides of one side and the other side of each pseudo bump in the first direction so as to have directivity along the first direction in a plan view, and the repellents of the three pseudo bumps are arranged at intervals from each other along a second direction orthogonal to the first direction. A semiconductor device.

2. When paying attention to two adjacent pseudo bumps inclined in an oblique direction inclined with respect to both the first direction and the second direction in a plan view, among the pair of repellents of one pseudo bump, the repellent on the side closer to the other pseudo bump and, among the pair of repellents of the other pseudo bump, the repellent on the side closer to the one pseudo bump overlap with each other in the second direction. The semiconductor device according to claim 1.

3. The terminal includes a flat region where no repellent is formed between the repellent on one side and the repellent on the other side of each pseudo bump in the first direction. The semiconductor device according to claim 1 or 2.

4. A substrate, a device region provided on the substrate, terminals that cover the device region in a plan view, and a plurality of pseudo bumps disposed on the terminals, wherein the plurality of pseudo bumps are arranged in a honeycomb structure layout including one central bump and six peripheral bumps densely arranged in a layout positioned at vertices of a hexagon around the central bump in a plan view, repellents are formed by bulges of a part of the terminals along sides from lower parts to side parts of each of the plurality of pseudo bumps, and a pair of the repellents of each pseudo bump are formed on both sides of one side and the other side of each pseudo bump in the first direction so as to have directivity along the first direction in a plan view. In the semiconductor device, the repellents of the central bump and the repellents of two first peripheral bumps adjacent to the central bump in a second direction orthogonal to the first direction among the plurality of peripheral bumps are arranged at intervals along the second direction.

5. When focusing on the central bump and two second peripheral bumps adjacent to the central bump in an oblique direction inclined with respect to both the first direction and the second direction in a plan view, the repellent of the central bump faces a space region between the second peripheral bumps in the first direction. The semiconductor device according to claim 4.

6. The semiconductor device according to claim 5, wherein along the second direction, the repellents of the first peripheral bumps, the repellents of the second peripheral bumps, the repellents of the central bump, the repellents of the second peripheral bumps, and the repellents of the first peripheral bumps are arranged in order.

7. The honeycomb structure layout includes a plurality of triangular layouts in which two adjacent peripheral bumps among the central bump and the plurality of peripheral bumps are located at the vertices of a triangle in a plan view. In each of the triangular layouts, an equilateral triangle is formed by a virtual line connecting the vertices. The semiconductor device according to any one of claims 4 to 6.

8. A substrate, A device region provided on the substrate, A terminal covering the device region in a plan view, And a plurality of pseudo bumps disposed on the terminal, Repellents are formed by a part of the terminal bulging along the side from the lower part of each of the plurality of pseudo bumps, The repellents of each of the pseudo bumps are formed in a pair on both sides of one side and the other side of each of the pseudo bumps in the first direction so as to have directivity along the first direction in a plan view. Including a first line bump group and a second line bump group including the plurality of pseudo bumps each arranged along a second direction orthogonal to the first direction, The first line bump group and the second line bump group are alternately arranged in the first direction, In the semiconductor device, between the first line bump group and the second line bump group, the repellents of the pseudo bumps of the first line bump group and the repellents of the pseudo bumps of the second line bump group are alternately arranged at intervals along the second direction.

9. In a pair of the first line bump groups adjacent to each other in the first direction with the second line bump group therebetween, the repellents of the pseudo bumps in one of the first line bump groups and the repellents of the pseudo bumps in the other first line bump group face each other in a plan view through a space region between the plurality of pseudo bumps in the second line bump group. The semiconductor device according to claim 8.

10. The semiconductor device according to claim 1, 4, or 8, wherein materials of the terminal and the plurality of pseudo bumps are different.

11. The semiconductor device according to claim 10, wherein the material of the plurality of pseudo bumps is harder than the material of the terminal.

12. The semiconductor device according to claim 11, wherein the plurality of pseudo bumps are made of copper and the terminal is made of aluminum.

13. The semiconductor device according to claim 1, 4, or 8, wherein a pitch of the plurality of pseudo bumps is 50 μm or more and 250 μm or less.

14. The semiconductor device according to claim 1, 4, or 8, further including true bumps disposed on the terminal in a state of being connected to wires.

15. The semiconductor device according to claim 14, wherein the true bumps are made of the same material as the plurality of pseudo bumps.