Semiconductor device

Abstract

This semiconductor device includes: a chip that has a main surface; a trench electrode-type gate structure that is formed on the main surface and has a resistive portion; a pad electrode that is disposed on the main surface so as to overlap with the resistive portion and has an electrical first connection with the resistive portion; and a wiring electrode that is disposed on the main surface so as to overlap with the resistive portion at a different position from the pad electrode, has an electrical second connection with the resistive portion, and is electrically connected to the pad electrode via the resistive portion.

Description

Semiconductor Devices

[0001] This application claims priority from Japanese Patent Application No. 2022-178810 filed with the Japan Patent Office on November 8, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2020 / 0294989A1) discloses a semiconductor device including a semiconductor substrate, a MOS gate, a p-type region, an interlayer insulating film, a gate polysilicon layer, a gate pad, and a contact electrode. The MOS gate includes multiple gate electrodes embedded in multiple trenches formed in the semiconductor substrate. The p-type region is formed in a surface layer of the semiconductor substrate at a distance from the MOS gate. An interlayer insulating film covers the MOS gate and the p-type region on the semiconductor substrate.

[0003] The gate polysilicon layer is provided as a gate resistor. The gate polysilicon layer is disposed on a portion of the interlayer insulating film covering the p-type region at a distance from the MOS gate and faces the p-type region across the interlayer insulating film. The gate pad is disposed on the gate polysilicon layer and electrically connected to the gate polysilicon layer. The contact electrode is disposed on the gate polysilicon layer at a distance from the gate pad and electrically connected to the gate polysilicon layer.

[0004] US Patent Application Publication No. 2020 / 0294989

[0005] SUMMARY The present disclosure provides a semiconductor device having a novel layout associated with a resistor.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface and having a resistor portion; a pad electrode arranged on the main surface so as to overlap the resistor portion and having a first electrical connection portion to the resistor portion; and a wiring electrode arranged on the main surface so as to overlap the resistor portion at a position different from the pad electrode, having a second electrical connection portion to the resistor portion and electrically connected to the pad electrode via the resistor portion.

[0007] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type first gate structure formed on the main surface and having a resistor portion; a trench electrode type second gate structure formed on the main surface at a distance from the first gate structure and not having the resistor portion; and a pad electrode arranged on the main surface so as to overlap the resistor portion of the first gate structure and the second gate structure, having an electrical connection portion to the resistor portion but not having an electrical connection portion to the second gate structure.

[0008] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type first gate structure formed on the main surface and having a resistor portion; a trench electrode type second gate structure formed on the main surface at a distance from the first gate structure and not having the resistor portion; and a pad electrode overlapping the resistor portion of the first gate structure and disposed on the main surface so as not to overlap the second gate structure, having an electrical connection portion to the resistor portion but not having an electrical connection portion to the second gate structure.

[0009] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type first gate structure formed on the main surface and having a resistor portion; a trench electrode type second gate structure formed on the main surface at a distance from the first gate structure and not having the resistor portion; a trench electrode type third gate structure formed on the main surface at a distance from the first gate structure and the second gate structure and not having the resistor portion; and a pad electrode overlapping the resistor portion of the first gate structure and the second gate structure but arranged on the main surface so as not to overlap the third gate structure, having an electrical connection portion to the resistor portion but not having electrical connection portions to the second gate structure and the third gate structure.

[0010] The present disclosure provides a semiconductor device including a chip having a main surface, a first surface portion located inside the main surface, a second surface portion recessed in the thickness direction outside the first surface portion, and a mesa portion defined on the main surface by a connection surface portion connecting the first surface portion and the second surface portion, and a trench electrode type gate structure formed on the first surface portion and having a resistor portion.

[0011] The present disclosure provides a semiconductor device including: a chip having a main surface; a plurality of trench electrode type gate structures formed on the main surface; an interlayer film covering the plurality of gate structures on the main surface; a pad electrode arranged on the interlayer film so as to overlap at least one of the gate structures and electrically connected to at least one of the gate structures through the interlayer film; and a wiring electrode arranged on the interlayer film at a distance from the pad electrode, electrically connected to at least one of the gate structures through the interlayer film, and electrically connected to the pad electrode via a portion of at least one of the gate structures.

[0012] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface and having a resistor portion; and a trench electrode type source structure formed on the main surface adjacent to the gate structure.

[0013] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed in a strip shape extending in a first direction on the main surface and having a resistor portion; and a trench electrode type electrode structure formed on the main surface at a distance from the gate structure in the first direction and applied with a potential different from that of the gate structure.

[0014] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface and having a resistor portion; a trench electrode type first electrode structure formed on the main surface and spaced apart in one direction from the gate structure and having a potential different from that of the gate structure; and a trench electrode type second electrode structure formed on the main surface and spaced apart in an orthogonal direction perpendicular to the one direction from the gate structure and having a potential different from that of the gate structure.

[0015] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface and having a resistive portion in part; a pad electrode arranged on the main surface so as to overlap the resistive portion and having an electrical connection portion to the resistive portion; and a pad insulating film covering the connection portion of the pad electrode and having a pad opening that exposes an area of ​​the pad electrode outside the connection portion.

[0016] The present disclosure provides a semiconductor device including a gate pad, a gate wiring physically separated from the gate pad, and a gate resistor having a parallel resistance circuit including a plurality of resistance elements and electrically interposed between the gate pad and the gate wiring.

[0017] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0018] FIG. 1 is a plan view showing a semiconductor device according to a specific embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of the first main surface. FIG. 4 is an enlarged plan view showing an example layout of the active region. FIG. 5 is an enlarged plan view showing an example layout of the first side end region. FIG. 6 is an enlarged plan view showing an example layout of the first termination region. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 5 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 5 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5 . FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 6 . FIG. 14 is a cross-sectional view showing the structure of the peripheral region. FIG. 15 is a plan view showing a pad region. FIG. 16 is a plan view showing an example layout of a gate electrode and a source electrode. FIG. 17 is an enlarged plan view showing a main portion of FIG. 16 together with a gate structure. FIG. 18 is an enlarged plan view showing a layout example of region XVIII shown in FIG. 17. FIG. 19 is an enlarged plan view showing a first gate structure according to the first layout example. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 19. FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 19. FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 19. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. 19. FIG. 24 is a circuit diagram showing the electrical configuration of a gate resistor. FIG. 25 is an enlarged plan view showing a first gate structure according to the second layout example. FIG. 26 is an enlarged plan view showing a first gate structure according to the third layout example. FIG. 27 is a cross-sectional view showing another example of a chip. FIG. 28 is a cross-sectional view showing another example of a chip.

[0019] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0020] When the term "substantially equal" is used in a description in which a comparison target is present, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0021] In the following description, the conductivity type of a semiconductor region (impurity region) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." The "p-type" is a conductivity type resulting from a trivalent element, and the "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0022] FIG. 1 is a plan view showing a semiconductor device 1 according to a specific embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface 3. The semiconductor device 1 is a semiconductor switching device including an insulated gate transistor structure. The transistor structure may be referred to as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure.

[0023] 1 to 3, in this embodiment, a semiconductor device 1 includes a chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In other words, the semiconductor device 1 is a "wide bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like. A wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).

[0024] In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device." The semiconductor device 1 may also be referred to as a "SiC-MISFET." The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.

[0025] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.

[0026] In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be more than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0027] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0028] Hereinafter, the third side surface 5C side in the first direction X may be referred to as one side of the first direction X, and the fourth side surface 5D side in the first direction X may be referred to as the other side of the first direction X. Furthermore, the first side surface 5A side in the second direction Y may be referred to as one side of the second direction Y, and the second side surface 5B side in the second direction Y may be referred to as the other side of the second direction Y.

[0029] The chip 2 may have a thickness of 5 μm or more and 200 μm or less. The thickness of the chip 2 may be set to a value belonging to any one of the following ranges: 5 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less. The thickness of the chip 2 is preferably 100 μm or less.

[0030] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may be set to a value belonging to any one of the ranges of 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D are preferably 5 mm or more.

[0031] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2. A drain potential as a high potential (first potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "drain region," a "drift region," or the like. The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0032] In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer). The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 3 μm or more and 30 μm or less. The thickness of the first semiconductor region 6 is particularly preferably 5 μm or more and 25 μm or less.

[0033] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as a "drain region." The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 within the chip 2. The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0034] In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 may have a thickness of 1 μm or more and 200 μm or less. The thickness of the second semiconductor region 7 may be 150 μm or less, 100 μm or less, 50 μm or less, or 40 μm or less. The thickness of the second semiconductor region 7 may be 5 μm or more. The thickness of the second semiconductor region 7 is preferably 10 μm or more. In this embodiment, the thickness of the second semiconductor region 7 is greater than the thickness of the first semiconductor region 6.

[0035] The semiconductor device 1 includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A to 10D formed on the first main surface 3. The active surface 8, outer surface 9, and first to fourth connecting surfaces 10A to 10D define an active plateau 11 on the first main surface 3.

[0036] The active surface 8 may be referred to as the “first surface portion,” the outer peripheral surface 9 may be referred to as the “second surface portion,” the first to fourth connecting surfaces 10A to 10D may be referred to as “connecting surface portions,” and the active plateau 11 may be referred to as the “mesa portion.” The active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D (i.e., the active plateau 11) may be considered to be components of the chip 2 (first main surface 3).

[0037] The active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 8 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 8 is formed by the c-plane (Si-plane). In this embodiment, the active surface 8 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0038] The outer peripheral surface 9 is located outside the active surface 8 and is recessed in the thickness direction of the chip 2 (toward the second main surface 4) relative to the active surface 8. Specifically, the outer peripheral surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6. The outer peripheral surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8.

[0039] The outer peripheral surface 9 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 8. In this embodiment, the outer peripheral surface 9 is formed by the c-plane (Si-plane). The outer peripheral surface 9 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 9 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 5 μm or less. The circumferential depth DO is preferably 2.5 μm or less.

[0040] The first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer peripheral surface 9. The first connection surface 10A is located on the first side surface 5A side, the second connection surface 10B is located on the second side surface 5B side, the third connection surface 10C is located on the third side surface 5C side, and the fourth connection surface 10D is located on the fourth side surface 5D side. The first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y. The third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.

[0041] The first to fourth connection surfaces 10A to 10D may extend substantially perpendicularly between the active surface 8 and the outer peripheral surface 9 so as to define a quadrangular pillar-shaped active plateau 11. The first to fourth connection surfaces 10A to 10D may be inclined obliquely downward from the active surface 8 toward the outer peripheral surface 9 so as to define a quadrangular pyramid-shaped active plateau 11. In this way, the active plateau 11 is defined in a protruding shape in the first semiconductor region 6 on the first main surface 3. The active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.

[0042] 3, semiconductor device 1 includes, on first main surface 3, active region 12, first side end region 13, second side end region 14, first termination region 15, second termination region 16, and outer periphery region 17. Active region 12 is a region where the output current (drain current) of the transistor is generated. Active region 12 is provided in an inner portion of active surface 8 and spaced apart from the periphery of active surface 8 (first to fourth connection surfaces 10A to 10D). In this embodiment, active region 12 is provided in a quadrangular shape having four sides parallel to first to fourth side surfaces 5A to 5D in a plan view.

[0043] The proportion of the active region 12 in the active surface 8 is preferably 50% or more and 95% or less. The proportion of the active region 12 may be a value belonging to any one of the ranges of 50% or more and 60% or more, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and 95% or less. The proportion of the active region 12 is preferably 70% or more.

[0044] The first side end region 13 is provided as a non-active region on one side (the third connection surface 10C side) in the first direction X with respect to the active region 12 on the active surface 8. The first side end region 13 is provided in a strip shape extending in the second direction Y in a plan view.

[0045] The second side end region 14 is provided as a non-active region on the active surface 8 on the other side in the first direction X (toward the fourth connection surface 10D) of the active region 12, and faces the first side end region 13 across the active region 12 in the first direction X. The second side end region 14 is provided in a strip shape extending in the second direction Y in a plan view.

[0046] The first termination region 15 is provided as an inactive region on one side in the second direction Y (the first connection surface 10A side) of the active region 12. In this embodiment, the first termination region 15 is provided in a strip shape extending in the first direction X in a plan view, and faces the active region 12, the first side end region 13, and the second side end region 14 in the second direction Y.

[0047] The second termination region 16 is provided as an inactive region on the other side in the second direction Y (the second connection surface 10B side) of the active region 12. In this embodiment, the second termination region 16 is provided in a strip shape extending in the first direction X in a plan view, and faces the active region 12, the first side end region 13, and the second side end region 14 in the second direction Y.

[0048] The outer peripheral region 17 is provided on the outer peripheral surface 9 as a non-active region. In this embodiment, the outer peripheral region 17 is provided in a ring shape (specifically, a rectangular ring shape) surrounding the active surface 8 (active plateau 11) in a plan view. That is, the outer peripheral region 17 surrounds the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in a plan view.

[0049] 4 is an enlarged plan view showing an example layout of the active region 12. FIG. 5 is an enlarged plan view showing an example layout of the first side end region 13. FIG. 6 is an enlarged plan view showing an example layout of the first termination region 15. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4.

[0050] Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 5. Fig. 10 is a cross-sectional view taken along line XX in Fig. 5. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 5. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 5. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 6. Fig. 14 is a cross-sectional view showing the structure of the outer peripheral region 17.

[0051] 4 to 14 mainly show the layout on the third connecting surface 10C side (third side surface 5C side). Because the layout on the fourth connecting surface 10D side (fourth side surface 5D side) is substantially the same as the layout on the third side surface 5C side, the third connecting surface 10C side will be mainly described below. The layout on the fourth connecting surface 10D side can be obtained by replacing "first side end region 13" with "second side end region 14" and "third connecting surface 10C" with "fourth connecting surface 10D" in the following description.

[0052] 4 to 14 , semiconductor device 1 includes p-type body region 18 (first impurity region) formed in a surface layer portion of first main surface 3 (active surface 8). Body region 18 is formed at an interval from the bottom of first semiconductor region 6 toward active surface 8. Body region 18 is formed in a layer shape extending along active surface 8. Body region 18 is preferably formed over the entire active surface 8 and exposed from first to fourth connecting surfaces 10A to 10D.

[0053] The semiconductor device 1 includes an n-type source region 19 (second impurity region) formed in a surface layer portion of the body region 18 in the active region 12. The source region 19 is formed at a distance from the bottom of the body region 18 toward the active surface 8. In other words, the source region 19 is formed in a region on the active surface 8 side of the body region 18. The source region 19 has a higher n-type impurity concentration than the first semiconductor region 6. The source region 19 forms a transistor channel together with the first semiconductor region 6 in the body region 18.

[0054] In this embodiment, the source region 19 is not formed in the first side end region 13, the second side end region 14, the first termination region 15, or the second termination region 16. Of course, the source region 19 may be formed in at least one of the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16, as long as the source region 19 does not affect the electrical characteristics of the channel. Alternatively, the source region 19 may be formed over the entire active surface 8.

[0055] The semiconductor device 1 includes a plurality of trench electrode type gate structures 20 formed on the first main surface 3 (active surface 8). The gate structures 20 may also be referred to as "trench gate structures." A gate potential is applied to the gate structures 20 as a control potential. The plurality of gate structures 20 control inversion and non-inversion of a channel in the body region 18 in response to the gate potential.

[0056] The plurality of gate structures 20 are arranged in the active region 12 at intervals inward from the periphery (first to fourth connection surfaces 10A to 10D) of the active surface 8, and define the active region 12 in an inner portion of the active surface 8. The plurality of gate structures 20 are each formed in a strip shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y. The plurality of gate structures 20 penetrate the body region 18 and the source region 19 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0057] Each gate structure 20 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z. The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 2 μm or less. The first depth D1 is less than the aforementioned peripheral depth DO. The first depth D1 may be 0.1 μm or more and 3 μm or less. The first depth D1 is preferably 0.5 μm or more and 1.5 μm or less.

[0058] Each gate structure 20 includes a first trench 21, a first insulating film 22, and a first buried electrode 23. The first trench 21 is formed in the active surface 8 and defines a wall surface of the gate structure 20. The first insulating film 22 covers the wall surface of the first trench 21. The first insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0059] In this embodiment, the first insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 22 includes a silicon oxide film made of an oxide of the chip 2. The first buried electrode 23 is embedded in the first trench 21 across the first insulating film 22 and faces the channel across the first insulating film 22. The first buried electrode 23 may include p-type or n-type conductive polysilicon.

[0060] The semiconductor device 1 includes a plurality of trench electrode type source structures 25 formed on the first main surface 3 (active surface 8) in the active region 12. A source potential as a low potential (a second potential lower than the drain potential) is applied to the plurality of source structures 25. The source structures 25 may also be referred to as "trench source structures," "first source structures," "first trench source structures," or the like.

[0061] The source structures 25 are formed on the active surface 8 in the active region 12 so as to be adjacent to the gate structures 20 in the second direction Y. Specifically, the source structures 25 are disposed in regions between pairs of adjacent gate structures 20, respectively, and face the gate structures 20 in the second direction Y. In other words, the source structures 25 and the gate structures 20 are arranged alternately in the second direction Y.

[0062] The plurality of source structures 25 are each formed in a strip shape extending in the first direction X in a plan view. In this embodiment, the plurality of source structures 25 are drawn out from the active region 12 to at least one of the first side end region 13 and the second side end region 14 (in this embodiment, both). The plurality of source structures 25 face the gate structure 20 in the second direction Y in the active region 12, but do not face the gate structure 20 in the second direction Y in the first side end region 13 (second side end region 14).

[0063] The plurality of source structures 25 penetrate at least one (both in this embodiment) of the third connection surface 10C and the fourth connection surface 10D and are exposed from at least one (both in this embodiment) of the third connection surface 10C and the fourth connection surface 10D. The plurality of source structures 25 penetrate the body region 18 and the source region 19 to reach the first semiconductor region 6 in the active region 12, and penetrate the body region 18 to reach the first semiconductor region 6 in the first side end region 13 (second side end region 14). The plurality of source structures 25 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0064] Each source structure 25 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. The second width W2 may be approximately equal to the aforementioned first width W1. The second width W2 may be equal to or greater than the first width W1. The second width W2 may be greater than the first width W1. The second width W2 may be equal to or greater than 0.1 μm and equal to or less than 3 μm. Preferably, the second width W2 is equal to or greater than 0.5 μm and equal to or less than 2 μm.

[0065] The second depth D2 is equal to or greater than the first depth D1 described above. In this embodiment, the second depth D2 is greater than the first depth D1. The second depth D2 is preferably 1.5 to 3 times the first depth D1. In this embodiment, the second depth D2 is approximately equal to the outer circumferential depth DO described above. The second depth D2 may be 0.1 μm to 5 μm. It is particularly preferable that the second depth D2 be 2.5 μm or less.

[0066] Each source structure 25 is disposed at a first interval I1 from the gate structure 20 in the second direction Y. The first interval I1 is preferably 0.5 to 2 times the first width W1 (second width W2). It is particularly preferable that the first interval I1 be less than the first width W1 (second width W2). The first interval I1 may be 0.1 μm to 2.5 μm. The first interval I1 is preferably 0.5 μm to 1.5 μm.

[0067] Each source structure 25 includes a second trench 26, a second insulating film 27, and a second buried electrode 28. The second trench 26 is formed in the active surface 8 and defines a wall surface of the source structure 25. In this embodiment, the sidewall of the second trench 26 communicates with the third connection surface 10C and the fourth connection surface 10D. The bottom wall of the second trench 26 communicates with the outer peripheral surface 9.

[0068] The second insulating film 27 covers the wall surface of the second trench 26. The second insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 27 includes a silicon oxide film made of an oxide of the chip 2. The second buried electrode 28 is buried in the second trench 26 with the second insulating film 27 sandwiched therebetween. The second buried electrode 28 may include p-type or n-type conductive polysilicon.

[0069] The semiconductor device 1 includes a plurality of trench electrode-type edge structures 30 formed on the first main surface 3 (active surface 8) in the first edge region 13. A source potential is applied to the plurality of edge structures 30. The edge structures 30 may also be referred to as "trench edge structures," "second source structures," "second trench source structures," or the like. The plurality of edge structures 30 are also formed in the second edge region 14. The configuration on the second edge region 14 side is similar to the configuration on the first edge region 13 side. The description of the first edge region 13 side applies to the description of the second edge region 14 side.

[0070] The side edge structures 30 are respectively arranged in the first side edge region 13 on the periphery of the active surface 8 (third connection surface 10C) and in regions between the multiple gate structures 20. The multiple side edge structures 30 face the multiple gate structures 20 in a one-to-one correspondence in the first direction X. The multiple side edge structures 30 are respectively arranged in regions between pairs of source structures 25 adjacent to each other in the second direction Y, and face the multiple source structures 25 in the second direction Y. The multiple side edge structures 30 are arranged alternately with the multiple source structures 25 in the second direction Y. The multiple side edge structures 30 are each formed in a strip shape extending in the first direction X in a plan view.

[0071] In this embodiment, the multiple side edge structures 30 on the first side edge region 13 side penetrate through the third connecting surface 10C and are exposed from the third connecting surface 10C. The multiple side edge structures 30 on the second side edge region 14 side penetrate through the fourth connecting surface 10D and are exposed from the fourth connecting surface 10D. The multiple side edge structures 30 penetrate through the body region 18 to reach the first semiconductor region 6 and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0072] Each side edge structure 30, like the source structure 25, has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. Each side edge structure 30 is spaced a second distance I2 from the gate structure 20 in the first direction X and a third distance I3 from the source structure 25 in the second direction Y.

[0073] The second interval I2 is preferably 0.5 to 2 times the first width W1 (second width W2). The second interval I2 is preferably 0.5 to 2 times the first interval I1. It is particularly preferable that the second interval I2 be 1.5 times or less the first interval I1. The second interval I2 may be approximately equal to the first interval I1. The second interval I2 may be 0.1 μm to 2.5 μm. The second interval I2 is preferably 0.5 μm to 1.5 μm.

[0074] The third interval I3 is preferably 0.5 to 2 times the first width W1 (second width W2). The third interval I3 may be less than the first width W1 (second width W2). The third interval I3 is preferably approximately equal to the first interval I1. The third interval I3 may be 0.1 μm to 2.5 μm. The third interval I3 is preferably 0.5 μm to 1.5 μm.

[0075] Each side edge structure 30 includes a third trench 31, a third insulating film 32, and a third buried electrode 33. The third trench 31 is formed in the active surface 8 and defines the wall surface of the side edge structure 30. The side wall of the third trench 31 communicates with the third connection surface 10C. The bottom wall of the third trench 31 communicates with the outer peripheral surface 9.

[0076] The third insulating film 32 covers the wall surface of the third trench 31. The third insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the third insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 32 includes a silicon oxide film made of an oxide of the chip 2. The third buried electrode 33 is buried in the third trench 31 with the third insulating film 32 sandwiched therebetween. The third buried electrode 33 may include p-type or n-type conductive polysilicon.

[0077] The semiconductor device 1 includes a plurality of trench electrode type termination structures 35 formed on the first main surface 3 (active surface 8) in the first termination region 15. A source potential is applied to the plurality of termination structures 35. The termination structures 35 may also be referred to as "trench termination structures," "third source structures," "third trench source structures," etc. The plurality of termination structures 35 are also formed in the second termination region 16. The configuration on the second termination region 16 side is similar to the configuration on the first termination region 15 side. The description on the first termination region 15 side applies to the description on the second termination region 16 side.

[0078] The multiple termination structures 35 are each formed in a strip shape extending in the first direction X and are arranged at intervals in the second direction Y. The multiple termination structures 35 are arranged continuously at equal intervals in the second direction Y so as to face each other with a part of the chip 2 in between. In other words, the multiple termination structures 35 face each other without the gate structure 20 in between.

[0079] The plurality of termination structures 35 face the plurality of gate structures 20 and the plurality of source structures 25 in the second direction Y. The plurality of termination structures 35 penetrate at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment) and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment).

[0080] That is, the plurality of termination structures 35 face the plurality of gate structures 20, the plurality of source structures 25, and the plurality of side edge structures 30 in the second direction Y. The plurality of termination structures 35 penetrate the body region 18 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0081] Each termination structure 35, like the source structures 25, has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. When the termination of the active region 12 is formed by the gate structure 20, the termination structure 35 is disposed at the first distance I1 described above from the gate structure 20. When the termination of the active region 12 is formed by the source structure 25, the termination structure 35 is disposed at the first distance I1 described above from the source structure 25.

[0082] Each termination structure 35 includes a fourth trench 36, a fourth insulating film 37, and a fourth buried electrode 38. The fourth trench 36 is formed in the active surface 8 and defines a wall surface of the termination structure 35. The sidewall of the fourth trench 36 communicates with the third connection surface 10C. The bottom wall of the fourth trench 36 communicates with the outer peripheral surface 9.

[0083] The fourth insulating film 37 covers the wall surface of the fourth trench 36. The fourth insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the fourth insulating film 37 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fourth insulating film 37 includes a silicon oxide film made of an oxide of the chip 2. The fourth buried electrode 38 is buried in the fourth trench 36 with the fourth insulating film 37 sandwiched therebetween. The fourth buried electrode 38 may include p-type or n-type conductive polysilicon.

[0084] The semiconductor device 1 includes a plurality of p-type first well regions 41 formed in regions along the plurality of gate structures 20 in the surface layer portion of the active surface 8 of the active region 12. In this embodiment, the first well regions 41 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 18. Of course, the p-type impurity concentration of the first well regions 41 may be lower than the p-type impurity concentration of the body region 18.

[0085] The multiple first well regions 41 cover the wall surfaces of the corresponding gate structures 20 at intervals from the adjacent source structures 25, and are electrically connected to the body region 18 in the surface layer portion of the active surface 8. The multiple first well regions 41 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between. The multiple first well regions 41 form pn junctions with the first semiconductor region 6.

[0086] The semiconductor device 1 includes a plurality of p-type second well regions 42 formed in regions along the plurality of source structures 25 in the surface layer portion of the active surface 8 of the active region 12. In this embodiment, the second well regions 42 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 18. Of course, the p-type impurity concentration of the second well regions 42 may be lower than the p-type impurity concentration of the body region 18. It is preferable that the p-type impurity concentration of the second well regions 42 is approximately equal to the p-type impurity concentration of the first well region 41.

[0087] The second well regions 42 cover the wall surfaces of the corresponding source structures 25 at intervals from the adjacent gate structures 20, and are electrically connected to the body region 18 in the surface portion of the active surface 8. The second well regions 42 cover the wall surfaces of the corresponding source structures 25 in the active region 12, the first side end region 13, and the second side end region 14, and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment).

[0088] The second well regions 42 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the second well regions 42 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the first well regions 41. The second well regions 42 form pn junctions with the first semiconductor region 6.

[0089] The semiconductor device 1 includes a plurality of p-type third well regions 43 formed in a region along the plurality of side edge structures 30 in a surface layer portion of the active surface 8 of the first side edge region 13 (second side edge region 14). In this embodiment, the third well regions 43 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 18. Of course, the p-type impurity concentration of the third well regions 43 may be lower than the p-type impurity concentration of the body region 18. It is preferable that the p-type impurity concentration of the third well regions 43 is approximately equal to the p-type impurity concentration of the first well region 41 (second well region 42).

[0090] The plurality of third well regions 43 cover the wall surfaces of the corresponding side edge structures 30 at intervals from the adjacent gate structures 20 and source structures 25, and are electrically connected to the body region 18 in the surface portion of the active surface 8. Of course, the third well regions 43 may be integrated with the first well region 41 in the region between the gate structures 20 and the side edge structures 30. The plurality of third well regions 43 are exposed from the third connection surface 10C (fourth connection surface 10D).

[0091] The plurality of third well regions 43 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the plurality of third well regions 43 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the plurality of first well regions 41. The bottoms of the plurality of third well regions 43 are formed at approximately the same depth as the bottoms of the plurality of second well regions 42. The plurality of third well regions 43 form pn junctions with the first semiconductor region 6.

[0092] The semiconductor device 1 includes at least one (in this embodiment, multiple) p-type fourth well region 44 formed in a region along the multiple termination structures 35 in the first termination region 15 (second termination region 16). In this embodiment, the fourth well region 44 has a higher p-type impurity concentration than the body region 18. Of course, the p-type impurity concentration of the fourth well region 44 may be lower than that of the body region 18. It is preferable that the p-type impurity concentration of the fourth well region 44 is approximately equal to the p-type impurity concentration of the first well region 41 (second well region 42).

[0093] The plurality of fourth well regions 44 cover the wall surfaces of the corresponding termination structures 35 at intervals from the adjacent termination structures 35, and are electrically connected to the body region 18 in the surface portion of the active surface 8. The plurality of fourth well regions 44 extend in a strip shape along the corresponding termination structures 35 in a plan view, and are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D (both in this embodiment).

[0094] The multiple fourth well regions 44 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the multiple fourth well regions 44 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the multiple first well regions 41. The bottoms of the multiple fourth well regions 44 are preferably formed at approximately the same depth as the bottoms of the multiple second well regions 42. The multiple fourth well regions 44 form pn junctions with the first semiconductor region 6.

[0095] The semiconductor device 1 includes a plurality of p-type contact regions 45 formed in regions along the plurality of source structures 25 in a surface layer portion of the active surface 8 of the active region 12. The contact regions 45 may also be referred to as "back gate regions." The contact regions 45 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 18. The p-type impurity concentration of the contact regions 45 is higher than the p-type impurity concentration of the second well region 42.

[0096] The plurality of contact regions 45 cover the wall surfaces of the corresponding source structures 25 in the corresponding second well regions 42. The plurality of contact regions 45 are formed in a one-to-many correspondence with each source structure 25. The plurality of contact regions 45 are formed at intervals along the corresponding source structures 25.

[0097] The plurality of contact regions 45 extend from within the corresponding second well region 42 to the surface portion of the body region 18 along the wall surface of the corresponding source structure 25 and are exposed from the active surface 8. The plurality of contact regions 45 are formed in the active region 12, but are not formed in the first side end region 13, the second side end region 14, the first termination region 15, or the second termination region 16. In other words, the contact regions 45 are not formed in the third well region 43 or the fourth well region 44. Furthermore, the plurality of contact regions 45 face the gate structure 20 in the second direction Y, but do not face the side end structure 30 in the second direction Y.

[0098] In this embodiment, the plurality of contact regions 45 are each formed in a strip shape extending in the first direction X in a plan view. The length of each of the plurality of contact regions 45 in the first direction X is preferably equal to or greater than the second width W2. The length of each of the plurality of contact regions 45 is preferably greater than the distance between two adjacent contact regions 45 in the first direction X.

[0099] The plurality of contact regions 45 along one source structure 25 face the plurality of contact regions 45 along another source structure 25 in the second direction Y. That is, in this embodiment, the plurality of contact regions 45 are arranged in a matrix form at intervals in the first direction X and the second direction Y as a whole in a plan view.

[0100] The plurality of contact regions 45 along one source structure 25 may be arranged offset in the first direction X so as to face the regions between the plurality of contact regions 45 along another source structure 25 in the second direction Y. In other words, the plurality of contact regions 45 may be arranged in a staggered pattern as a whole in a plan view with intervals in the first direction X and the second direction Y.

[0101] 14 , the semiconductor device 1 includes a p-type outer well region 46 formed in a surface layer portion of the outer peripheral surface 9. The outer well region 46 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 45. In this embodiment, the p-type impurity concentration of the outer well region 46 is higher than the p-type impurity concentration of the body region 18. Of course, the p-type impurity concentration of the outer well region 46 may be lower than that of the body region 18. It is preferable that the outer well region 46 has a p-type impurity concentration approximately equal to that of the first well region 41 (second well region 42).

[0102] The outer well region 46 is formed at a distance from the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8 in plan view, and extends in a band shape along the active surface 8. In this embodiment, the outer well region 46 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in plan view.

[0103] The outer well region 46 extends from the surface layer portion of the outer peripheral surface 9 toward the surface layer portions of the first to fourth connection surfaces 10A to 10D, and covers the first to fourth connection surfaces 10A to 10D. The outer well region 46 is electrically connected to the body region 18 at the surface layer portion of the active surface 8. The outer well region 46 is connected to the second well region 42, the third well region 43, and the fourth well region 44 at the third connection surface 10C (fourth connection surface 10D).

[0104] The outer well region 46 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The bottom of the outer well region 46 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the gate structure 20.

[0105] Specifically, the bottom of the outer well region 46 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the source structure 25. The bottom of the outer well region 46 is located closer to the bottom of the first semiconductor region 6 than the bottom of the contact region 45. The bottom of the outer well region 46 is preferably formed at a depth position substantially equal to the bottom of the second well region 42. The outer well region 46 forms a pn junction with the first semiconductor region 6.

[0106] The semiconductor device 1 includes a p-type outer contact region 47 formed in a surface layer portion of the outer peripheral surface 9. The outer contact region 47 has a higher p-type impurity concentration than the body region 18. The p-type impurity concentration of the outer contact region 47 is higher than the outer well region 46. It is preferable that the p-type impurity concentration of the outer contact region 47 is approximately equal to the p-type impurity concentration of the contact region 45.

[0107] The outer contact region 47 is formed in the surface layer portion of the outer well region 46 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) in plan view, and is formed in a band shape extending along the active surface 8. In this embodiment, the outer contact region 47 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 8 in plan view.

[0108] The outer contact region 47 is formed at a distance from the bottom of the outer well region 46 toward the outer peripheral surface 9, and faces the first semiconductor region 6 across a part of the outer well region 46. The outer contact region 47 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the source structure 25. The bottom of the outer contact region 47 is preferably formed at a depth position substantially equal to the bottom of the contact region 45.

[0109] Semiconductor device 1 includes at least one (preferably two to twenty) p-type field region 48 formed in the surface layer of outer peripheral surface 9. In this embodiment, semiconductor device 1 includes four field regions 48. The multiple field regions 48 are formed in an electrically floating state and relieve the electric field within chip 2 at outer peripheral surface 9.

[0110] The number, width, depth, p-type impurity concentration, etc. of the field regions 48 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The field regions 48 may have a lower p-type impurity concentration than the outer contact region 47. The field regions 48 may have a higher p-type impurity concentration than the outer well region 46. The field regions 48 may have a lower p-type impurity concentration than the outer well region 46.

[0111] The plurality of field regions 48 are formed in a region between the periphery of the outer peripheral surface 9 and the outer well region 46. The plurality of field regions 48 are arranged at intervals from the outer well region 46 side toward the periphery of the outer peripheral surface 9. The plurality of field regions 48 are formed in a band shape extending along the active surface 8 in a plan view. In this embodiment, the plurality of field regions 48 are formed in a ring shape (specifically, a square ring) surrounding the active surface 8 in a plan view.

[0112] The plurality of field regions 48 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of field regions 48 are located closer to the bottom of the first semiconductor region 6 than the bottom wall of the source structure 25. The bottoms of the plurality of field regions 48 are located closer to the bottom of the first semiconductor region 6 than the bottom of the contact region 45. The bottoms of the plurality of field regions 48 may be formed at a depth position substantially equal to the bottom of the second well region 42.

[0113] The semiconductor device 1 includes a main surface insulating film 50 covering the first main surface 3. The main surface insulating film 50 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 50 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 50 include a silicon oxide film made of an oxide of the chip 2.

[0114] The main surface insulating film 50 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D. The main surface insulating film 50 is connected to the first insulating film 22, the second insulating film 27, the third insulating film 32, and the fourth insulating film 37 on the active surface 8, and exposes the first buried electrode 23, the second buried electrode 28, the third buried electrode 33, and the fourth buried electrode 38.

[0115] The main surface insulating film 50 covers the outer well region 46, the outer contact region 47, and the plurality of field regions 48 on the outer peripheral surface 9. In this embodiment, the main surface insulating film 50 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the main surface insulating film 50 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.

[0116] The main surface insulating film 50 is connected to the second insulating film 27, the third insulating film 32 and the fourth insulating film 37 at the first to fourth connecting surfaces 10A to 10D, and exposes the second buried electrode 28, the third buried electrode 33 and the fourth buried electrode 38.

[0117] The semiconductor device 1 includes a sidewall wiring 51 formed on the outer peripheral surface 9 so as to cover at least one of the first to fourth connecting surfaces 10A to 10D. Specifically, the sidewall wiring 51 is disposed on the main surface insulating film 50. The sidewall wiring 51 also functions as a "sidewall structure" that reduces the step formed between the active surface 8 and the outer peripheral surface 9.

[0118] The sidewall wiring 51 is preferably formed in a strip shape extending along at least one of the third connecting surface 10C and the fourth connecting surface 10D. In this embodiment, the sidewall wiring 51 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D so as to surround the active surface 8 in a plan view. The portions of the sidewall wiring 51 that cover the four corners of the active surface 8 are formed in a curved shape toward the outer peripheral surface 9.

[0119] The sidewall wiring 51 includes a portion extending in a film-like manner along the outer peripheral surface 9 and a portion extending in a film-like manner along the first to fourth connecting surfaces 10A to 10D. The portion of the sidewall wiring 51 located on the outer peripheral surface 9 may cover the outer peripheral surface 9 in a film-like manner in a region on the outer peripheral surface 9 side of the active surface 8. In other words, the portion of the sidewall wiring 51 located on the outer peripheral surface 9 may have a thickness less than the thickness of the active plateau 11 (peripheral depth DO).

[0120] The sidewall wiring 51 faces the outer well region 46 at the outer peripheral surface 9, with the main surface insulating film 50 therebetween. The sidewall wiring 51 may also face the outer contact region 47, with the main surface insulating film 50 therebetween. In this embodiment, the sidewall wiring 51 is formed at a distance from the field region 48 toward the active surface 8 in plan view.

[0121] The sidewall wiring 51 covers the first to fourth connecting surfaces 10A to 10D with the main surface insulating film 50 interposed therebetween. The sidewall wiring 51 faces the second well region 42, the third well region 43, the fourth well region 44, and the outer well region 46 at the first to fourth connecting surfaces 10A to 10D with the main surface insulating film 50 interposed therebetween. In this embodiment, the sidewall wiring 51 also faces the body region 18 with the main surface insulating film 50 interposed therebetween.

[0122] The sidewall wiring 51 covers the exposed portion (second buried electrode 28) of the source structure 25, the exposed portion (third buried electrode 33) of the side edge structure 30, and the exposed portion (fourth buried electrode 38) of the termination structure 35 on the first to fourth connecting surfaces 10A to 10D. As a result, the sidewall wiring 51 is electrically connected to the source structure 25, the side edge structure 30, and the termination structure 35, and applies a source potential from the outer peripheral surface 9 side.

[0123] The sidewall wiring 51 has an overlapping portion 52 that extends from at least one of the first to fourth connecting surfaces 10A to 10D onto the edge of the active surface 8. The overlapping portion 52 covers the active surface 8 in a film-like manner in plan view and is formed in a band shape that extends along the edge of the active surface 8. In this embodiment, the overlapping portion 52 is formed in a ring shape (specifically, a quadrangular ring) that surrounds the inner portion of the active surface 8 in plan view.

[0124] The overlapping portions 52 are formed on the active surface 8 at intervals from the plurality of gate structures 20 toward the peripheral edge of the active surface 8, and cover the exposed portions (second buried electrodes 28) of the source structures 25, the exposed portions (third buried electrodes 33) of the edge structures 30, and the exposed portions (fourth buried electrodes 38) of the termination structures 35. In this way, the sidewall wiring 51 is electrically connected to the source structures 25, the edge structures 30, and the termination structures 35 on the active surface 8.

[0125] In this embodiment, the sidewall wiring 51 includes p-type or n-type conductive polysilicon and is formed integrally with the second buried electrode 28, the third buried electrode 33, and the fourth buried electrode 38. Of course, the sidewall wiring 51 may be formed separately from the second buried electrode 28, the third buried electrode 33, and the fourth buried electrode 38.

[0126] The semiconductor device 1 includes a plurality of gate connection electrodes 53 that cover the plurality of gate structures 20 in the active region 12 in a film-like manner. The gate connection electrodes 53 may be referred to as "connection electrodes," "connection electrode films," "gate connection electrode films," etc. The gate connection electrodes 53 may be considered to be components of the gate structures 20.

[0127] The gate connection electrode 53 is formed as an external connection portion (contact portion) of the gate structure 20, and at least one gate connection electrode 53 is provided for each gate structure 20. In this embodiment, a plurality of gate connection electrodes 53 are provided at intervals in a one-to-many correspondence with each gate structure 20. In this embodiment, the plurality of gate connection electrodes 53 selectively cover the inner portions and both end portions of the corresponding gate structures 20.

[0128] Each gate connection electrode 53 is connected to the first buried electrode 23 in a portion covering the corresponding gate structure 20, and has a portion that is extended from above the first buried electrode 23 onto the main surface insulating film 50. In this embodiment, each gate connection electrode 53 is formed integrally with the corresponding first buried electrode 23. That is, each gate connection electrode 53 includes a portion where part of the first buried electrode 23 is extended in the form of a film to a region outside the gate structure 20 (above the main surface insulating film 50). Of course, the gate connection electrode 53 may be formed separately from the first buried electrode 23.

[0129] The plurality of gate connection electrodes 53 are formed at intervals from the plurality of side edge structures 30 in the first direction X in plan view, and are formed at intervals from the plurality of source structures 25 in the second direction Y. In other words, the plurality of gate connection electrodes 53 expose the plurality of source structures 25 and the plurality of side edge structures 30.

[0130] The gate connection electrodes 53 are arranged alternately with the source structures 25 in the second direction Y in plan view. In this embodiment, the gate connection electrodes 53 are each formed in a strip shape extending in the first direction X. The gate connection electrodes 53 do not face the side edge structures 30 in the second direction Y in plan view.

[0131] The gate connection electrode 53 has an electrode surface extending along the active surface 8. In this embodiment, the gate connection electrode 53 is formed in a tapered shape (a truncated quadrangular pyramid shape) from the active surface 8 toward the electrode surface in a cross-sectional view. The electrode surface is preferably formed to be wider than the gate structure 20 in the second direction Y. In other words, the electrode surface preferably has a portion facing the gate structure 20 in the normal direction Z and a portion facing a region outside the gate structure 20 (i.e., the main surface insulating film 50) in the normal direction Z.

[0132] In this embodiment, the gate connection electrode 53 includes p-type or n-type conductive polysilicon. The gate connection electrode 53 has an electrode thickness TE. The electrode thickness TE is preferably at least 0.5 times the first width W1 (second width W2) described above. The electrode thickness TE is preferably not more than the peripheral depth DO described above. The electrode thickness TE is preferably not more than the second depth D2 described above. It is particularly preferable that the electrode thickness TE be less than the second depth D2 (periphery depth DO).

[0133] The electrode thickness TE is preferably equal to or less than the first depth D1. Of course, the electrode thickness TE may be greater than the first depth D1. It is particularly preferable that the electrode thickness TE is less than the first depth D1. The electrode thickness TE may be equal to or greater than 0.05 μm and equal to or less than 2.5 μm. The electrode thickness TE is preferably equal to or greater than 0.5 μm and equal to or less than 1.5 μm.

[0134] Fig. 15 is a plan view showing the pad region 55. Fig. 16 is a plan view showing an example layout of the gate electrode 80 and the source electrode 100. Fig. 17 is an enlarged plan view showing a main part of Fig. 16 together with the gate structure 20. Fig. 18 is an enlarged plan view showing an example layout of the region XVIII shown in Fig. 17.

[0135] Fig. 19 is an enlarged plan view showing a main portion of Fig. 18 together with a first gate structure 20A according to a first layout example. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 19. Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in Fig. 19. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 19. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII shown in Fig. 19.

[0136] 15 to 23, semiconductor device 1 includes a pad region 55 set on first main surface 3. Pad region 55 is a region where a pad electrode (a gate pad 81 described later) for gate structure 20 is arranged. In this embodiment, pad region 55 is set on active surface 8 with a space therebetween from outer peripheral surface 9.

[0137] Specifically, the pad region 55 is set in the active region 12. The pad region 55 also serves as a region that partially shields the current path of the output current generated in the active region 12. A structure located directly below the pad region 55 on the active surface 8 functions as a breakdown voltage structure. In this embodiment, the pad region 55 is set in the active region 12 at a distance from the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in a plan view.

[0138] The pad region 55 is set in a region on one side in the second direction Y of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view. In this embodiment, the pad region 55 is located on the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. In other words, the pad region 55 faces the center of the first side surface 5A (first connecting surface 10A) in the second direction Y in a plan view.

[0139] The pad region 55 has a planar area smaller than the planar area of ​​the active surface 8 (first main surface 3). The proportion of the pad region 55 in the active surface 8 (first main surface 3) is preferably 1% or more and 25% or less. The proportion of the pad region 55 may be a value belonging to any one of the ranges of 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less. The proportion of the pad region 55 is preferably 10% or less.

[0140] The semiconductor device 1 includes a first gate region 56, a second gate region 57, and a third gate region 58 as arrangement regions for the multiple gate structures 20. The first gate region 56 is a region in the active region 12 that passes through the pad region 55 in the first direction X. In this embodiment, the first gate region 56 is provided in a region on one side (the first side surface 5A side) of the middle portion of the pad region 55 in the second direction Y.

[0141] In this embodiment, the width of the first gate region 56 in the second direction Y is less than half the width of the pad region 55. Of course, the width of the first gate region 56 may be half or more the width of the pad region 55. In other words, the first gate region 56 may have a portion located in a region on the other side (the second side surface 5B side) in the second direction Y with respect to the intermediate portion of the pad region 55.

[0142] The second gate region 57 is a region in the active region 12 that passes through the pad region 55 in the first direction X and is adjacent to the first gate region 56 in the second direction Y. The second gate region 57 is provided in a region on the other side (the second side surface 5B side) of the first gate region 56 in the second direction Y.

[0143] In this embodiment, the width of the second gate region 57 in the second direction Y is greater than the width of the first gate region 56 and less than the width of the pad region 55. The width of the second gate region 57 may be greater than half the width of the pad region 55. Of course, when the width of the first gate region 56 is equal to or greater than half the width of the pad region 55, the width of the second gate region 57 may be less than half the width of the pad region 55.

[0144] The third gate region 58 is a region in the active region 12 that does not pass through the pad region 55. In other words, the third gate region 58 is the entire region of the active region 12 that is located on the other side in the second direction Y of the pad region 55. The third gate region 58 is provided on the other side in the second direction Y (the second side surface 5B side) of the second gate region 57, and faces the first gate region 56 in the second direction Y across the second gate region 57.

[0145] In the second direction Y, the width of the third gate region 58 is larger than the width of the first gate region 56. The width of the third gate region 58 is larger than the width of the second gate region 57. The width of the third gate region 58 is larger than the sum of the widths of the first gate region 56 and the second gate region 57 (i.e., the width of the pad region 55).

[0146] The above-mentioned plurality of gate structures 20 includes a plurality of gate structures 20 that pass through the pad region 55 in the active region 12, and a plurality of gate structures 20 that are located outside the pad region 55 in the active region 12. The plurality of gate structures 20 are classified into at least one (a plurality in this embodiment) first gate structure 20A, at least one (a plurality in this embodiment) second gate structure 20B, and at least one (a plurality in this embodiment) third gate structure 20C according to their locations within the active region 12 and their electrical properties.

[0147] The first gate structure 20A is disposed in the first gate region 56 and has at least one resistor portion 60 in the middle portion in the longitudinal direction (first direction X). In Figures 18 and 19, the resistor portion 60 is surrounded by a two-dot chain line. The resistor portion 60 is a portion that constitutes at least a part of the resistor (specifically, the gate resistor RG). The number of first gate structures 20A disposed in the first gate region 56 is not limited to a specific number as long as it is one or more. In this embodiment, multiple (two or more) first gate structures 20A are disposed in the first gate region 56.

[0148] In this embodiment, each first gate structure 20A has a plurality of resistor portions 60. Each resistor portion 60 is formed using a portion of the first gate structure 20A. That is, each resistor portion 60 is a trench electrode-type resistor structure including a first trench 21, a first insulating film 22, and a first buried electrode 23. The main body of the resistor portion 60 is formed by a portion of the first buried electrode 23. The resistance value of each resistor portion 60 can be adjusted by the resistance value (impurity concentration) of the first buried electrode 23, the length of the resistor portion 60 in the first direction X, the width of the resistor portion 60 in the second direction Y (the width of the first trench 21), the depth of the resistor portion 60 (the depth of the first trench 21), etc.

[0149] The plurality of resistor portions 60 include a first resistor portion 60A on one longitudinal side (the third side surface 5C side) and a second resistor portion 60B on the other longitudinal side (the fourth side surface 5D side). The first resistor portion 60A is provided at the intersection of one side (the third side surface 5C side) of the pad region 55 and the first gate structure 20A. The first resistor portion 60A is provided so as to straddle the inside and outside of the pad region 55, and has a first electrical end portion 61 located within the pad region 55 and a second electrical end portion 62 located outside the pad region 55.

[0150] The second resistor portion 60B is provided at an intersection of the other side (fourth side surface 5D side) of the pad region 55 and the first gate structure 20A with a gap therebetween. The second resistor portion 60B is provided so as to straddle the inside and outside of the pad region 55, and has an electrical first end 61 located within the pad region 55 and an electrical second end 62 located outside the pad region 55.

[0151] The multiple first gate structures 20A are arranged at intervals in the second direction Y so that the multiple resistance portions 60 are positioned on the same straight line extending along the second direction Y. In other words, the multiple first resistance portions 60A are arranged in a line in the second direction Y, and the multiple second resistance portions 60B are arranged in a line in the second direction Y.

[0152] The plurality of first gate structures 20A penetrate the body region 18 and the source region 19 in regions inside and outside the pad region 55. That is, a channel is formed in a region outside the plurality of resistor portions 60 in the surface layer portion of the first main surface 3. The channel is also formed in a region along the plurality of resistor portions 60 in the surface layer portion of the first main surface 3. Such a configuration is effective in generating an output current near the boundary of the pad region 55 (near the resistor portions 60).

[0153] The second gate structure 20B is disposed in the second gate region 57 and does not have the aforementioned resistor portion 60. The number of second gate structures 20B disposed in the second gate region 57 is not limited to a specific number as long as it is one or more. In this embodiment, a plurality of (two or more) second gate structures 20B are disposed in the second gate region 57.

[0154] The number of second gate structures 20B is preferably greater than the number of first gate structures 20A. In other words, the generated current value controlled by the plurality of second gate structures 20B (the amount of current generated in the second gate region 57) is preferably greater than the generated current value controlled by the plurality of first gate structures 20A (the amount of current generated in the first gate region 56).

[0155] Of course, the number of second gate structures 20B may be less than the number of first gate structures 20A. The combined resistance value of the multiple resistance sections 60 can also be adjusted by adjusting the ratio (number) of first gate structures 20A to the total number of first gate structures 20A and second gate structures 20B.

[0156] The plurality of second gate structures 20B penetrate the body region 18 and the source region 19 in regions inside and outside the pad region 55. That is, a channel is formed along the portions of the second gate structures 20B located inside and outside the pad region 55 in the surface layer portion of the first main surface 3. Such a configuration is effective in generating an output current near the boundary of the pad region 55.

[0157] The third gate structure 20C is disposed in the third gate region 58 and does not have the aforementioned resistor portion 60. The number of third gate structures 20C disposed in the third gate region 58 is not limited to a specific number as long as it is one or more. In this embodiment, a plurality of (two or more) third gate structures 20C are disposed in the third gate region 58.

[0158] The number of third gate structures 20C is preferably greater than the number of first gate structures 20A. The number of third gate structures 20C is preferably greater than the number of second gate structures 20B. In other words, the generated current value controlled by the plurality of third gate structures 20C (the amount of current generated in the third gate region 58) is preferably greater than the generated current value controlled by the plurality of second gate structures 20B (the amount of current generated in the second gate region 57).

[0159] It is particularly preferable that the number of third gate structures 20C is greater than the total number of first gate structures 20A and second gate structures 20B. In other words, it is preferable that the generated current value controlled by the plurality of third gate structures 20C is greater than the generated current value controlled by the plurality of first gate structures 20A and the plurality of second gate structures 20B.

[0160] The aforementioned plurality of source structures 25 includes a plurality of source structures 25 passing through the pad region 55 and a plurality of source structures 25 located outside the pad region 55. That is, the plurality of source structures 25 includes at least one (a plurality in this embodiment) source structure 25 adjacent to at least one (a plurality in this embodiment) first gate structure 20A in the second direction Y in the first gate region 56. The plurality of source structures 25 are arranged alternately with the plurality of first gate structures 20A in the second direction Y in the first gate region 56.

[0161] The plurality of source structures 25 have a portion in the first gate region 56 that faces the resistor portion 60 of the first gate structure 20A, with a portion of the chip 2 in between, and a portion that faces a portion of the first gate structure 20A outside the resistor portion 60, with a portion of the chip 2 in between. In this embodiment, the plurality of source structures 25 face the entire first gate structure 20A in the first gate region 56, with a portion of the chip 2 in between.

[0162] The plurality of source structures 25 also includes at least one (a plurality in this embodiment) source structure 25 adjacent to at least one (a plurality in this embodiment) second gate structure 20B in the second direction Y in the second gate region 57. The plurality of source structures 25 also includes a source structure 25 interposed between the first gate structure 20A and the second gate structure 20B. The plurality of source structures 25 are arranged alternately with the plurality of second gate structures 20B in the second direction Y in the second gate region 57.

[0163] The plurality of source structures 25 also includes at least one (a plurality of in this embodiment) source structure 25 adjacent to at least one (a plurality of in this embodiment) third gate structure 20C in the second direction Y in the third gate region 58. The plurality of source structures 25 also includes a source structure 25 interposed between the second gate structure 20B and the third gate structure 20C. The plurality of source structures 25 are arranged alternately with the plurality of third gate structures 20C in the second direction Y in the third gate region 58.

[0164] The above-mentioned first well region 41 is formed in a region along the plurality of first gate structures 20A, a region along the plurality of second gate structures 20B, and a region along the plurality of third gate structures 20C inside and outside the pad region 55. Therefore, bias in the electric field inside and outside the pad region 55 is suppressed, and the first well region 41 provides an electric field relaxation effect.

[0165] Similarly, the second well region 42 described above is formed in a region along the plurality of source structures 25 inside and outside the pad region 55. Therefore, bias in the electric field inside and outside the pad region 55 is suppressed, and an electric field relaxation effect is obtained by the second well region 42. In this embodiment, the contact region 45 described above is not formed in the pad region 55.

[0166] Of course, the contact regions 45 may be formed in the pad region 55 in a layout similar to that outside the pad region 55. In this case, the multiple contact regions 45 may include at least one contact region 45 formed in a region along at least one resistor portion 60 (first resistor portion 60A and second resistor portion 60B) of the first gate structure 20A.

[0167] The aforementioned multiple side end structures 30 face the multiple first gate structures 20A, the multiple second gate structures 20B, and the multiple third gate structures 20C in a one-to-one correspondence in the first direction X in the first side end region 13 (second side end region 14).

[0168] The side edge structures 30 have a length in the first direction X that is shorter than the lengths of the first gate structures 20A, the second gate structures 20B, and the third gate structures 20C. The length of the side edge structures 30 in the first direction X is preferably longer than the length of the resistor portions 60 of the first gate structures 20A. Of course, the length of the side edge structures 30 in the first direction X may be shorter than the length of the resistor portion 60.

[0169] The configuration of the first resistor section 60A side of the first gate structure 20A will be described below. The configuration of the second resistor section 60B side of the first gate structure 20A is the same as the configuration of the first resistor section 60A side. Therefore, the description of the second resistor section 60B side will be omitted below. The description of the second resistor section 60B side can be obtained by replacing "first resistor section 60A" with "second resistor section 60B" in the following description.

[0170] The semiconductor device 1 includes at least one resistive electrode 65 that selectively covers the first resistive portions 60A of the multiple first gate structures 20A in a film-like manner. The resistive electrode 65 may also be referred to as an "electrode film," "resistive film," "resistive electrode film," or the like. Each resistive electrode 65, together with each first resistive portion 60A, constitutes a part of a resistor (specifically, a gate resistor RG). Each resistive electrode 65 may be considered as one component of each first resistive portion 60A. The resistance value of each resistive portion 60A can also be adjusted by the material and layout of the resistive electrode 65.

[0171] The resistive electrode 65 includes at least one of a conductive polysilicon film and an alloy crystal film. The alloy crystal film includes alloy crystals composed of a metal element and a non-metal element. The alloy crystal film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the resistive electrode 65 includes p-type or n-type conductive polysilicon.

[0172] In this embodiment, the plurality of resistive electrodes 65 are arranged in the same layer as the plurality of gate connecting electrodes 53, with a gap therebetween. The plurality of resistive electrodes 65 are also arranged in the same layer as the plurality of overlapping portions 52 of the sidewall wirings 51, with a gap therebetween. In other words, the plurality of resistive electrodes 65 are arranged in regions other than the overlapping portions 52 and the gate connecting electrodes 53.

[0173] The plurality of resistive electrodes 65 partially cover the corresponding first resistive portion 60A. In this embodiment, the plurality of resistive electrodes 65 are provided in a one-to-many correspondence with each corresponding first resistive portion 60A, and cover the corresponding first resistive portion 60A at multiple locations.

[0174] Specifically, the plurality of resistive electrodes 65 include a plurality of first resistive electrodes 65A and a plurality of second resistive electrodes 65B. The plurality of first resistive electrodes 65A are arranged in the pad region 55 at intervals from one another, and each cover the first end 61 of a corresponding one of the first resistor portions 60A.

[0175] Specifically, each of the first resistance electrodes 65A covers the first end 61 of a corresponding first resistance portion 60A in a film-like manner as a single covering target. In other words, each of the first resistance electrodes 65A is provided in one-to-one correspondence with the first end 61 of the corresponding first resistance portion 60A and is electrically connected to the first end 61.

[0176] Each first resistive electrode 65A exposes a region (first buried electrode 23) of the corresponding first gate structure 20A other than the first end 61. That is, each first resistive electrode 65A is disposed at a distance from the second end 62 of the first resistive portion 60A toward the first end 61 of the first resistive portion 60A, and exposes the first buried electrode 23 from the inner portion of the first resistive portion 60A.

[0177] In this embodiment, the multiple first resistance electrodes 65A are each formed in a strip shape extending in the first direction X in a plan view, and are opposed to each other in the second direction Y. In other words, the multiple first resistance electrodes 65A are arranged in a stripe shape extending along the multiple first resistance portions 60A in a plan view.

[0178] The multiple first resistance electrodes 65A are arranged at intervals in the second direction Y so as to be positioned on the same straight line extending in the second direction Y. In this embodiment, each first resistance electrode 65A is arranged shifted to the other side in the first direction X (toward the pad region 55) with respect to the straight line connecting the multiple gate connection electrodes 53 on the multiple second gate structures 20B side in the second direction Y, and does not face the multiple gate connection electrodes 53 in the second direction Y.

[0179] Of course, the plurality of first resistance electrodes 65A may be arranged offset in the first direction X from at least one first resistance electrode 65A so as not to face at least one first resistance electrode 65A in the second direction Y. Such a configuration is effective when finely adjusting the resistance value of each first resistance portion 60A.

[0180] The multiple first resistive electrodes 65A are arranged at intervals in the second direction Y from another first resistive electrode 65A covering the first gate structure 20A (resistive portion 60) that is not to be covered. The multiple first resistive electrodes 65A are arranged at intervals in the second direction Y from the multiple source structures 25, exposing the multiple source structures 25. In other words, the multiple first resistive electrodes 65A are arranged alternately with the multiple source structures 25 in the second direction Y in a plan view.

[0181] The second resistance electrodes 65B are arranged at intervals from one another outside the pad region 55, and each cover the second end 62 of a corresponding first resistance portion 60A (second resistance portion 60B). Specifically, each of the second resistance electrodes 65B covers the second end 62 of the corresponding first resistance portion 60A in a film-like manner as a single covering target. In other words, each second resistance electrode 65B is provided in one-to-one correspondence with the second end 62 of the corresponding first resistance portion 60A, and is electrically connected to the second end 62.

[0182] Each second resistive electrode 65B exposes a region (first buried electrode 23) of the corresponding gate structure 20 other than the second end 62. That is, each second resistive electrode 65B is disposed at a distance from the first resistive electrode 65A (first end 61 of the first resistive portion 60A) toward the second end 62 of the first resistive portion 60A, and exposes the first buried electrode 23 from an inner portion of the first resistive portion 60A. That is, each second resistive electrode 65B exposes the first buried electrode 23 from a region between the corresponding second resistive electrode 65B and the first resistive electrode 65A.

[0183] In this embodiment, the second resistance electrodes 65B are each formed in a strip shape extending in the first direction X in a plan view and are opposed to each other in the second direction Y. In other words, the second resistance electrodes 65B are arranged in a stripe shape extending along the first resistance portions 60A in a plan view.

[0184] The second resistance electrodes 65B are arranged at intervals in the second direction Y so as to be positioned on the same straight line extending along the second direction Y. In this embodiment, each second resistance electrode 65B is positioned on an extension of a straight line connecting the gate connection electrodes 53 on the second gate structures 20B side in the second direction Y, and faces the gate connection electrodes 53 in the second direction Y.

[0185] Of course, the multiple second resistance electrodes 65B may be arranged offset in the first direction X from at least one second resistance electrode 65B so as not to face at least one second resistance electrode 65B in the second direction Y. Such a configuration is effective when finely adjusting the resistance value of each first resistance section 60A. Of course, the multiple second resistance electrodes 65B may be arranged offset to one side or the other in the first direction X with respect to a line connecting the multiple gate connection electrodes 53 in the second direction Y so as not to face the multiple gate connection electrodes 53 in the second direction Y.

[0186] The second resistive electrodes 65B are arranged at intervals in the second direction Y from other second resistive electrodes 65B that cover the first gate structures 20A (resistive portions 60) that are not to be covered. The second resistive electrodes 65B are arranged at intervals in the second direction Y from the source structures 25, exposing the source structures 25. In other words, the second resistive electrodes 65B are arranged alternately with the source structures 25 in the second direction Y in a plan view.

[0187] Each resistive electrode 65 is connected to the first buried electrode 23 in the corresponding first resistive portion 60A, and has a portion that extends from above the first buried electrode 23 onto the main surface insulating film 50. That is, each resistive electrode 65 is formed wider than the corresponding first resistive portion 60A in the second direction Y. Each resistive electrode 65 faces the body region 18 and the source region 19 in the stacking direction in a region outside the first resistive portion 60A.

[0188] In this embodiment, each resistive electrode 65 is made of the same conductive material as the corresponding first buried electrode 23 and is formed integrally with the first buried electrode 23. In other words, each resistive electrode 65 includes a portion of the first buried electrode 23 that is drawn out in the form of a film to an area outside the first resistor portion 60A (on the main surface insulating film 50). Of course, each resistive electrode 65 may be formed separately from the first buried electrode 23.

[0189] Each resistive electrode 65 has a resistive surface extending along the active surface 8. In this embodiment, each resistive electrode 65 is formed in a tapered shape (a truncated quadrangular pyramid shape) from the active surface 8 toward the resistive surface in a cross-sectional view. The resistive surface is preferably formed to be wider than the first resistive portion 60A in the second direction Y. In other words, the resistive surface preferably has a portion facing the first resistive portion 60A in the normal direction Z and a portion facing a region outside the first resistive portion 60A (i.e., the main surface insulating film 50) in the normal direction Z.

[0190] The resistive electrode 65 has a resistive thickness TR. The resistive thickness TR is adjusted as appropriate depending on the resistance value to be achieved. The resistive thickness TR is preferably at least 0.5 times the first width W1 described above. The resistive thickness TR is preferably equal to or less than the outer circumferential depth DO (second depth D2) described above. It is particularly preferable that the resistive thickness TR be less than the outer circumferential depth DO (second depth D2).

[0191] The resistor thickness TR is preferably equal to or less than the first depth D1 described above. Most preferably, the resistor thickness TR is less than the first depth D1. The resistor thickness TR may be approximately equal to the electrode thickness TE described above. The resistor thickness TR may be equal to or greater than 0.05 μm and equal to or less than 2.5 μm. The resistor thickness TR is preferably equal to or greater than 0.5 μm and equal to or less than 1.5 μm.

[0192] Of course, the resistor thickness TR may be greater than the first depth D1. The resistor thickness TR may be greater than the outer circumferential depth DO (second depth D2). When the resistor electrode 65 is made of an alloy crystal film, the resistor thickness TR may be less than the first depth D1. In this case, the resistor thickness TR may be 0.1 nm or more and 100 nm or less.

[0193] The semiconductor device 1 includes an insulating interlayer film 70 that covers the main surface insulating film 50. The interlayer film 70 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 70 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 70 preferably includes a silicon oxide film.

[0194] The interlayer film 70 covers the gate structure 20 (first buried electrode 23), the source structure 25 (second buried electrode 28), the side edge structure 30 (third buried electrode 33), and the termination structure 35 (fourth buried electrode 38) on the active surface 8. The interlayer film 70 also covers the plurality of gate connection electrodes 53 and the plurality of resistive electrodes 65 on the active surface 8.

[0195] The interlayer film 70 covers the outer well region 46, the outer contact region 47, and the plurality of field regions 48 on the outer peripheral surface 9, sandwiching the main surface insulating film 50 therebetween. The interlayer film 70 covers the sidewall wiring 51 on the first to fourth connecting surfaces 10A to 10D. In this embodiment, the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the interlayer film 70 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.

[0196] The semiconductor device 1 includes a plurality of gate openings 71 formed in an interlayer film 70. The plurality of gate openings 71 are formed in portions of the interlayer film 70 that cover the plurality of gate structures 20, and penetrate the interlayer film 70 so as to selectively expose the plurality of gate structures 20.

[0197] Specifically, the plurality of gate openings 71 are formed in portions of the interlayer film 70 that cover the plurality of gate connection electrodes 53, respectively, and expose the plurality of gate connection electrodes 53. In other words, the plurality of gate openings 71 expose portions of the plurality of gate structures 20 via the plurality of gate connection electrodes 53. The plurality of gate openings 71 are provided in a one-to-one correspondence with the plurality of gate connection electrodes 53.

[0198] The semiconductor device 1 includes a plurality of resistor openings 72 formed in an interlayer film 70. The plurality of resistor openings 72 penetrate the interlayer film 70 so as to selectively expose a plurality of resistor portions 60 (first resistor portion 60A and second resistor portion 60B). The plurality of resistor openings 72 are provided in a one-to-many correspondence with each resistor portion 60, exposing each resistor portion 60 from a plurality of locations. In other words, a plurality of resistor openings 72 are provided corresponding to one resistor portion 60.

[0199] The plurality of resistor openings 72 are spaced apart to expose the first ends 61 and the second ends 62 of the plurality of resistor portions 60. Specifically, the plurality of resistor openings 72 are formed in portions of the interlayer film 70 that cover the plurality of resistor electrodes 65 (first resistor electrode 65A and second resistor electrode 65B), respectively, and expose the plurality of resistor electrodes 65.

[0200] Specifically, the plurality of resistor openings 72 include a plurality of first resistor openings 72 A and a plurality of second resistor openings 72 B. In this embodiment, the plurality of first resistor openings 72 A are provided in a one-to-one correspondence with the first ends 61 of the plurality of resistor portions 60, and expose the first ends 61 of the plurality of resistor portions 60, respectively.

[0201] Specifically, the first resistor openings 72A are provided in one-to-one correspondence with the first resistor electrodes 65A, and expose the first resistor electrodes 65A, respectively. That is, each first resistor opening 72A exposes the first end 61 of the corresponding resistor portion 60 through the corresponding first resistor electrode 65A. Each first resistor opening 72A exposes an inner portion of each first resistor electrode 65A at a distance from the periphery of the corresponding first resistor electrode 65A.

[0202] In this embodiment, the multiple first resistor openings 72A are formed in a band shape extending in the first direction X in a plan view, and are arranged in a line at intervals in the second direction Y. Of course, the multiple first resistor openings 72A may be formed in a rectangular shape, a polygonal shape, a circle, or the like.

[0203] The multiple first resistor openings 72A face each other in the second direction Y. The multiple first resistor openings 72A may be arranged offset in the first direction X from at least one first resistor opening 72A so as not to face at least one first resistor opening 72A in the second direction Y. The multiple first resistor openings 72A are formed offset to the other side in the first direction X (toward the pad region 55) from a straight line connecting, in the second direction Y, the multiple gate openings 71 exposing the multiple gate connection electrodes 53 on the multiple second gate structures 20B side, and do not face the multiple gate openings 71 in the second direction Y.

[0204] A plurality of first resistor openings 72A may be provided in a one-to-many correspondence with each of the first resistor electrodes 65A. That is, a plurality of first resistor openings 72A may be provided corresponding to one first resistor electrode 65A. In this case, the plurality of first resistor openings 72A are formed at intervals in the first direction X so as to expose the inner portion of the corresponding one first resistor electrode 65A (resistive electrode 65) from a plurality of locations.

[0205] In this embodiment, the second resistor openings 72B are provided in a one-to-one correspondence with the second ends 62 of the resistor portions 60, and expose the second ends 62 of the resistor portions 60 at intervals from the first resistor openings 72A. Specifically, the second resistor openings 72B are provided in a one-to-one correspondence with the second resistor electrodes 65B, and expose the second resistor electrodes 65B, respectively.

[0206] That is, each second resistor opening 72B exposes the second end 62 of the corresponding resistor portion 60 via the corresponding second resistor electrode 65B. Each second resistor opening 72B exposes an inner portion of the corresponding second resistor electrode 65B at a distance from the periphery of the second resistor electrode 65B. In this embodiment, the multiple second resistor openings 72B are formed in a strip shape extending in the first direction X in a plan view and are arranged in a row at intervals in the second direction Y. Of course, the multiple second resistor openings 72B may be formed in a rectangular, polygonal, circular, or other shape.

[0207] The second resistor openings 72B face the first resistor openings 72A in the first direction X and face each other in the second direction Y. The second resistor openings 72B may be arranged offset in the first direction X from at least one second resistor opening 72B so as not to face at least one second resistor opening 72B in the second direction Y.

[0208] The second resistance openings 72B are located on extensions of lines connecting, in the second direction Y, the gate openings 71 that expose the gate connection electrodes 53 on the second gate structures 20B sides, and face the gate openings 71 in the second direction Y. The second resistance openings 72B may be formed shifted to one side or the other in the first direction X with respect to the lines connecting the gate openings 71 in the second direction Y so as not to face the gate openings 71 in the second direction Y.

[0209] A plurality of second resistor openings 72B may be provided in a one-to-many correspondence with each second resistor electrode 65B. That is, a plurality of second resistor openings 72B may be provided corresponding to one second resistor electrode 65B. In this case, the plurality of second resistor openings 72B are formed at intervals in the first direction X so as to expose the inner portion of the corresponding one second resistor electrode 65B (resistive electrode 65) from multiple locations.

[0210] The semiconductor device 1 includes a plurality of source openings 73 formed in the interlayer film 70. The plurality of source openings 73 are formed in portions of the interlayer film 70 outside the pad region 55 that cover the plurality of source structures 25, and penetrate the interlayer film 70 to selectively expose the plurality of source structures 25. Specifically, the plurality of source openings 73 expose the corresponding source structure 25, as well as the source structures 25 and contact regions 45 located on both sides of the corresponding source structure 25.

[0211] The plurality of source openings 73 may be formed in a strip shape extending along the corresponding source structures 25. Of course, the plurality of source openings 73 may be formed in a one-to-many correspondence with the corresponding source structures 25. In this case, the plurality of source openings 73 may be formed at intervals along the corresponding source structures 25.

[0212] The semiconductor device 1 includes an outer opening 74 formed in the interlayer film 70. The outer opening 74 penetrates the main surface insulating film 50 and the interlayer film 70 so as to selectively expose the outer contact region 47 and the sidewall wiring 51. The outer opening 74 is formed in a strip or ring shape extending along the outer contact region 47 and the sidewall wiring 51 so as to surround the active surface 8 (active plateau 11) in plan view.

[0213] The semiconductor device 1 includes a gate electrode 80 disposed on the active surface 8 (first main surface 3). Specifically, the gate electrode 80 has a resistance value lower than the resistance values ​​of the multiple resistor sections 60 and the multiple resistor electrodes 65, and is disposed on the interlayer film 70. The gate electrode 80 includes a gate pad 81. The gate pad 81 may also be referred to as a "pad electrode," a "gate pad electrode," a "control pad electrode," or the like.

[0214] Gate pad 81 is an external terminal electrode to which a gate potential is applied from the outside. Gate pad 81 is disposed on a portion of interlayer film 70 that covers pad region 55. That is, in this embodiment, gate pad 81 is disposed on active region 12 at a distance from first side end region 13, second side end region 14, first termination region 15, and second termination region 16 in plan view.

[0215] Furthermore, the gate pad 81 is disposed in a region on one side in the second direction Y of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view. The gate pad 81 is located on the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. In other words, the gate pad 81 faces the center of the first side surface 5A (first connecting surface 10A) in the second direction Y in a plan view.

[0216] The gate pad 81 is spaced apart inward from the ends of the multiple side edge structures 30 in the first direction X on the active surface 8 in plan view, and faces the multiple side edge structures 30 in the first direction X. In this configuration, the gate pad 81 does not face the multiple side edge structures 30 in the stacking direction. The gate pad 81 is spaced apart from the multiple termination structures 35 in the second direction Y in plan view, and faces the multiple termination structures 35 in the second direction Y. In this configuration, the gate pad 81 does not face the multiple termination structures 35 in the stacking direction.

[0217] The gate pad 81 partially faces the plurality of gate structures 20 and the plurality of source structures 25 across the interlayer film 70. Specifically, the gate pad 81 is arranged so as to overlap the plurality of first gate structures 20A and the plurality of second gate structures 20B in plan view, but not to overlap the plurality of third gate structures 20C.

[0218] The gate pad 81 is arranged inward of the active surface 8 at a distance from both end portions of the plurality of first gate structures 20A in the first direction X in plan view. The gate pad 81 covers the inner portions of the plurality of first gate structures 20A with the interlayer film 70 interposed therebetween, and exposes both end portions of the plurality of first gate structures 20A.

[0219] The gate pad 81 is arranged inward of the active surface 8 at a distance from both end portions of the plurality of second gate structures 20B in the first direction X in plan view. The gate pad 81 covers the inner portions of the plurality of second gate structures 20B with the interlayer film 70 therebetween, and exposes both end portions of the plurality of second gate structures 20B. The gate pad 81 is arranged at a distance from the plurality of third gate structures 20C in plan view, and does not face the plurality of third gate structures 20C in the stacking direction.

[0220] The gate pad 81 covers the inner portions of the source structures 25 with the interlayer film 70 sandwiched therebetween, and exposes both ends of the source structures 25. The gate pad 81 faces the body region 18, the source region 19, the first well regions 41, and the second well regions 42 with the interlayer film 70 sandwiched therebetween. In this embodiment, the gate pad 81 does not face the contact region 45. Of course, if the contact region 45 is formed in the pad region 55, the gate pad 81 may face the contact region 45.

[0221] In this embodiment, the gate pad 81 is disposed on the interlayer film 70 at a horizontal distance from the gate connection electrode 53, and does not face the gate connection electrode 53 in the stacking direction. In other words, the gate pad 81 faces a portion of the gate structure 20 that is exposed from the gate connection electrode 53. In this embodiment, the gate pad 81 faces, in plan view, a region between at least two gate connection electrodes 53 disposed on both sides of the gate structure 20 in the first direction X in the first direction X.

[0222] The gate pad 81 faces, in the second direction Y, at least one gate connection electrode 53 arranged inside the gate structure 20 in a plan view. Of course, the gate pad 81 may be arranged shifted to one side or the other side in the first direction X with respect to an imaginary line that crosses, in the second direction Y, the gate connection electrode 53 arranged inside the gate structure 20 in a plan view.

[0223] The gate pad 81 is disposed on the interlayer film 70 at a distance in the horizontal direction from the overlapping portion 52 of the sidewall wiring 51, and does not face the overlapping portion 52 in the stacking direction. In other words, the gate pad 81 is disposed on a region surrounded by the sidewall wiring 51 in a plan view.

[0224] The planar area of ​​the gate pad 81 is smaller than the planar area of ​​the active region 12 and larger than the planar area of ​​the resistor region. The proportion of the gate pad 81 in the active surface 8 is preferably 1% or more and 25% or less. The proportion of the gate pad 81 may be a value belonging to any one of the ranges of 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less. The proportion of the gate pad 81 is preferably 10% or less.

[0225] The gate pad 81 covers the first ends 61 of the plurality of resistor portions 60 at a distance from the second ends 62 of the plurality of resistor portions 60, and penetrates the interlayer film 70 to be electrically connected to the first ends 61 of the plurality of resistor portions 60. Specifically, the gate pad 81 covers the first ends 61 of the plurality of first resistor portions 60A and the first ends 61 of the plurality of second resistor portions 60B, and penetrates the interlayer film 70 to be electrically connected to the first ends 61 of the plurality of first resistor portions 60A and the first ends 61 of the plurality of second resistor portions 60B.

[0226] In this embodiment, the gate pad 81 is connected to a plurality of first resistance electrodes 65A and is electrically connected to the first ends 61 of a plurality of resistance sections 60 (a plurality of first resistance sections 60A and a plurality of second resistance sections 60B) via the plurality of first resistance electrodes 65A.

[0227] Specifically, the gate pad 81 includes a pad main body 82, a first resistor connection portion 83, and a second resistor connection portion 84. The pad main body 82 is formed as the main body of the gate pad 81 in a region of the interlayer film 70 outside the region that covers the multiple resistor portions 60. In this embodiment, the pad main body 82 forms the inner portion of the gate pad 81 in plan view, and faces the multiple gate structures 20 and the multiple source structures 25 across the interlayer film 70.

[0228] In this embodiment, the pad main body 82 has a pad width WP in the first direction X that is larger than the length of the plurality of resistor portions 60. Of course, the pad width WP may be smaller than the length of the plurality of resistor portions 60. In this embodiment, the pad main body 82 is formed in a quadrangular shape in a plan view. Of course, the pad main body 82 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, or the like.

[0229] The first resistor connection portion 83 is an electrical connection portion to the first ends 61 of the plurality of first resistor portions 60A, and is drawn out in the form of a film onto a region of the interlayer film 70 that covers the first ends 61 of the plurality of first resistor portions 60A from the pad main body portion 82. In this embodiment, the first resistor connection portion 83 is formed as a peripheral portion of the gate pad 81 in a plan view.

[0230] Specifically, the first resistor connection portion 83 forms a periphery (side) of the gate pad 81 on one side in the first direction X, extending in the second direction Y. Of course, the first resistor connection portion 83 may be drawn out in a finger shape (line shape) from the pad main body portion 82 toward the region above the plurality of first resistor portions 60A.

[0231] The first resistor connection portion 83 penetrates the plurality of first resistor openings 72A from above the interlayer film 70 and is connected to the plurality of first resistor electrodes 65A on the side of the plurality of first resistor portions 60A within the plurality of first resistor openings 72A. In other words, the first resistor connection portion 83 penetrates the interlayer film 70 and is mechanically and electrically connected to the plurality of first resistor electrodes 65A. As a result, the gate pad 81 is electrically connected to the first ends 61 of the plurality of first resistor portions 60A via the plurality of first resistor electrodes 65A.

[0232] The second resistor connection portion 84 is an electrical connection portion to the first ends 61 of the second resistor portions 60B, and is drawn out in the form of a film onto a region of the interlayer film 70 that covers the first ends 61 of the second resistor portions 60B from the pad main body portion 82. In this embodiment, the second resistor connection portion 84 is formed as a peripheral portion of the gate pad 81 in a plan view.

[0233] Specifically, the second resistor connection portion 84 forms a periphery (side) of the gate pad 81 that extends in the second direction Y on the other side of the first direction X. Of course, the second resistor connection portion 84 may be drawn out in a finger shape (line shape) from the pad main body portion 82 toward the region above the plurality of second resistor portions 60B.

[0234] The second resistor connection portion 84 penetrates the plurality of first resistor openings 72A from above the interlayer film 70 and is connected to the plurality of first resistor electrodes 65A on the side of the plurality of second resistor portions 60B within the plurality of first resistor openings 72A. In other words, the second resistor connection portion 84 penetrates the interlayer film 70 and is mechanically and electrically connected to the plurality of first resistor electrodes 65A. As a result, the gate pad 81 is electrically connected to the first ends 61 of the plurality of second resistor portions 60B via the plurality of first resistor electrodes 65A.

[0235] The gate electrode 80 includes a gate wiring 85 disposed on the interlayer film 70 at a distance from the gate pad 81. The gate wiring 85 may also be referred to as a "wiring electrode," a "gate wiring electrode," a "control wiring electrode," or the like. The gate wiring 85 has a resistance value lower than the resistance values ​​of the multiple resistor sections 60 and the multiple resistive electrodes 65. The gate wiring 85 is disposed on a portion of the interlayer film 70 that covers the active surface 8, and is selectively routed within the active region 12.

[0236] In this embodiment, the gate wiring 85 is disposed at a distance inward from the periphery of the active surface 8, and is not disposed on the outer circumferential surface 9. The gate wiring 85 is electrically connected to the resistor portions 60 of the plurality of first gate structures 20A at positions in the active region 12 that are different from the gate pad 81, and is electrically connected to the gate pad 81 via the plurality of resistor portions 60.

[0237] Specifically, the gate wiring 85 is spaced apart from the first ends 61 of the plurality of resistor portions 60 and penetrates the interlayer film 70 to be electrically connected to the second ends 62 of the plurality of resistor portions 60. In this embodiment, the gate wiring 85 is mechanically and electrically connected to the plurality of second resistance electrodes 65B. That is, the gate wiring 85 is electrically connected to the second ends 62 of the plurality of resistor portions 60 via the plurality of second resistance electrodes 65B.

[0238] The gate wiring 85 is routed from a region above the plurality of resistor portions 60 to a region outside the plurality of resistor portions 60, and is also electrically connected to portions of the plurality of first gate structures 20A outside the plurality of resistor portions 60. Furthermore, the gate wiring 85 is electrically connected to the plurality of second gate structures 20B and the plurality of third gate structures 20C in addition to the plurality of first gate structures 20A.

[0239] That is, the gate wiring 85 transmits the gate potential applied to the gate pad 81 to the plurality of first gate structures 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C. Specifically, the gate wiring 85 extends in a line shape so as to intersect (specifically, orthogonally cross) the plurality of first gate structures 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C, and penetrates the interlayer film 70 to be electrically connected to the plurality of first gate structures 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C.

[0240] That is, the gate wiring 85 is electrically connected to the plurality of first gate structures 20A and the plurality of second gate structures 20B located directly below the gate pad 81, as well as the plurality of third gate structures 20C located outside directly below the gate pad 81. In this embodiment, the gate wiring 85 is electrically connected to the first gate structure 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C via the plurality of gate connection electrodes 53.

[0241] In this embodiment, the gate wiring 85 includes a first resistance wiring 86 , a second resistance wiring 87 , a first connection wiring 88 , a second connection wiring 89 , a first line wiring 90 , a second line wiring 91 and a third line wiring 92 .

[0242] The first resistance wiring 86 is provided as an electrical connection portion for the second ends 62 of the multiple first resistance portions 60A. The first resistance wiring 86 is disposed on the interlayer film 70 at a distance from the gate pad 81 on one side in the first direction X, and is formed in a line shape extending in the second direction Y.

[0243] The first resistance wiring 86 has a base end on one side in the second direction Y and a tip end on the other side in the second direction Y. The base end of the first resistance wiring 86 protrudes further to one side in the second direction Y than the gate pad 81. The tip end of the first resistance wiring 86 protrudes further to the other side in the second direction Y than the gate pad 81.

[0244] The first resistance wiring 86 intersects (specifically, orthogonally) the plurality of first gate structures 20A and the plurality of second gate structures 20B. Specifically, the first resistance wiring 86 intersects (specifically, orthogonally) the second ends 62 of the plurality of first resistor portions 60A. The first resistance wiring 86 extends from above the interlayer film 70 into the plurality of gate openings 71 and the plurality of second resistance openings 72B.

[0245] The first resistance wiring 86 is mechanically and electrically connected to the gate connection electrodes 53 of the second gate structures 20B within the gate openings 71. As a result, the first resistance wiring 86 is electrically connected to the second gate structures 20B via the gate connection electrodes 53.

[0246] The first resistance wiring 86 is mechanically and electrically connected to the second resistance electrodes 65B in the second resistance openings 72B, so that the first resistance wiring 86 is electrically connected to the first gate structures 20A via the first resistance portions 60A, and is electrically connected to the gate pad 81 via the first resistance portions 60A.

[0247] The first resistance wiring 86 connects the plurality of first resistance parts 60A in parallel between the gate pad 81. In other words, the first resistance wiring 86 electrically connects the plurality of first gate structures 20A and the plurality of second gate structures 20B to the gate pad 81 via the parallel circuit of the plurality of first resistance parts 60A.

[0248] The first resistance wiring 86 may intersect (specifically, orthogonally intersect) at least one (one or more) third gate structures 20C. In this case, the first resistance wiring 86 may be mechanically and electrically connected to the gate connection electrodes 53 of the at least one (one or more) third gate structures 20C within the at least one (one or more) gate openings 71.

[0249] The second resistance wiring 87 is provided as an electrical connection portion for the second ends 62 of the plurality of second resistance portions 60B. The second resistance wiring 87 is disposed on the interlayer film 70 at a distance from the gate pad 81 on the other side in the first direction X, and is formed in a line shape extending in the second direction Y.

[0250] The second resistance wiring 87 has a base end on one side in the second direction Y and a tip end on the other side in the second direction Y. The base end of the second resistance wiring 87 protrudes further to one side in the second direction Y than the gate pad 81. The tip end of the second resistance wiring 87 protrudes further to the other side in the second direction Y than the gate pad 81.

[0251] The second resistance wiring 87 intersects (specifically, orthogonally) the plurality of first gate structures 20A and the plurality of second gate structures 20B. Specifically, the second resistance wiring 87 intersects (specifically, orthogonally) the second ends 62 of the plurality of second resistance portions 60B. The second resistance wiring 87 extends from above the interlayer film 70 into the plurality of second resistance openings 72B and the plurality of gate openings 71.

[0252] The second resistance wiring 87 is mechanically and electrically connected to the gate connection electrodes 53 of the second gate structures 20B within the gate openings 71. As a result, the second resistance wiring 87 is electrically connected to the second gate structures 20B via the gate connection electrodes 53.

[0253] The second resistance wiring 87 is mechanically and electrically connected to the second resistance electrodes 65B in the second resistance openings 72B, so that the second resistance wiring 87 is electrically connected to the first gate structures 20A via the second resistance portions 60B, and is electrically connected to the gate pad 81 via the second resistance portions 60B.

[0254] The second resistance wiring 87 connects the plurality of second resistance portions 60B in parallel between the gate pad 81. In other words, the second resistance wiring 87 electrically connects the plurality of first gate structures 20A and the plurality of second gate structures 20B to the gate pad 81 via the parallel circuit of the plurality of second resistance portions 60B.

[0255] The second resistance wiring 87 may intersect (specifically, orthogonally intersect) at least one (one or more) third gate structures 20C. In this case, the second resistance wiring 87 may be mechanically and electrically connected to the gate connection electrodes 53 of at least one (one or more) third gate structures 20C within at least one (one or more) gate openings 71.

[0256] The first connection wiring 88 is disposed on the other side in the second direction Y (the second side surface 5B side) of the gate pad 81. The first connection wiring 88 extends in a line in the first direction X in a region between the tip end of the first resistance wiring 86 and the tip end of the second resistance wiring 87, and mechanically and electrically connects the tip end of the first resistance wiring 86 and the tip end of the second resistance wiring 87.

[0257] The first connection wiring 88 electrically connects the plurality of first resistance portions 60A and the plurality of second resistance portions 60B. Specifically, the first connection wiring 88 connects in parallel a parallel circuit including the plurality of first resistance portions 60A and a parallel circuit including the plurality of second resistance portions 60B between the first connection wiring 88 and the gate pad 81. In this embodiment, the first connection wiring 88 covers the plurality of gate structures 20 (third gate structures 20C) and the plurality of source structures 25.

[0258] The second connection wiring 89 is disposed on one side in the second direction Y (the side of the first side surface 5A) of the gate pad 81, and faces the first connection wiring 88 across the gate pad 81. The second connection wiring 89 extends linearly in the first direction X in a region between the base end of the first resistance wiring 86 and the base end of the second resistance wiring 87, and mechanically and electrically connects the base end of the first resistance wiring 86 and the base end of the second resistance wiring 87.

[0259] The second connection wiring 89 electrically connects the plurality of first resistor portions 60A and the plurality of second resistor portions 60B. Specifically, the second connection wiring 89 connects in parallel a parallel circuit including the plurality of first resistor portions 60A and a parallel circuit including the plurality of second resistor portions 60B between the second connection wiring 89 and the gate pad 81. In this embodiment, the second connection wiring 89 covers the plurality of termination structures 35. Of course, the second connection wiring 89 may cover either or both of at least one gate structure 20 and at least one source structure 25. The second connection wiring 89 does not necessarily have to be provided and may be removed as necessary.

[0260] The first line wiring 90 is drawn out from the first resistance wiring 86 to one side in the first direction X and is electrically connected to the second ends 62 of the multiple first resistance portions 60A via the first resistance wiring 86. The first line wiring 90 has a first extension portion 90a and a second extension portion 90b. The first extension portion 90a is drawn out in a line shape from the base end of the first resistance wiring 86 to one side in the first direction X and faces the multiple termination structures 35 with the interlayer film 70 sandwiched between them.

[0261] Of course, the first extension portion 90a may cover either or both of the at least one gate structure 20 and the at least one source structure 25. The tip portion of the first extension portion 90a is formed at a distance from the third connection surface 10C inwardly of the active surface 8 in plan view. The tip portion of the first extension portion 90a may be formed at a distance from the positions of the ends of the multiple side edge structures 30 in the first direction X inwardly of the active surface 8. Of course, the tip portion of the first extension portion 90a may be drawn out to a portion facing the multiple side edge structures 30 in the second direction Y.

[0262] The second extension portion 90b is drawn out from the tip of the first extension portion 90a in the second direction Y and extends linearly along the third side surface 5C (third connection surface 10C). In plan view, the second extension portion 90b intersects (specifically, perpendicular to) one end of the plurality of gate structures 20 and one end of the plurality of source structures 25 in the second direction Y. Specifically, the second extension portion 90b intersects (specifically, perpendicular to) one end of the plurality of first gate structures 20A, one end of the plurality of second gate structures 20B, one end of the plurality of third gate structures 20C, and one end of the plurality of source structures 25.

[0263] The second extension portion 90b is formed inward of the active surface 8 at a distance from the positions of the ends of the plurality of side edge structures 30 in the first direction X in plan view, and does not face the plurality of side edge structures 30 in the stacking direction. Of course, a portion of the second extension portion 90b may be drawn out from the active region 12 to the first side edge region 13 and face the plurality of side edge structures 30 in the stacking direction. The tip portion of the second extension portion 90b may be located above the active region 12 or above the second termination region 16.

[0264] The second extension portion 90b enters the plurality of gate openings 71 from above the interlayer film 70 and is electrically connected to one end of the plurality of gate structures 20 in the plurality of gate openings 71. Specifically, the second extension portion 90b is electrically connected to one end of the plurality of first gate structures 20A, one end of the plurality of second gate structures 20B, and one end of the plurality of third gate structures 20C. In other words, the second extension portion 90b is electrically connected to one end of the plurality of first gate structures 20A and one end of the plurality of second gate structures 20B located directly below the gate pad 81.

[0265] The second extension portion 90b is mechanically and electrically connected to the plurality of gate connection electrodes 53 within the plurality of gate openings 71. As a result, the second extension portion 90b is electrically connected to one end of the plurality of gate structures 20 via the plurality of gate connection electrodes 53. In this manner, the first line wiring 90 electrically connects the plurality of first gate structures 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C to the gate pad 81 via the plurality of first resistance portions 60A and the plurality of second resistance portions 60B.

[0266] The second line wiring 91 is drawn out from the second resistance wiring 87 to the other side in the first direction X and is electrically connected to the second ends 62 of the plurality of second resistance portions 60B via the second resistance wiring 87. The second line wiring 91 has a third extension portion 91 a and a fourth extension portion 91 b. The third extension portion 91 a is drawn out in a line shape from the base end of the second resistance wiring 87 to the other side in the first direction X and faces the plurality of termination structures 35 with the interlayer film 70 interposed therebetween.

[0267] Of course, the third extension portion 91a may cover either or both of the at least one gate structure 20 and the at least one source structure 25. The tip portion of the third extension portion 91a is formed at a distance from the fourth connection surface 10D inwardly of the active surface 8 in plan view. The tip portion of the third extension portion 91a may be formed at a distance from the positions of the ends of the multiple side edge structures 30 in the first direction X inwardly of the active surface 8. Of course, the tip portion of the third extension portion 91a may be drawn out to a portion facing the multiple side edge structures 30 in the second direction Y.

[0268] The fourth extension portion 91b is drawn out from the tip of the third extension portion 91a in the second direction Y and extends linearly along the fourth side surface 5D (fourth connection surface 10D). In plan view, the fourth extension portion 91b intersects (specifically, orthogonal to) the other ends of the plurality of gate structures 20 and the other ends of the plurality of source structures 25 in the second direction Y. Specifically, the fourth extension portion 91b intersects (specifically, orthogonal to) the other ends of the plurality of first gate structures 20A, the other ends of the plurality of second gate structures 20B, the other ends of the plurality of third gate structures 20C, and the other ends of the plurality of source structures 25.

[0269] The fourth extension portion 91b is formed inward of the active surface 8 at a distance from the positions of the ends of the plurality of side edge structures 30 in the first direction X in plan view, and does not face the plurality of side edge structures 30 in the stacking direction. Of course, a portion of the fourth extension portion 91b may be drawn out from the active region 12 to the second side edge region 14 and face the plurality of side edge structures 30 in the stacking direction. The tip of the fourth extension portion 91b may be located above the active region 12 or above the second termination region 16.

[0270] The fourth extension portion 91b enters the plurality of gate openings 71 from above the interlayer film 70 and is electrically connected to the other ends of the plurality of gate structures 20 within the plurality of gate openings 71. Specifically, the fourth extension portion 91b is electrically connected to the other ends of the plurality of first gate structures 20A, the other ends of the plurality of second gate structures 20B, and the other ends of the plurality of third gate structures 20C. In other words, the fourth extension portion 91b is electrically connected to the other ends of the plurality of first gate structures 20A and the other ends of the plurality of second gate structures 20B located directly below the gate pad 81.

[0271] The fourth extension portion 91b is mechanically and electrically connected to the plurality of gate connection electrodes 53 within the plurality of gate openings 71. As a result, the fourth extension portion 91b is electrically connected to the other ends of the plurality of gate structures 20 via the plurality of gate connection electrodes 53. In this manner, the second line wiring 91 electrically connects the plurality of first gate structures 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C to the gate pad 81 via the plurality of first resistance portions 60A and the plurality of second resistance portions 60B.

[0272] The third line wiring 92 is arranged in a region on the other side in the second direction Y (toward the second side surface 5B) of the gate pad 81, and extends in a line shape along the second direction Y in the region between the gate pad 81 and the second connection surface 10B. Specifically, the third line wiring 92 is drawn out from the first connection wiring 88 toward the inner portion of the active region 12, and is electrically connected to the plurality of first resistor portions 60A and the plurality of second resistor portions 60B via the first resistance wiring 86, the second resistance wiring 87, and the first connection wiring 88. In other words, the third line wiring 92 is electrically connected to the gate pad 81 via the plurality of first resistor portions 60A and the plurality of second resistor portions 60B.

[0273] The third line wiring 92 intersects (specifically, orthogonally) the inner portions of the plurality of gate structures 20 and the inner portions of the plurality of source structures 25 in a plan view. Specifically, the third line wiring 92 intersects (specifically, orthogonally) the plurality of third gate structures 20C. The third line wiring 92 enters the plurality of gate openings 71 from above the interlayer film 70 and is electrically connected to the inner portions of the plurality of third gate structures 20C within the plurality of gate openings 71.

[0274] Specifically, the third line wiring 92 is connected to the plurality of gate connection electrodes 53 within the plurality of gate openings 71, and is electrically connected to inner portions of the plurality of third gate structures 20C via the plurality of gate connection electrodes 53. In this manner, the third line wiring 92 electrically connects the plurality of third gate structures 20C to the gate pad 81 via the plurality of first resistance portions 60A and the plurality of second resistance portions 60B.

[0275] In this embodiment, the gate electrode 80 includes a gate subpad 93 disposed on the interlayer film 70 at a distance from the gate pad 81. The gate subpad 93 may be referred to as a "subpad electrode" or the like. The presence or absence of the gate subpad 93 is optional, and it may be omitted as necessary. The gate subpad 93 has a planar area smaller than that of the gate pad 81. The gate subpad 93 is formed narrower than the gate pad 81 in the second direction Y and wider than the first resistance wiring 86 (second resistance wiring 87) in the first direction X.

[0276] The gate subpad 93 is a pad (dummy pad) for electrical testing to measure the gate resistance RG during the manufacturing process, and is electrically connected to the gate pad 81 via a plurality of resistance portions 60 (a plurality of first resistance portions 60A and a plurality of second resistance portions 60B). In the electrical test, a test signal is applied between the gate pad 81 and the gate subpad 93.

[0277] For example, a gate potential may be applied to either the gate pad 81 or the gate subpad 93, and a ground potential may be applied to the other. In other words, the gate subpad 93 is a terminal to which a potential different from that of the gate pad 81 is applied. The gate subpad 93 is an open terminal after the manufacturing process, and is excluded from the targets for connection of conductive bonding members such as bonding wires.

[0278] For example, when the semiconductor device 1 is mounted in a semiconductor package, the entire area of ​​the gate subpad 93 is directly or indirectly covered with an insulator (e.g., a sealing resin containing multiple fillers and a matrix resin) to electrically insulate it from other structures. Of course, the gate subpad 93 may be electrically connected to a lead terminal of the semiconductor package via a bonding wire or the like so that a test signal can be input even after the semiconductor device 1 is mounted in the semiconductor package.

[0279] The location of the gate subpad 93 is arbitrary. The gate subpad 93 may be arranged on at least one of the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, and the outer periphery region 17. In this embodiment, the gate subpad 93 is arranged on the active region 12 at a distance from the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in a plan view.

[0280] In this embodiment, the gate subpad 93 is disposed at a distance from the gate pad 81 on one side in the first direction X (toward the third connection surface 10C) and faces the gate pad 81 in the first direction X. That is, the gate subpad 93 is disposed in an area on one side in the second direction Y (toward the first side surface 5A) of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view. In this embodiment, the gate subpad 93 is disposed shifted to one side or the other in the first direction X with respect to the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.

[0281] The gate subpad 93 partially faces the plurality of gate structures 20 and the plurality of source structures 25 across the interlayer film 70. The gate subpad 93 is disposed inward of the active surface 8 at a distance from the ends of the plurality of side edge structures 30 in the first direction X in plan view, and faces the plurality of side edge structures 30 in the first direction X. The gate subpad 93 does not face the plurality of side edge structures 30 in the stacking direction.

[0282] The gate subpad 93 is arranged inward of the active surface 8 at a distance from both end portions of the plurality of gate structures 20 in the first direction X in a plan view. The gate subpad 93 covers the inner portions of the plurality of gate structures 20 with the interlayer film 70 therebetween, and exposes both end portions of the plurality of gate structures 20. The gate subpad 93 covers the inner portions of the plurality of source structures 25 with the interlayer film 70 therebetween, and exposes both end portions of the plurality of source structures 25.

[0283] The gate subpad 93 faces the body region 18, the source region 19, the plurality of first well regions 41, and the plurality of second well regions 42, with the interlayer film 70 sandwiched therebetween. The gate subpad 93 may also face the plurality of contact regions 45, with the interlayer film 70 sandwiched therebetween. In this embodiment, the gate subpad 93 is disposed on the interlayer film 70 at a distance from the gate connection electrode 53 in the horizontal direction, and does not face the gate connection electrode 53 in the stacking direction. In other words, the gate subpad 93 faces a portion of the gate structure 20 that is exposed from the gate connection electrode 53.

[0284] The gate subpad 93 is disposed on the interlayer film 70 at a horizontal distance from the overlapping portion 52 of the sidewall wiring 51, and does not face the overlapping portion 52 in the stacking direction. In other words, the gate subpad 93 is disposed on a region surrounded by the sidewall wiring 51 in a plan view.

[0285] In this embodiment, the gate subpad 93 is connected to the gate wiring 85, and is electrically connected to the plurality of gate structures 20, the plurality of resistor portions 60, and the gate pad 81 via the gate wiring 85. In consideration of the wiring resistance of the gate wiring 85, it is preferable that the gate subpad 93 be connected to a portion of the gate wiring 85 that is located in the vicinity of the plurality of resistor portions 60.

[0286] For example, the gate subpad 93 is preferably connected to the first resistance wiring 86, the second resistance wiring 87, the first connection wiring 88, the second connection wiring 89, etc. In this embodiment, the gate subpad 93 is connected to the first resistance wiring 86. In this embodiment, the gate subpad 93 overlaps a plurality of second gate structures 20B but does not overlap a plurality of third gate structures 20C. Of course, the gate subpad 93 may overlap some or all of the first gate structures 20A. Furthermore, the gate subpad 93 may overlap at least one third gate structure 20C.

[0287] The gate electrode 80 preferably has a thickness greater than that of the resistive electrode 65 (the thickness of the gate connection electrode 53). The thickness of the gate electrode 80 is preferably greater than that of the interlayer film 70. The thickness of the gate electrode 80 may be 0.5 μm or more and 10 μm or less. The thickness of the gate electrode 80 is preferably 1 μm or more and 5 μm or less.

[0288] In this embodiment, the gate electrode 80 has a layered structure including a first electrode film 94 and a second electrode film 95, which are layered in this order from the interlayer film 70 side. The first electrode film 94 is formed as a barrier electrode. The first electrode film 94 includes at least one of a Ti film, a TiN film, and a W film. In this embodiment, the first electrode film 94 includes a Ti film.

[0289] The second electrode film 95 has a thickness greater than that of the first electrode film 94 and forms the main body of the gate electrode 80. The second electrode film 95 includes at least one of an Al film, a Cu film, an Al alloy film, and a Cu alloy film. The second electrode film 95 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 95 includes an Al alloy film (an AlSiCu alloy film in this embodiment).

[0290] The first electrode film 94 of the gate pad 81 covers the interlayer film 70 in the pad body 82, and extends into the first resistor openings 72A from above the interlayer film 70 in the first resistor connection portion 83 (second resistor connection portion 84). The first electrode film 94 of the gate pad 81 covers the opening wall surfaces of the first resistor openings 72A in a film-like manner, and covers the first resistor electrodes 65A in a film-like manner.

[0291] The second electrode film 95 of the gate pad 81 covers the first electrode film 94 in the pad main body 82 and faces the interlayer film 70 with the first electrode film 94 sandwiched between them. The second electrode film 95 of the gate pad 81 covers the first electrode film 94 in the first resistor connection portion 83 (second resistor connection portion 84) and backfills the multiple first resistor openings 72A. The second electrode film 95 of the gate pad 81 is electrically connected to the multiple first resistor electrodes 65A via the first electrode film 94 in the multiple first resistor openings 72A.

[0292] The first electrode film 94 of the gate wiring 85 covers the interlayer film 70 in a film-like manner, and extends from above the interlayer film 70 into the plurality of gate openings 71 and the plurality of second resistor openings 72B. The first electrode film 94 of the gate wiring 85 covers the opening wall surfaces of the plurality of gate openings 71 in a film-like manner, and also covers the plurality of gate connection electrodes 53. The first electrode film 94 of the gate wiring 85 covers the opening wall surfaces of the plurality of second resistor openings 72B in a film-like manner, and also covers the plurality of second resistor electrodes 65B in a film-like manner.

[0293] The second electrode film 95 of the gate wiring 85 backfills the plurality of gate openings 71 and the plurality of second resistor openings 72B with the first electrode film 94 of the gate wiring 85 in between, and covers the first electrode film 94 in a film form on the interlayer film 70. The second electrode film 95 of the gate wiring 85 is electrically connected to the plurality of gate connection electrodes 53 and the plurality of second resistor electrodes 65B via the first electrode film 94.

[0294] The semiconductor device 1 includes a source electrode 100 disposed on the interlayer film 70 at a distance from the gate electrode 80. The source electrode 100 has a resistance value lower than the resistance values ​​of the plurality of resistor sections 60 and the plurality of resistor electrodes 65. The source electrode 100 includes at least one (a plurality in this embodiment) source pad 101. The source pad 101 may also be referred to as a "low potential pad electrode," a "source pad electrode," a "channel pad," a "different potential pad," or the like.

[0295] The source pad 101 includes a first source pad 101A and a second source pad 101B. The first source pad 101A is disposed in a region on one side in the first direction X on a portion of the interlayer film 70 that covers the active region 12. Specifically, the first source pad 101A is disposed in a region on one side in the first direction X that is partitioned by the gate wiring 85 (first line wiring 90 and third line wiring 92).

[0296] The first source pad 101A has a plane area smaller than that of the active region 12. The plane area of ​​the first source pad 101A is larger than that of the gate pad 81. The proportion of the active surface 8 (first main surface 3) occupied by the first source pad 101A is preferably 25% or more and 50% or less.

[0297] The first source pad 101A is disposed on the active region 12 at a distance from the first side edge region 13 in a plan view. That is, the first source pad 101A is disposed at a distance inward from the ends of the plurality of side edge structures 30 in the first direction X toward the active surface 8 in a plan view, and faces the plurality of side edge structures 30 in the first direction X. The first source pad 101A does not face the plurality of side edge structures 30 in the stacking direction.

[0298] The first source pad 101A partially faces the plurality of gate structures 20 and the plurality of source structures 25 across the interlayer film 70. The first source pad 101A is disposed inward of the active surface 8 at a distance from both end positions of the plurality of gate structures 20 in the first direction X in a plan view.

[0299] The first source pad 101A covers inner portions of the plurality of gate structures 20 with the interlayer film 70 therebetween, and exposes one end portions of the plurality of gate structures 20. The first source pad 101A covers inner portions of the plurality of source structures 25 with the interlayer film 70 therebetween, and exposes one end portions of the plurality of source structures 25. The first source pad 101A extends from above the interlayer film 70 into the plurality of source openings 73, and is electrically connected to the plurality of source structures 25, source regions 19, and contact regions 45 within the plurality of source openings 73.

[0300] In this embodiment, the first source pad 101A includes a first pad portion 101a and a second pad portion 101b. A source potential for the main source may be applied to the first pad portion 101a from an external source. A source potential for source sensing may be applied to the second pad portion 101b from an external source. Of course, a source potential for the main source may also be applied to the second pad portion 101b.

[0301] The first pad portion 101a is located in a region on the other side (the second side surface 5B side) of the gate pad 81 in the second direction Y, and faces the gate pad 81 in the second direction Y. That is, in this embodiment, the first pad portion 101a covers the plurality of third gate structures 20C, and is electrically connected to the plurality of source structures 25, source regions 19, and contact regions 45 adjacent to the plurality of third gate structures 20C.

[0302] The second pad portion 101b is located in an area on one side (the third side surface 5C side) of the gate pad 81 in the first direction X, and faces the gate pad 81 in the first direction X. Specifically, the second pad portion 101b faces the gate pad 81 in the first direction X, with a part of the gate wiring 85 (the first resistance wiring 86) sandwiched between them.

[0303] In this embodiment, second pad portion 101b faces gate pad 81 across gate subpad 93 in plan view. A portion of second pad portion 101b that is aligned with gate subpad 93 is recessed in a rectangular shape along gate subpad 93 in plan view. Second pad portion 101b may be extended from active region 12 to first termination region 15 and cover at least one termination structure 35.

[0304] The second pad portion 101b covers at least one (in this embodiment, multiple) first gate structure 20A. The second pad portion 101b may cover all or a portion of the first gate structures 20A. The second pad portion 101b is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) first gate structure 20A.

[0305] The second pad portion 101b also covers at least one (in this embodiment, multiple) second gate structures 20B. The second pad portion 101b may cover all or a portion of the second gate structures 20B. The second pad portion 101b is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) second gate structure 20B. In this manner, the second pad portion 101b is electrically connected to multiple source structures 25 arranged directly below the gate pad 81.

[0306] The second source pad 101B is disposed in a region on the other side in the first direction X on a portion of the interlayer film 70 that covers the active region 12. Specifically, the second source pad 101B is disposed in a region defined by the gate wiring 85 (the second line wiring 91 and the third line wiring 92) in the region on the other side in the first direction X, and faces the first source pad 101A across a part of the gate wiring 85 in the first direction X.

[0307] The second source pad 101B has a planar area smaller than that of the active region 12. The planar area of ​​the second source pad 101B is larger than that of the gate pad 81. The proportion of the active surface 8 (first main surface 3) occupied by the second source pad 101B is preferably 25% or more and 50% or less.

[0308] The second source pad 101B is disposed on the active region 12 at a distance from the second side edge region 14 in a plan view. That is, the second source pad 101B is disposed at a distance inward from the ends of the plurality of side edge structures 30 in the first direction X toward the active surface 8 in a plan view, and faces the plurality of side edge structures 30 in the first direction X. The second source pad 101B does not face the plurality of side edge structures 30 in the stacking direction.

[0309] The second source pad 101B partially faces the plurality of gate structures 20 and the plurality of source structures 25 across the interlayer film 70. The second source pad 101B is disposed inward of the active surface 8 at a distance from both end positions of the plurality of gate structures 20 in the first direction X in plan view.

[0310] The second source pad 101B covers inner portions of the plurality of gate structures 20 with the interlayer film 70 therebetween and exposes the other ends of the plurality of gate structures 20. The second source pad 101B covers inner portions of the plurality of source structures 25 with the interlayer film 70 therebetween and exposes the other ends of the plurality of source structures 25. The second source pad 101B extends into the plurality of source openings 73 from above the interlayer film 70 and is electrically connected to the plurality of source structures 25, source regions 19, and contact regions 45 within the plurality of source openings 73.

[0311] In this embodiment, the second source pad 101B includes a third pad portion 101c and a fourth pad portion 101d. A source potential for the main source may be applied to the third pad portion 101c from the outside. A source potential for source sensing may be applied to the fourth pad portion 101d from the outside. Of course, a source potential for the main source may also be applied to the fourth pad portion 101d.

[0312] The third pad portion 101c is located in a region on the other side (the second side surface 5B side) of the gate pad 81 in the second direction Y, faces the first pad portion 101a in the first direction X, and faces the gate pad 81 in the second direction Y. That is, in this embodiment, the third pad portion 101c covers the plurality of third gate structures 20C and is electrically connected to the plurality of source structures 25, source regions 19, and contact regions 45 adjacent to the plurality of third gate structures 20C.

[0313] The fourth pad portion 101d is located in a region on the other side (the fourth side surface 5D side) of the gate pad 81 in the first direction X, and faces the second pad portion 101b across the gate pad 81 in the first direction X. Specifically, the fourth pad portion 101d faces the gate pad 81 in the first direction X across a part of the gate wiring 85 (the second resistance wiring 87). The fourth pad portion 101d may be drawn from the active region 12 to the first termination region 15 and cover at least one termination structure 35.

[0314] The fourth pad portion 101d covers at least one (in this embodiment, multiple) first gate structure 20A. The fourth pad portion 101d may cover all or some of the first gate structures 20A. The fourth pad portion 101d is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) first gate structure 20A.

[0315] Furthermore, the fourth pad portion 101d covers at least one (in this embodiment, multiple) second gate structures 20B. The fourth pad portion 101d may cover all or a portion of the second gate structures 20B. The fourth pad portion 101d is electrically connected to at least one (in this embodiment, multiple) source structure 25, source region 19, and multiple contact regions 45 adjacent to at least one (in this embodiment, multiple) second gate structure 20B. In this manner, the fourth pad portion 101d is electrically connected to multiple source structures 25 arranged directly below the gate pad 81.

[0316] The source electrode 100 includes a source wiring 102. The source wiring 102 may also be referred to as a "low-potential wiring electrode," "source wiring electrode," "channel wiring," "different-potential wiring," or the like. The source wiring 102 transmits the source potential applied to the source pad 101 to other regions. In this embodiment, the source wiring 102 is drawn out from the source pad 101 onto the interlayer film 70 so as to be located closer to the outer periphery region 17 than the gate wiring 85. The source wiring 102 is drawn out from the active surface 8 side to the outer periphery surface 9 side, passing through the first to fourth connection surfaces 10A to 10D.

[0317] The source wiring 102 is formed in a strip shape extending along the first to fourth connecting faces 10A to 10D, and faces the sidewall wiring 51 across the interlayer film 70. In this embodiment, the source wiring 102 is formed in a ring shape (specifically, a quadrangular ring shape) extending along the first to fourth connecting faces 10A to 10D.

[0318] The source wiring 102 covers the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 on the active surface 8, and surrounds the active region 12. In other words, the source wiring 102 surrounds the gate pad 81, the gate wiring 85, and the plurality of source pads 101.

[0319] The source wiring 102 enters the outer opening 74 from above the interlayer film 70 in the peripheral region 17, and is electrically connected to the outer contact region 47 and the sidewall wiring 51 within the outer opening 74. The source potential applied to the source pad 101 is transmitted to the sidewall wiring 51 via the source wiring 102. The source potential applied to the sidewall wiring 51 is transmitted from the peripheral region 17 to the plurality of source structures 25, the plurality of side edge structures 30, and the plurality of termination structures 35.

[0320] The source electrode 100 preferably has a thickness greater than that of the resistive electrode 65 (the thickness of the gate connection electrode 53). The thickness of the source electrode 100 is preferably greater than that of the interlayer film 70. The thickness of the source electrode 100 is preferably approximately equal to that of the gate electrode 80. The thickness of the source electrode 100 may be 0.5 μm or more and 10 μm or less. The thickness of the source electrode 100 is preferably 1 μm or more and 5 μm or less.

[0321] In this embodiment, the source electrode 100 has a layered structure including a first electrode film 103 and a second electrode film 104, which are layered in this order from the interlayer film 70 side. The first electrode film 103 is formed as a barrier electrode. The first electrode film 103 includes at least one of a Ti film, a TiN film, and a W film. In this embodiment, the first electrode film 103 includes a Ti film. It is preferable that the first electrode film 103 has a thickness approximately equal to that of the first electrode film 94 of the gate electrode 80.

[0322] The second electrode film 104 has a thickness greater than that of the first electrode film 103 and forms the main body of the source electrode 100. The second electrode film 104 preferably has a thickness approximately equal to that of the second electrode film 95 of the gate electrode 80. The second electrode film 104 includes at least one of an Al film, a Cu film, an Al alloy film, and a Cu alloy film.

[0323] The second electrode film 104 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 104 includes an Al alloy film (an AlSiCu alloy film in this embodiment).

[0324] The semiconductor device 1 includes a pad insulating film 110 that selectively covers the gate electrode 80, the source electrode 100, and the interlayer film 70. With respect to the gate electrode 80, the pad insulating film 110 covers the periphery of the gate pad 81, the periphery of the gate subpad 93, and the entire area of ​​the gate wiring 85.

[0325] In this embodiment, the pad insulating film 110 covers the first resistor connection portion 83 and the second resistor connection portion 84 of the gate pad 81. In other words, the pad insulating film 110 covers the connection portions of the gate pad 81 to the plurality of resistor portions 60 (the plurality of first resistor electrodes 65A and the plurality of second resistor electrodes 65B).

[0326] The pad insulating film 110 also covers the first resistance wiring 86 and the second resistance wiring 87 of the gate wiring 85. In other words, the pad insulating film 110 covers the connection portions of the gate wiring 85 to the plurality of resistance sections 60 (the plurality of first resistance electrodes 65A and the plurality of second resistance electrodes 65B).

[0327] The pad insulating film 110 also covers the gap portion of the interlayer film 70 that is exposed from the region between the gate pad 81 and the gate wiring 85, and has a portion that covers the plurality of resistor portions 60 across the gap portion. It is preferable that the pad insulating film 110 covers the entire area of ​​the plurality of resistor portions 60 in a plan view.

[0328] The pad insulating film 110 has a gate pad opening 111 that exposes an inner portion of the gate pad 81. The gate pad opening 111 exposes an area of ​​the gate pad 81 other than the first resistor connection portion 83 and the second resistor connection portion 84. In other words, the gate pad opening 111 exposes the pad main body portion 82 of the gate pad 81. The gate pad opening 111 is formed in a quadrangular shape in a plan view. The gate pad opening 111 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, or the like in a plan view.

[0329] The pad insulating film 110 has a gate subpad opening 112 that exposes the inner portion of the gate subpad 93. The gate subpad opening 112 is formed in a quadrangular shape in a plan view, and has a planar area that is smaller than the planar area of ​​the gate pad opening 111. The gate subpad opening 112 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, or the like in a planar view.

[0330] With respect to the source electrode 100, the pad insulating film 110 covers the peripheral portion of the first source pad 101A, the peripheral portion of the second source pad 101B, and the entire area of ​​the source wiring 102. The pad insulating film 110 includes a first source pad opening 113 exposing the first pad portion 101a, a second source pad opening 114 exposing the second pad portion 101b, a third source pad opening 115 exposing the third pad portion 101c, and a fourth source pad opening 116 exposing the fourth pad portion 101d.

[0331] The second source pad opening 114 exposes the second pad portion 101b at a distance from the first source pad opening 113, and the fourth source pad opening 116 exposes the fourth pad portion 101d at a distance from the third source pad opening 115.

[0332] The first to fourth source pad openings 113 to 116 preferably have a planar area larger than the planar area of ​​the gate subpad opening 112. The planar areas of the first to fourth source pad openings 113 to 116 are preferably larger than the planar area of ​​the gate pad opening 111. Of course, the planar areas of the second source pad opening 114 and the fourth source pad opening 116 may be smaller than the planar area of ​​the gate pad opening 111.

[0333] The planar area of ​​the second source pad opening 114 is preferably less than the planar area of ​​the first source pad opening 113. The planar area of ​​the third source pad opening 115 is preferably greater than the planar area of ​​the second source pad opening 114. The planar area of ​​the third source pad opening 115 is preferably approximately equal to the planar area of ​​the first source pad opening 113.

[0334] The planar area of ​​the fourth source pad opening 116 is preferably less than the planar area of ​​the third source pad opening 115. The planar area of ​​the fourth source pad opening 116 is preferably approximately equal to the planar area of ​​the second source pad opening 114. The first to fourth source pad openings 113 to 116 are formed in a quadrangular shape in plan view. The first to fourth source pad openings 113 to 116 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, or the like in plan view.

[0335] In this embodiment, the second source pad opening 114 is formed spaced apart from the first source pad opening 113. However, the second source pad opening 114 may be connected to the first source pad opening 113 and form one pad opening together with the first source pad opening 113. Similarly, the fourth source pad opening 116 may be connected to the third source pad opening 115 and form one pad opening together with the third source pad opening 115.

[0336] The pad insulating film 110 covers the outer well region 46, the outer contact region 47, and the plurality of field regions 48 with the interlayer film 70 sandwiched therebetween in the peripheral region 17. The pad insulating film 110 covers the sidewall wiring 51 with the interlayer film 70 and the source wiring 102 sandwiched therebetween at the first to fourth connecting surfaces 10A to 10D.

[0337] The pad insulating film 110 is formed in the outer peripheral region 17 at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2, and defines a dicing street 117 between itself and the periphery of the chip 2. The dicing street 117 is formed in a band shape extending along the periphery of the chip 2 in a plan view. In this embodiment, the dicing street 117 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. In this embodiment, the dicing street 117 exposes the interlayer film 70.

[0338] Of course, when the main surface insulating film 50 and the interlayer film 70 expose the outer peripheral surface 9, the dicing street 117 may also expose the outer peripheral surface 9. The dicing street 117 may have a width of 1 μm or more and 200 μm or less. The width of the dicing street 117 is the width in a direction perpendicular to the extension direction of the dicing street 117. The width of the dicing street 117 is preferably 5 μm or more and 50 μm or less.

[0339] The pad insulating film 110 preferably has a thickness greater than the thickness of the gate electrode 80 and the thickness of the source electrode 100. The thickness of the pad insulating film 110 is preferably greater than the total thickness of the gate electrode 80 and the source electrode 100. The thickness of the pad insulating film 110 is preferably less than the thickness of the chip 2. The thickness of the pad insulating film 110 may be 3 μm or more and 35 μm or less. The thickness of the pad insulating film 110 is preferably 25 μm or less.

[0340] In this embodiment, the pad insulating film 110 has a laminated structure including an inorganic insulating film 118 and an organic insulating film 119 laminated in this order from the chip 2 side (interlayer film 70 side). The pad insulating film 110 only needs to include at least one of the inorganic insulating film 118 and the organic insulating film 119, and does not necessarily need to include both the inorganic insulating film 118 and the organic insulating film 119 at the same time.

[0341] The inorganic insulating film 118 selectively covers the gate electrode 80, the source electrode 100, and the interlayer film 70, and defines a part of the gate pad opening 111, a part of the gate subpad opening 112, a part of the first source pad opening 113, a part of the second source pad opening 114, a part of the third source pad opening 115, a part of the fourth source pad opening 116, and a part of the dicing street 117.

[0342] The inorganic insulating film 118 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 118 preferably includes an insulating material different from that of the interlayer film 70. The inorganic insulating film 118 preferably includes a silicon nitride film. The inorganic insulating film 118 preferably has a thickness less than that of the interlayer film 70. The thickness of the inorganic insulating film 118 may be 0.1 μm or more and 5 μm or less.

[0343] The organic insulating film 119 selectively covers the inorganic insulating film 118 and defines a portion of the gate pad opening 111, a portion of the gate subpad opening 112, a portion of the first source pad opening 113, a portion of the second source pad opening 114, a portion of the third source pad opening 115, a portion of the fourth source pad opening 116, and a portion of the dicing street 117.

[0344] The organic insulating film 119 may expose the inorganic insulating film 118 at the wall surface of the gate pad opening 111. The organic insulating film 119 may expose the inorganic insulating film 118 at the wall surface of the gate subpad opening 112. The organic insulating film 119 may expose the inorganic insulating film 118 at the wall surface of the first source pad opening 113. The organic insulating film 119 may expose the inorganic insulating film 118 at the wall surface of the second source pad opening 114.

[0345] The organic insulating film 119 may expose the inorganic insulating film 118 at the wall surface of the third source pad opening 115. The organic insulating film 119 may expose the inorganic insulating film 118 at the wall surface of the fourth source pad opening 116. The organic insulating film 119 may expose the inorganic insulating film 118 at the wall surface of the dicing street 117. Of course, the organic insulating film 119 may cover the entire area of ​​the inorganic insulating film 118 so that the inorganic insulating film 118 is not exposed.

[0346] The organic insulating film 119 is preferably made of a resin film other than a thermosetting resin. The organic insulating film 119 may be made of a light-transmitting resin or a transparent resin. The organic insulating film 119 may be made of a negative-type or positive-type photosensitive resin film. The organic insulating film 119 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film.

[0347] The organic insulating film 119 preferably has a thickness greater than that of the inorganic insulating film 118. The organic insulating film 119 preferably has a thickness greater than that of the interlayer film 70. The organic insulating film 119 particularly preferably has a thickness greater than that of the gate electrode 80 and that of the source electrode 100. The thickness of the organic insulating film 119 may be 3 μm or more and 30 μm or less. The thickness of the organic insulating film 119 is preferably 20 μm or less.

[0348] The semiconductor device 1 includes a drain electrode 120 covering the second main surface 4. The drain electrode 120 may be referred to as a "drain pad," "drain pad electrode," "high potential pad electrode," or the like. The drain electrode 120 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 120 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain electrode 120 may cover the second main surface 4 so as to partially expose the periphery of the chip 2.

[0349] The breakdown voltage that can be applied between the source electrode 100 and the drain electrode 120 (between the first main surface 3 and the second main surface 4) may be 500 V or more. The breakdown voltage may be 600 V or more. The breakdown voltage may be 1000 V or more. The breakdown voltage may be 3000 V or more. The breakdown voltage may be 5000 V or less. Of course, the breakdown voltage may be 3000 V or less.

[0350] 24 is a circuit diagram showing the electrical configuration of the gate resistor RG. As shown in Fig. 24, the gate wiring 85 is electrically connected to the gate pad 81 via the gate resistor RG. The gate resistor RG is formed by a parallel circuit of a first parallel resistor circuit RC1 and a second parallel resistor circuit RC2.

[0351] The first parallel resistor circuit RC1 is electrically interposed between the gate pad 81 and the first resistor wiring 86 and is composed of a plurality of first resistor units 60A connected in parallel. The plurality of first resistor units 60A may have the same resistance value or different resistance values. The resistance value of each first resistor unit 60A can be adjusted by adjusting the distance between the first resistor opening 72A and the second resistor opening 72B on the first resistor unit 60A side.

[0352] The second parallel resistance circuit RC2 is electrically interposed between the gate pad 81 and the second resistance wiring 87 and is composed of a plurality of second resistance units 60B connected in parallel. The plurality of second resistance units 60B may have the same resistance value or different resistance values.

[0353] The second resistor portions 60B may have the same resistance value as the first resistor portions 60A, or may have a different resistance value from the first resistor portions 60A. The resistance value of each second resistor portion 60B can also be adjusted by adjusting the distance between the first resistor opening 72A and the second resistor opening 72B on the second resistor portion 60B side.

[0354] The resistance value of the gate resistor RG is determined by the combined resistance of the first parallel resistance circuit RC1 and the second parallel resistance circuit RC2. The resistance value of the first parallel resistance circuit RC1 is determined by the combined resistance of the multiple first resistance sections 60A. The resistance value of the first parallel resistance circuit RC1 may be adjusted by the resistance values ​​of the multiple first resistance sections 60A or by the number of the multiple first resistance sections 60A. The resistance value of the second parallel resistance circuit RC2 is determined by the combined resistance of the multiple second resistance sections 60B. The resistance value of the second parallel resistance circuit RC2 may be adjusted by the resistance values ​​of the multiple second resistance sections 60B or by the number of the multiple second resistance sections 60B.

[0355] The gate resistor RG does not necessarily have to include both the first parallel resistance circuit RC1 and the second parallel resistance circuit RC2 at the same time, and may be configured with only one of the first parallel resistance circuit RC1 and the second parallel resistance circuit RC2. Such a configuration can be realized by adjusting the presence or absence of the first resistor opening 72A and the second resistor opening 72B and the presence or absence of the first resistor wiring 86 and the second resistor wiring 87 at the layout level.

[0356] For example, if the gate resistor RG is composed only of the second parallel resistor circuit RC2, the gate pad 81 and the gate wiring 85 are electrically separated from the multiple first resistor units 60A. In this case, at least the first resistor opening 72A is removed on the first resistor unit 60A side. Of course, either or both of the second resistor opening 72B and the first resistor wiring 86 may be removed.

[0357] Similarly, when the gate resistance RG is composed of only the first parallel resistance circuit RC1, the gate pad 81 and the gate wiring 85 are electrically separated from the second resistance units 60B. In this case, at least the first resistance opening 72A is removed on the second resistance unit 60B side. Of course, either or both of the second resistance opening 72B and the second resistance wiring 87 may be removed.

[0358] The gate resistor RG slows down the switching speed during switching operations to suppress surge currents. In other words, the gate resistor RG suppresses noise caused by surge currents. Because the gate resistor RG is formed on the first main surface 3 (active surface 8), it is not externally connected to the semiconductor device 1. This reduces the number of components mounted on a circuit board.

[0359] Because the gate resistor RG includes a portion of the plurality of gate structures 20 (a plurality of first gate structures 20A) incorporated in the thickness direction of the chip 2, the area occupied by the gate resistor RG with respect to the first main surface 3 is limited. In particular, because the gate resistor RG utilizes a portion of at least one (a plurality in this embodiment) first gate structure 20A of the plurality of gate structures 20 as the resistance portion 60, there is no need to provide a separate area dedicated to the gate resistor RG on the first main surface 3 (active surface 8). Therefore, a reduction in the area of ​​the active region 12 resulting from the introduction of the gate resistor RG is suppressed.

[0360] The plurality of gate structures 20 includes a plurality of first gate structures 20A, a plurality of second gate structures 20B, and a plurality of third gate structures 20C. The plurality of first gate structures 20A each have a resistor portion 60 and are arranged in a pad region 55. The plurality of second gate structures 20B do not have a resistor portion 60 and are arranged in the pad region 55. The plurality of third gate structures 20C do not have a resistor portion 60 and are arranged outside the pad region 55.

[0361] The gate pad 81 is disposed in the pad region 55 at a distance from the plurality of third gate structures 20C, and covers the plurality of first gate structures 20A and the plurality of second gate structures 20B. The gate pad 81 is electrically connected to the resistor portions 60 of the plurality of first gate structures 20A.

[0362] The gate wiring 85 covers the resistor portions 60 of the plurality of first gate structures 20A at a distance from the gate pad 81, and is electrically connected to the gate pad 81 via the resistor portions 60 of the plurality of first gate structures 20A. The gate wiring 85 is further routed from the resistor portions 60 of the plurality of first gate structures 20A to regions outside the resistor portions 60, and is electrically connected to the plurality of first gate structures 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C.

[0363] That is, the plurality of first gate structures 20A, the plurality of second gate structures 20B, and the plurality of third gate structures 20C are controlled by the gate potential inside and outside the pad region 55. Therefore, the electric field distribution caused by the plurality of gate structures 20 inside the pad region 55 (directly below the gate pad 81) becomes similar to the electric field distribution caused by the plurality of gate structures 20 outside the pad region 55 (outside directly below the gate pad 81). As a result, a decrease in breakdown voltage caused by the layout of the plurality of gate structures 20 inside and outside the pad region 55 is suppressed.

[0364] The semiconductor device 1 also includes a plurality of source structures 25 arranged adjacent to the plurality of gate structures 20 inside and outside the pad region 55. The plurality of source structures 25 are controlled by source potentials inside and outside the pad region 55. Therefore, the electric field distribution caused by the plurality of source structures 25 inside the pad region 55 is the same as the electric field distribution caused by the plurality of source structures 25 outside the pad region 55. This suppresses a decrease in breakdown voltage caused by the layout of the plurality of source structures 25 inside the pad region 55.

[0365] As described above, the semiconductor device 1 includes the chip 2, the trench electrode type first gate structure 20A (gate structure 20), the gate pad 81 (pad electrode), and the gate wiring 85 (wiring electrode). The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.

[0366] The gate pad 81 is disposed on the first main surface 3 so as to overlap the resistor portion 60, and has a first electrical connection portion (a first resistor connection portion 83 and a second resistor connection portion 84 in this embodiment) to the resistor portion 60. The gate wiring 85 is disposed on the first main surface 3 so as to overlap the resistor portion 60 at a position different from the gate pad 81, and has a second electrical connection portion (a first resistor wiring portion 86 and a second resistor wiring portion 87 in this embodiment) to the resistor portion 60. The gate wiring 85 is electrically connected to the gate pad 81 via the resistor portion 60.

[0367] This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with a resistor. In particular, this configuration makes it possible to incorporate the resistor portion 60 into a part of the first gate structure 20A, and the gate pad 81 overlaps the resistor portion 60, eliminating the need to provide a separate region for the resistor on the first main surface 3. Therefore, it is possible to prevent the chip 2 from becoming too large in a configuration that includes a resistor.

[0368] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a trench electrode type second gate structure 20B (gate structure 20), and a gate pad 81 (pad electrode). The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.

[0369] The second gate structure 20B is formed on the first main surface 3 at a distance from the first gate structure 20A. Unlike the first gate structure 20A, the second gate structure 20B does not have a resistor portion 60. A gate pad 81 is disposed on the first main surface 3 so as to overlap the resistor portion 60 of the first gate structure 20A and the second gate structure 20B. The gate pad 81 has an electrical connection portion to the resistor portion 60 but does not have an electrical connection portion to the second gate structure 20B.

[0370] This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with resistors. In particular, this configuration makes it possible to relax design rule restrictions imposed by the resistor portion 60 for the second gate structure 20B, since the resistor portion 60 is not incorporated in the second gate structure 20B. Therefore, this configuration makes it possible to provide a unique concept (layout) for the multiple gate structures 20 arranged in the region directly below the gate pad 81, while also preventing the chip 2 from becoming larger in size in a configuration that includes resistors.

[0371] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a trench electrode type third gate structure 20C (gate structure 20), and a gate pad 81 (pad electrode). The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.

[0372] The third gate structure 20C is formed on the first main surface 3 at a distance from the first gate structure 20A, and unlike the first gate structure 20A, does not have a resistor portion 60. A gate pad 81 is arranged on the first main surface 3 so as to overlap the resistor portion 60 of the first gate structure 20A but not overlap the third gate structure 20C. The gate pad 81 has an electrical connection portion to the resistor portion 60, but does not have an electrical connection portion to the second gate structure 20B.

[0373] This configuration can provide a semiconductor device 1 having a novel layout associated with resistors. In particular, this configuration can relax design rule restrictions for the third gate structure 20C due to the resistor portion 60, since the resistor portion 60 is not incorporated in the third gate structure 20C. Therefore, this configuration can provide a unique concept (layout) for the multiple gate structures 20 arranged inside and outside the region directly below the gate pad 81, while also preventing the chip 2 from becoming larger in size in a configuration that includes resistors.

[0374] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a trench electrode type second gate structure 20B (gate structure 20), a trench electrode type third gate structure 20C (gate structure 20), and a gate pad 81 (pad electrode). The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.

[0375] The second gate structure 20B is formed on the first main surface 3 at a distance from the first gate structure 20A. Unlike the first gate structure 20A, the second gate structure 20B does not have a resistor portion 60. The third gate structure 20C is formed on the first main surface 3 at a distance from the first gate structure 20A and the second gate structure 20B. Unlike the first gate structure 20A, the third gate structure 20C does not have a resistor portion 60.

[0376] The gate pad 81 is arranged on the first main surface 3 so as to overlap the resistor portion 60 of the first gate structure 20A and the second gate structure 20B, but not overlap the third gate structure 20C. The gate pad 81 has an electrical connection portion to the resistor portion 60, but does not have an electrical connection portion to the second gate structure 20B or the third gate structure 20C.

[0377] This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with resistors. In particular, this configuration does not incorporate resistor portion 60 into second gate structure 20B and third gate structure 20C, so that design rule restrictions imposed by resistor portion 60 can be relaxed for second gate structure 20B and third gate structure 20C. Therefore, this configuration makes it possible to provide a unique concept (layout) for multiple gate structures 20 arranged inside and outside the region directly below gate pad 81, while simultaneously suppressing an increase in the size of chip 2 in a configuration including resistors.

[0378] From another perspective, the semiconductor device 1 includes a chip 2, an active plateau 11 (mesa portion), and a trench electrode-type first gate structure 20A (gate structure 20). The chip 2 has a first main surface 3. The active plateau 11 is defined on the first main surface 3 by an active surface 8 (first surface portion), an outer peripheral surface 9 (second surface portion), and first to fourth connection surfaces 10A to 10D (connection surface portions). The active surface 8 is located inside the first main surface 3. The outer peripheral surface 9 is recessed in the thickness direction outside the active surface 8. The first to fourth connection surfaces 10A to 10D connect the active surface 8 and the outer peripheral surface 9. The first gate structure 20A is formed on the active surface 8 and has a resistor portion 60.

[0379] This configuration can provide a semiconductor device 1 having a novel layout associated with a resistor. In particular, this configuration can prevent the electrical characteristics and layout on the outer peripheral surface 9 side from being limited by the layout of the first gate structure 20A, since the first gate structure 20A is disposed on the active surface 8.

[0380] From another perspective, the semiconductor device 1 includes a chip 2, a plurality of trench electrode type gate structures 20, an interlayer film 70, a gate pad 81 (pad electrode), and a gate wiring 85 (wiring electrode). The chip 2 has a first main surface 3. The gate structures 20 are formed on the first main surface 3. The interlayer film 70 covers the plurality of gate structures 20 on the first main surface 3.

[0381] The gate pad 81 is disposed on the interlayer film 70 so as to overlap at least one gate structure 20, and is electrically connected to at least one gate structure 20 through the interlayer film 70. The gate wiring 85 is disposed on the interlayer film 70 at a distance from the gate pad 81, and is electrically connected to at least one gate structure 20 through the interlayer film 70. The gate wiring 85 is electrically connected to the gate pad 81 via a portion of at least one gate structure 20.

[0382] This configuration makes it possible to provide a semiconductor device 1 having a novel layout associated with a resistor. In particular, this configuration makes it possible to adjust the resistance value between the gate pad 81 and the gate wiring 85 by adjusting the number of gate structures 20 electrically connected to the gate pad 81 and the gate wiring 85.

[0383] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode-type first gate structure 20A (gate structure 20), and a trench electrode-type source structure 25 (electrode structure). The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60. The source structure 25 is formed on the first main surface 3 so as to be adjacent to the first gate structure 20A.

[0384] This configuration makes it possible to provide the semiconductor device 1 having a novel layout associated with the resistor. In particular, this configuration makes it possible to adjust the electrical characteristics (such as the electric field strength) around the gate structure 20 by the source structure 25.

[0385] In such a configuration, the semiconductor device 1 preferably includes a resistive electrode 65 covering the resistive portion 60 of the first gate structure 20A at a distance from the source structure 25. For example, it is possible to form the source structure 25 deeper than the first gate structure 20A and form the resistive electrode 65 that electrically connects the first gate structure 20A and the source structure 25. In other words, it is possible to use the source structure 25 adjacent to the first gate structure 20A as part of the resistor.

[0386] In this case, since the source structure 25 functions as a resistor, the source structure 25 is required to have the same level of reliability as the first gate structure 20 A. In general, the process difficulty of a relatively deep trench structure is higher than the process difficulty of a relatively shallow trench structure.

[0387] Therefore, the process error that may occur in the relatively deep source structure 25 is larger than the process error that may occur in the relatively shallow first gate structure 20A. Examples of the process error that may occur in the first gate structure 20A include process errors that may occur in the depth of the first trench 21 and the film thickness of the first insulating film 22. Examples of the process error that may occur in the source structure 25 include process errors that may occur in the depth of the second trench 26 and the film thickness of the second insulating film 27.

[0388] Therefore, if the source structure 25 is used as a trench structure for another resistor, the electrical characteristics of the source structure 25 may be inferior to those of the first gate structure 20A due to process errors. This problem may be solved by imposing strict process conditions on the source structure 25. However, such a design change further increases the process difficulty, leading to increased costs.

[0389] In this regard, according to the configuration in which the source structure 25 is electrically separated from the first gate structure 20A, the resistance section 60 can be designed separately from the source structure 25, and the source structure 25 can be designed separately from the resistance section 60. Therefore, a decrease in the reliability of the resistance section 60 caused by the source structure 25 can be suppressed, and a decrease in the reliability of the source structure 25 caused by the resistance section 60 can be suppressed.

[0390] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode-type first gate structure 20A (gate structure 20), and a trench electrode-type side edge structure 30 (electrode structure). The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 in a strip shape extending in a first direction X, and has a resistor portion 60. The side edge structure 30 is formed on the first main surface 3 at a distance from the first gate structure 20A in the first direction X, and is supplied with a potential (source potential) different from that of the first gate structure 20A.

[0391] This configuration can provide a semiconductor device 1 having a novel layout associated with a resistor. In particular, this configuration can adjust the electrical characteristics (such as the electric field strength) around the first gate structure 20A by the side edge structure 30.

[0392] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode-type first gate structure 20A (gate structure 20), a trench electrode-type source structure 25 (first electrode structure), and a trench electrode-type side edge structure 30 (second electrode structure). The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 and has a resistor portion 60.

[0393] The source structure 25 is formed on the first main surface 3 at a distance from the first gate structure 20A in one direction (second direction Y), and is supplied with a potential (source potential) different from that of the first gate structure 20A. The side edge structure 30 is formed on the first main surface 3 at a distance from the first gate structure 20A in an orthogonal direction (first direction X) perpendicular to the one direction, and is supplied with a potential (source potential) different from that of the first gate structure 20A.

[0394] This configuration can provide the semiconductor device 1 having a novel layout associated with the resistor. In particular, this configuration can adjust the electrical characteristics (e.g., electric field strength) around the first gate structure 20A by the source structure 25 and the side edge structure 30.

[0395] From another perspective, the semiconductor device 1 includes a chip 2, a trench electrode type first gate structure 20A (gate structure 20), a gate pad 81 (pad electrode), and a pad insulating film 110. The chip 2 has a first main surface 3. The first gate structure 20A is formed on the first main surface 3 and partially includes a resistor portion 60.

[0396] The gate pad 81 is disposed on the first main surface 3 so as to overlap the resistor portion 60, and has a first resistor connection portion 83 (second resistor connection portion 84) that is an electrical connection portion to the resistor portion 60. The pad insulating film 110 covers the first resistor connection portion 83 (second resistor connection portion 84) of the gate pad 81, and has a gate pad opening 111 that exposes an area of ​​the gate pad 81 outside the first resistor connection portion 83 (second resistor connection portion 84).

[0397] This configuration makes it possible to provide the semiconductor device 1 having a novel layout associated with the resistor. In particular, this configuration makes it possible to protect the first resistor connection portion 83 (second resistor connection portion 84) by the pad insulating film 110. This prevents peeling of the first resistor connection portion 83 (second resistor connection portion 84) and prevents poor connection of the gate pad 81 to the resistor portion 60.

[0398] From another perspective, the semiconductor device 1 includes a gate pad 81, a gate wiring 85, and a gate resistor RG. The gate wiring 85 is physically separated from the gate pad 81. The gate resistor RG has a first parallel resistance circuit RC1 (a second parallel resistance circuit RC2) including a plurality of resistance portions 60 (resistance elements), and is electrically interposed between the gate pad 81 and the gate wiring 85.

[0399] This configuration makes it possible to provide the semiconductor device 1 having a novel layout associated with the resistors. In particular, this configuration makes it possible to adjust the resistance value of the gate resistor RG by adjusting the resistance values ​​and number of the multiple resistor sections 60.

[0400] In such a configuration, the plurality of resistance portions 60 are preferably formed by utilizing portions of the plurality of trench electrode type gate structures 20. The gate resistor RG may have a first parallel resistance circuit RC1 including a plurality of resistance portions 60 (first resistance portions 60A), and a second parallel resistance circuit RC2 including a plurality of resistance portions 60 (second resistance portions 60B) and connected in parallel to the first parallel resistance circuit RC1.

[0401] The layout of the semiconductor device 1 is particularly effective when a chip 2 including a SiC single crystal is employed. The layout of the semiconductor device 1 provides various ideas that contribute to improving electrical characteristics from various perspectives for designs associated with resistance in SiC semiconductor devices (wide bandgap semiconductor devices).

[0402] 25 is an enlarged plan view showing a main part of FIG. 19 together with a first gate structure 20A according to layout example 2. In layout example 1, the resistor portion 60 of each first gate structure 20A is covered with a plurality of resistor electrodes 65 (first resistor electrodes 65A and second resistor electrodes 65B).

[0403] In contrast, in the second layout example, the resistor portion 60 of each first gate structure 20A is covered by a single resistor electrode 65. In the following, the configuration of the first resistor portion 60A side will be described, and a description of the second resistor portion 60B side will be omitted. The description of the second resistor portion 60B side can be obtained by replacing "first resistor portion 60A" with "second resistor portion 60B" in the following description.

[0404] The plurality of resistive electrodes 65 are provided at the intersections of one side (the third side surface 5C side) of the pad region 55 and the first gate structures 20A. The plurality of resistive electrodes 65 are provided so as to straddle the regions inside and outside the pad region 55, and have first electrical electrode ends 121 located inside the pad region 55 and second electrical electrode ends 122 located outside the pad region 55.

[0405] Each of the plurality of resistive electrodes 65 covers a corresponding one of the first resistor portions 60A as a single coating target in the form of a film, and is electrically connected to the corresponding one of the first resistor portions 60A. In other words, each of the resistive electrodes 65 is provided in a one-to-one correspondence with each of the resistor portions 60. In this embodiment, the plurality of resistive electrodes 65 are each formed in a strip shape extending in the first direction X in plan view, and face each other in the second direction Y. In other words, the plurality of resistive electrodes 65 are arranged in a strip shape extending along the plurality of first resistor portions 60A in plan view.

[0406] Each resistive electrode 65 covers the first end 61 and the second end 62 of the corresponding first resistive portion 60A. Specifically, the first electrode end 121 of each resistive electrode 65 covers the first end 61 of the corresponding first resistive portion 60A, and the second electrode end 122 of each resistive electrode 65 covers the second end 62 of the corresponding first resistive portion 60A. In other words, each resistive electrode 65 has a layout in which the first resistive electrode 65A and the second resistive electrode 65B according to the first layout example are integrally formed.

[0407] The multiple resistive electrodes 65 are arranged at intervals in the second direction Y from other resistive electrodes 65 that cover the resistive portions 60 that are not to be covered. The multiple resistive electrodes 65 are arranged at intervals in the second direction Y from the multiple source structures 25, exposing the multiple source structures 25. In other words, the multiple resistive electrodes 65 are arranged alternately with the multiple source structures 25 in the second direction Y in a plan view.

[0408] Each resistive electrode 65 exposes a region (first buried electrode 23) other than the resistive portion 60 of the corresponding first gate structure 20A. That is, each resistive electrode 65 covers the corresponding first gate structure 20A at a distance from the gate connection electrode 53 in the first direction X, and faces the corresponding gate connection electrode 53 along the corresponding first gate structure 20A. Each resistive electrode 65 exposes the first buried electrode 23 from between itself and the corresponding gate connection electrode 53.

[0409] The plurality of resistive electrodes 65 have portions facing the plurality of second gate structures 20B in the second direction Y. First electrode ends 121 of the plurality of resistive electrodes 65 do not face the gate connection electrodes 53 on the second gate structure 20B side in the second direction Y. In this embodiment, second electrode ends 122 of the plurality of resistive electrodes 65 face the plurality of gate connection electrodes 53 on the second gate structure 20B side in the second direction Y.

[0410] That is, the multiple resistive electrodes 65 have portions that are located on the same straight line extending in the second direction Y as the multiple gate connection electrodes 53 on the second gate structure 20B side. Of course, the multiple resistive electrodes 65 may be formed so as to be shifted in the first direction X from the straight line connecting the multiple gate connection electrodes 53 in the second direction Y so as not to face the multiple gate connection electrodes 53 on the second gate structure 20B side in the second direction Y. Other configurations of the resistive electrodes 65 are the same as those in the first layout example.

[0411] In this embodiment, the first resistor openings 72A expose first electrode ends 121 of the resistor electrodes 65, respectively. The second resistor openings 72B expose second electrode ends 122 of the resistor electrodes 65, respectively. The gate pad 81 is electrically connected to the first electrode ends 121 of the resistor electrodes 65 in the first resistor openings 72A, respectively. The gate wiring 85 (first resistor wiring 86 and second resistor wiring 87) is electrically connected to the second electrode ends 122 of the resistor electrodes 65 in the second resistor openings 72B, respectively.

[0412] 26 is an enlarged plan view showing a main portion of FIG. 18 together with a first gate structure 20A according to a third layout example. In the first layout example, the resistor portion 60 of each first gate structure 20A is covered with a plurality of resistor electrodes 65 (first resistor electrodes 65A and second resistor electrodes 65B). In contrast, in the third layout example, the resistor portion 60 of each first gate structure 20A is not covered with a resistor electrode 65. Such a configuration may be adopted.

[0413] Other embodiments of the chip 2 are shown below. Fig. 27 is a cross-sectional view showing another embodiment of the chip 2. Referring to Fig. 27, the semiconductor device 1 may include a second semiconductor region 7 thinner than the first semiconductor region 6 inside the chip 2. In other words, the chip 2 may include an epitaxial layer thicker than the semiconductor substrate.

[0414] The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less (preferably 5 μm or more and 25 μm or less). The second semiconductor region 7 may have a thickness of 0.1 μm or more and less than 50 μm. The thickness of the second semiconductor region 7 may be 5 μm or more (preferably 10 μm or more).

[0415] FIG. 28 is a cross-sectional view showing another embodiment of the chip 2. Referring to FIG. 28, the semiconductor device 1 may include only the first semiconductor region 6 without the second semiconductor region 7 inside the chip 2. In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D of the chip 2. That is, in this embodiment, the chip 2 does not include a semiconductor substrate and has a single-layer structure made of an epitaxial layer. The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less (preferably 5 μm or more and 25 μm or less).

[0416] The above-described embodiment may be implemented in other embodiments. For example, in the above-described embodiment, the pad region 55 (gate pad 81) is located on an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. However, the pad region 55 (gate pad 81) may be positioned to one side or the other in the first direction X with respect to the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.

[0417] In this case, the pad region 55 (gate pad 81) may be disposed at any corner of the active surface 8 in a plan view. Of course, the pad region 55 (gate pad 81) may also be disposed at the center of the active surface 8 in a plan view.

[0418] In the above embodiment, an example has been shown in which the gate wiring 85 includes the third line wiring 92. However, the gate wiring 85 may be configured without the third line wiring 92. In this case, the first source pad 101A and the second source pad 101B of the source pad 101 may be integrally formed.

[0419] In the above-described embodiment, an example has been shown in which the gate pad 81 penetrates the interlayer film 70 (through the resistor opening 72) and is connected to the resistor electrode 65. For example, as another example of such a connection form, the gate pad 81 may be connected to the resistor electrode 65 through a via electrode embedded in the interlayer film 70 (through the resistor opening 72).

[0420] In the above-described embodiment, an example has been shown in which the gate wiring 85 penetrates the interlayer film 70 (through the resistor opening 72) and is connected to the resistor electrode 65. For example, as another example of such a connection form, the gate wiring 85 may be connected to the resistor electrode 65 through a via electrode embedded in the interlayer film 70 (resistor opening 72). Similarly, the gate wiring 85 may be connected to the gate structure 20 (gate connection electrode 53) through a via electrode embedded in the interlayer film 70 (gate opening 71).

[0421] In the above embodiment, an example has been shown in which the source pad 101 is connected to the source structure 25 through the interlayer film 70 (via the source opening 73). For example, as another example of such a connection form, the source pad 101 may be connected to the source structure 25 via a via electrode embedded in the interlayer film 70 (source opening 73).

[0422] For example, in these connection examples, the via electrode may include a via body electrode (e.g., W-based metal) embedded in the interlayer film 70 (resistor opening 72) via a barrier electrode film (e.g., Ti-based metal film).

[0423] In the above-described embodiments, a structure may be adopted in which the conductivity type of an "n-type" semiconductor region is inverted to "p-type" and the conductivity type of a "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0424] In the above-described embodiment, the n-type second semiconductor region 7 is shown. However, a p-type second semiconductor region 7 may be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0425] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0426] [A1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B); a pad electrode (81) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) and having a first electrical connection portion (83, 84) to the resistor portion (60, 60A, 60B); and a wiring electrode (85) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) at a position different from the pad electrode (81), having a second electrical connection portion (86, 87) to the resistor portion (60, 60A, 60B) and electrically connected to the pad electrode (81) via the resistor portion (60, 60A, 60B).

[0427] [A2] The semiconductor device (1) according to A1, wherein the chip (2) is a wide bandgap semiconductor chip (2).

[0428] [A3] The semiconductor device (1) according to A2, wherein the chip (2) is a SiC chip (2).

[0429] [A4] A semiconductor device (1) according to any one of A1 to A3, wherein the wiring electrode (85) has an electrical connection portion (90, 91) to a portion of the gate structure (20, 20A) other than the resistance portion (60, 60A, 60B).

[0430] [A5] The semiconductor device (1) described in A4 further includes a gate connection electrode (53) that selectively covers a portion of the gate structure (20, 20A) other than the resistance portion (60, 60A, 60B), and the wiring electrode (85) is electrically connected to the portion of the gate structure (20, 20A) other than the resistance portion (60, 60A, 60B) via the gate connection electrode (53).

[0431] [A6] A semiconductor device (1) according to any one of A1 to A5, in which a plurality of gate structures (20, 20A) each having the resistance portion (60, 60A, 60B) are formed, the pad electrode (81) has a plurality of first connection portions (83, 84) to the plurality of resistance portions (60, 60A, 60B), and the wiring electrode (85) has a plurality of second connection portions (86, 87) to the plurality of resistance portions (60, 60A, 60B).

[0432] [A7] The semiconductor device (1) according to A6, wherein the wiring electrode (85) connects the plurality of resistor portions (60, 60A, 60B) in parallel together with the pad electrode (81).

[0433] [A8] The semiconductor device (1) according to A6 or A7, wherein the plurality of gate structures (20, 20A) are arranged at intervals so that the plurality of resistor portions (60, 60A, 60B) are positioned on the same straight line.

[0434] [A9] The semiconductor device (1) according to any one of A1 to A8, further including a channel formed in a region along a portion of the gate structure (20, 20A) outside the resistor portion (60, 60A, 60B) in a surface layer portion of the main surface (3).

[0435] [A10] The semiconductor device (1) according to A9, wherein the channel is also formed in a region of the gate structure (20, 20A) along the resistor portion (60, 60A, 60B) in the surface layer portion of the main surface (3).

[0436] [A11] The semiconductor device (1) according to A8 or A9, further comprising a channel pad electrode (101) arranged on the main surface (3) at a distance from the pad electrode (81) and the wiring electrode (85) so as to overlap the channel, and having an electrical connection portion to the channel.

[0437] [A12] The semiconductor device (1) according to A11, wherein the channel pad electrode (101) is arranged on the main surface (3) so as to overlap the gate structure (20, 20A).

[0438] [A13] The semiconductor device (1) according to any one of A1 to A12, further comprising at least one resistive electrode (65, 65A, 65B) covering the resistive portion (60, 60A, 60B), wherein the first connecting portion (83, 84) of the pad electrode (81) is electrically connected to the resistive portion (60, 60A, 60B) via the resistive electrode (65, 65A, 65B), and the second connecting portion (86, 87) of the wiring electrode (85) is electrically connected to the resistive portion (60, 60A, 60B) via the resistive electrode (65, 65A, 65B).

[0439] [A14] The semiconductor device (1) according to any one of A1 to A13, further comprising a trench electrode type source structure (25) formed on the main surface (3) adjacent to the gate structure (20, 20A), and the pad electrode (81) overlaps the source structure (25).

[0440] [A15] The semiconductor device (1) according to A14, wherein the wiring electrode (85) overlaps the source structure (25).

[0441] [A16] A semiconductor device (1) according to any one of A1 to A15, further comprising a pad insulating film (110) that selectively covers the pad electrode (81) and has a pad opening (111) that partially exposes the pad electrode (81).

[0442] [A17] A semiconductor device (1) described in A16, wherein the pad insulating film 110 partially faces the resistor portion (60, 60A, 60B) across the first connection portion (83, 84) of the pad electrode (81), and exposes portions of the pad electrode (81) other than the first connection portion (83, 84).

[0443] [A18] A semiconductor device (1) according to A16 or A17, wherein the pad insulating film 110 partially faces the resistor portion (60, 60A, 60B) across the second connection portion (86, 87) of the wiring electrode (85).

[0444] [A19] The semiconductor device (1) according to any one of A1 to A18, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); and an impurity region (18) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), wherein the gate structure (20, 20A) penetrates the impurity region (18) so as to reach the semiconductor region (6).

[0445] [A20] The semiconductor device (1) according to A19, further comprising a second conductivity type (p-type) well region (41) formed in a surface portion of the main surface (3) in a region along the wall surface of the gate structure (20, 20A).

[0446] [B1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode-type first gate structure (20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B); a trench electrode-type second gate structure (20B) formed on the main surface (3) at a distance from the first gate structure (20A) and not having the resistor portion (60, 60A, 60B); and a pad electrode (81) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) of the first gate structure (20A) and the second gate structure (20B), having electrical connection portions (83, 84) to the resistor portion (60, 60A, 60B) but not having an electrical connection portion to the second gate structure (20B).

[0447] [B2] The semiconductor device (1) according to B1, wherein at least one of the first gate structures (20A) is formed on the main surface (3), and a greater number of the second gate structures (20B) than the number of the first gate structures (20A) are formed on the main surface (3).

[0448] [B3] The semiconductor device (1) according to B1 or B2, wherein the second gate structure (20B) has a depth (D1) substantially equal to the depth (D1) of the first gate structure (20A).

[0449] [B4] The semiconductor device (1) according to any one of B1 to B3, wherein the second gate structure (20B) has a width (W1) approximately equal to the width (W1) of the first gate structure (20A).

[0450] [B5] The semiconductor device (1) according to any one of B1 to B4, further including a wiring electrode (85) arranged on the main surface (3) at a distance from the pad electrode (81), having an electrical connection portion (86, 87) to the resistor portion (60, 60A, 60B), and electrically connected to the pad electrode (81) via the resistor portion (60, 60A, 60B).

[0451] [B6] The semiconductor device (1) described in B5, wherein the wiring electrode (85) has an electrical connection portion (90, 91) to a portion of the first gate structure (20A) other than the resistance portion (60, 60A, 60B).

[0452] [B7] The semiconductor device (1) according to B5 or B6, wherein the wiring electrode (85) has an electrical connection portion (90, 91) to the second gate structure (20B).

[0453] [B8] The semiconductor device (1) according to any one of B5 to B7, further comprising a gate connection electrode (53) that selectively covers the second gate structure (20B), and the wiring electrode (85) is electrically connected to the second gate structure (20B) via the gate connection electrode (53).

[0454] [B9] The semiconductor device (1) according to any one of B5 to B8, further including a wiring-side electrode film (65, 65B) that selectively covers the resistor portion (60, 60A, 60B), and the wiring electrode (85) is electrically connected to the resistor portion (60, 60A, 60B) via the wiring-side electrode film (65, 65B).

[0455] [B10] The semiconductor device (1) according to any one of B1 to B9, further including a pad-side electrode film (65, 65A) that selectively covers the resistor portion (60, 60A, 60B), and the pad electrode (81) is electrically connected to the resistor portion (60, 60A, 60B) via the pad-side electrode film (65, 65A).

[0456] [B11] The semiconductor device (1) according to any one of B1 to B10, further comprising a trench electrode type third gate structure (20C) formed on the main surface (3) at a distance from the first gate structure (20A) and the second gate structure (20B) and not having the resistance portion (60, 60A, 60B), wherein the pad electrode (81) is arranged on the main surface (3) so as not to overlap the third gate structure (20C), and not having an electrical connection portion to the third gate structure (20C).

[0457] [B12] The semiconductor device (1) according to any one of B1 to B11, further comprising a trench electrode type electrode structure (25) formed in a region between the first gate structure (20A) and the second gate structure (20B) on the main surface (3) and to which a potential different from that of the first gate structure (20A) and the second gate structure (20B) is applied, and the pad electrode (81) overlaps the electrode structure (25).

[0458] [B13] The semiconductor device (1) according to B12, wherein the electrode structure (25) has a depth (D2) equal to or greater than the depth (D1) of the first gate structure (20A).

[0459] [B14] The semiconductor device (1) according to B12 or B13, wherein the electrode structure (25) has a width (W2) equal to or greater than the width (W1) of the first gate structure (20A).

[0460] [B15] The semiconductor device (1) according to any one of B12 to B14, wherein the electrode structure (25) is a source structure (25) to which a source potential is applied.

[0461] [B16] The semiconductor device (1) according to any one of B12 to B15, further comprising a different potential pad electrode (101) arranged on the main surface (3) at a distance from the pad electrode (81) so as to overlap the electrode structure (25), and having an electrical connection portion to the electrode structure (25).

[0462] [B17] The semiconductor device (1) according to B16, wherein the different potential pad electrode (101) overlaps the first gate structure (20A) at a position different from that of the pad electrode (81).

[0463] [B18] The semiconductor device (1) according to any one of B1 to B17, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); and an impurity region (18) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), wherein the first gate structure (20A) penetrates the impurity region (18) to reach the semiconductor region (6), and the second gate structure (20B) penetrates the impurity region (18) to reach the semiconductor region (6).

[0464] [B19] The semiconductor device (1) according to B18, further comprising: a first well region (41) of a second conductivity type (p-type) formed in a region along a wall surface of the first gate structure (20A) in a surface layer portion of the main surface (3); and a second well region (41) of a second conductivity type (p-type) formed in a region along a wall surface of the second gate structure (20B) in a surface layer portion of the main surface (3).

[0465] [B20] The semiconductor device (1) according to any one of B1 to B19, wherein the chip (2) is a wide bandgap semiconductor chip (2).

[0466] [C1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type first gate structure (20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B); a trench electrode type second gate structure (20C) formed on the main surface (3) at a distance from the first gate structure (20A) and not having the resistor portion (60, 60A, 60B); and a pad electrode (81) overlapping the resistor portion (60, 60A, 60B) of the first gate structure (20A) and disposed on the main surface (3) so as not to overlap the second gate structure (20C), having electrical connection portions (83, 84) to the resistor portion (60, 60A, 60B), but not having an electrical connection portion to the second gate structure (20C).

[0467] [C2] The semiconductor device (1) described in C1, wherein at least one of the first gate structures (20A) is formed on the main surface (3), and a greater number of the second gate structures (20C) than the number of the first gate structures (20A) are formed on the main surface (3).

[0468] [C3] The semiconductor device (1) according to C1 or C2, wherein the second gate structure (20C) has a depth (D1) substantially equal to the depth (D1) of the first gate structure (20A).

[0469] [C4] A semiconductor device (1) according to any one of C1 to C3, wherein the second gate structure (20C) has a width (W1) approximately equal to the width (W1) of the first gate structure (20A).

[0470] [C5] A semiconductor device (1) according to any one of C1 to C4, further including a wiring electrode (85) arranged on the main surface (3) at a distance from the pad electrode (81), having an electrical connection portion (86, 87) to the resistor portion (60, 60A, 60B), and electrically connected to the pad electrode (81) via the resistor portion (60, 60A, 60B).

[0471] [C6] The semiconductor device (1) according to C5, wherein the wiring electrode (85) has an electrical connection portion (90, 91) to a portion of the first gate structure (20A) other than the resistance portion (60, 60A, 60B).

[0472] [C7] The semiconductor device (1) according to C5 or C6, wherein the wiring electrode (85) has an electrical connection portion (90, 91, 92) to the second gate structure (20C).

[0473] [C8] The semiconductor device (1) according to any one of C5 to C7, further comprising a gate connection electrode (53) that selectively covers the second gate structure (20C), and the wiring electrode (85) is electrically connected to the second gate structure (20C) via the gate connection electrode (53).

[0474] [C9] The semiconductor device (1) according to any one of C5 to C8, further including a wiring-side electrode film (65, 65B) that selectively covers the resistor portion (60, 60A, 60B), and the wiring electrode (85) is electrically connected to the resistor portion (60, 60A, 60B) via the wiring-side electrode film (65, 65B).

[0475] [C10] The semiconductor device (1) according to any one of C1 to C9, further including a pad-side electrode film (65, 65A) that selectively covers the resistor portion (60, 60A, 60B), and the pad electrode (81) is electrically connected to the resistor portion (60, 60A, 60B) via the pad-side electrode film (65, 65A).

[0476] [C11] The semiconductor device (1) according to any one of C1 to C10, further comprising a trench electrode type third gate structure (20B) formed on the main surface (3) at a distance from the first gate structure (20A) and the second gate structure (20C) in a region between the first gate structure (20A) and the second gate structure (20C), and not having the resistance portion (60, 60A, 60B), wherein the pad electrode (81) is arranged on the main surface (3) so as to overlap the third gate structure (20B), and not having an electrical connection portion to the third gate structure (20B).

[0477] [C12] The semiconductor device (1) according to any one of C1 to C11, further comprising a trench electrode type electrode structure (25) formed on the main surface (3) adjacent to the second gate structure (20C) and to which a potential different from that of the second gate structure (20C) is applied, and the pad electrode (81) is arranged on the main surface (3) so as not to overlap the electrode structure (25).

[0478] [C13] The semiconductor device (1) according to C12, wherein the electrode structure (25) has a depth (D2) equal to or greater than the depth (D1) of the first gate structure (20A).

[0479] [C14] The semiconductor device (1) according to C12 or C13, wherein the electrode structure (25) has a width (W2) equal to or greater than the width (W1) of the first gate structure (20A).

[0480] [C15] The semiconductor device (1) according to any one of C12 to C14, wherein the electrode structure (25) is a source structure (25) to which a source potential is applied.

[0481] [C16] The semiconductor device (1) according to any one of C12 to C15, further comprising a different potential pad electrode (101) arranged on the main surface (3) at a distance from the pad electrode (81) so as to overlap the electrode structure (25), and having an electrical connection portion to the electrode structure (25).

[0482] [C17] The semiconductor device (1) according to C16, wherein the different potential pad electrode (101) overlaps the first gate structure (20A) at a position different from that of the pad electrode (81).

[0483] [C18] The semiconductor device (1) according to any one of C1 to C17, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); and an impurity region (18) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), wherein the first gate structure (20A) penetrates the impurity region (18) to reach the semiconductor region (6), and the second gate structure (20C) penetrates the impurity region (18) to reach the semiconductor region (6).

[0484] [C19] The semiconductor device (1) according to C18, further comprising: a first well region (41) of a second conductivity type (p-type) formed in a region along a wall surface of the first gate structure (20A) in a surface layer portion of the main surface (3); and a second well region (41) of a second conductivity type (p-type) formed in a region along a wall surface of the second gate structure (20C) in a surface layer portion of the main surface (3).

[0485] [C20] A chip (2) having a main surface (3), a trench electrode type first gate structure (20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B), a trench electrode type second gate structure (20B) formed on the main surface (3) at a distance from the first gate structure (20A) and not having the resistor portion (60, 60A, 60B), and a gate structure (20B) formed on the main surface (3) at a distance from the first gate structure (20A) and the second gate structure (20B) and having the resistor portion (60, 60A, 60B). and a pad electrode (81) that overlaps the resistor portion (60, 60A, 60B) of the first gate structure (20A) and the second gate structure (20B) and is disposed on the main surface (3) so as not to overlap the third gate structure (20C), has electrical connection portions (83, 84) to the resistor portion (60, 60A, 60B), and has no electrical connection portions to the second gate structure (20B) and the third gate structure (20C).

[0486] [D1] A semiconductor device (1) comprising: a chip (2) having a main surface (3); a mesa portion (11) defined on the main surface (3) by a first surface portion (8) located inside the main surface (3), a second surface portion (9) recessed in the thickness direction outside the first surface portion (8), and connection surface portions (10A-10D) connecting the first surface portion (8) and the second surface portion (9); and a trench electrode type gate structure (20, 20A) formed on the first surface portion (8) and having a resistor portion (60, 60A, 60B).

[0487] [D2] A semiconductor device (1) as described in D1, including a pad electrode (81) arranged on the first surface portion (8) so as to be electrically connected to the resistance portion (60, 60A, 60B), and a wiring electrode (85) arranged on the first surface portion (8) so as to be electrically connected to the resistance portion (60, 60A, 60B) at a position different from the pad electrode (81).

[0488] [D3] The semiconductor device (1) according to D2, wherein the pad electrode (81) is arranged on the first surface portion (8) at a distance inward from the connection surface portion (10A to 10D).

[0489] [D4] A semiconductor device (1) according to D2 or D3, wherein the wiring electrode (85) is arranged on the first surface portion (8) at a distance inward from the connection surface portion (10A to 10D).

[0490] [D5] A semiconductor device (1) according to any one of D1 to D4, wherein the gate structure (20, 20A) has a depth (D1) that is less than the depth (DO) of the second surface portion (9).

[0491] [D6] A semiconductor device (1) according to any one of D1 to D5, further including a trench electrode type electrode structure (25, 30) formed on the first surface portion (8) adjacent to the gate structure (20, 20A) and to which a potential different from that of the gate structure (20, 20A) is applied.

[0492] [D7] The semiconductor device (1) described in D6, wherein the gate structure (20, 20A) is formed in a strip shape extending in a first direction (X), and the electrode structure (25) is formed on the first surface portion (8) at a distance from the gate structure (20, 20A) in a second direction (Y) perpendicular to the first direction (X), and is formed in a strip shape extending in the first direction (X).

[0493] [D8] The semiconductor device (1) according to D7, wherein the electrode structure (25) has a length in the first direction (X) that is greater than the length of the gate structure (20, 20A).

[0494] [D9] The semiconductor device (1) according to D7 or D8, wherein the electrode structure (25) penetrates the connection surface portion (10A to 10D).

[0495] [D10] A semiconductor device (1) according to any one of D7 to D9, further comprising a different potential pad electrode (101) arranged on the first surface portion (8) so as to be electrically connected to the electrode structure (25), and to which a different potential than that of the gate structure (20, 20A) is applied.

[0496] [D11] The semiconductor device (1) described in D6, wherein the gate structure (20, 20A) is formed on the first surface portion (8) at a distance from the connection surface portion (10A to 10D), and the electrode structure (30) is formed in a region on the first surface portion (8) between the connection surface portion (10A to 10D) and the gate structure (20, 20A).

[0497] [D12] The semiconductor device (1) described in D11, wherein the gate structure (20, 20A) is formed in a strip shape extending in a first direction (X), and the electrode structure (30) is formed at a distance from the gate structure (20, 20A) in the first direction (X) and faces the gate structure (20, 20A) in the first direction (X).

[0498] [D13] The semiconductor device (1) according to D12, wherein the electrode structure (30) has a length in the first direction (X) that is shorter than the length of the gate structure (20, 20A).

[0499] [D14] The semiconductor device (1) according to D12 or D13, wherein the electrode structure (30) has a length in the first direction (X) that is greater than the length of the resistor portion (60, 60A, 60B).

[0500] [D15] The semiconductor device (1) according to any one of D11 to D14, wherein the electrode structure (30) penetrates the connection surface portion (10A to 10D).

[0501] [D16] A semiconductor device (1) according to any one of D11 to D15, further comprising a different potential pad electrode (101) arranged on the first surface portion (8) at a distance from the electrode structure (30) and to which a different potential than that of the gate structure (20, 20A) is applied.

[0502] [D17] The semiconductor device (1) described in any one of D1 to D5 further includes a trench electrode type first electrode structure (25) formed on the first surface portion (8) so as to be adjacent to the gate structure (20, 20A) in one direction (Y) and to which a potential different from that of the gate structure (20, 20A) is applied, and a trench electrode type second electrode structure (30) formed on the first surface portion (8) so as to be adjacent to the gate structure (20, 20A) in an orthogonal direction (X) perpendicular to the one direction (Y) and to which a potential different from that of the gate structure (20, 20A) is applied.

[0503] [D18] The semiconductor device (1) described in D17, wherein the gate structure (20, 20A) is formed at a distance from the connection surface portion (10A to 10D), and the second electrode structure (30) is formed in a region between the connection surface portion (10A to 10D) and the gate structure (20, 20A).

[0504] [D19] A semiconductor device (1) according to any one of D1 to D18, further comprising a sidewall structure (51) arranged on the second surface portion (9) so as to cover the connection surface portion (10A to 10D).

[0505] [D20] The semiconductor device (1) according to D19, wherein the sidewall structure (51) is made of wiring that transmits a potential different from that of the gate structure (20, 20A).

[0506] [E1] A semiconductor device (1) including: a chip (2) having a main surface (3); a plurality of trench electrode type gate structures (20) formed on the main surface (3); an interlayer film (70) covering the plurality of gate structures (20) on the main surface (3); a pad electrode (81) arranged on the interlayer film (70) so as to overlap at least one of the gate structures (20) and electrically connected to at least one of the gate structures (20) through the interlayer film (70); and a wiring electrode (85) arranged on the interlayer film (70) at a distance from the pad electrode (81), electrically connected to at least one of the gate structures (20) through the interlayer film (70), and electrically connected to the pad electrode (81) via a portion of at least one of the gate structures (20).

[0507] [E2] The semiconductor device (1) described in E1, wherein the pad electrode (81) is electrically connected to a plurality of the gate structures (20), and the wiring electrode (85) is electrically connected to the pad electrode (81) via a plurality of the gate structures (20).

[0508] [E3] The semiconductor device (1) according to E1 or E2, further comprising: a plurality of first electrode films (65A) covering the plurality of gate structures (20), respectively; and a plurality of second electrode films (65B) covering the plurality of gate structures (20, 20A) at intervals from the plurality of first electrode films (65A), wherein the interlayer film (70) covers the plurality of first electrode films (65A) and the plurality of second electrode films (65B), the pad electrode (81) is disposed on the interlayer film (70) so as to overlap the plurality of first electrode films (65A) and is electrically connected to the plurality of gate structures (20, 20A) via the plurality of first electrode films (65A), and the wiring electrode (85) is disposed on the interlayer film (70) so as to overlap the plurality of second electrode films (65B) and is electrically connected to the plurality of gate structures (20, 20A) via the plurality of second electrode films (65B).

[0509] [E4] The semiconductor device (1) according to E3, wherein the plurality of first electrode films (65A) are arranged at intervals so as to be positioned on the same straight line.

[0510] [E5] The semiconductor device (1) according to E3 or E4, wherein the plurality of second electrode films (65B) are arranged at intervals so as to be positioned on the same straight line.

[0511] [F1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B); and a trench electrode type source structure (25) formed on the main surface (3) adjacent to the gate structure (20, 20A).

[0512] [F2] The semiconductor device (1) according to F1, further comprising a resistive electrode (65, 65A, 65B) covering the resistive portion (60, 60A, 60B) of the gate structure (20, 20A) at a distance from the source structure (25).

[0513] [F3] A semiconductor device (1) according to F1 or F2, wherein the source structure (25) has a portion facing the resistor portion (60, 60A, 60B) of the gate structure (20, 20A) across a portion of the chip (2).

[0514] [F4] A semiconductor device (1) according to any one of F1 to F3, wherein the source structure (25) has a portion that faces a portion of the gate structure (20, 20A) outside the resistor portion (60, 60A, 60B) across a portion of the chip (2).

[0515] [F5] The semiconductor device (1) according to any one of F1 to F4, wherein the source structure (25) faces the entire area of ​​the gate structure (20, 20A) across a portion of the chip (2).

[0516] [F6] The semiconductor device (1) according to any one of F1 to F5, further comprising a source pad (101) arranged on the main surface (3) so as to partially overlap the source structure (25) and electrically connected to the source structure (25).

[0517] [F7] The semiconductor device (1) according to F6, wherein the source pad (101) is arranged on the main surface (3) so as to partially overlap the gate structure (20, 20A).

[0518] [F8] The semiconductor device (1) according to F6 or F7, wherein the source pad (101) is arranged on the main surface (3) so as not to overlap the resistor portion (60, 60A, 60B) of the gate structure (20, 20A).

[0519] [F9] The semiconductor device (1) according to any one of F1 to F8, further comprising a gate pad (81) arranged on the main surface (3) so as to partially overlap the gate structure (20, 20A) and electrically connected to the resistor portion (60, 60A, 60B).

[0520] [F10] The semiconductor device (1) according to F9, wherein the gate pad (81) is arranged on the main surface (3) so as to partially overlap the source structure (25).

[0521] [G1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed in a strip shape extending in a first direction (X) on the main surface (3) and having a resistance portion (60, 60A, 60B); and a trench electrode type electrode structure (30) formed on the main surface (3) at a distance from the gate structure (20, 20A) in the first direction (X) and to which a potential different from that of the gate structure (20, 20A) is applied.

[0522] [G2] The semiconductor device (1) according to G1, including: a gate pad (81) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B); and a gate wiring (85) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B) at a position different from the gate pad (81).

[0523] [H1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed on the main surface (3) and having a resistor portion (60, 60A, 60B); a trench electrode type first electrode structure (25) formed on the main surface (3) at a distance from the gate structure (20, 20A) in one direction (Y) and to which a potential different from that of the gate structure (20, 20A) is applied; and a trench electrode type second electrode structure (30) formed on the main surface (3) at a distance from the gate structure (20, 20A) in an orthogonal direction (X) perpendicular to the one direction (Y) and to which a potential different from that of the gate structure (20, 20A) is applied.

[0524] [H2] The semiconductor device (1) according to H1, including: a gate pad (81) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B); and a gate wiring (85) arranged on the main surface (3) so as to be electrically connected to the resistor portion (60, 60A, 60B) at a position different from the gate pad (81).

[0525] [I1] A semiconductor device (1) including: a chip (2) having a main surface (3); a trench electrode type gate structure (20, 20A) formed on the main surface (3) and partially having a resistor portion (60, 60A, 60B); a pad electrode (81) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) and having an electrical connection portion (83, 84) to the resistor portion (60, 60A, 60B); and a pad insulating film (110) covering the connection portion (83, 84) of the pad electrode (81) and having a pad opening (111) that exposes an area of ​​the pad electrode (81) other than the connection portion (83, 84).

[0526] [I2] The semiconductor device (1) described in I1, wherein the pad electrode (81) has a pad main body portion (82) located outside the resistor portion (60, 60A, 60B) and the connection portion (83, 84) drawn from the pad main body portion (82) to an area above the resistor portion (60, 60A, 60B), and the pad opening (111) exposes the pad main body portion (82).

[0527] [I3] The semiconductor device (1) according to I1 or I2 further includes a wiring electrode (85) arranged on the main surface (3) so as to overlap the resistor portion (60, 60A, 60B) at a distance from the pad electrode (81), the wiring electrode (85) having an electrical connection wiring portion (86, 87) to the resistor portion (60, 60A, 60B), and electrically connected to the pad electrode (81) via the resistor portion (60, 60A, 60B).

[0528] [I4] The semiconductor device (1) according to I3, wherein the pad insulating film (110) covers the connection wiring portions (86, 87) of the wiring electrodes (85).

[0529] [I5] A semiconductor device (1) according to any one of I1 to I4, further comprising an interlayer film (70) covering the main surface (3), and the pad electrode (81) being disposed on the interlayer film (70).

[0530] [I6] The semiconductor device (1) described in I5, wherein the pad insulating film (110) has a portion that directly covers the interlayer film (70) so as to face the resistor portion (60, 60A, 60B) of the gate structure (20, 20A) across the interlayer film (70).

[0531] [I7] The semiconductor device (1) according to I5 or I6, wherein the pad insulating film (110) includes an insulator different from the interlayer film (70).

[0532] [I8] The semiconductor device (1) according to any one of I1 to I7, wherein the pad insulating film (110) includes an organic insulating film (119).

[0533] [I9] The semiconductor device (1) according to any one of I1 to I8, wherein the pad insulating film (110) includes an inorganic insulating film (118).

[0534] [I10] The semiconductor device (1) described in any one of I1 to I9, wherein the pad insulating film (110) has a laminated structure including an inorganic insulating film (118) and an organic insulating film (119) laminated in this order from the pad electrode (81) side.

[0535] [J1] A semiconductor device (1) comprising: a gate pad (81); a gate wiring (85) physically separated from the gate pad (81); and a gate resistor (RG) having a parallel resistance circuit (R1, R2) including a plurality of resistance elements (60, 60A, 60B) and electrically interposed between the gate pad (81) and the gate wiring (85).

[0536] [J2] The semiconductor device (1) according to J1, wherein the plurality of resistance elements (60, 60A, 60B) are each formed using a portion of a plurality of trench gate structures (20).

[0537] [J3] The semiconductor device (1) according to J1 or J2, wherein the gate resistor (RG) has a plurality of the parallel resistance circuits (R1, R2) connected in parallel.

[0538] The elements and features of the above items can be combined as appropriate. While specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be combined as appropriate without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0539] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 6 first semiconductor region 8 active surface (first surface portion) 9 outer peripheral surface (second surface portion) 10A first connection surface (connection surface portion) 10B second connection surface (connection surface portion) 10C third connection surface (connection surface portion) 10D fourth connection surface (connection surface portion) 11 active plateau (mesa portion) 18 body region (impurity region) 20 gate structure 20A first gate structure 20B second gate structure 20C third gate structure 25 source structure (electrode structure) 30 side end structure (electrode structure) 41 first well region 51 sidewall wiring (sidewall structure) 53 gate connection electrode 60 resistance portion (resistance element) 60A first resistance portion (resistance element) 60B second resistance portion (resistance element) 65 resistance electrode (electrode film) 65A DESCRIPTION OF SYMBOLS First resistance electrode (electrode film) 65B Second resistance electrode (electrode film) 70 Interlayer film 81 Gate pad (pad electrode) 82 Pad main body 83 First resistance connection portion (connection portion) 84 Second resistance connection portion (connection portion) 85 Gate wiring (wiring electrode) 86 First resistance wiring (connection wiring portion) 87 Second resistance wiring (connection wiring portion) 90 First line wiring (connection portion) 91 Second line wiring (connection portion) 92 Third line wiring (connection portion) 101 Source pad (channel pad electrode) 110 Pad insulating film 111 Gate pad opening 118 Inorganic insulating film 119 Organic insulating film RG Gate resistance RC1 First parallel resistance circuit RC2 Second parallel resistance circuit D1 First depth D2 Second depth DO Peripheral depth W1 First width W2 Second width X First direction Y Second direction Z Normal direction

Claims

1. A chip having a main surface, A trench electrode type gate structure formed on the main surface and having a resistance portion, A pad electrode disposed on the main surface so as to overlap the resistance portion and having an electrical first connection portion for the resistance portion, A wiring electrode disposed on the main surface so as to overlap the resistance portion at a position different from the pad electrode, having an electrical second connection portion for the resistance portion, and electrically connected to the pad electrode via the resistance portion. A semiconductor device comprising:

2. The semiconductor device according to claim 1, wherein the chip is a wide bandgap semiconductor chip.

3. The semiconductor device according to claim 1, wherein the wiring electrode has an electrical connection portion for a portion other than the resistance portion of the gate structure.

4. A plurality of the gate structures each having the resistance portion are formed, The pad electrode has a plurality of the first connection portions for the plurality of the resistance portions, The semiconductor device according to claim 1, wherein the wiring electrode has a plurality of the second connection portions for the plurality of the resistance portions.

5. The semiconductor device according to claim 4, wherein the wiring electrode connects a plurality of the resistance portions in parallel with the pad electrode.

6. The semiconductor device according to claim 4, wherein the plurality of the gate structures are arranged at intervals such that the plurality of the resistance portions are located on the same straight line.

7. The semiconductor device according to any one of claims 1 to 6, further comprising a channel formed in a region along a portion other than the resistance portion of the gate structure in a surface layer portion of the main surface.

8. The semiconductor device according to claim 7, wherein the channel is also formed in a region along the resistance portion of the gate structure in a surface layer portion of the main surface.

9. The semiconductor device according to claim 7, further comprising a channel pad electrode disposed on the main surface at a distance from the pad electrode and the wiring electrode so as to overlap the channel and having an electrical connection portion for the channel.

10. The semiconductor device according to claim 9, wherein the channel pad electrode is disposed on the main surface so as to overlap the gate structure.

11. Further comprising at least one resistance electrode film covering the resistance portion, The first connection portion of the pad electrode is electrically connected to the resistance portion via the resistance electrode film, The semiconductor device according to any one of claims 1 to 6, wherein the second connection portion of the wiring electrode is electrically connected to the resistance portion via the resistance electrode film.

12. Further including a trench electrode type source structure formed on the main surface so as to be adjacent to the gate structure, The semiconductor device according to any one of claims 1 to 6, wherein the pad electrode overlaps the source structure.

13. The semiconductor device according to any one of claims 1 to 6, further including a pad insulating film having a pad opening that selectively covers the pad electrode and partially exposes the pad electrode.

14. The semiconductor device according to claim 13, wherein the pad insulating film partially faces the resistance portion with the first connection portion of the pad electrode interposed therebetween, and exposes portions of the pad electrode other than the first connection portion.

15. A chip having a main surface; A trench electrode type first gate structure formed on the main surface and having a resistance portion; A trench electrode type second gate structure formed on the main surface at a distance from the first gate structure and not having a resistance portion; A semiconductor device including a pad electrode disposed on the main surface so as to overlap the resistance portion of the first gate structure and the second gate structure, having an electrical connection portion for the resistance portion, and not having an electrical connection portion for the second gate structure.

16. At least one of the first gate structures is formed on the main surface, The semiconductor device according to claim 15, wherein a number of the second gate structures greater than the number of the first gate structures are formed on the main surface.

17. The semiconductor device according to claim 15, further including a wiring electrode disposed on the main surface at a distance from the pad electrode, electrically connected to the pad electrode via the resistance portion, and electrically connected to the second gate structure.

18. Further including a trench electrode type third gate structure formed on the main surface at a distance from the first gate structure and the second gate structure and not having a resistance portion, The semiconductor device according to any one of claims 15 to 17, wherein the pad electrode is disposed on the main surface so as not to overlap the third gate structure and does not have an electrical connection portion for the third gate structure.

19. A chip having a main surface; A trench electrode type gate structure formed on the main surface and having a resistance portion partially. A pad electrode disposed on the main surface so as to overlap the resistance portion and having an electrical connection portion to the resistance portion; A semiconductor device including a pad insulating film having a pad opening that covers the connection portion of the pad electrode and exposes a region other than the connection portion of the pad electrode.

20. The pad electrode has a pad main body portion located outside the resistance portion and the connection portion drawn from the pad main body portion to a region on the resistance portion. The semiconductor device according to claim 19, wherein the pad opening exposes the pad main body portion.