Semiconductor device and method for manufacturing semiconductor device

Abstract

The semiconductor device comprises: a semiconductor element; a sealing resin; and a wiring part electrically connected to the semiconductor element. The sealing resin has a first resin surface and a second resin surface which face sides opposite from each other in a thickness direction. The wiring part includes a first metal layer and a second metal layer. The first metal layer includes a penetration wiring part exposed from the second resin surface. The second metal layer includes a connecting wiring part electrically connected to the penetration wiring part and the semiconductor element. At least a portion of the connecting wiring part is formed into an uneven shape as seen in the thickness direction.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 discloses an example of a semiconductor device including a semiconductor element. The semiconductor device in this document includes a semiconductor element, a wiring portion, and a sealing resin. An electrode pad of the semiconductor element is electrically connected to the wiring portion. The wiring portion is covered with the sealing resin.

[0003] Japanese Patent Application Laid-Open No. 2020-136629

[0004] When peeling occurs between the wiring portion and the sealing resin, cracks may develop to the outside of the sealing resin, which may cause moisture to infiltrate into the semiconductor device.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress peeling between a wiring portion and a sealing resin, and a method for manufacturing such a semiconductor device.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element, a sealing resin, and a wiring portion electrically connected to the semiconductor element. The sealing resin has a first resin surface facing a first side in a thickness direction and a second resin surface facing a second side. The wiring portion includes a first metal layer including a through wiring portion exposed from the second resin surface, and a second metal layer including a connecting wiring portion electrically connected to the through wiring portion and the semiconductor element. At least a portion of the connecting wiring portion has an uneven shape when viewed in the thickness direction.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: forming a first metal layer having a plurality of through-hole wiring portions on a substrate; forming a first resin layer on the substrate to cover the first metal layer; thinning the first resin layer from the side opposite the substrate to expose the plurality of through-hole wiring portions from the first resin layer; forming a mask layer having a plurality of openings on the first resin layer and the first metal layer; forming a second metal layer using the mask layer to be conductive to the first metal layer; mounting a semiconductor element on the second metal layer; forming a second resin layer on the first resin layer to cover the second metal layer and the semiconductor element; and removing the substrate. In the step of forming the mask layer, at least some of the openings are formed to have an uneven shape.

[0008] According to the above configuration, peeling between the wiring portion and the sealing resin in the semiconductor device can be suppressed.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a partial bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a partial plan view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 13 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. Fig. 16 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. Fig. 17 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. Fig. 18 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. Fig. 19 is a partial plan view showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 20 is a partial plan view showing a semiconductor device according to a third embodiment of the present disclosure. Fig. 21 is a partial plan view showing a semiconductor device according to a fourth embodiment of the present disclosure.

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0012] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0013] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0014] 1 to 5 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a semiconductor element 1, a sealing resin 2, and a wiring portion 3.

[0015] 1 and 2 are partial plan views showing the semiconductor device A1. Fig. 3 is a partial enlarged plan view showing the semiconductor device A1. Fig. 4 is a partial bottom view showing the semiconductor device A1. Fig. 5 is a cross-sectional view taken along line V-V in Fig. 1. For ease of understanding, a second resin layer 22, which will be described later, is omitted from Figs. 1 and 2.

[0016] In these figures, for convenience of explanation, three mutually orthogonal directions (z direction, x direction, y direction) are referred to. The z direction is an example of a "thickness direction." The x direction is a direction orthogonal to the z direction. The y direction is a direction orthogonal to the z direction and the x direction.

[0017] Semiconductor element 1: The semiconductor element 1 is an element made of a semiconductor material that performs the main electrical function of the semiconductor device A1. The semiconductor element 1 is a so-called active element, such as an integrated circuit (IC) such as an LSI (Large Scale Integration), a voltage control element such as an LDO (Low Drop Out), or an amplification element such as an operational amplifier.

[0018] The semiconductor element 1 of this embodiment has an element body 11 and multiple electrodes 12. The element body 11 is a main body portion whose main component is a semiconductor. The multiple electrodes 12 are provided on the z2 side of the element body 11 in the z direction and are so-called pad electrodes. The electrodes 12 include, for example, Cu (copper), Al (aluminum), etc.

[0019] Sealing resin 2: The sealing resin 2 covers the semiconductor element 1. The sealing resin 2 has a first resin surface 201, a second resin surface 202, a third resin surface 203, a fourth resin surface 204, a fifth resin surface 205, and a sixth resin surface 206. The first resin surface 201 is a surface facing the z1 side in the z direction. The second resin surface 202 is a surface facing the z2 side in the z direction. The third resin surface 203 is a surface facing the x1 side in the x direction. The fourth resin surface 204 is a surface facing the x2 side in the x direction. The fifth resin surface 205 is a surface facing the y1 side in the y direction. The sixth resin surface 206 is a surface facing the y2 side in the y direction. As shown in FIG. 5 , in the illustrated example, the fifth resin surface 205 has a recess 2051. The recess 2051 is a portion of the fifth resin surface 205 located on the z2 side in the z direction, and is recessed toward the y2 side in the y direction. The sixth resin surface 206 has a recess 2061. The recess 2061 is a portion of the sixth resin surface 206 located on the z2 side in the z direction, and is recessed toward the y1 side in the y direction.

[0020] The sealing resin 2 has a first resin layer 21 and a second resin layer 22. The first resin layer 21 is a layer located on the z2 side in the z direction. The first resin layer 21 is made of, for example, a black epoxy resin. The first resin layer 21 may also contain a filler (not shown). The second resin surface 202 is made of the first resin layer 21. The first resin layer 21 has a seventh resin surface 207. The seventh resin surface 207 is a surface facing the z1 side in the z direction. The second resin layer 22 is stacked on the seventh resin surface 207 of the first resin layer 21 and covers the semiconductor element 1. The second resin layer 22 is made of, for example, a black epoxy resin. The first resin layer 21 may also contain a filler (not shown). The first resin surface 201 is made of the second resin layer 22. In the illustrated example, the thickness of the first resin layer 21 in the z direction is thinner than the thickness of the second resin layer 22 in the z direction. The thickness of the first resin layer 21 is, for example, not less than 20 μm and not more than 100 μm, and the thickness of the second resin layer 22 is, for example, not less than 400 μm and not more than 1200 μm.

[0021] Wiring section 3: The wiring section 3 forms a conductive path for realizing the electrical function of the semiconductor element 1. The wiring section 3 of this embodiment includes a first metal layer 31 and a second metal layer 32.

[0022] The first metal layer 31 is located between the second resin surface 202 and the seventh resin surface 207 in the z direction. The first metal layer 31 is mainly composed of, for example, Cu (copper) and is formed by, for example, electrolytic plating. The first metal layer 31 may further include a base layer and a plating layer stacked on top of each other. The base layer is composed of a Ti (titanium) layer and a Cu (copper) layer stacked on top of each other, and has a thickness of approximately 200 nm to 800 nm. The plating layer contains, for example, Cu (copper) and is set to be thicker than the base layer.

[0023] The first metal layer 31 of this embodiment includes a plurality of through wiring portions 310. Each of the plurality of through wiring portions 310 penetrates the first resin layer 21 in the z direction and reaches the first resin surface 201 and the seventh resin surface 207. The number, shape, arrangement, etc. of the plurality of through wiring portions 310 are not limited in any way. In this embodiment, the plurality of through wiring portions 310 are arranged in two rows in the x direction along the fifth resin surface 205 and the sixth resin surface 206. In the illustrated example, the through wiring portion 310 has a back surface 311 and an end surface 312. The back surface 311 is a surface exposed from the second resin surface 202. The end surface 312 faces the y1 side or the y2 side in the y direction and is exposed from the fifth resin surface 205 or the sixth resin surface 206. In the illustrated example, the back surface 311 is rectangular when viewed in the z direction.

[0024] The second metal layer 32 is located between the first resin layer 21 and the second resin layer 22 and is formed on the seventh resin surface 207. The thickness of the second metal layer 32 is, for example, 10 μm or more and 60 μm or less. The second metal layer 32 is mainly composed of, for example, Cu (copper). In this embodiment, the second metal layer 32 includes an underlayer and a plating layer stacked together. The underlayer is composed of a Ti (titanium) layer and a Cu (copper) layer stacked together and has a thickness of 200 nm or more and 800 nm or less. The underlayer can be formed by, for example, sputtering. The plating layer contains, for example, Cu and is thicker than the underlayer. The plating layer can be formed by, for example, electrolytic plating. Note that the constituent material and formation method of the second metal layer 32 are not limited to those described above. For example, a Ni (nickel) layer may be formed between the underlayer and the plating layer. The Ni layer can be formed by, for example, electrolytic plating. The area where the second metal layer 32 is formed is not limited to the embodiments shown in FIGS.

[0025] The second metal layer 32 includes a plurality of interconnection portions 320, which electrically connect the through-wiring portions 310 to the electrodes 12 of the semiconductor element 1. The interconnection portions 320 are in contact with the through-wiring portions 310. The electrodes 12 are electrically connected to the interconnection portions 320 via a conductive bonding material 39. The conductive bonding material 39 is, for example, solder.

[0026] The interconnection section 320 includes a first edge 321 , a second edge 322 , a pair of first sides 323 , a pair of second sides 324 , and a plurality of intermediate sides 325 and 326 .

[0027] The first edge 321 is the edge of the interconnection portion 320 on the side to which the electrode 12 is conductively joined. The second edge 322 is the edge opposite the first edge 321. In the example shown, the first edge 321 is exposed from the fifth resin surface 205 or the sixth resin surface 206. A pair of first sides 323 extend from both ends of the first edge 321. The second sides 324 extend from both ends of the second edge 322 and overlap with the through-wiring portion 310 when viewed in the z direction. The multiple intermediate sides 325 and the multiple intermediate sides 326 are interposed between the pair of first sides 323 and the pair of second sides 324, and connect the pair of first sides 323 and the pair of second sides 324.

[0028] In this embodiment, as shown in Figures 2 and 3, each of the pair of first sides 323 has an uneven shape. The pitch of the uneven shape is not limited in any way, and in this embodiment, it is 15 µm or more and 100 µm or less. Furthermore, the specific shape of the uneven shape is not limited in any way, and various shapes such as a shape composed of multiple curves, such as a sine wave shape, or a triangular wave shape, a rectangular wave shape, etc. may be appropriately adopted. In the illustrated example, the uneven shape of the first side 323 is a sine wave shape. When the first side 323 has a sine wave shape, the distance between the peaks and valleys (corresponding to twice the amplitude of the sine wave) is, for example, 15 µm or more and 100 µm or less.

[0029] The wiring portion 3 of this embodiment also includes a plurality of surface metal layers 33. The surface metal layers 33 cover the rear surface 311 and the end surfaces 312. The surface metal layers 33 have a structure in which, for example, a Ni (nickel) layer, a Pd (palladium) layer, and an Au (gold) layer are laminated in this order. However, the surface metal layer 33 is not limited to this, and may be a Ni (nickel) layer and an Au (gold) layer laminated in this order, or may be an Au (gold) layer only, or an Sn (tin) layer only.

[0030] Next, a method for manufacturing the semiconductor device A1 will be described below with reference to FIGS.

[0031] First, as shown in Fig. 6, a substrate 4 is prepared. The substrate 4 is made of, for example, a single-crystal semiconductor material, and in this embodiment, it is a single-crystal Si (silicon) material. In the step of preparing the substrate 4, for example, a Si wafer is prepared as the substrate 4. In this embodiment, the thickness of the substrate 4 is, for example, about 725 to 775 µm. The substrate 4 is not limited to a Si (silicon) wafer, and may be, for example, a glass substrate.

[0032] Next, a first metal layer 31A is formed on the substrate 4. The first metal layer 31A includes a plurality of through-hole wiring portions 310. In the process of forming the first metal layer 31A, a base layer in contact with the substrate 4 is first formed. This base layer is formed by sputtering. In this embodiment, a Ti (titanium) layer in contact with the substrate 4 is formed, and then a Cu (copper) layer in contact with the Ti (titanium) layer is formed. Therefore, the base layer is formed from a Ti (titanium) layer and a Cu (copper) layer stacked on top of each other. In this embodiment, the thickness of the Ti (titanium) layer is approximately 10 nm to 30 nm, and the thickness of the Cu (copper) layer is approximately 200 nm to 800 nm. Note that the constituent material and thickness of the base layer are not limited to those described above. Next, a plating layer in contact with the base layer is formed. The plating layer is formed by forming a resist pattern using photolithography and electroplating. Specifically, a photosensitive resist is applied to cover the entire surface of the base layer, and then the photosensitive resist is exposed and developed. This forms a patterned mask layer. The photosensitive resist is applied, for example, using a spin coater, but is not limited to this. At this time, a portion of the base layer is exposed from the mask layer. Next, electrolytic plating is performed using the base layer as a conductive path. As a result, a plating layer is deposited on the base layer exposed from the resist pattern. In this embodiment, the constituent material of the plating layer is, for example, Cu (copper). After the plating layer is formed, the mask layer is removed. Through the above steps, a first metal layer 31A including a plurality of through wiring portions 310 is formed.

[0033] Next, as shown in FIG. 7, a first resin layer 21A is formed. The first resin layer 21A is formed to cover the first metal layer 31A. The process of forming the first resin layer 21A is performed, for example, by molding. In this embodiment, the first resin layer 21A has electrical insulation properties and is made of a synthetic resin, for example, a black epoxy resin as a main component. By this process, the first metal layer 31A is completely covered with the first resin layer 21A.

[0034] Next, as shown in FIG. 8 , the first resin layer 21A is thinned from the z1 side opposite the semiconductor element 1 in the z direction. The thinning method is not limited to this, and in this embodiment, grinding is used, for example. In the process of grinding the first resin layer 21A, a mechanical grinder is used, for example. Note that the grinding of the first resin layer 21A is not limited to grinding using a mechanical grinder. In the grinding process of the first resin layer 21A, the first resin layer 21A is ground until the through wiring portion 310 is exposed. This process exposes the through wiring portion 310 from the seventh resin surface 207 of the first resin layer 21A. Furthermore, grinding marks, which are marks caused by grinding with a grindstone, are formed on the seventh resin surface 207. In this embodiment, the grinding marks are formed across from the seventh resin surface 207 to the through wiring portion 310. In this embodiment, when the first resin layer 21A is ground, a portion of the through wiring portion 310 is ground away. After grinding, burrs may occur in the through wiring portion 310 due to the difference in material between the through wiring portion 310 and the first resin layer 21A. A chemical treatment may be performed to remove the burrs. In this case, the through wiring portion 310 may be slightly recessed toward the z2 side in the z direction from the seventh resin surface 207.

[0035] 9 and 10 , a mask layer 5 is formed. In this embodiment, prior to forming the mask layer 5, a base layer (not shown) is formed on the seventh resin surface 207 and the through wiring portion 310. The base layer is formed by, for example, a sputtering method. In the step of forming the base layer, a Ti (titanium) layer is formed to cover the first resin layer 21A and the through wiring portion 310, and then a Cu (copper) layer is formed in contact with the Ti (titanium) layer. Therefore, the base layer is formed from a Ti layer and a Cu layer stacked on top of each other.

[0036] Next, a photosensitive resist is applied to cover the entire surface of the base layer, and the photosensitive resist is exposed and developed to perform patterning. This forms a mask layer 5. The mask layer 5 has a plurality of openings 51. The plurality of openings 51 expose the base layer. The plurality of openings 51 have a size, shape, and arrangement corresponding to the plurality of interconnection portions 320.

[0037] 11 , a plating layer is deposited on the underlayer exposed from the plurality of openings 51 of the mask layer 5 by electrolytic plating using the underlayer as a conductive path. In this embodiment, a metal layer containing, for example, Cu (copper) is deposited as the plating layer. At this time, the plating layer is formed integrally with the underlayer.

[0038] Next, as shown in FIG. 12 , the mask layer 5 is removed. This forms a second metal layer 32A including a plurality of interconnection wiring portions 320. Next, a plurality of conductive bonding materials 39 are formed. The conductive bonding materials 39 are formed, for example, by electrolytic plating using the second metal layer 32A as a conductive path, to deposit the conductive bonding materials 39 on the second metal layer 32A exposed from the mask layer (not shown). In this embodiment, the conductive bonding materials 39 are formed by sequentially stacking a metal layer containing Cu (copper), a metal layer containing Ni (nickel), and an alloy layer containing Sn (tin). The alloy layer containing Sn (tin) is, for example, a lead-free solder such as an Sn (tin)-Sb (antimony)-based alloy or an Sn (tin)-Ag (silver)-based alloy. The mask layer formed in this process is then removed.

[0039] Additionally, unnecessary portions of the base layer used in forming the second metal layer 32A (portions extending beyond the interconnection portion 320) are removed. This removal process is performed by wet etching using a mixed solution of HSO (sulfuric acid) and HO (hydrogen peroxide), for example.

[0040] Next, as shown in FIG. 13 , the semiconductor element 1 is mounted. The mounting of the semiconductor element 1 is performed, for example, by flip-chip bonding. Specifically, after applying flux to the semiconductor element 1, the multiple electrodes 12 of the semiconductor element 1 are temporarily attached to multiple conductive bonding materials 39 using, for example, a flip-chip bonder. The conductive bonding materials 39 are then melted by reflow to bond to the multiple electrodes 12. The conductive bonding materials 39 are then cooled and solidified. As a result, the semiconductor element 1 is mounted on the second metal layer 32A, and the multiple electrodes 12 of the semiconductor element 1 are conductively bonded to the multiple interconnect wiring portions 320.

[0041] Next, as shown in FIG. 14 , a second resin layer 22A is formed. The process of forming the second resin layer 22A (second resin layer formation process) is performed, for example, by molding. Like the first resin layer 21A, the second resin layer 22A has electrical insulation properties and is made of a synthetic resin primarily composed of, for example, a black epoxy resin. In this embodiment, the second resin layer 22A, which covers the semiconductor element 1, the first metal layer 31A, and the second metal layer 32A, is formed on the seventh resin surface 207 of the first resin layer 21A. The second resin layer 22A completely covers the semiconductor element 1 and the second metal layer 32A. Before performing molding to form the second resin layer 22A, an underfill (not shown), primarily composed of, for example, an epoxy resin, may be filled between the semiconductor element 1 and the seventh resin surface 207 of the first resin layer 21A.

[0042] Next, as shown in FIG. 15 , the substrate 4 is removed. In the process of removing the substrate 4, grinding is performed using a mechanical grinder. Note that the grinding method is not limited to grinding using a mechanical grinder. In this embodiment, the substrate 4 is ground from the z1 side toward the z2 side in the z direction to completely remove the substrate 4. In this embodiment, the substrate 4 is completely ground, and portions of the plurality of through-wiring portions 310 are also ground. By the process of removing the substrate 4, a second resin surface 202 is formed on the first resin layer 21A, and back surfaces 311 are formed on the plurality of through-wiring portions 310. The second resin surface 202 and the back surface 311 are flush with each other. Note that when a glass substrate is used as the substrate 4, the substrate 4 is removed by peeling the glass substrate by chemical treatment or laser irradiation.

[0043] Next, as shown in FIG. 16 , multiple recesses 291 are formed. The multiple recesses 291 are formed, for example, by forming grooves from the z2 side in the z direction using a dicing blade Db1. The recesses 291 are recessed from the second resin surface 202 toward the z1 side in the z direction, penetrating the first resin layer 21 and the second metal layer 32 to reach the second resin layer 22. The multiple recesses 291 overlap the outline of the semiconductor device A1 to be formed by this manufacturing method when viewed in the z direction. By forming the recesses 291 in the fuschia, end faces 312 are formed in the through-wiring portions 310.

[0044] Next, as shown in FIG. 17 , a surface metal layer 33 is formed. The process of forming the surface metal layer 33 is performed by electroless plating. In this embodiment, a Ni (nickel) layer, a Pd (palladium) layer, and an Au (gold) layer are deposited in this order by electroless plating. At this time, a Ni layer is formed to cover the back surface 311 and end surface 312 of the through wiring portion 310, a Pd layer is formed on the Ni layer, and an Au layer is formed on the Pd layer. Note that the method of forming the surface metal layer 33 is not limited to this, and the Ni (nickel) layer and the Au (gold) layer may be deposited in this order, or only an Au (gold) layer may be deposited, or only an Sn (tin) layer may be deposited.

[0045] Next, as shown in FIG. 18 , a cutting step is performed. In this cutting step, for example, a dicing blade Db2 is used to cut along the plurality of recesses 291. The dicing blade Db2 is thinner than the dicing blade Db1. This completely cuts the second resin layer 22A. Then, a plurality of semiconductor devices A1 are obtained. The plurality of recesses 291 remain as recesses 2051 and recesses 2061 in the semiconductor device A1.

[0046] Next, the operation of the semiconductor device A1 and the method for manufacturing the semiconductor device A1 will be described.

[0047] According to this embodiment, the interconnection part 320 has a portion that is uneven when viewed in the z direction. The uneven portion increases the contact area between the interconnection part 320 and the sealing resin 2 (second resin layer 22). This makes it possible to suppress peeling between the interconnection part 3 and the sealing resin 2.

[0048] In this embodiment, the pair of first sides 323 have uneven portions. The first sides 323 are close to the portions of the interconnection portion 320 that are conductively joined to the plurality of electrodes 12 of the semiconductor element 1. The semiconductor, which is the main component of the semiconductor element 1, and the resin, which is the main component of the sealing resin 2, have different linear expansion coefficients. Therefore, if the semiconductor element 1 generates heat during operation of the semiconductor device A1, there is a risk that peeling will occur between the pair of first sides 323 and the sealing resin 2 (first resin layer 21). According to this embodiment, peeling at the pair of first sides 323 can be suppressed.

[0049] In the manufacturing method of the semiconductor device A1, the second metal layer 32A is formed using the mask layer 5 formed on the first resin layer 21A, thereby enabling the interconnection portion 320 to be appropriately formed with a desired uneven shape in the desired location. Furthermore, the mask layer 5 is formed by patterning using photolithography, for example, which allows for fine processing. Therefore, the uneven shape of the desired shape and pitch can be more easily and reliably formed in the interconnection portion 320.

[0050] 19 to 21 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each of the modified examples and embodiments can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0051] 19 shows a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A2 of this embodiment, the first edge 321 has an uneven shape. The pitch of the uneven shape of the first edge 321 is the same as the pitch of the uneven shape of the first side 323, for example.

[0052] This embodiment also makes it possible to suppress peeling between the wiring portion 3 and the sealing resin 2. Furthermore, since the first edge 321 has an uneven shape, peeling between the wiring portion 3 and the sealing resin 2 inside the semiconductor device A1 can be further suppressed. Furthermore, as can be understood from this embodiment, there is no limitation on which part of the interconnection wiring portion 320 has an uneven shape, and for example, the first edge 321 may have an uneven shape and the first side 323 may not have an uneven shape.

[0053] 20 shows a semiconductor device according to a third embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, a portion of each of a pair of second sides 324 is formed with a concave-convex shape. The pitch of the concave-convex shape of the second sides 324 is, for example, the same as the pitch of the concave-convex shape of the first sides 323. In the illustrated example, the portion of the second sides 324 that connects to the second edge 322 is formed with a concave-convex shape.

[0054] This embodiment also makes it possible to prevent peeling between the wiring portion 3 and the sealing resin 2. Furthermore, since the pair of second sides 324 includes portions with an uneven shape, it is possible to prevent cracks that lead to the outside of the semiconductor device A1 from occurring between the sealing resin 2 and the wiring portion 3.

[0055] 21 shows a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A4 of this embodiment, the interconnection portion 320 has an uneven shape except for the second edge 322. That is, the first edge 321, the pair of first sides 323, the pair of second sides 324, the plurality of intermediate sides 325, and the plurality of intermediate sides 326 have an uneven shape.

[0056] This embodiment also makes it possible to prevent the wiring portion 3 from peeling off from the sealing resin 2. Furthermore, this embodiment makes it possible to suitably prevent the sealing resin 2 from peeling off from the wiring portion 3.

[0057] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiment. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways.

[0058] Supplementary Note 1. A semiconductor device comprising: a semiconductor element; a sealing resin; and a wiring portion conducting to the semiconductor element, wherein the sealing resin has a first resin surface facing a first side in a thickness direction and a second resin surface facing a second side, wherein the wiring portion includes a first metal layer including a through wiring portion exposed from the second resin surface, and a second metal layer including a connecting wiring portion conducting to the through wiring portion and the semiconductor element, wherein at least a portion of the connecting wiring portion has an uneven shape when viewed in the thickness direction. Supplementary Note 2. The semiconductor device according to Supplementary Note 1, wherein the thickness of the connecting wiring portion is 10 μm or more and 60 μm or less, and the pitch of the uneven shape is 15 μm or more and 100 μm or less. Supplementary Note 3. The semiconductor device according to Supplementary Note 1 or 2, wherein the uneven shape is formed by a plurality of curves. Supplementary Note 4. The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the interconnection portion has a first edge on a side electrically connected to the semiconductor element and a pair of first sides extending from the first edge, and the first sides have an uneven shape when viewed in the thickness direction. Supplementary Note 5. The semiconductor device according to Supplementary Note 4, wherein the first edge has an uneven shape when viewed in the thickness direction. Supplementary Note 6. The semiconductor device according to Supplementary Note 4 or 5, wherein the interconnection portion has a second edge opposite the first edge and a pair of second sides extending from the second edge and overlapping the through-wiring portion when viewed in the thickness direction, and at least a portion of the second sides has an uneven shape when viewed in the thickness direction. Supplementary Note 7. The semiconductor device according to Supplementary Note 6, wherein a portion of the second sides connected to the second edge has an uneven shape when viewed in the thickness direction. Supplementary Note 8. The semiconductor device according to Supplementary Note 7, wherein the portion of the second sides connected to the second edge has an uneven shape when viewed in the thickness direction. Supplementary Note 9. The semiconductor device according to any one of Supplementary Notes 6 to 8, wherein the interconnection portion has a plurality of intermediate sides interposed between the pair of first sides and the pair of second sides, and the intermediate sides have an uneven shape when viewed in the thickness direction.Supplementary Note 10. The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the sealing resin includes a first resin layer and a second resin layer stacked in the thickness direction, the first resin surface is constituted by the second resin layer, and the second resin surface is constituted by the first resin layer.Appendix 11. The semiconductor device according to Appendix 10, wherein the through wiring portion penetrates the first resin layer in the thickness direction. Appendix 12. The semiconductor device according to Appendix 10 or 11, wherein the first resin layer has a seventh resin surface in contact with the second resin layer, and the second resin layer is formed on the seventh resin surface. Appendix 13. The semiconductor device according to Appendix 9, wherein the through wiring portion has a back surface exposed from the second resin surface. Appendix 14. The semiconductor device according to Appendix 13, wherein the wiring portion includes a surface metal layer covering the back surface. Appendix 15. The semiconductor device according to Appendix 14, wherein the through wiring portion has an end surface exposed in a direction perpendicular to the thickness direction and connected to the back surface. Appendix 16. The semiconductor device according to Appendix 15, wherein the surface metal layer covers the end surface. Appendix 17. The semiconductor device according to any of Appendixes 1 to 16, wherein the semiconductor element has an electrode facing the interconnection portion, and the electrode is conductively joined to the interconnection portion via a conductive bonding material. Appendix 18. A method for manufacturing a semiconductor device, comprising: a step of forming a first metal layer having a plurality of through wiring portions on a substrate; a step of forming a first resin layer on the substrate to cover the first metal layer; a step of thinning the first resin layer from the side opposite to the substrate to expose the plurality of through wiring portions from the first resin layer; a step of forming a mask layer having a plurality of openings on the first resin layer and the first metal layer; a step of forming a second metal layer that is conductive to the first metal layer using the mask layer; a step of mounting a semiconductor element on the second metal layer; a step of forming a second resin layer on the first resin layer to cover the second metal layer and the semiconductor element; and a step of removing the substrate, wherein in the step of forming the mask layer, at least a portion of the openings are formed into an uneven shape.

[0059] A1, A2, A3, A4: semiconductor device 1: semiconductor element 2: sealing resin 3: wiring portion 4: substrate 5: mask layer 11: element body 12: electrode 21: first resin layer 21A: first resin layer 22: second resin layer 22A: second resin layer 31: first metal layer 31A: first metal layer 32: second metal layer 32A: second metal layer 33: surface metal layer 39: conductive bonding material 51: opening 201: first resin surface 202: second resin surface 203: third resin surface 204: fourth resin surface 205: fifth resin surface 206: sixth resin surface 207: seventh resin surface 291: recess 310: through wiring portion 311: back surface 312: end surface 320: interconnect wiring portion 321: first edge 322: Second edge 323: First side 324: Second side 325, 326: Middle sides 2051, 2061: Recesses Db1, Db2: Dicing blades

Claims

1. A semiconductor element; A sealing resin; a wiring portion electrically connected to the semiconductor element, the sealing resin has a first resin surface facing a first side in a thickness direction and a second resin surface facing a second side; the wiring portion includes a first metal layer including a through wiring portion exposed from the second resin surface, and a second metal layer including a connecting wiring portion that is electrically connected between the through wiring portion and the semiconductor element, At least a portion of the interconnection portion has an uneven shape when viewed in the thickness direction.

2. the interconnection portion has a thickness of 10 μm or more and 60 μm or less; 2. The semiconductor device according to claim 1, wherein the pitch of said uneven shape is 15 [mu]m or more and 100 [mu]m or less.

3. The semiconductor device according to claim 1 , wherein the uneven shape is formed by a plurality of curved lines.

4. the interconnection portion has a first edge on a side electrically connected to the semiconductor element, and a pair of first sides extending from the first edge; The semiconductor device according to claim 1 , wherein the first side has an uneven shape when viewed in the thickness direction.

5. The semiconductor device according to claim 4 , wherein the first edge has an uneven shape when viewed in the thickness direction.

6. the interconnection portion has a second edge opposite to the first edge, and a pair of second sides extending from the second edge and overlapping with the through-wiring portion when viewed in the thickness direction; The semiconductor device according to claim 4 , wherein at least a portion of the second side has an uneven shape when viewed in the thickness direction.

7. The semiconductor device according to claim 6 , wherein a portion of the second side connected to the second edge has an uneven shape when viewed in the thickness direction.

8. The semiconductor device according to claim 7 , wherein the second edge is exposed from the sealing resin.

9. the interconnection portion has a plurality of intermediate sides interposed between the pair of first sides and the pair of second sides, The semiconductor device according to claim 6 , wherein the intermediate side has an uneven shape when viewed in the thickness direction.

10. the sealing resin includes a first resin layer and a second resin layer stacked in the thickness direction, the first resin surface is constituted by the second resin layer, 4. The semiconductor device according to claim 1, wherein the second resin surface is formed by the first resin layer.

11. The semiconductor device according to claim 10 , wherein the through wiring portion penetrates the first resin layer in the thickness direction.

12. the first resin layer has a seventh resin surface in contact with the second resin layer, The semiconductor device according to claim 10 , wherein the second resin layer is formed on the seventh resin surface.

13. The semiconductor device according to claim 9 , wherein the through wiring portion has a back surface exposed from the second resin surface.

14. The semiconductor device according to claim 13 , wherein the wiring portion includes a surface metal layer covering the rear surface.

15. The semiconductor device according to claim 14 , wherein the through wiring portion has an end surface that is exposed in a direction perpendicular to the thickness direction and that is connected to the rear surface.

16. The semiconductor device according to claim 15 , wherein the surface metal layer covers the end faces.

17. the semiconductor element has an electrode facing the interconnection portion, 4. The semiconductor device according to claim 1, wherein said electrodes are electrically connected to said interconnection portions via a conductive bonding material.

18. forming a first metal layer having a plurality of through wiring portions on a substrate; forming a first resin layer on the substrate to cover the first metal layer; a step of thinning the first resin layer from a side opposite to the substrate to expose the plurality of through wiring portions from the first resin layer; forming a mask layer having a plurality of openings on the first resin layer and the first metal layer; forming a second metal layer using the mask layer and electrically connecting to the first metal layer; Mounting a semiconductor element on the second metal layer; forming a second resin layer on the first resin layer to cover the second metal layer and the semiconductor element; removing the substrate; Equipped with In the step of forming the mask layer, at least a part of the opening is formed to have an uneven shape.