Semiconductor device and method for producing semiconductor device

Abstract

According to the present invention, a front surface electrode (14) forms an ohmic contact with a semiconductor substrate (8) by the intermediary of a contact structure which is composed of a TiSix film (11), a TiN film (12) and a metal plug (13). The TiSix film (11) is directly deposited by sputtering so as to extend from a lateral wall of a contact hole (9a) (a lateral surface of an interlayer insulating film (9)) along the inner wall of a source contact trench (8a). An end part of the TiSix film (11) ends on the lateral surface of the interlayer insulating film (9). The TiSix film (11) has a uniform thickness from the lateral wall of the contact hole (9a) to the lateral wall of the source contact trench (8a). The TiN film (12) is provided along the surface of the TiSix film (11). The metal plug (13) is buried in the contact hole (9a) and the source contact trench (8a) so as to be positioned above the TiN film (12). Consequently, the reliability of a semiconductor device (10) is improved.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Conventionally, semiconductor devices have been proposed that have a contact structure between a front electrode and a semiconductor substrate, such as an adhesion layer made of titanium (Ti) or a barrier layer made of titanium silicon nitride (Ti-Si-N), or a titanium silicide (TiSi) film formed by silicidation of a Ti film, or a TiSi film formed by plasma enhanced chemical vapor deposition (PECVD) (see, for example, Patent Documents 1 to 5 listed below). Also proposed is a semiconductor device with a gate electrode that includes a TiSi film deposited by sputtering (see, for example, Patent Document 6 listed below).

[0003] JP 10-321812 JP 10-79431 JP 10-79481 JP 7-297136 JP 2015-124397 Patent No. 3988342

[0004] However, in Patent Documents 1 to 4, the Ti film included in the stacked structure of the front electrode inhibits the effect of hydrogen annealing for repairing crystal damage in the semiconductor substrate. Furthermore, in Patent Document 4, the volume expansion of the TiSi film due to silicidation increases local stress in the semiconductor substrate. In Patent Document 5, chlorine (Cl) included in the gas composition introduced by PECVD for forming the TiSi film causes corrosion of the semiconductor substrate.

[0005] The present disclosure aims to provide a highly reliable semiconductor device and a method for manufacturing the semiconductor device in order to solve the problems of the conventional techniques described above.

[0006] A semiconductor device according to one aspect of the present disclosure is as follows: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between a front surface of the semiconductor substrate and the first semiconductor region. An element structure including a pn junction between the second semiconductor region and the first semiconductor region is provided on the front surface side of the semiconductor substrate. An interlayer insulating film is provided on the front surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A contact hole penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate. The contact structure contacts the semiconductor substrate at the contact hole.

[0007] The first electrode is electrically connected to the second semiconductor region via the contact structure. The second electrode is provided on the back surface of the semiconductor substrate. The contact structure is composed of a titanium silicide film, a titanium nitride film, and a metal plug. The titanium silicide film is in contact with the semiconductor substrate in the contact hole and extends onto the surface of the interlayer insulating film along the sidewall of the contact hole. The titanium nitride film is provided along the surface of the titanium silicide film. The metal plug is buried on the titanium nitride film inside the contact hole.

[0008] A method for manufacturing a semiconductor device according to one aspect of the present disclosure is as follows: a first step is performed in which a second semiconductor region of a second conductivity type is formed in a surface region of the front surface of a semiconductor substrate, the second semiconductor region being in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate, and an element structure including a pn junction between the second semiconductor region and the first semiconductor region is formed; a second step is performed in which an interlayer insulating film is formed on the front surface of the semiconductor substrate to cover the element structure; a third step is performed in which a contact hole is formed that penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate; a fourth step is performed in which a contact structure is formed in the contact hole to contact the semiconductor substrate; and a fifth step is performed in which a first electrode is formed that is electrically connected to the second semiconductor region via the contact structure.

[0009] After the fifth step, a first annealing step is performed to repair crystal damage to the semiconductor substrate by heat treatment in a hydrogen atmosphere. The fourth step includes first to third deposition steps. In the first deposition step, a titanium silicide film is deposited by sputtering to cover the entire surface of the interlayer insulating film and to be in contact with the semiconductor substrate in the contact hole. In the second deposition step, a titanium nitride film is deposited by sputtering on the surface of the titanium silicide film. In the third deposition step, a metal plug is embedded on the titanium nitride film inside the contact hole. The contact structure is formed, consisting of the titanium silicide film, the titanium nitride film, and the metal plug.

[0010] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure have the effect of improving reliability.

[0011] FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. FIG. 8 is a cross-sectional view showing a state during the manufacture of a semiconductor device according to the second embodiment. FIG. 9 is a diagram showing the relationship between the degree of recovery of crystal damage in a semiconductor substrate due to hydrogen annealing and a barrier metal. FIG. 10 is a cross-sectional view showing the structure of a first comparative example. FIG. 11 is a cross-sectional view showing the structure of a second comparative example. FIG. 12 is a cross-sectional view showing a state during the manufacture of a second comparative example. FIG. 13 is a cross-sectional view showing a state during the manufacture of a second comparative example. FIG. 14 is a cross-sectional view showing a state during the manufacture of a second comparative example. FIG. 15 is a cross-sectional view showing a state during the manufacture of a second comparative example. FIG. 16 is a cross-sectional view showing a state during the manufacture of a second comparative example. FIG. 17 is a cross-sectional view showing a state during the manufacture of a second comparative example. FIG. 18 is a cross-sectional view showing a state during the manufacture of a second comparative example.

[0012] <Outline of Embodiments of the Present Disclosure> (1) A semiconductor device according to one aspect of the present disclosure is as follows: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between a front surface of the semiconductor substrate and the first semiconductor region. An element structure including a pn junction between the second semiconductor region and the first semiconductor region is provided on the front surface side of the semiconductor substrate. An interlayer insulating film is provided on the front surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A contact hole penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate. The contact structure contacts the semiconductor substrate at the contact hole.

[0013] The first electrode is electrically connected to the second semiconductor region via the contact structure. The second electrode is provided on the back surface of the semiconductor substrate. The contact structure is composed of a titanium silicide film, a titanium nitride film, and a metal plug. The titanium silicide film is in contact with the semiconductor substrate in the contact hole and extends onto the surface of the interlayer insulating film along the sidewall of the contact hole. The titanium nitride film is provided along the surface of the titanium silicide film. The metal plug is buried on the titanium nitride film inside the contact hole.

[0014] According to the above disclosure, the first electrode and the semiconductor substrate are electrically connected via a TiSix film (titanium silicide film), thereby reducing the contact resistance between the first electrode and the semiconductor substrate. Furthermore, according to the above disclosure, forming the TiSix film does not require special high-temperature heat treatment, such as silicidation. This makes it possible to suppress localized stress in the semiconductor substrate. Furthermore, since a Ti film that adsorbs hydrogen is not formed on the surface of the interlayer insulating film, it is easy to repair crystal damage to the semiconductor substrate caused by hydrogen annealing. Furthermore, since a Ti film is not formed on the surface of the interlayer insulating film, it is possible to prevent a decrease in adhesion with the interlayer insulating film due to a reaction between the material gas and the Ti film during metal plug formation.

[0015] (2) The semiconductor device according to the present disclosure may further include a contact trench of a predetermined depth provided on the front surface of the semiconductor substrate, the contact trench being continuous with the contact hole, and the titanium silicide film may be provided along the sidewall of the contact hole and the inner wall of the contact trench.

[0016] According to the above disclosure, the stress applied to the interlayer insulating film and the semiconductor substrate becomes uniform on the sidewalls of the contact hole and the sidewalls of the contact trench.

[0017] (3) In the semiconductor device according to the present disclosure, in the above-mentioned (2), the thickness of the titanium silicide film may be uniform from the sidewall of the contact hole to the sidewall of the contact trench.

[0018] According to the above disclosure, the stress applied to the interlayer insulating film and the semiconductor substrate becomes uniform on the sidewalls of the contact hole and the sidewalls of the contact trench.

[0019] (4) In addition, in the semiconductor device according to the present disclosure, in the above-mentioned (2), the interlayer insulating film may be located at a distance of 10 nm or less from the contact trench in a direction parallel to the front surface of the semiconductor substrate.

[0020] According to the above disclosure, the step coverage of the metal plug is improved.

[0021] (5) In the semiconductor device according to any one of (1) to (4) above, the titanium silicide film may terminate at a side surface of the interlayer insulating film, and the first electrode may be provided on the upper surface of the interlayer insulating film in contact with the interlayer insulating film.

[0022] According to the above disclosure, the adhesion of the first electrode is improved, and peeling of the first electrode from the interlayer insulating film can be suppressed.

[0023] (6) In addition, in the semiconductor device according to any one of (1) to (4) above, the titanium silicide film covers the entire surface of the interlayer insulating film, and the first electrode is provided on the upper surface of the interlayer insulating film via the titanium silicide film and the titanium nitride film.

[0024] According to the above disclosure, it is possible to suppress damage to the interlayer insulating film caused by ultrasonic vibrations during wire bonding to the first electrode.

[0025] (7) A method for manufacturing a semiconductor device according to one aspect of this disclosure is as follows: a first step is performed in which a second semiconductor region of a second conductivity type is formed in a surface region of the front surface of a semiconductor substrate, the second semiconductor region being in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate, and an element structure including a pn junction between the second semiconductor region and the first semiconductor region is formed; a second step is performed in which an interlayer insulating film is formed on the front surface of the semiconductor substrate to cover the element structure; a third step is performed in which a contact hole is formed that penetrates the interlayer insulating film in the depth direction and reaches the semiconductor substrate; and a fourth step is performed in which a contact structure is formed in the contact hole to contact the semiconductor substrate.

[0026] A fifth step is performed to form a first electrode electrically connected to the second semiconductor region via the contact structure. After the fifth step, a first annealing step is performed to repair crystal damage to the semiconductor substrate by heat treatment in a hydrogen atmosphere. The fourth step includes first to third deposition steps. In the first deposition step, a titanium silicide film is deposited by sputtering to cover the entire surface of the interlayer insulating film and to be in contact with the semiconductor substrate in the contact hole. In the second deposition step, a titanium nitride film is deposited by sputtering on the surface of the titanium silicide film. In the third deposition step, a metal plug is embedded on the titanium nitride film inside the contact hole. The contact structure is formed, consisting of the titanium silicide film, the titanium nitride film, and the metal plug.

[0027] According to the above disclosure, the first electrode and the semiconductor substrate are electrically connected via a TiSix film (titanium silicide film), thereby reducing the contact resistance between the first electrode and the semiconductor substrate. Furthermore, according to the above disclosure, forming the TiSix film does not require special high-temperature heat treatment, such as silicidation. This makes it possible to suppress localized stress in the semiconductor substrate. Furthermore, since a Ti film that adsorbs hydrogen is not formed on the surface of the interlayer insulating film, it is easy to repair crystal damage to the semiconductor substrate caused by hydrogen annealing. Furthermore, since a Ti film is not formed on the surface of the interlayer insulating film, it is possible to prevent a decrease in adhesion with the interlayer insulating film due to a reaction between the material gas and the Ti film during metal plug formation.

[0028] (8) The method for manufacturing a semiconductor device according to the present disclosure further includes, in the above-described (7), a sixth step of forming a contact trench of a predetermined depth in the front surface of the semiconductor substrate, the contact trench being continuous with the contact hole, after the third step and before the fourth step. In the first deposition step, the titanium silicide film may be formed on the surface of the interlayer insulating film and along the inner wall of the contact trench.

[0029] According to the disclosure above, the contact area between the TiSix film and the semiconductor substrate is increased, so that an increase in the contact resistance between the first electrode and the semiconductor substrate can be suppressed.

[0030] (9) Furthermore, the method for manufacturing a semiconductor device according to the present disclosure may further include, in the above-described (8), a seventh step of planarizing the interlayer insulating film after the sixth step and before the fourth step.

[0031] According to the above disclosure, it is possible to improve the embedding property of the metal plug in the contact trench.

[0032] (10) In addition, in the method for manufacturing a semiconductor device according to this disclosure, in any one of the above-mentioned (7) to (9), the first deposition step and the second deposition step may be performed consecutively using the same sputtering apparatus.

[0033] According to the above disclosure, the process can be simplified and costs can be reduced.

[0034] (11) In the method for manufacturing a semiconductor device according to the present disclosure, in any one of (7) to (10) above, the fourth step may further include a removal step of etching back the titanium nitride film and the titanium silicide film using the metal plug as a mask to expose an upper surface of the interlayer insulating film. In the fifth step, the first electrode may be formed on the upper surface of the interlayer insulating film in contact with the interlayer insulating film.

[0035] According to the above disclosure, the adhesion of the first electrode is improved, and peeling of the first electrode from the interlayer insulating film can be suppressed.

[0036] (12) In the method for manufacturing a semiconductor device according to any one of (7) to (11) above, the first deposition step may be performed in an atmosphere at a temperature of 300° C. or less.

[0037] According to the above disclosure, it is possible to suppress stresses that occur locally in a semiconductor substrate.

[0038] (13) In addition, in the method for manufacturing a semiconductor device according to any one of (7) to (12) above, after the first annealing step, an irradiation step of irradiating the semiconductor substrate with radiation may be performed. After the irradiation step, a second annealing step of adjusting a parasitic diode formed at the pn junction to have a predetermined reverse recovery characteristic by heat treatment in a hydrogen atmosphere may be performed.

[0039] According to the above disclosure, it is possible to repair the crystal damage that causes the gate threshold voltage to decrease.

[0040] <Findings underlying the present disclosure> Problems to be solved by the present embodiment include reducing the contact (electrical contact) resistance between the front electrode and the semiconductor substrate, and recovering, by hydrogen annealing (heat treatment in a hydrogen atmosphere), crystal damage caused in the semiconductor substrate by irradiation with radiation such as electron beams, impurity ion implantation, etc. Conventionally, a method has been known in which a titanium silicide (TiSix) film is formed between the front electrode and the semiconductor substrate by subjecting a Ti film to a silicidation reaction with the semiconductor substrate (Si substrate) because titanium (Ti) has low contact resistance with n-type silicon (Si). However, the volume expansion of the TiSix film due to silicidation increases stress locally generated in the semiconductor substrate.

[0041] The higher the heat treatment temperature for silicidation, the lower the contact resistance between the TiSix film and the semiconductor substrate, but the greater the local stress generated in the semiconductor substrate due to the volumetric expansion of the TiSix film caused by silicidation. For example, when the contact structure of the front electrode is embedded in a contact trench provided on the front surface of the semiconductor substrate to increase the contact area with the semiconductor substrate and thereby reduce the contact resistance between the front electrode and the semiconductor substrate, the TiSix film is formed along the inner wall of the contact trench. Because the contact trench is narrow and shallow, there is a concern that the volumetric expansion of the TiSix film caused by silicidation will further increase the local stress generated in the semiconductor substrate.

[0042] Furthermore, when a TiSix film is formed by a silicide reaction with a semiconductor substrate, a Ti film, which is a material film for the TiSix film, is formed to cover the entire surface of the interlayer insulating film. However, this Ti film easily absorbs hydrogen, hindering the effect of hydrogen annealing to repair crystal damage to the semiconductor substrate. Therefore, even if hydrogen annealing is performed, it is difficult to restore characteristics such as gate threshold voltage. In particular, the p-type base region and n-type - In a product (semiconductor device) that has been irradiated with radiation such as electron beams in order to improve switching characteristics such as the reverse recovery time trr of a parasitic diode (body diode) formed at a pn junction (main junction) with a type drift region, crystal damage caused in the semiconductor substrate by the radiation irradiation is not sufficiently repaired.

[0043] It is possible to set the predetermined characteristics of a product to a predetermined value by, for example, excessively increasing the impurity dose in a predetermined diffusion region within the semiconductor substrate, anticipating the degradation due to the crystal damage of the semiconductor substrate. However, in this case, the predetermined characteristics may be higher than the predetermined value due to the recovery of the crystal damage of the semiconductor substrate by hydrogen annealing, which is likely to cause characteristic fluctuations in reliability tests such as high-temperature application tests. As a result, product specifications must be designed to take into account some degree of characteristic fluctuations due to crystal damage of the semiconductor substrate, resulting in inferior product reliability (the reliability of various characteristics evaluated in reliability tests such as high-temperature application tests). This embodiment is intended to solve this problem.

[0044] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0045] (Details of First Embodiment) A semiconductor device according to a first embodiment that solves the above-described problems will be described below using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS field effect transistor having an insulated gate formed of a three-layer structure of metal-oxide film-semiconductor) as an example. FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. A semiconductor device 10 according to the first embodiment shown in FIG. 1 is a vertical MOSFET with a trench gate structure (element structure) that has a contact structure made of a titanium silicide (TiSix) film 11 (where x is a positive number), a titanium nitride (TiN) film 12, and a metal plug (extraction electrode portion) 13 between a front surface electrode (first electrode) 14 and a semiconductor substrate (semiconductor chip) 8.

[0046] The semiconductor substrate 8 is, for example, n - n-type drift region (first semiconductor region) 1 - Type Si bulk substrate, or n + The n-type drain region 15 + n-type starting substrate (Si bulk substrate) - n-type drift region 1 - The semiconductor substrate 8 is a Si substrate on which an n-type epitaxial layer is stacked. - n-type drift region 1 - In the case of a type Si bulk substrate, + The n-type drain region 15 is a diffusion region formed in the surface region of the back surface of the semiconductor substrate 8 by ion implantation. + The n-type drain region 15 is connected to the back surface of the semiconductor substrate 8. - Between the n-type drift region 1, - The n-type drift region 1 is provided on the entire rear surface of the semiconductor substrate 8. + A back electrode (second electrode) 16 is provided in contact with the type drain region 15 to serve as a drain electrode.

[0047] The trench gate structure has a p-type base region (second semiconductor region) 2, an n + type source region 3, p + The p-type base region 2, n-type contact region 4, trench 5, gate insulating film 6, and gate electrode 7 are provided on the front surface side of a semiconductor substrate 8. + type source region 3 and p + The p-type contact region 4 is a diffusion region formed by ion implantation in the surface region of the front surface of the semiconductor substrate 8. The p-type base region 2 is a region between the front surface of the semiconductor substrate 8 and the n-type - Between the n-type drift region 1, - The n-type drift region 1 is provided in contact with the n-type drift region 1. + type source region 3 and p + The contact regions 4 are selectively provided between the front surface of the semiconductor substrate 8 and the p-type base region 2 in contact with the p-type base region 2 .

[0048] n + type source region 3 and p +The contact region 4 is in ohmic contact with the TiSix film 11. + The contact region 4 is provided at a distance from the trench 5. + The n-type contact region 4 is formed on the front surface of the semiconductor substrate 8. + n-type source region 3 + The ion implantation reaches a deep position on the side of the drain region 15 (the back surface side of the semiconductor substrate 8). + The p-type contact region 4 may not be provided. + The p-type base region 2 is in contact with the TiSix film 11 instead of the n-type contact region 4. + type source region 3, p + type contact region 4 and n + The portion excluding the drain region 15 is n - This is the type drift region 1.

[0049] The trench 5 is formed in a depth direction from the front surface of the semiconductor substrate 8 to the n-type + through the p-type source region 3 and the p-type base region 2; - The n-type drift region 1 terminates inside the n-type drift region 1. A gate insulating film 6 is provided along the inner wall (side wall and bottom surface) of the trench 5. A gate electrode 7 is buried on the gate insulating film 6 inside the trench 5. + a p-type source region 3, a p-type base region 2, and an n - The upper ends of the gate electrode 7 and the gate insulating film 6 (the end on the opening side of the trench 5) are located n-type from the front surface of the semiconductor substrate 8. + It may terminate at a deep position on the side of the type drain region 15 (i.e., inside the trench 5).

[0050] The interlayer insulating film 9 is provided on the front surface of the semiconductor substrate 8 and covers the gate electrode 7. A contact hole 9a is provided, penetrating the interlayer insulating film 9 in the depth direction to reach the semiconductor substrate 8. The cross-sectional shape of the contact hole 9a may be substantially rectangular or may be substantially tapered (trapezoidal) with its width narrowing toward the semiconductor substrate 8. When the source contact trench 8a described below is provided, it is preferable to improve the embeddability of the metal plug 13 into the source contact trench 8a by making the thickness of the interlayer insulating film 9 relatively thin to reduce the aspect ratio (depth / width) of the contact hole 9a or by rounding the upper surface corners (boundaries between the upper surface and side surfaces) of the interlayer insulating film 9 by reflow (planarization) of the interlayer insulating film 9.

[0051] The interlayer insulating film 9 is composed of a silicon oxide (SiO2) film such as a BPSG (Boro Phospho Silicate Glass) film 9-2. For example, by setting the sum of the boron (B) concentration and phosphorus (P) concentration of the BPSG film 9-2 to, for example, 6 mol% or less and reflowing the BPSG film 9-2, the width w1 of the contact hole 9a is relatively widened on the opposite side to the semiconductor substrate 8 side (i.e., the portion continuous with the source contact trench 8a). This makes it difficult for the contact hole 9a to be blocked when the W film 13a (see FIG. 5) is filled in, thereby improving the embeddability of the metal plug 13 in the source contact trench 8a.

[0052] The interlayer insulating film 9 may include a deposited SiO film (hereinafter referred to as an HTO film) 9-1 deposited by typical high-temperature oxidation (HTO). In this case, the interlayer insulating film 9 has a two-layer structure, for example, with an HTO film 9-1 and a BPSG film 9-2 stacked in this order. The HTO film 9-1 has high film density and insulating performance comparable to that of a thermal oxide film, and has better insulating properties than a deposited SiO film formed by PECVD or sputtering. The inclusion of the HTO film 9-1 in the interlayer insulating film 9 improves the short-circuit resistance between electrodes electrically insulated by the interlayer insulating film 9 (between the gate electrode 7 and the front electrode 14), thereby improving the reliability of the semiconductor device 10. A deposited SiO film using TEOS (tetraethoxysilane) may be used instead of the HTO film 9-1.

[0053] A source contact trench 8a is provided in the front surface of the semiconductor substrate 8, continuing from the contact hole 9a of the interlayer insulating film 9. The source contact trench 8a extends from the front surface of the semiconductor substrate 8 to the n-type + through the p-type source region 3 + The source contact trench 8 a is formed on the n-type contact region 4 from the front surface of the semiconductor substrate 8 . + n-type source region 3 + The bottom surface of the source contact trench 8a reaches a deep position on the side of the p-type drain region 15. + The source contact trench 8a is surrounded by the contact region 4 and has a p + The source contact trench 8a has a sidewall that is exposed to the n-type contact region 4. + type source region 3 and p + The source contact region 4 is exposed. The cross-sectional shape of the source contact trench 8 a may be substantially rectangular, or may be substantially tapered with a width w2 narrowing toward the back surface side of the semiconductor substrate 8.

[0054] The width w2 of the source contact trench 8a is narrower than the width w1 of the contact hole 9a. The reason for this is that after the source contact trench 8a, which is continuous with the contact hole 9a, is formed in a self-aligned manner using the etching mask used to form the contact hole 9a, the interlayer insulating film 9 (BPSG film 9-2) is reflowed, causing the side surface of the interlayer insulating film 9 (the sidewall of the contact hole 9a) to move (set back) by a predetermined distance d in a direction away from the source contact trench 8a, thereby widening the width w1 of the contact hole 9a. Between the side surface of the interlayer insulating film 9 and the sidewall of the source contact trench 8a, the front surface of the semiconductor substrate 8 is exposed by a distance d of approximately 10 nm or less, resulting in a step with a height difference of the distance d.

[0055] By providing the source contact trench 8a, the contact area between the TiSix film 11 and the semiconductor substrate 8 is increased. Therefore, even if the width w1 of the contact hole 9a is narrowed by narrowing the width between the adjacent trenches 5 for miniaturization, it is possible to suppress an increase in the contact resistance between the front surface electrode 14 and the semiconductor substrate 8. In addition, by providing the source contact trench 8a, when the semiconductor substrate 8 is turned off, - Holes in the type drift region 1 are easily extracted to the front surface electrode 14, improving the avalanche resistance. When the semiconductor device 10 is designed for a low breakdown voltage class of about 250 V or less or when miniaturized, avalanche breakdown is more likely to occur due to parasitic bipolar action, so providing the source contact trench 8 a is recommended. By providing the source contact trench 8 a, the avalanche resistance can be improved not only in the case of a low breakdown voltage class but also in all breakdown voltage classes.

[0056] The source contact trench 8 a may not be provided. In this case, the n-type semiconductor substrate 8 is formed on the front surface exposed through the contact hole 9 a. + type source region 3 and p +The source contact region 4 is in ohmic contact with the TiSix film 11. The TiSix film 11 and the TiN film 12 are provided from the sidewall (side surface of the interlayer insulating film 9) to the bottom surface (front surface of the semiconductor substrate 8 exposed in the contact hole 9a) of the contact hole 9a, and a metal plug 13 is buried on the TiN film 12 inside the contact hole 9a. The conditions of the TiSix film 11 and the TiN film 12 on the sidewall and bottom surfaces of the contact hole 9a are the same as those of the sidewall and bottom surfaces of the source contact trench 8a.

[0057] A TiSix film 11 and a TiN film 12 are laminated in this order on the sidewall of the contact hole 9a (the side surface of the interlayer insulating film 9), the surface connecting the sidewall of the contact hole 9a and the sidewall of the source contact trench 8a (hereinafter referred to as the step surface), and along the inner wall of the source contact trench 8a. The TiSix film 11 and the TiN film 12 are not provided on the upper surface of the interlayer insulating film 9. The upper surface of the interlayer insulating film 9 refers to the surface of the interlayer insulating film 9 other than the portion that forms the sidewall of the contact hole 9a. The front surface electrode 14 is in direct contact with the upper surface of the interlayer insulating film 9, thereby improving adhesion of the front surface electrode 14 and preventing peeling of the front surface electrode 14 from the interlayer insulating film 9.

[0058] Furthermore, by not providing the TiSix film 11 and the TiN film 12 on the upper surface of the interlayer insulating film 9, it is possible to suppress damage to the relatively hard TiSix film 11 and the TiN film 12 caused by ultrasonic vibrations during wire bonding to the front surface electrode 14. Furthermore, by not providing the TiSix film 11 and the TiN film 12 on the upper surface of the interlayer insulating film 9, the effect of hydrogen annealing for recovering crystal damage to the semiconductor substrate 8 is not hindered. Therefore, for example, irradiation with radiation such as an electron beam can be prevented. - By controlling the carrier lifetime of the type drift region 1, crystal damage caused in the semiconductor substrate 8 can be repaired by hydrogen annealing, and characteristics such as the gate threshold voltage can be restored.

[0059] The TiSix film 11 and the TiN film 12 are formed (deposited) by sputtering and tend to be thicker at the bottom of the source contact trench 8a than at the sidewall of the contact hole 9a, the step surface (the front surface of the semiconductor substrate 8), and the source contact trench 8a. The thicknesses of the TiSix film 11 and the TiN film 12 are substantially uniform from the sidewall of the contact hole 9a to the sidewall of the source contact trench 8a. This results in uniform stress being applied to the interlayer insulating film 9 and the semiconductor substrate 8 on the sidewall of the contact hole 9a and the sidewall of the source contact trench 8a. "Substantially uniform thickness" means that the thicknesses are substantially the same within a range that includes tolerances due to manufacturing process variations.

[0060] The TiSix film 11 is formed on the inner wall of the source contact trench 8a. + type source region 3 and p + The source contact trench 8a is in ohmic contact with the source contact region 4. By providing the source contact trench 8a, the contact area between the TiSix film 11 and the semiconductor substrate 8 can be increased, thereby reducing the contact resistance between the TiSix film 11 and the semiconductor substrate 8. Therefore, even if the width w1 of the contact hole 9a is narrowed due to miniaturization, an increase in the contact resistance between the front surface electrode 14 and the semiconductor substrate 8 can be suppressed. The TiN film 12 is a barrier metal that has the function of preventing diffusion of metal atoms from the front surface electrode 14 to the semiconductor substrate 8 and the function of preventing mutual reaction between parts facing each other across the TiN film 12.

[0061] The end of the TiSix film 11 terminates on the surface of the interlayer insulating film 9 (e.g., on the side surface of the interlayer insulating film 9). The end of the TiN film 12 terminates on the surface of the TiSix film 11. The TiSix film 11 has higher adhesion to the interlayer insulating film 9 than the TiN film 12. Therefore, providing the TiSix film 11 between the TiN film 12 and the interlayer insulating film 9 improves the adhesion of the front surface electrode 14. A metal plug 13 is provided on the TiN film 12 so as to fill the contact hole 9a and the source contact trench 8a. The height position of the upper surface of the metal plug 13 is either at the same height as the end of the TiN film 12 or lower toward the semiconductor substrate 8 than the height position of the end of the TiN film 12. The material of the metal plug 13 is, for example, tungsten (W), which has a high embedding property and therefore has poor adhesion to the semiconductor substrate 8. By providing the TiSix film 11 and the TiN film 12 between the semiconductor substrate 8 and the metal plug 13, the adhesion of the metal plug 13 is improved.

[0062] The TiSix film 11, TiN film 12, and metal plug 13 form a contact structure for the front surface electrode 14. The front surface electrode 14 may be embedded in the contact hole 9a and the source contact trench 8a instead of the metal plug 13 without providing the metal plug 13. In this case, the TiN film 12 does not need to be provided. That is, the contact structure for the front surface electrode 14 may be formed only by the TiSix film 11 that makes ohmic contact with the semiconductor substrate 8. The front surface electrode 14 is provided from the upper surface of the interlayer insulating film 9 to the upper surface of the metal plug 13, in contact with them. The front surface electrode 14 is, for example, an aluminum (Al) film or an Al alloy film. The front surface electrode 14 is connected to the p-type base region 2, n-type base region 3, and p-type base region 4 via the metal plug 13, the TiN film 12, and the TiSix film 11. + type source region 3 and p + It is electrically connected to the contact region 4 and functions as a source electrode.

[0063] A method for manufacturing the semiconductor device 10 according to the first embodiment will be described. FIGS. 2 to 6 are cross-sectional views showing the semiconductor device according to the first embodiment in the course of its manufacture. First, as shown in FIG. 2, n -A trench gate structure, an interlayer insulating film 9 (HTO film 9-1 and BPSG film 9-2), and contact holes 9a are formed on the front surface of the semiconductor substrate 8, which will become the type drift region 1 (steps 1 to 3). Next, the front surface of the semiconductor substrate 8 is etched using the same resist mask used to form the contact holes 9a, to form source contact trenches 8a that are continuous with the contact holes 9a (step 6). The resist mask used to form the source contact trenches 8a is then removed. In this case, it is also possible to remove the resist mask after forming the contact holes 9a and then form the source contact trenches 8a using the interlayer insulating film 9 as a mask.

[0064] Next, the BPSG film 9-2 is reflowed by heat treatment while oxidizing the exposed surface of the semiconductor substrate 8 (here, the inner wall of the source contact trench 8a) (step 7). This rounds the upper corners of the BPSG film 9-2, and the side surface of the BPSG film 9-2 retreats a predetermined distance d away from the source contact trench 8a. Next, the oxide film covering the semiconductor substrate 8 within the contact hole 9a is removed. At this time, the end of the HTO film 9-1 (the portion exposed by the retreat of the side surface of the BPSG film 9-2 by the predetermined distance d) is also removed along with the oxide film, and the side surface of the HTO film 9-1 also retreats a predetermined distance d away from the source contact trench 8a.

[0065] In this manner, the side surfaces of the interlayer insulating film 9 (HTO film 9-1 and BPSG film 9-2) are recessed by a predetermined distance d in a direction away from the source contact trench 8a, thereby widening the width w1 of the contact hole 9a. This improves the embedding ability of the W film 13a (see FIG. 5) deposited on the front surface of the semiconductor substrate 8 in a later process into the source contact trench 8a. Furthermore, by reflowing the BPSG film 9-2 while oxidizing the exposed surface of the semiconductor substrate 8, the distance d by which the side surfaces of the interlayer insulating film 9 are recessed in a direction away from the source contact trench 8a can be reduced to approximately 10 nm or less. This improves the step coverage of the W film 13a deposited on the front surface of the semiconductor substrate 8 in a later process.

[0066] Next, as shown in FIG. 3, in an atmosphere at a temperature of about 300° C. or less (e.g., about 200° C.), a TiSix film 11 is deposited (formed) along the surface (top and side surfaces) of the interlayer insulating film 9 and the inner wall (bottom and sidewalls) of the source contact trench 8a by sputtering (first deposition step). The thickness of the TiSix film 11 is, for example, about 40 nm. Because no special heat treatment such as silicidation of the Ti film is performed, the TiSix film 11 maintains its thickness at the time of sputtering and does not expand in volume. Next, as shown in FIG. 4, in an atmosphere at a temperature of about 300° C. or less (e.g., about 200° C.), a TiN film 12 is deposited (formed) along the surface of the TiSix film 11 by sputtering (second deposition step).

[0067] The TiSix film 11 and the TiN film 12 may be formed using different sputtering apparatuses. Alternatively, the TiSix film 11 and the TiN film 12 may be formed consecutively using the same sputtering apparatus capable of mounting multiple sputtering targets, by appropriately switching the sputtering targets, introduced gases, and the like. By forming the TiSix film 11 and the TiN film 12 consecutively using the same sputtering apparatus, the process can be simplified and costs can be reduced. The conditions for the sputtering targets, introduced gases, and the like used to form the TiSix film 11 and the TiN film 12, respectively, can be general conditions.

[0068] 5, a W film 13a is deposited (formed) on the outermost surface of the semiconductor substrate 8 so as to fill the contact hole 9a and the source contact trench 8a by CVD using WF gas as a material gas and monosilane (SiH) gas or hydrogen (H) gas as a source gas. At this time, the TiSix film 11 and TiN film 12 covering the entire surface of the interlayer insulating film 9 function as barrier metal. Therefore, even if the material gas for the W film 13a permeates the TiN film 12 at a location where its function as a barrier metal has deteriorated, a chemical reaction that generates fluorine (F) or H, which would reduce adhesion to the interlayer insulating film 9, does not occur, as would occur if a titanium (Ti) film were provided as a barrier metal.

[0069] 6, the W film 13a is etched back to leave the W film 13a only inside the contact hole 9a and the source contact trench 8a (third deposition step). The W film 13a left inside the contact hole 9a and the source contact trench 8a becomes the metal plug 13. Next, the TiN film 12 and the TiSix film 11 are etched back using the metal plug 13 as an etching mask to expose the top surface of the interlayer insulating film 9 (removal step). The dry etching for etching back the W film 13a and the dry etching for etching back the TiN film 12 and the TiSix film 11 may be performed consecutively by switching etching gases, or may be performed using different etching apparatuses.

[0070] Next, a front electrode 14 is formed on the outermost surface of the front surface of the semiconductor substrate 8 by sputtering and photoetching (fifth step). Then, the resist mask used to form the front electrode 14 is removed (ashing). After that, crystal damage to the semiconductor substrate 8 is repaired by hydrogen annealing in an atmosphere at a temperature of, for example, about 380°C (first annealing step). This hydrogen annealing may be performed at any time after the formation of the front electrode 14, but it is effective to perform it after the semiconductor substrate 8 has been damaged by etching, ashing, or the like. Then, a n-type silicon nitride film is formed on the back side of the semiconductor substrate 8. + A type drain region 15 and a back electrode 16 are formed.

[0071] At any time after the hydrogen annealing, the semiconductor substrate 8 is irradiated with radiation such as electron beams from the front or back surface (irradiation step). - The carrier lifetime of the type drift region 1 may be controlled. After the radiation exposure, instead of completely repairing the crystal damage caused by the radiation exposure, the amount of crystal damage in the semiconductor substrate 8 may be adjusted by performing hydrogen annealing in a temperature atmosphere of, for example, about 350°C so that the reverse recovery characteristics of the parasitic diode have a predetermined lifetime (reverse recovery time) (second annealing step). This hydrogen annealing after the radiation exposure may repair the crystal damage that causes the gate threshold voltage to decrease. This completes the semiconductor device 10 shown in FIG. 1 .

[0072] The operation of the semiconductor device 10 according to the first embodiment will be described. When a positive voltage is applied to the drain electrode (rear electrode 16) with respect to the source electrode (front electrode 14), p + The p-type contact region 4 and the p-type base region 2 and the n - Type drift region 1 and n + The pn junction (main junction) with the gate electrode 7 is reverse biased. In this state, if the voltage applied to the gate electrode 7 is less than the gate threshold voltage, the semiconductor device 10 (MOSFET) remains in the off state.

[0073] Only the front electrode 14 is disposed on the interlayer insulating film 9 of the semiconductor device 10, and the effect of hydrogen annealing is not hindered. Therefore, even if the semiconductor device 10 is irradiated with radiation such as electron beams to improve the switching characteristics of the parasitic diode, the crystal damage in the semiconductor substrate 8 is almost completely repaired by the subsequent hydrogen annealing, and the gate threshold voltage characteristics are restored (see FIG. 9 ). Therefore, the semiconductor device 10 remains normally-off.

[0074] On the other hand, when a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 7 while a voltage positive with respect to the source electrode is applied to the drain electrode, a channel (n-type inversion layer) is formed in the p-type base region 2 along the sidewall of the trench 5. + type drain region 15 to n - through the drift region 1 and the channel + A drift current (main current) flows toward the source region 3, and the semiconductor device 10 turns on.

[0075] As described above, according to the first embodiment, the front surface electrode and the semiconductor substrate are electrically connected via the TiSix film deposited on the semiconductor substrate by sputtering. By electrically connecting the front surface electrode and the semiconductor substrate via the TiSix film, it is possible to reduce the contact resistance between the front surface electrode and the semiconductor substrate. Furthermore, according to the first embodiment, forming the TiSix film on the semiconductor substrate does not require a special high-temperature heat treatment, for example, at 600°C or higher, such as silicidation, and the TiSix film is directly deposited by sputtering in a low-temperature atmosphere of 300°C or lower, thereby suppressing stress locally occurring in the semiconductor substrate.

[0076] Furthermore, for example, when a TiSix film is formed by a silicide reaction with a semiconductor substrate, the Ti film, which is the material film for the TiSix film, covers the entire surface of the interlayer insulating film. This impairs the effectiveness of hydrogen annealing for repairing crystalline damage to the semiconductor substrate, or it is necessary to remove the portion of the Ti film covering the top surface of the interlayer insulating film in order to obtain the effect of hydrogen annealing. On the other hand, according to the first embodiment, by directly depositing the TiSix film by sputtering, a Ti film is not formed on the surface of the interlayer insulating film, which facilitates repair of crystalline damage to the semiconductor substrate caused by hydrogen annealing. For example, even in products (semiconductor devices) that have been irradiated with radiation such as electron beams to improve switching characteristics such as the reverse recovery time of the body diode, crystalline damage to the semiconductor substrate can be sufficiently repaired by hydrogen annealing.

[0077] That is, according to the first embodiment, it is not necessary to set the gate threshold voltage high in advance, for example, by excessively increasing the impurity dose in a predetermined diffusion region in the semiconductor substrate, assuming that the gate threshold voltage will be lowered due to crystal damage to the semiconductor substrate. Therefore, characteristic fluctuations are less likely to occur in reliability tests such as high-temperature application tests, improving product reliability (the reliability of various characteristics evaluated in reliability tests such as high-temperature application tests). Furthermore, according to the first embodiment, since a Ti film is not used as a barrier metal, problems caused by the reaction between a material gas and a Ti film during metal plug formation (see the comparative example described below) do not occur. Therefore, it is possible to prevent a decrease in adhesion with the interlayer insulating film.

[0078] Furthermore, for example, when a CVD method is used to deposit a TiSix film and a TiN film, the TiSix film and the TiN film cannot be successively formed in the same CVD apparatus because the conditions, such as the gas species, used to form the TiSix film and the TiN film are different. On the other hand, according to the first embodiment, by depositing the TiSix film by sputtering, the TiSix film and the TiN film can be successively formed in the same sputtering apparatus. This simplifies the process and reduces costs. Furthermore, the process of transporting the semiconductor wafer between the formation of the TiSix film and the formation of the TiN film can be omitted, thereby suppressing contamination during wafer transport, improving the yield rate, and improving product reliability.

[0079] (Details of Second Embodiment) A semiconductor device according to a second embodiment that solves the above-mentioned problems will be described below. Fig. 7 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. Fig. 8 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the second embodiment. A semiconductor device 20 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment (see Fig. 1) in that the TiSix film 21 and the TiN film 22 that form the contact structure of the front surface electrode 14 extend between the front surface electrode 14 and the interlayer insulating film 9 to cover the entire surface of the interlayer insulating film 9.

[0080] The TiSix film 21 and the TiN film 22 inside the contact hole 9a and the source contact trench 8a have the same configurations as the TiSix film 11 and the TiN film 12, respectively, of the first embodiment. The TiSix film 21 and the TiN film 22 function as barrier metals that suppress diffusion of metal atoms from the front surface electrode 14 into the interlayer insulating film 9. The TiSix film 21 and the TiN film 22 have the function of suppressing damage to the interlayer insulating film 9 due to ultrasonic vibrations that occur during wire bonding to the front surface electrode 14.

[0081] The method for manufacturing the semiconductor device 20 according to the second embodiment is the same as the method for manufacturing the semiconductor device 10 according to the first embodiment except that the etch-back of the TiSix film 11 and the TiN film 12 (see FIG. 6) is omitted. That is, similar to the first embodiment, the steps from the formation of the trench gate structure to the formation of the metal plug 13 are performed in order (FIGS. 2 to 5 and 8). Thereafter, the steps from the formation of the front surface electrode 14 onward are performed in order while leaving the TiSix film 11 and the TiN film 12 on the upper surface of the interlayer insulating film 9 (FIG. 8), thereby completing the semiconductor device 20 shown in FIG.

[0082] Even if the TiSix film 11 and the TiN film 12 are left on the upper surface of the interlayer insulating film 9, the effect of hydrogen annealing for recovering crystal damage to the semiconductor substrate 8 is not hindered. Furthermore, the TiSix film 21 has higher adhesion to the interlayer insulating film 9 than the TiN film 22 and the front surface electrode 14. Therefore, the TiSix film 21 improves the adhesion of the front surface electrode 14. Furthermore, the process for removing part of the TiSix film 11 and the TiN film 12 can be omitted, which allows for a reduction in the number of processes and particles.

[0083] As described above, according to the second embodiment, even if the upper surface of the interlayer insulating film is covered with a TiSix film and a TiN film, it is possible to obtain the same effects as those of the first embodiment. According to the second embodiment, the number of steps is reduced and particles are reduced, thereby improving the yield rate and reducing costs.

[0084] (Experimental Example) The relationship between the degree of recovery of crystal damage in a semiconductor substrate due to hydrogen annealing and the barrier metal was examined. Figure 9 is a diagram showing the relationship between the degree of recovery of crystal damage in a semiconductor substrate due to hydrogen annealing and the barrier metal. Figure 9 shows the results of examining the degree of recovery of crystal damage in a semiconductor substrate due to hydrogen annealing using four samples (hereinafter referred to as samples 1 to 4) with different conditions (presence or absence of barrier metal, presence or absence of crystal damage in the semiconductor substrate) for a typical trench gate structure MOSFET (hereinafter referred to as an experimental example).

[0085] Sample 1 has a Ti film on the interlayer insulating film as a barrier metal, and the semiconductor substrate does not suffer from crystalline damage due to radiation exposure (Ti present, no damage). Sample 2 has a Ti film on the interlayer insulating film as a barrier metal, and the semiconductor substrate suffers from crystalline damage due to radiation exposure (Ti present, damage). Sample 3 has no barrier metal, and the semiconductor substrate suffers from crystalline damage due to radiation exposure (Ti absent, damage). Sample 4 has no barrier metal, and the semiconductor substrate does not suffer from crystalline damage due to radiation exposure (Ti absent, no damage).

[0086] 9 indicates whether the gate threshold voltage after recovery from crystal damage in the semiconductor substrate due to hydrogen annealing has recovered to the design value of the gate threshold voltage, and the degree of recovery from crystal damage in the semiconductor substrate due to hydrogen annealing in Sample 4 is used as the reference (=100%). In Fig. 9, "damaged / no damage" indicates the presence or absence of crystal damage due to radiation exposure, and hydrogen annealing was performed on all of Samples 1 to 4 in a state where similar crystal damage had occurred in the semiconductor substrate during other manufacturing processes (e.g., ion implantation, etc.).

[0087] 9, the results of Sample 2 confirmed that having a Ti film as a barrier metal does not sufficiently recover crystal damage to the semiconductor substrate caused by radiation exposure. Furthermore, the results of Sample 3 confirmed that not having a Ti film as a barrier metal allows recovery of crystal damage to the semiconductor substrate caused by radiation exposure to the same degree as Samples 1 and 4, which are free of crystal damage caused by radiation exposure. Furthermore, the fact that the damage recovery rate of Sample 3 is higher than that of Sample 1 indicates that not having a Ti film as a barrier metal also increases the recovery rate of crystal damage caused to the semiconductor substrate in processes other than radiation exposure.

[0088] Comparative Examples As comparative examples, MOSFETs will be described in which the contact resistance between the front electrode and the semiconductor substrate is reduced by providing a high-hardness, high-melting-point metal film, such as Ti or nickel (Ni), or a titanium silicide (TiSi) film formed by silicidating a Ti film, between the front electrode and the semiconductor substrate. Figures 10 and 11 are cross-sectional views showing the structures of comparative examples 1 and 2, respectively. Semiconductor devices 110 and 120 shown in Figures 10 and 11 (hereinafter referred to as comparative examples 1 and 2) are vertical MOSFETs with a typical trench gate structure, and each has a different contact structure between a front electrode 114 and a semiconductor substrate 108.

[0089] In Comparative Examples 1 and 2, the trench gate structure includes a p-type base region 102 and an n-type + type source region 103, p + The gate electrode 107 is formed of a gate-type contact region 104, a trench 105, a gate insulating film 106, and a gate electrode 107. The gate electrode 107 is connected to the front surface of the semiconductor substrate 108 and the n-type contact region 104. - The interlayer insulating film 109 is provided on the front surface of the semiconductor substrate 108 and covers the gate electrode 107. The back surface of the semiconductor substrate 108 and the n-type drift region 101 are - Between the n-type drift region 101, + The semiconductor substrate 108 has an n-type drain region 115 on the rear surface thereof. + A back electrode 116 serving as a drain electrode is provided in contact with the drain region 115 .

[0090] Comparative Example 1 (semiconductor device 110 shown in FIG. 10) has a source contact trench 108a on the front surface of a semiconductor substrate 108, the source contact trench 108a being continuous with a contact hole 109a in an interlayer insulating film 109. The inner wall of the source contact trench 108a is provided with n + type source region 103 and p + The source contact region 104 is exposed. A metal film 111 having high hardness and a high melting point, such as Ti or Ni, and a TiN film 112 are formed in this order by sputtering along the sidewall of the contact hole 109a (the side surface of the interlayer insulating film 109) and the inner wall of the source contact trench 108a.

[0091] The metal film 111 and the TiN film 112 extend onto the upper surface of the interlayer insulating film 109, covering the entire upper surface of the interlayer insulating film 109. A W plug 113 is provided on the TiN film 112 so as to fill the contact hole 109a and the source contact trench 108a. A front surface electrode 114 is provided on the TiN film 112 and the W plug 113. The front surface electrode 114 is connected to the n-type semiconductor substrate 106 via the W plug 113, the TiN film 112, and the metal film 111. + type source region 103 and p + It is electrically connected to the contact region 104 and functions as a source electrode.

[0092] Comparative Example 2 (semiconductor device 120 shown in FIG. 11 ) differs from Comparative Example 1 in that a TiSi film 121 is provided only on the Si portion instead of the metal film 111. Comparative Example 2 does not have a source contact trench 108 a, resulting in a structure in which the thickness of the interlayer insulating film 109 remains thicker than in Comparative Example 1. The TiSi film 121 is formed by a silicide reaction between Ti atoms in the Ti film (Ti film 121 a described later: see FIGS. 13 and 14 ) and Si atoms in the semiconductor substrate 108, and is provided only on the Si portion (i.e., the front surface of the semiconductor substrate 108) within the contact hole 109 a of the interlayer insulating film 109.

[0093] The TiSi film 121 is not provided on the surface of the interlayer insulating film 109. The thickness of the TiSi film 121 is, for example, about 60 nm, and is formed on the n-type surface of the semiconductor substrate 108. +The TiN film 122 is formed along the surface of the TiSi film 121 and the surface of the interlayer insulating film 109. The W plug 123 is embedded in the contact hole 109a and on the TiN film 122. The TiN film 122 is formed along the surface of the TiSi film 121 and the surface of the interlayer insulating film 109. The W plug 123 is embedded in the contact hole 109a and on the TiN film 122.

[0094] A method for manufacturing the comparative example 2 (semiconductor device 120 shown in FIG. 11) will be described. FIGS. 12 to 18 are cross-sectional views showing the state during the manufacturing of the comparative example 2. First, as shown in FIG. 12, a p-type base region 102 and an n-type base region 103 are formed on the front surface side of a semiconductor substrate 108 by a general method. + type source region 103, p + A trench gate structure is formed, which is composed of mold contact region 104, trench 105, gate insulating film 106, and gate electrode 107. Next, interlayer insulating film 109 is formed over the entire front surface of semiconductor substrate 108. Next, contact hole 109a is formed so as to penetrate interlayer insulating film 109 in the depth direction and reach semiconductor substrate 108.

[0095] 13, a Ti film 121a having a thickness of, for example, about 40 nm is formed by sputtering in an atmosphere at a temperature of about 300° C. along the surface of interlayer insulating film 109 and the surface of the portion of semiconductor substrate 108 exposed in contact hole 109a. Next, as shown in FIG. 14, a silicide reaction is caused between Ti film 121a and semiconductor substrate 108 by rapid thermal annealing (RTA) at, for example, about 600° C., to form a TiSi film 121 on the front surface of semiconductor substrate 108 within contact hole 109a. Volume expansion due to silicidation increases the thickness of TiSi film 121 to about 60 nm.

[0096] Next, as shown in Fig. 15, the remaining portion of the Ti film 121a that remains unreacted on the surface of the interlayer insulating film 109 is removed. Next, as shown in Fig. 16, a TiN film 122 is formed by sputtering along the surface of the TiSi film 121 and the surface of the interlayer insulating film 109. Next, as shown in Fig. 17, a W film 123a is formed by CVD on the outermost surface of the front surface of the semiconductor substrate 108 so as to fill the contact hole 109a. Next, as shown in Fig. 18, the W film 123a is etched back, leaving only the portion that will become the W plug 123 in the contact hole 109a.

[0097] Next, a front surface electrode 114 is formed on the top surface of the semiconductor substrate 108. + Next, an n-type drain region 115 and a back surface electrode 116 are formed. - The carrier lifetime of the type drift region 101 is controlled. - The irradiation (radiation for controlling the carrier lifetime of the type drift region 101) causes crystal damage in the semiconductor substrate 108, causing fluctuations in various characteristics such as the gate threshold voltage. Therefore, the crystal damage in the semiconductor substrate 8 is then repaired by hydrogen annealing, thereby completing Comparative Example 2.

[0098] In the above-described comparative example 1, a contact structure using not only a Ti film (metal film 111) but also two layers of a Ti film and a TiN film or three layers of a Ti film, a TiN film, and a Ti film is known. A Ti film has low contact resistance with n-type Si (semiconductor substrate 108). Therefore, in comparative example 1, even if the width of the contact hole 109a is narrowed due to miniaturization, it is possible to suppress an increase in the contact resistance between the front surface electrode 114 and the semiconductor substrate 108. However, in comparative example 1, if the metal film 111 between the front surface electrode 114 and the interlayer insulating film 109 is a Ti film, the effect of hydrogen annealing is inhibited by this Ti film.

[0099] Furthermore, in Comparative Example 1, there is a risk that WF gas, which is a material gas for the W plug 113, may permeate the TiN film 12 and come into contact with the Ti film. When WF gas comes into contact with the Ti film, fluorine and H are generated, which reduce adhesion to the interlayer insulating film 109. Furthermore, a portion of the Ti film is lost, causing lifting or cracks in the overlying TiN film 112. This reduces the adhesion of the front electrode 114. For example, the above problem can be solved by replacing the metal film 111 with a Ni film or by removing the portion of the Ti film covering the surface of the interlayer insulating film 109, but this reduces the function of the metal film 111 as a barrier metal.

[0100] Furthermore, if the portion of the Ti film (metal film 111) covering the surface of the interlayer insulating film 109 is removed, the interlayer insulating film 109 will be damaged by ultrasonic vibrations during wire bonding to the front electrode 114. Furthermore, removing the portion of the Ti film covering the surface of the interlayer insulating film 109 increases the number of processes and reduces the yield rate due to particle generation, resulting in increased costs. Furthermore, if the portion of the Ti film covering the surface of the interlayer insulating film 109 is removed, the TiN film 112, which has lower adhesion to the interlayer insulating film 109 than the Ti film, will come into contact with the interlayer insulating film 109, thereby reducing the adhesion between the interlayer insulating film 109 and the front electrode 114.

[0101] In Comparative Example 2, removing the remaining portion of the Ti film 121a, which is the material of the TiSi film 121 (see FIG. 15), increases the number of steps and generates particles, resulting in a decrease in the yield rate, as in Comparative Example 1. If the remaining portion of the Ti film 121a is left on the interlayer insulating film 109 without being removed, the same problems as in Comparative Example 1 occur during the formation of the W plug 123 and during hydrogen annealing. Furthermore, in Comparative Example 2, the contact resistance between the TiSi film 121 and the semiconductor substrate 108 is reduced, but the volume expansion caused by silicidation makes the thickness of the TiSi film 121 thicker than the thickness of the Ti film 121a at the time of deposition, and the greater the thickness, the greater the stress locally generated in the semiconductor substrate 108.

[0102] Furthermore, in Comparative Examples 1 and 2, assuming that hydrogen annealing will not sufficiently repair the crystal damage in the semiconductor substrate 108, when the predetermined characteristics of the product are adjusted to predetermined values ​​by preliminarily setting the predetermined characteristics higher in anticipation of the reduction due to crystal damage in the semiconductor substrate 108, for example by excessively increasing the impurity dose in a predetermined diffusion region in the semiconductor substrate 108, there is a risk that the predetermined characteristics will become higher than the predetermined value due to the repair of the crystal damage in the semiconductor substrate 108 by hydrogen annealing. As a result, characteristic fluctuations are likely to occur in reliability tests such as high-temperature application tests, and the reliability of the products (semiconductor devices 110, 120) will be inferior.

[0103] For example, in Patent Document 4, a polycrystalline silicon (poly-Si) film deposited on a semiconductor substrate is heated to approximately 500°C and reacted with titanium radicals generated to silicidate the film, thereby forming a TiSi film. Therefore, as in Comparative Example 2, the volume expansion of the TiSi film due to silicidation increases the stress locally generated in the semiconductor substrate. Furthermore, if the silicidation of the polycrystalline silicon film does not reach the semiconductor substrate from the top surface of the polycrystalline silicon film in the depth direction, the contact resistance with the semiconductor substrate increases. Furthermore, since a Ti film is included in the metal wiring, the effect of hydrogen annealing is hindered, as in Comparative Example 1.

[0104] For example, in the above-mentioned Patent Document 5, a TiSi film is formed directly on a semiconductor substrate by PECVD. However, if chlorine (Cl) contained in the PECVD gas composition diffuses into the semiconductor substrate or is mixed as a residue in the TiSi film or the semiconductor substrate, it can cause corrosion of the TiSi film or the semiconductor substrate. Furthermore, a deposited film formed using a plasma-converted material gas has high stress and high resistance. To reduce the resistance of the deposited film, it is expected that it will be necessary to uniform the thickness of the deposited film across the surface by, for example, heat treatment to reduce the sheet resistance, which increases the number of processes.

[0105] In addition, in the above-mentioned Patent Document 5, a TiSi film is formed by reacting a Si film with a Ti film when forming a Ti film by PECVD after forming a Si film on a semiconductor substrate by CVD. However, it is difficult to form a Si film by any method other than crystal growth through a chemical reaction between an introduced gas and a semiconductor substrate (Si substrate). Even if a Si film can be formed by CVD, if the Ti film formed on the entire outermost surface of the semiconductor substrate, including the surface of the Si film, is subsequently reacted with the Si film, the stress of the TiSi film increases due to volume expansion. Furthermore, the remaining Ti film that remains unreacted inhibits the effect of hydrogen annealing, as in Comparative Example 1.

[0106] On the other hand, according to the first and second embodiments (see FIGS. 1 and 7), the metal films provided on at least a portion of the surface of the interlayer insulating film 9 and functioning as barrier metals are the TiSix films 11 and 21 and the TiN films 12 and 22, and no Ti film is provided. Therefore, the effect of hydrogen annealing is not hindered, and there is no decrease in adhesion to the interlayer insulating film 9 due to contact between the material gas of the metal plugs 13 and 23 and the metal film functioning as a barrier metal. Furthermore, the TiSix films 11 and 21 are formed by sputtering in a low-temperature atmosphere of about 300° C. or less, which makes it possible to suppress stresses locally occurring in the semiconductor substrate 8. This improves product reliability.

[0107] Furthermore, according to the second embodiment (see FIG. 7 ), the entire surface of the interlayer insulating film 9 is covered with the TiSix film 21 and the TiN film 22, thereby improving the effect as a barrier metal. Furthermore, the TiSix film 21 and the TiN film 22 can suppress damage to the interlayer insulating film 9 due to ultrasonic vibrations during wire bonding to the front electrode 14. Furthermore, according to the second embodiment, the TiSix film 21 and the TiN film 22 are not selectively removed, which reduces the number of processes and particles, thereby improving the yield rate and reducing costs.

[0108] Furthermore, in the above Patent Documents 1 to 4, the TiSiN film included in the laminated structure of the front surface electrode, unlike the TiSix films 11 and 21 of the first and second embodiments, inhibits the effect of hydrogen annealing for recovering crystal damage in the semiconductor substrate. Furthermore, in Patent Document 1, a Ti film is formed, followed by sputtering to form a TiSiN layer, and then oxidation or heat treatment is performed to oxidize the upper surface of the TiSiN layer, thereby forming a titanium silicon nitride oxide layer, which is an oxide layer of the TiSiN layer, and these are laminated to form a capacitor, which differs from the formation of contact with the semiconductor substrate as in the first and second embodiments. Furthermore, in Patent Document 1, a high-temperature heat treatment exceeding 600°C is performed, which increases stress locally generated in the semiconductor substrate due to volume expansion caused by alloying.

[0109] In Patent Document 2, a TiSiN layer is formed between the semiconductor substrate and the interlayer insulating film, which differs from the structure of the TiSix films 11 and 21 in the first and second embodiments. Furthermore, high-temperature heat treatment is performed, which increases local stress in the semiconductor substrate due to volume expansion caused by alloying. Patent Document 3 relates to a structure in which a first conductive layer containing Si is formed on the surface of a semiconductor substrate, a second conductive layer containing a refractory metal such as a TiSiN layer, Si, and nitrogen, and a third conductive layer containing a platinum group element are formed thereon, and these conductive layers are connected to each other. This structure prevents interdiffusion of Si and the platinum group element even during high-temperature heat treatment, which differs from the structure in which a contact with the semiconductor substrate is formed as in the first and second embodiments. Furthermore, high-temperature heat treatment is performed in Patent Document 3, which increases local stress in the semiconductor substrate due to volume expansion caused by alloying.

[0110] In Patent Document 4, a high-aspect-ratio contact hole is formed in an interlayer insulating film, reaching the semiconductor substrate, and a polycrystalline or amorphous Si film having a thickness that does not fill the contact hole is laminated on the surface of the interlayer insulating film, the side surfaces of the contact hole, and the bottom surface of the contact hole (semiconductor substrate surface). A Ti film is deposited by PECVD while converting the Si film into a TiSi film, and a TiN film is further formed on the surface of the Ti film. This method differs from the methods for forming the TiSix films 11 and 21 in Embodiments 1 and 2. Furthermore, this method differs from Embodiments 1 and 2 in that a polycrystalline or amorphous Si film is laminated. Furthermore, in Patent Document 4, the volume expansion of the TiSi film due to silicidation by high-temperature plasma increases stress locally generated in the semiconductor substrate, and plasma damage may also remain.

[0111] The first example of the contact layer formation method in Patent Document 5 involves forming a high-aspect-ratio contact hole in an interlayer insulating film that reaches the semiconductor substrate, and then depositing a TiSi film by PECVD to a thickness that does not fill the contact hole. This differs from the methods of forming the TiSix films 11 and 21 in the first and second embodiments. Furthermore, in Patent Document 5, chlorine (Cl) contained in the gas composition introduced by PECVD for forming the TiSi film can cause fluctuations in the characteristics of the semiconductor substrate, reduced reliability, and corrosion. Furthermore, there is a risk of residual plasma damage. Furthermore, in the first example of the contact layer formation method in Patent Document 5, if a heat treatment at a temperature higher than the formation temperature of the TiSi film is performed after the formation of the TiSi film, localized stress in the semiconductor substrate increases.

[0112] The second example of the contact layer formation method in Patent Document 5 involves forming a high-aspect ratio contact hole in an interlayer insulating film that reaches the semiconductor substrate, forming a Si film by low-pressure CVD (LPCVD) to a thickness that does not fill the contact hole, and then forming a Ti film by PECVD while reacting with the Si film to convert it into a TiSi film, which differs from the methods of forming the TiSix films 11 and 21 in the first and second embodiments. Furthermore, in the second example of the contact layer formation method in Patent Document 5, residual Cl from the TiCl gas used can cause characteristic fluctuations and reduced reliability, and there is a risk of residual plasma damage. Furthermore, due to silicidation in plasma, the volume expansion of the TiSi film increases stress locally generated in the semiconductor substrate.

[0113] In Patent Document 6, a polysilicon film is formed as a gate electrode to reduce gate resistance, and a TiSi film is formed on the polysilicon film by a PVD method, and an oxide film is formed on the side surface of the gate electrode to prevent the gate width from being narrowed due to large side etching of the TiSi film, but the document does not disclose a contact structure for the front surface electrode, and is different from the document in which a contact with the semiconductor substrate is formed as in Embodiments 1 and 2. Furthermore, in Patent Document 6, a high-temperature heat treatment is performed, which increases stress locally generated in the semiconductor substrate due to volume expansion caused by alloying.

[0114] In contrast to this, in the first and second embodiments, the TiSix film is deposited on the semiconductor substrate by sputtering as described above, and therefore the problems encountered in the above cited documents 1 to 6 do not occur.

[0115] The present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, the above-described embodiments are not limited to MOSFETs with trench gate structures, and can be applied to various semiconductor devices in which the contact structure of the front electrode makes ohmic contact with the semiconductor substrate through a contact hole in an interlayer insulating film. Furthermore, although the first conductivity type is n-type and the second conductivity type is p-type in the above-described embodiments, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0116] As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and are particularly suitable for semiconductor devices that are miniaturized using contact trenches.

[0117] 1n - n-type drift region 2 p-type base region 3 + Type source region 4p + 1. Type contact region 5: Trench 6: Gate insulating film 7: Gate electrode 8: Semiconductor substrate 8a: Source contact trench 9: Interlayer insulating film 9-1: HTO film 9-2: BPSG film 9a: Contact hole 10, 20: Semiconductor device 11, 21: TiSix film 12, 22: TiN film 13, 23: Metal plug 13a: W film 14: Front electrode 15 + Drain region 16 Back electrode d Distance that the side surface of the interlayer insulating film recedes in the direction away from the source contact trench w1 Width of the contact hole w2 Width of the source contact trench

Claims

1. a first semiconductor region of a first conductivity type provided within a semiconductor substrate; a second semiconductor region of a second conductivity type provided between the front surface of the semiconductor substrate and the first semiconductor region; an element structure including a pn junction between the second semiconductor region and the first semiconductor region, the pn junction being provided on a front surface side of the semiconductor substrate; an interlayer insulating film provided on a front surface of the semiconductor substrate and covering the element structure; a contact hole that penetrates the interlayer insulating film in a depth direction and reaches the semiconductor substrate; a contact structure in contact with the semiconductor substrate in the contact hole; a first electrode electrically connected to the second semiconductor region via the contact structure; A second electrode provided on a rear surface of the semiconductor substrate; Equipped with The contact structure includes: a titanium silicide film in contact with the semiconductor substrate in the contact hole and extending onto a surface of the interlayer insulating film along a sidewall of the contact hole; a titanium nitride film provided along a surface of the titanium silicide film; a metal plug embedded on said titanium nitride film inside said contact hole.

2. a contact trench having a predetermined depth and provided on the front surface of the semiconductor substrate so as to be continuous with the contact hole; 2. The semiconductor device according to claim 1, wherein the titanium silicide film is provided along the sidewall of the contact hole and the inner wall of the contact trench.

3. 3. The semiconductor device according to claim 2, wherein the thickness of said titanium silicide film is uniform from the side wall of said contact hole to the side wall of said contact trench.

4. 3. The semiconductor device according to claim 2, wherein the interlayer insulating film is located at a distance of 10 nm or less from the contact trench in a direction parallel to the front surface of the semiconductor substrate.

5. the titanium silicide film is terminated on a side surface of the interlayer insulating film, 2. The semiconductor device according to claim 1, wherein the first electrode is provided on an upper surface of the interlayer insulating film so as to be in contact with the interlayer insulating film.

6. the titanium silicide film covers the entire surface of the interlayer insulating film, 2. The semiconductor device according to claim 1, wherein the first electrode is provided on an upper surface of the interlayer insulating film via the titanium silicide film and the titanium nitride film.

7. a first step of forming a second semiconductor region of a second conductivity type in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate in a surface region of a front surface of the semiconductor substrate, and forming an element structure including a pn junction between the second semiconductor region and the first semiconductor region; a second step of forming an interlayer insulating film covering the element structure on a front surface of the semiconductor substrate; a third step of forming a contact hole that penetrates the interlayer insulating film in a depth direction and reaches the semiconductor substrate; a fourth step of forming a contact structure in contact with the semiconductor substrate in the contact hole; a fifth step of forming a first electrode electrically connected to the second semiconductor region via the contact structure; a first annealing step of recovering crystal damage of the semiconductor substrate by heat treatment in a hydrogen atmosphere after the fifth step; Including, The fourth step comprises: a first deposition step of depositing a titanium silicide film by sputtering, the titanium silicide film covering the entire surface of the interlayer insulating film and contacting the semiconductor substrate in the contact hole; a second deposition step of depositing a titanium nitride film on the surface of the titanium silicide film by sputtering; a third deposition step of burying a metal plug on the titanium nitride film inside the contact hole; a contact structure including the titanium silicide film, the titanium nitride film, and the metal plug;

8. a sixth step of forming a contact trench having a predetermined depth in the front surface of the semiconductor substrate, the contact trench being continuous with the contact hole, after the third step and before the fourth step; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the first deposition step, the titanium silicide film is formed along a surface of the interlayer insulating film and an inner wall of the contact trench.

9. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising a seventh step of planarizing the interlayer insulating film after the sixth step and before the fourth step.

10. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first deposition step and the second deposition step are carried out consecutively using the same sputtering apparatus.

11. the fourth step further includes a removal step of etching back the titanium nitride film and the titanium silicide film using the metal plug as a mask to expose an upper surface of the interlayer insulating film; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the fifth step, the first electrode is formed on an upper surface of the interlayer insulating film so as to be in contact with the interlayer insulating film.

12. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the first deposition step is carried out in an atmosphere having a temperature of 300[deg.] C. or less.

13. an irradiation step of irradiating the semiconductor substrate with radiation after the first annealing step; 8. The method for manufacturing a semiconductor device according to claim 7, further comprising a second annealing step of adjusting a parasitic diode formed at the pn junction to have a predetermined reverse recovery characteristic by heat treatment in a hydrogen atmosphere after the irradiation step.

14. 2. The semiconductor device according to claim 1, wherein the titanium silicide film is a deposited film.

15. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the second deposition step is carried out in an atmosphere having a temperature of 300[deg.] C. or less.