Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor which inhibits the occurrence of inter-layer peeling at a boundary between an internal electrode layer and a dielectric layer while having a large capacity.　This multilayer ceramic capacitor 1 includes an internal layer part 11 in which dielectric layers 14 and internal electrode layers 15 are alternately layered, wherein: a first internal electrode layer 15A and a second internal electrode layer 15B include facing portions overlapping each other in a plan view from a layering direction T, and lead-out portions that are led out to an end face C or a side face B of the multilayer body 2 from the facing portions, and that do not overlap each other in a plan view from the layering direction T; the internal electrode layer 15 has communicating holes P which communicate in the layering direction T and into which a dielectric constituting the dielectric layer 14 is inserted; and the existence rate of the communicating holes P into which the dielectric is inserted is higher in a connecting region JA of the facing portions to which the lead-out portions are connected than in the center of the facing portions, and is higher in said connection region than in the center of the lead-out portions.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In general, a multilayer ceramic capacitor comprises an element body in which internal electrode layers and dielectric layers are alternately laminated, and external electrodes provided on the outer surfaces of the element body, with the dielectric layers being made of a ceramic dielectric material.

[0003] In order to increase the capacitance of a multilayer ceramic capacitor, it is necessary to increase the opposing area between adjacent internal electrode layers within the element body. To achieve this, it is effective to increase the density of the conductive material that makes up the internal electrode layers, i.e., the density of the internal electrode layers, which increases the continuity of the internal electrode layers and increases the opposing area.

[0004] However, as the continuity of the internal electrode layers increases, the difference in shrinkage rate between the internal electrode layers and the dielectric layers increases, causing delamination at the boundary between the internal electrode layers and the dielectric layers. In particular, delamination becomes more pronounced when subjected to repeated thermal history, leading to structural defects within the element, which are likely to cause insulation failure when voltage is applied, resulting in failure.

[0005] For this reason, there is a need to develop a multilayer ceramic capacitor that has high capacitance yet suppresses the occurrence of delamination.

[0006] JP 2016-127262 A

[0007] An object of the present invention is to provide a multilayer ceramic capacitor that has a large capacitance and is capable of suppressing the occurrence of delamination at the boundary between the internal electrode layers and the dielectric layers.

[0008] The inventors discovered that by adjusting the distribution of the through holes into which the dielectric has penetrated in the internal electrode layer, it is possible to suppress the occurrence of delamination at the boundary between the internal electrode layer and the dielectric layer, and have thus completed the present invention.

[0009] That is, the present invention provides a multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, the laminate having two main surfaces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction; and external electrodes connected to the internal electrode layers on at least either the side surfaces or the end surfaces of the laminate, wherein the internal electrode layers comprise first internal electrode layers and second internal electrode layers, and the first internal electrode layers and the second internal electrode layers comprise opposing portions overlapping each other in a plan view from the lamination direction, and lead portions drawn from the opposing portions to the end surfaces or the side surfaces of the laminate and not overlapping each other in a plan view from the lamination direction, the internal electrode layers have through holes that communicate in the lamination direction and through which the dielectric constituting the dielectric layers enter, This is a multilayer ceramic capacitor in which the rate of presence of communicating holes into which the dielectric has entered is higher in a connection region of the opposing portion where the lead portion is connected than in a central portion of the opposing portion and higher than in a central portion of the lead portion.

[0010] According to the present invention, it is possible to suppress the occurrence of delamination at the boundary between the internal electrode layer and the dielectric layer while achieving a large capacity.

[0011] 1 is a schematic perspective view of a multilayer ceramic capacitor 1; FIG. 2 is a cross-sectional view cut in the II-II direction in FIG. 1 , showing the upper half above the center in the stacking direction T (first embodiment); FIG. 3 is a cross-sectional view cut in the III-III direction in FIG. 1 , showing the upper half above the center in the stacking direction T (first embodiment); FIG. 4 is a cross-sectional view taken along the first internal electrode layer 15A of the multilayer ceramic capacitor 1; FIG. 5 is a cross-sectional view taken along the second internal electrode layer 15B of the multilayer ceramic capacitor 1; FIG. 6 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1; FIG. 7 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1; FIG. 8 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1; FIG. 9 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1 (first embodiment); FIG. 10 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1 (first embodiment); FIG. 11 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1 (first embodiment); FIG. 12 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1 (first embodiment); FIG. 13 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1 (second embodiment); FIG. 14 is a process diagram illustrating a manufacturing method of the multilayer ceramic capacitor 1 (second embodiment); 5A to 5C are process diagrams illustrating a method for manufacturing the multilayer ceramic capacitor 1 (second embodiment).

[0012] First Embodiment The following describes a multilayer ceramic capacitor 1 of the present invention. The multilayer ceramic capacitor 1 is a three-terminal multilayer ceramic capacitor in which side external electrodes 4 and end external electrodes 3 are provided on two opposing side surfaces B and two opposing end surfaces C, respectively. However, by changing the shape of the internal electrode layers 15, in particular the shapes of the side surface lead portions 15Ab and end surface lead portions 15Bb described below, the positions at which the external electrodes are arranged can be changed. Therefore, the present invention can also be used for three-terminal multilayer ceramics, two-terminal ceramic capacitors, or multilayer ceramic capacitors of other shapes.

[0013] Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Fig. 2 is a cross section (WT cross section) of the multilayer ceramic capacitor 1 cut in the II-II direction in Fig. 1, showing the upper half above the center in the stacking direction T. Fig. 3 is a cross section (LT cross section) of the multilayer ceramic capacitor 1 cut in the III-III direction in Fig. 1, showing the upper half above the center in the stacking direction T.

[0014] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 includes end surface external electrodes 3 provided on both end surfaces C in the length direction L of the laminate 2, and side surface external electrodes 4 provided on both side surfaces B in the width direction W of the laminate 2. The laminate 2 includes inner layer portions 11 including multiple pairs of dielectric layers 14 and internal electrode layers 15, and outer layer portions 12.

[0015] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited, but may be 0.6 mm or more and 3.2 mm or less in the length direction L, 0.3 mm or more and 2.5 mm or less in the stacking direction T, and 0.3 mm or more and 2.5 mm or less in the width direction W.

[0016] In this specification, the term indicating the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked in the multilayer ceramic capacitor 1 as the stacking direction T. The direction that intersects with the stacking direction T and in which the pair of end face external electrodes 3 are provided is referred to as the length direction L. The direction that intersects with both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the stacking direction T, the length direction L, and the width direction W are perpendicular to one another.

[0017] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. The dimensions of the laminate 2 are not particularly limited, but may be 0.6 mm or more and 3.2 mm or less in the length direction L, 0.3 mm or more and 2.5 mm or less in the stacking direction T, and 0.3 mm or more and 2.5 mm or less in the width direction W.

[0018] (Inner Layer Portion 11) The inner layer portion 11 includes a plurality of dielectric layers 14 and internal electrode layers 15 stacked in the stacking direction T.

[0019] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, such as BaTiO ３ A dielectric ceramic having these as its main component is used. Alternatively, the ceramic material may be one to which at least one of a manganese compound, an iron compound, a chromium compound, a cobalt compound, a nickel compound, or the like is added to the main component. The dielectric layer 14 includes a dielectric layer 14c made from a ceramic green sheet, which will be described later, and dielectric layers 14a and 14b made from a ceramic paste applied to the ceramic green sheet.

[0020] (Internal Electrode Layer 15) The internal electrode layer 15 is preferably formed from a metal material typified by, for example, Ni, Cu, Ag, Pd, an Ag-Pd alloy, Au, or the like.

[0021] The thickness of the internal electrode layers 15 is not particularly limited, but is preferably 0.25 μm or more and 0.6 μm or less, and more preferably 0.3 μm or more and 0.5 μm or less. 14 to 1000 internal electrode layers 15 can be built in the internal layer portion 11.

[0022] The internal electrode layer 15 comprises first internal electrode layers 15A and second internal electrode layers 15B arranged alternately, and the first internal electrode layers 15A and second internal electrode layers 15B comprise opposing portions that overlap each other when viewed in a plane from the stacking direction T, and drawn-out portions that are drawn out from the opposing portions to the end face C or side face B of the laminate 2 and do not overlap each other when viewed in a plane from the stacking direction T.

[0023] The first internal electrode layer 15A and the second internal electrode layer 15B form capacitance via the dielectric layer 14 at opposing portions where they overlap each other in a plan view from the stacking direction T. Furthermore, the extension portions extending from the opposing portions are extended to the end face C or the side face B of the laminate 2 to connect the opposing portions to the external electrodes. The shape of the extension portions can be changed in various ways to correspond to the positions and shapes of the external electrodes to be arranged depending on the form of mounting on a wiring board. Figures 1 to 3 show a multilayer ceramic capacitor 1 in which the two side face extension portions 15Ab of the first internal electrode layer 15A each extend to the opposing side face B of the laminate 2, and the two end face extension portions 15Bb of the second internal electrode layer 15B each extend to the opposing end face C of the laminate 2.

[0024] Fig. 4 is a cross-sectional view taken along the first internal electrode layer 15A of the multilayer ceramic capacitor 1. Fig. 5 is a cross-sectional view taken along the second internal electrode layer 15B of the multilayer ceramic capacitor 1.

[0025] (First Internal Electrode Layer 15A) As shown in FIG. 4 , the first internal electrode layer 15A is slightly smaller than the laminate 2 and has a substantially rectangular first opposing portion 15Aa whose sides are spaced a fixed distance from the end face C and the side face B, and side lead portions 15Ab extending from the first opposing portion 15Aa to both side faces B. The first opposing portion 15Aa includes a connection region JA that is a portion connected to the side lead portions 15Ab. FIGS. 2 and 4 show the connection region JA of the first opposing portion 15Aa to which the side lead portions 15Ab are connected. In this embodiment, the first opposing portion 15Aa has two connection regions JA corresponding to the two side lead portions 15Ab. The side lead portions 15Ab extending to the two opposing side faces B are exposed on the side faces B of the laminate 2 and connected to side external electrodes 4 provided on both side faces B in the width direction W of the laminate 2.

[0026] In the first internal electrode layer 15A, the length of the side lead portion 15Ab in the longitudinal direction L is shorter than the length of the first opposing portion 15Aa in the longitudinal direction L. By shortening the length of the side lead portion 15Ab in the longitudinal direction L in this way, it is possible to suppress the intrusion of moisture from the outside, thereby improving the reliability of the multilayer ceramic capacitor. Figure 4 shows a configuration in which both of the two side lead portions 15Ab are shorter than the first opposing portion 15Aa in the longitudinal direction L.

[0027] (Second Internal Electrode Layer 15B) As shown in FIG. 5 , the second internal electrode layer 15B extends as a whole between both end faces C in the length direction L of the laminate 2 and is spaced a fixed distance from both side faces B in the width direction W. In the second internal electrode layer 15B, the central portion of the octagonal shape, which is a fixed distance away from both end faces C, is the second opposing portion 15Ba, and the portions extending from the second opposing portion 15Ba to the two opposing end faces C are the end surface drawn-out portions 15Bb. The second opposing portion 15Ba includes a connection region JB, which is a portion connected to the end surface drawn-out portion 15Bb. FIGS. 2 and 5 show the connection region JB of the second opposing portion 15Ba to which the end surface drawn-out portion 15Bb is connected. In this embodiment, the second opposing portion 15Ba has two connection regions JB corresponding to the two end surface drawn-out portions 15Bb. The end surface lead portions 15Bb extend to two opposing end surfaces C, are exposed at the end surfaces C of the laminate 2, and are connected to the end surface external electrodes 3 provided on both side surfaces in the longitudinal direction L of the laminate 2. The second opposing portion 15Ba and the first opposing portion 15Aa face each other and form a capacitance.

[0028] The end surface drawn-out portion 15Bb has a transition region whose length in the width direction W gradually decreases, and an extension region that extends from the transition region to the end surface C and whose length in the width direction W is shorter than the length in the width direction of the second opposing portion 15Ba. By shortening the length in the width direction W of the extension portion of the end surface drawn-out portion 15Bb in this way, it is possible to suppress the intrusion of moisture from the outside, thereby improving the reliability of the multilayer ceramic capacitor. Figure 5 shows a configuration in which both of the extension portions of the two end surface drawn-out portions 15Bb are shorter in the width direction W than the second opposing portion 15Ba.

[0029] 2 and 3, the outer layer portion 12 is a dielectric layer of a constant thickness disposed on the main surface A side of the inner layer portion 11. The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11.

[0030] The thickness of the dielectric layer is not particularly limited, but is preferably 0.3 μm to 1.5 μm, and more preferably 0.5 μm to 1 μm. The laminate 2 consisting of the inner layer portion 11 and the outer layer portion 12 can be formed from 14 to 1,000 dielectric layers.

[0031] (End surface external electrodes 3) End surface external electrodes 3 are arranged on both end surfaces C of the laminate 2. End surface drawn-out portions 15Bb of the second internal electrode layers 15B are connected to the end surface external electrodes 3. The end surface external electrodes 3 cover not only the end surfaces C but also parts of the main surfaces A and side surfaces B on the end surface C side.

[0032] (Side surface external electrodes 4) Side surface external electrodes 4 are arranged on both side surfaces B of the laminate 2. The side surface external electrodes 4 are connected to the side surface lead portions 15Ab of the first internal electrode layers 15A. The side surface external electrodes 4 cover not only the side surfaces B but also a portion of the main surface A on the side surface B side.

[0033] The end surface external electrodes 3 and the side surface external electrodes 4 may have a structure including, for example, an underlying electrode layer and a plating layer disposed on the underlying electrode layer.

[0034] The base electrode layer includes at least one layer selected from a baked layer, a conductive resin layer, a direct plating layer, and the like, as described below.

[0035] (Baked Layer) The baked layer is formed by applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be baked simultaneously with the internal electrodes or may be baked after the internal electrodes are baked. The baking temperature is preferably 700 to 900°C.

[0036] The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal includes at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc.

[0037] The thickness of the baked layer is preferably, for example, 3 μm or more and 70 μm or less. The baked layer may be a multi-layered layer.

[0038] (Conductive Resin Layer) The conductive resin layer is formed on the surface of the baked layer or directly on the surface of the laminate. The conductive resin layer may be a multi-layered layer.

[0039] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baked layer or the laminate, and then performing a heat treatment at a temperature of 250 to 550°C or higher to thermally cure the resin and form a conductive resin layer. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, it is preferable to keep the oxygen concentration at 100 ppm or less.

[0040] The thickness of the conductive resin layer at the center of the end face C is preferably, for example, not less than 10 μm and not more than 150 μm.

[0041] The resin for the conductive resin layer can be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, and adhesion. The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0042] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0043] Because the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the ceramic electronic component is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the ceramic electronic component.

[0044] The metal contained in the conductive resin layer can be Ag, Cu, or an alloy thereof. Alternatively, a metal powder whose surface is coated with Ag can be used. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu or Ni as the metal powder. Alternatively, Cu that has been subjected to an oxidation prevention treatment can be used.

[0045] The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity of all metals, making it suitable as an electrode material, and because Ag is a noble metal, it does not oxidize and has high resistance.The reason for using Ag-coated metal is that it makes it possible to use a cheaper base metal while maintaining the above-mentioned properties of Ag.

[0046] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0047] The shape of the metal contained in the conductive resin layer is not particularly limited. The conductive filler may be spherical, flat, or the like. The average particle size of the metal contained in the conductive resin layer is not particularly limited, but can be, for example, about 0.3 μm or more and 10 μm or less.

[0048] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, a current path is formed inside the conductive resin layer.

[0049] (Plating Layer) A plating layer may be provided directly on the end surfaces of the laminate where the internal electrodes are exposed. That is, the multilayer ceramic capacitor may have a structure including plating layers that are electrically connected directly to the internal electrode layers and the surface electrode layers. In such a case, a catalyst may be applied to the surface of the laminate as a pretreatment, and then the plating layer may be formed directly.

[0050] The plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing the metal. For example, when the first internal electrode layer and the second internal electrode layer are formed using Ni, the direct plating layer is preferably formed using Cu, which has good bonding properties with Ni.

[0051] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99 volume % or more.

[0052] When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which makes the process more complicated. Therefore, electrolytic plating is usually preferred. As a plating method, barrel plating is preferably used. If necessary, an upper layer plating electrode may be formed on the surface of the lower layer plating electrode in the same manner.

[0053] When the base electrode layer is a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0054] The plating layer disposed on the base electrode layer contains, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0055] The plating layer may be formed of multiple layers. Preferably, it has a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, allowing for easier mounting. The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0056] (Communicating holes P) The internal electrode layers 15 communicate with each other in the stacking direction T, and have communicating holes P through which a part of the dielectric constituting the dielectric layers 14 sandwiching the internal electrode layers 15 in the stacking direction T has entered. Inside the communicating holes P, columnar crystals of the dielectric are formed, which can increase the adhesion between the internal electrode layers 15 and the dielectric layers 14.

[0057] In the first internal electrode layer 15A, the presence rate of the dielectric-filled through holes P is higher in the connection region JA where the side lead portion 15Ab of the first opposing portion 15Aa is connected than in the center of the first opposing portion 15Aa and higher than in the center of the side lead portion 15Ab. The presence rate of the dielectric-filled through holes P can be confirmed by polishing the end face C of the multilayer ceramic capacitor 1 parallel to the end face C to expose a cross section and observing this cross section using a scanning electron microscope. Specifically, the presence rate of the dielectric-filled through holes P in the connection region JA is measured on a cross section obtained by polishing the multilayer ceramic capacitor 1 perpendicular to the longitudinal direction L to a position that is half the longitudinal dimension of the multilayer ceramic capacitor 1. Next, the above cross section is divided into three regions so that the thickness dimension of the inner layer portion is equally divided into three regions. Thereafter, in each region, a field of view is specified with the center being an end of one of the opposing portions of the first internal electrode layers 15A, so that the magnification is such that 15 layers of the first internal electrode layers 15A are included. Analysis of the SEM image within the specified field of view for each region is performed, and based on the area of ​​the first internal electrode layers 15A, the area of ​​the communicating holes, and the area of ​​the communicating holes P into which the dielectric has penetrated that are actually present in the analysis range, the presence rate of the communicating holes P into which the dielectric has penetrated is calculated using the following formula (1): Presence rate (%) of communicating holes P into which the dielectric has penetrated = (area of ​​communicating holes P into which the dielectric has penetrated / area of ​​internal electrode layer + area of ​​communicating holes) × 100 ... (1) Finally, the values ​​for 15 layers measured in each of the three regions are averaged to obtain the presence rate of communicating holes P into which the dielectric has penetrated in the connection region JA. The presence rate of the through holes P into which the dielectric has penetrated in the central portion of the first opposing portion 15Aa is measured on a cross section of the multilayer ceramic capacitor 1 that has been polished perpendicular to the longitudinal direction L to a position that is half the longitudinal dimension of the multilayer ceramic capacitor 1. Next, the cross section is divided into three regions so that the thickness dimension of the inner layer portion is divided into three equal parts. After that, in each region, the field of view is specified so that the magnification is such that 15 first internal electrode layers 15A are included, with the center being the central portion of the first opposing portion 15Aa of the first internal electrode layer 15A.SEM images are analyzed within the specified field of view for each region, and the percentage of through holes P into which the dielectric has penetrated is calculated using the following formula (1) based on the area of ​​the first internal electrode layer 15A, the area of ​​the through holes, and the area of ​​the through holes P into which the dielectric has penetrated that are actually present within the analysis range. Percentage of through holes P into which the dielectric has penetrated (%) = (area of ​​through holes P into which the dielectric has penetrated / area of ​​internal electrode layer + area of ​​through holes) × 100 (1). Finally, the average of the 15 layers measured in each of the three regions is taken to determine the percentage of through holes P into which the dielectric has penetrated in the center of the first opposing portion 15Aa. Furthermore, the percentage of through holes P into which the dielectric has penetrated in the center of the side lead portion 15Ab is measured on a cross section polished perpendicular to the longitudinal direction L to a position that is half the longitudinal dimension of the multilayer ceramic capacitor 1. Next, the cross section is divided into three regions so that the thickness dimension of the inner layer portion is divided into three equal parts. Thereafter, in each region, a field of view is specified, centered on the center of one of the side lead portions 15Ab of the first internal electrode layer 15A, so that the magnification is such that 15 layers of the first internal electrode layer 15A are included. Analysis of the SEM image within the specified field of view for each region is performed, and based on the area of ​​the first internal electrode layer 15A that actually exists in the analysis range, the area of ​​the communicating holes, and the area of ​​the communicating holes P into which the dielectric has penetrated, the presence rate of the communicating holes P into which the dielectric has penetrated is calculated using the following formula (1): Presence rate of communicating holes P into which the dielectric has penetrated (%) = (area of ​​communicating holes P into which the dielectric has penetrated / area of ​​internal electrode layer + area of ​​communicating holes) × 100 ... (1) Finally, the values ​​for 15 layers measured in each of the three regions are averaged to obtain the presence rate of the communicating holes P into which the dielectric has penetrated in the side lead portion 15Ab. In addition, it is preferable that the rate of presence of communicating holes P into which the dielectric has entered in the connection region JA is 20% or more and 60% or less, the rate of presence of communicating holes P into which the dielectric has entered in the central portion of the first opposing portion 15Aa is 2% or more and 25% or less, and the rate of presence of communicating holes P into which the dielectric has entered in the central portion of the side extraction portion 15Ab is 2% or more and 25% or less.

[0058] 2 , in the spacing in the stacking direction T between the first internal electrode layers 15A adjacent to each other in the stacking direction T, a spacing T1 at a portion overlapping with the second internal electrode layer 15B in a connection region JA where the first opposing portion 15Aa and the side lead portion 15Ab are joined when the first internal electrode layer 15A is viewed in a plane from the stacking direction T is longer than a spacing T2 at a center of the first opposing portion 15Aa and also has a portion longer than a spacing T3 at the side lead portion 15Ab that does not overlap with the second internal electrode layer 15B when the first internal electrode layer 15A is viewed in a plane from the stacking direction T. The spacing at each portion of the first internal electrode layer 15A in the stacking direction T can be measured by polishing the end face C of the multilayer ceramic capacitor 1 parallel to the end face C to expose a cross section and observing the cross section with a scanning electron microscope, similar to the measurement of the presence rate of communicating holes P into which the dielectric has penetrated. Specifically, the distance T1 between the connection region JA and the second internal electrode layer 15B is measured on a cross section obtained by polishing the multilayer ceramic capacitor 1 perpendicular to the longitudinal direction L to a position that is half the longitudinal dimension of the multilayer ceramic capacitor 1. The cross section is divided into three regions so that the thickness dimension of the inner layer portion is divided into thirds, and the dimension T1 is measured at 20 locations in each region using a scanning electron microscope (SEM). Finally, the average of these measurements is taken to define the distance T1 between the connection region JA and the second internal electrode layer 15B. Similarly to the measurement of T1, the distance T2 between the connection region JA and the second internal electrode layer 15B is measured on the cross section obtained by dividing the thickness dimension of the inner layer portion into three regions so that the thickness dimension is divided into thirds, and the dimension T2 is measured at 20 locations in each region using a scanning electron microscope (SEM). Finally, the average of these measurements is defined as the distance T2 between the connection region JA and the second internal electrode layer 15B. Furthermore, the distance T3 in the side lead portion 15Ab that does not overlap with the second internal electrode layer 15B when the first internal electrode layer 15A is viewed in plan from the stacking direction T is measured by dividing the above cross section into three regions so that the thickness dimension of the internal layer portion is divided into three equal parts, and measuring the dimension of T3 at 20 points in each region using a scanning electron microscope (SEM). Finally, the average value of these measurements is taken to be the distance T3 in the side lead portion 15Ab that does not overlap with the second internal electrode layer 15B when the first internal electrode layer 15A is viewed in plan from the stacking direction T.In addition, it is preferable that the spacing T1 of the portion overlapping with the second internal electrode layer 15B in the connection region JA be 1.2 μm or more and 6.0 μm or less, the spacing T2 at the center of the first opposing portion 15Aa be 1.1 μm or more and 5.0 μm or less, and the spacing T3 at the side lead-out portion 15Ab that does not overlap with the second internal electrode layer 15B when the first internal electrode layer 15A is viewed in a plane from the stacking direction T be 0.8 μm or more and 5.0 μm or less.

[0059] Multi-terminal multilayer ceramic capacitors with three or more external electrodes, such as those described in Patent Document 1, are known. However, such multi-terminal multilayer ceramic capacitors tend to have more complex overlapping patterns between multiple internal electrode layers and multiple dielectric layers than typical two-terminal ceramic capacitors. For example, the internal electrode layers of multi-terminal multilayer ceramic capacitors often do not have a simple rectangular shape, resulting in more complex overlapping patterns between the internal electrode layers and the dielectric layers. In this case, during the pressing process before firing the laminate, areas where pressure is difficult to apply are created, weakening the adhesion strength near those areas. In particular, the adhesion strength is weakened near the boundary between the opposing electrode portion and the lead portion, which is likely to be a point of variation in the overlapping pattern between the internal electrode layers and the dielectric layers, making delamination more likely to occur. According to the present embodiment, a multilayer ceramic capacitor capable of suppressing delamination can be provided, even in such multi-terminal capacitors.

[0060] (Method for Manufacturing the Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 will be described.

[0061] First Embodiment The method for manufacturing the multilayer ceramic capacitor 1 can be divided into a first embodiment and a second embodiment, depending on the positions at which the ceramic pastes 114a and 114b are disposed on the first ceramic green sheet 114A and the second ceramic green sheet 114B in the ceramic paste disposing step S2, which will be described later. Fig. 6 is a flowchart illustrating the method for manufacturing the multilayer ceramic capacitor 1. Figs. 7 to 16 are process diagrams illustrating the method for manufacturing the multilayer ceramic capacitor 1, with Figs. 9 to 12 showing the disposition of the ceramic pastes 114a and 114b according to the first embodiment and Figs. 13 to 16 showing the disposition of the ceramic pastes 114a and 114b according to the second embodiment.

[0062] (Internal electrode layer pattern forming step S1) First, as shown in Fig. 7, a first internal electrode layer pattern 115A that will become the first internal electrode layer 15A is formed using a conductive paste on a first ceramic green sheet 114A that will become the dielectric layer 14c. At this time, a sintering aid is sprayed at positions where communication holes are desired to be formed. As a result, when the ceramic body is fired, the metal that constitutes the internal electrode layer shrinks, making the internal electrode layer discontinuous and allowing communication holes to be formed. For example, Mn, Si, etc. can be used as the sintering aid. The first internal electrode layer pattern 115A has a shape in which a plurality of first internal electrode layers 15A are continuous in the width direction W but discontinuous in the length direction L.

[0063] 8, a second internal electrode layer pattern 115B that will become the second internal electrode layer 15B is formed on the second ceramic green sheet 114B that will become the dielectric layer 14c using a conductive paste. The second internal electrode layer pattern 115B has a shape in which a plurality of second internal electrode layers 15B are continuous in the length direction L but discontinuous in the width direction W.

[0064] The ceramic green sheet is a strip-shaped sheet formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0065] The first internal electrode layer pattern 115A and the second internal electrode layer pattern 115B are formed by printing such as screen printing, gravure printing, or letterpress printing.

[0066] (Ceramic Paste Arrangement Step S2) Next, as shown in FIG. 9, a ceramic paste 114a for forming the dielectric layer 14b is applied to the first ceramic green sheet 114A shown in FIG. 7 on which the first internal electrode layer pattern 115A has been formed. The thickness of the dielectric layer 14b is 0.4 to 0.8 times the thickness of the dielectric layer 14c. In the first embodiment, the ceramic paste 114a is arranged so as to fill the entire portion of the first ceramic green sheet 114A where the first internal electrode layer pattern 115A is not arranged, and to overlap both side edges of the first opposing portion 15Aa in the width direction W, excluding the connection region JA of the first opposing portion. The ceramic paste 114a is not arranged in the portion that will become the side lead portion 15Ab of the first internal electrode layer 15A.

[0067] 10, a ceramic paste 114b to become the dielectric layer 14a is applied to the second ceramic green sheet 114B shown in FIG. 8 on which the second internal electrode layer pattern 115B is formed. The thickness of the dielectric layer 14a is 0.4 to 0.8 times the thickness of the dielectric layer 14c. In the first embodiment, the ceramic paste 114b is arranged so as to fill the entire portion of the second ceramic green sheet 114B where the second internal electrode layer pattern 115B is not arranged, and further to overlap portions corresponding to both side edges in the width direction W of the second opposing portion 15Ba of the second internal electrode layer pattern 115B.

[0068] Ceramic paste 114a and ceramic paste 114b are applied by printing, such as screen printing, gravure printing, letterpress printing, etc. The ceramic paste may have a different component ratio from the dielectric material used to form the ceramic green sheets, may have the same component ratio, or may contain different components.

[0069] (Laminating step S3) Fig. 11 is a diagram illustrating the laminated state of the laminate 2 at the WT cross section at the center in the longitudinal direction L. For convenience of explanation, Fig. 11 schematically illustrates a state in which the plurality of laminated ceramic green sheets are spaced apart. The same applies to Figs. 12, 15, and 16.

[0070] As shown in the figure, a sheet in which a first internal electrode layer pattern 115A and a ceramic paste 114a are arranged on a first ceramic green sheet 114A shown in Fig. 9 and a sheet in which a second internal electrode layer pattern 115B and a ceramic paste 114b are arranged on a second ceramic green sheet 114B shown in Fig. 10 are alternately laminated. The ceramic paste 114b forms the dielectric layer 14a.

[0071] 12 is a diagram illustrating the stacking state of the laminate 2 in the LT cross section at the center in the width direction W. The first internal electrode layer patterns 115A and the second internal electrode layer patterns 115B both extend in the length direction L with a constant interval in the stacking direction T. The ceramic paste 114a forms the dielectric layer 14b.

[0072] Furthermore, outer layer ceramic green sheets 112 that will become the outer layer portions 12 are stacked on both sides of the stacked structure in the stacking direction T.

[0073] (Mother Block Forming Step S4) The outer layer ceramic green sheet 112 and the stacked sheets are thermocompression bonded to form a mother block.

[0074] (Mother Block Dividing Step S5) Next, the mother block is cut and divided in the length direction L and width direction W to manufacture a plurality of rectangular laminates 2.

[0075] (External electrode forming process S6) Next, end surface external electrodes 3 are formed on both end surfaces C of the laminate 2, and side surface external electrodes 4 are formed on both side surfaces B of the laminate 2. The end surface external electrodes 3 are connected to the end surface lead portions 15Bb of the second internal electrode layers 15B. The end surface external electrodes 3 are formed so as to cover not only the end surfaces C but also parts of the end surface C sides of the main surface A and the side surfaces B. The side surface external electrodes 4 are connected to the side surface lead portions 15Ab of the first internal electrode layers 15A. The side surface external electrodes 4 are formed so as to cover not only the side surfaces B but also parts of the side surfaces B sides of the main surface A.

[0076] (Firing step S7) Then, the laminate is heated in a nitrogen atmosphere at a set firing temperature for a predetermined time, thereby baking the external electrodes onto the laminate 2, and the multilayer ceramic capacitor 1 shown in FIG.

[0077] In the firing process, the laminated chip is subjected to a binder removal process and a firing process to form an element part (laminate 2). The firing process co-sinters the conductive paste layer and the green sheet for the dielectric layer, forming the internal electrode layer 15 and the dielectric layer 14, respectively. The conditions for the binder removal process can be determined depending on the type of organic binder contained in the green sheet and the conductive paste layer. The firing process can be performed at a temperature at which the laminated chip is sufficiently densified. The firing temperature depends on the materials of the dielectric and internal electrode layer, but is preferably 900°C to 1400°C.

[0078] As shown in FIG. 2 , in the multilayer ceramic capacitor 1 manufactured in this manner, in the spacing in the stacking direction T between the first internal electrode layers 15A adjacent to each other in the stacking direction T, when the first internal electrode layers 15A are viewed in a plane from the stacking direction T, the spacing T1 of the portions of the first opposing portions 15Aa that overlap with the second internal electrode layers 15B in the connection regions JA where the side lead portions 15Ab are joined is longer than the spacing T2 of the central portions of the first opposing portions 15Aa, and also has portions that are longer than the spacing T3 of the side lead portions 15Ab that do not overlap with the second internal electrode layers 15B when the first internal electrode layers 15A are viewed in a plane from the stacking direction T.

[0079] In this way, in the connection region JA where the side lead portion 15Ab of the first opposing portion 15Aa is joined, the distance T1 is larger than the other distances T2 and T3 in the portion overlapping with the second internal electrode layer 15B, and therefore this portion is likely to be subjected to pressure from the dielectric layer 14. For this reason, in this portion, a part of the dielectric forming the dielectric layer 14 is likely to enter the through holes P of the internal electrode layer 15, and columnar crystals of the dielectric are likely to be formed, making it possible to increase the adhesion between the internal electrode layer 15 and the dielectric layer 14.

[0080] Therefore, the presence rate of communicating holes P into which the dielectric has entered in the first internal electrode layer is higher in the connection region JA where the side extension portion 15Ab of the first opposing portion 15Aa connects than in the central portion of the first opposing portion 15Aa and also higher than in the central portion of the side extension portion 15Ab, thereby increasing the adhesion strength with the dielectric layer 14 in the connection region JA.

[0081] As shown in FIG. 3, the laminate 2 has first internal electrode layers 15A and second internal electrode layers 15B extending in the length direction L with the intervals in the stacking direction T being constant.

[0082] (External Electrode Forming Step S8) A plating layer is provided as needed. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating. In this manner, the multilayer ceramic capacitor 1 can be obtained.

[0083] Second Embodiment Next, a second embodiment of the present invention will be described. The second embodiment differs from the first embodiment in the ranges of ceramic pastes 114a and 114b that are placed on the ceramic green sheets on which the internal electrode layer patterns are formed.

[0084] Fig. 13 is a diagram showing a state in which ceramic paste 114a is arranged on a sheet on which first internal electrode layer patterns 115A are formed in the first ceramic green sheet 114A in the second embodiment, and corresponds to Fig. 9 of the first embodiment. As shown in Fig. 13, the ceramic paste 114a fills the entire portion of the first ceramic green sheet 114A where the first internal electrode layer patterns 115A are not arranged, and is arranged so as to overlap both side edges in the length direction L of the first opposing portion 15Aa and both side edges in the width direction W of the first opposing portion 15Aa excluding the connection region JA of the first opposing portion. Note that Figure 13 shows a configuration in which ceramic paste 114a is not placed in the portion that will become the side lead-out portion 15Ab of the first internal electrode layer 15A, but this is not limited to this, and ceramic paste 114a may also be placed in the portion that will become the side lead-out portion 15Ab of the first internal electrode layer 15A, and in the connection region JA where the first opposing portion 15Aa and the side lead-out portion 15Ab are joined.

[0085] Fig. 14 is a diagram showing a state in which ceramic paste 114b is arranged on a sheet on which second internal electrode layer patterns 115B are formed in the second ceramic green sheet 114B in the second embodiment, and corresponds to Fig. 10 of the first embodiment. As shown in Fig. 14, the ceramic paste 114b fills the entire portion of the second ceramic green sheet 114B where the second internal electrode layer patterns 115B are not arranged, and is arranged so as to overlap portions corresponding to both side edges in the width direction W of the second opposing portion 15Ba of the second internal electrode layer pattern 115B, and portions at both ends in the length direction L of the second opposing portion 15Ba and corresponding to four locations corresponding to both ends in the width direction W. The ceramic paste 114b is not arranged in portions that become end face drawn-out portions 15Bb of the second internal electrode layer 15B.

[0086] 15 and 16 show a state in which a sheet in which the first internal electrode layer pattern 115A and the ceramic paste 114a are arranged on the first ceramic green sheet 114A shown in FIG. 13 and a sheet in which the second internal electrode layer pattern 115B and the ceramic paste 114b that will become the dielectric layer 14a are arranged on the second ceramic green sheet 114B shown in FIG. 14 are alternately laminated.

[0087] 15, the ceramic paste 114b overlaps both ends of the second internal electrode layer pattern 115B in the width direction W. The ceramic paste 114b forms the dielectric layer 14a.

[0088] 16, the ceramic paste 114a overlaps both ends of the first internal electrode layer pattern 115A in the length direction L. The ceramic paste 114a forms the dielectric layer 14b. This configuration corresponds to Fig. 11 of the first embodiment, and a cross section corresponding to Fig. 2 of the first embodiment is formed.

[0089] For this reason, in the second embodiment, the presence rate of the communicating holes P into which the dielectric has penetrated in the second internal electrode layer 15B is higher in the connection region JB of the second opposing portion 15Ba where the end surface drawn-out portion 15Bb is connected than in the center of the second opposing portion 15Ba and higher than in the center of the end surface drawn-out portion 15Bb, thereby improving the adhesion to the dielectric layer 14. Note that the cross-sectional shape shown in Fig. 15 also corresponds to Fig. 11 of the first embodiment, and a cross section corresponding to Fig. 2 of the first embodiment is formed, so that the adhesion to the dielectric layer 14 can also be improved in the connection region JA where the first opposing portion 15Aa and the side surface drawn-out portion 15Ab are joined.

[0090] In this way, the second embodiment can also achieve the same effects as the first embodiment.

[0091] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments and can be embodied in various forms without departing from the spirit of the present invention. The present invention includes the following combinations.

[0092] <1> A multilayer ceramic capacitor comprising: a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, the laminate having two main surfaces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction; and external electrodes connected to the internal electrode layers on at least one of the side surfaces and the end surfaces of the laminate, wherein the internal electrode layers comprise first internal electrode layers and second internal electrode layers, and the first internal electrode layers and the second internal electrode layers comprise opposing portions overlapping each other in a plan view from the lamination direction, and lead portions drawn from the opposing portions to the end surfaces or the side surfaces of the laminate and not overlapping each other in a plan view from the lamination direction, and the internal electrode layers have through holes that communicate in the lamination direction and through which the dielectric constituting the dielectric layers enter, A multilayer ceramic capacitor, wherein the rate of presence of communicating holes into which the dielectric has entered is higher in a connection region of the opposing portion where the drawn-out portion is connected than in a center portion of the opposing portion and higher than in a center portion of the drawn-out portion.

[0093] <2> The multilayer ceramic capacitor according to <1>, wherein the internal electrode layers include the first internal electrode layer and the second internal electrode layer, wherein the first internal electrode layer includes a first opposing portion facing the second internal electrode layer via the dielectric layer, and a side surface drawn-out portion drawn from the first opposing portion to the side surface of the laminate, wherein the second internal electrode layer includes a second opposing portion facing the first internal electrode layer via the dielectric layer, and end surface drawn-out portions drawn from the opposing portion to the two end surfaces of the laminate, wherein the internal electrode layers have communicating holes that communicate in the stacking direction and through which dielectric constituting the dielectric layers has penetrated, and wherein the presence rate of the communicating holes in the first internal electrode layer is higher in a connection region of the first opposing portion where the side surface drawn-out portion is connected than in a center portion of the first opposing portion and higher than in a center portion of the side surface drawn-out portion.

[0094] <3> A multilayer ceramic capacitor according to <2>, wherein, in the spacing in the stacking direction between the first internal electrode layers adjacent to each other in the stacking direction, a spacing T1 in the connection region that overlaps with the second internal electrode layer when the first internal electrode layer is viewed in a plane from the stacking direction is longer than a spacing T2 in the center of the first opposing portion, and has a portion that is longer than a spacing T3 in the side lead-out portion that does not overlap with the second internal electrode layer when the first internal electrode layer is viewed in a plane from the stacking direction.

[0095] <4> A multilayer ceramic capacitor according to <2> or <3>, wherein in the first internal electrode layer having two side lead portions that are led out to two side surfaces of the laminate that are opposed in the width direction, the rate of presence of communicating holes into which the dielectric has entered is higher in the two connection regions where two of the side lead portions of the first opposing portions are connected than in the center of the first opposing portions and higher than in the center of the two lead portions.

[0096] <5> The multilayer ceramic capacitor according to any one of <2> to <4>, wherein in the first internal electrode layer, the length of the side lead portion in the longitudinal direction is shorter than the length of the first opposing portion in the longitudinal direction.

[0097] <6> A multilayer ceramic capacitor according to any one of <2> to <5>, wherein in the first internal electrode layer, the length in the longitudinal direction of the two side lead-out portions led out to the two side surfaces of the laminate opposing in the width direction is both shorter than the length in the longitudinal direction of the first opposing portion.

[0098] <7> The multilayer ceramic capacitor according to any one of <2> to <6>, wherein in the second internal electrode layer, the length in the width direction of the end surface drawn-out portion is shorter than the length in the width direction of the first opposing portion.

[0099] <8> The multilayer ceramic capacitor according to any one of <2> to <7>, wherein in the second internal electrode layer, the lengths of the two end surface drawn-out portions in the width direction are both shorter than the length of the first opposing portion in the width direction.

[0100] <9> A multilayer ceramic capacitor comprising: the laminate, which includes the inner layer portion in which the dielectric layers and the internal electrode layers are alternately stacked a plurality of times, and which has the two main surfaces opposing each other in the stacking direction, the two end faces opposing each other in a length direction intersecting the stacking direction, and the two side surfaces opposing each other in a width direction intersecting the stacking direction and the length direction; and external electrodes connected to the internal electrode layers at the side surfaces and the end surfaces of the laminate, wherein the internal electrode layers comprise the first internal electrode layers and the second internal electrode layers, and the first internal electrode layers comprise first opposing portions opposing the second internal electrode layers via the dielectric layers, and side surface drawn portions drawn from the first opposing portions to the side surfaces of the laminate, and the second internal electrode layers comprise second opposing portions opposing the first internal electrode layers via the dielectric layers, and end surface drawn portions drawn from the opposing portions to the two end surfaces of the laminate, and the internal electrode layers have through holes that communicate in the stacking direction and through which a dielectric constituting the dielectric layers enters, <8>. The multilayer ceramic capacitor according to any one of <1> to <8>, wherein the presence rate of the communicating holes in the second internal electrode layer is higher in a connection region of the second opposing portion where the end surface drawn-out portion is connected than in a center portion of the second opposing portion and higher than in a center portion of the end surface drawn-out portion.

[0101] A Principal surface B Side surface C End surface T1 Distance T2 Distance T3 Distance T Stacking direction W Width direction L Length direction P Through hole into which dielectric has penetrated JA Connection area JB Connection area 1 Multilayer ceramic capacitor 2 Laminate 3 End surface external electrode 4 Side surface external electrode 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 14a Dielectric layer 14b Dielectric layer 14c Dielectric layer 15 Internal electrode layer 15A First internal electrode layer 15Aa First opposing portion 15Ab Side surface lead-out portion 15B Second internal electrode layer 15Ba Second opposing portion 15Bb End surface lead-out portion 112 Ceramic green sheet for outer layer portion 114A First ceramic green sheet 114B Second ceramic green sheet 114a Ceramic paste 114b Ceramic paste 115A First internal electrode layer pattern 115B Second internal electrode layer pattern

Claims

1. a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately stacked, the laminate having two main surfaces opposing each other in a stacking direction, two end faces opposing each other in a length direction intersecting with the stacking direction, and two side surfaces opposing each other in a width direction intersecting with the stacking direction and the length direction; external electrodes connected to the internal electrode layers on at least one of the side surfaces and the end surfaces of the laminate; A multilayer ceramic capacitor comprising: the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer and the second internal electrode layer include opposing portions that overlap each other in a plan view from the stacking direction, and lead-out portions that are led out from the opposing portions to the end faces or the side faces of the laminate and do not overlap each other in a plan view from the stacking direction, the internal electrode layers communicate with each other in the stacking direction and have through holes into which the dielectric constituting the dielectric layers penetrate, A multilayer ceramic capacitor, wherein the rate of presence of communicating holes into which the dielectric has entered is higher in a connection region of the opposing portion where the drawn-out portion is connected than in a central portion of the opposing portion and higher than in a central portion of the drawn-out portion.

2. the internal electrode layers include the first internal electrode layers and the second internal electrode layers, the first internal electrode layer includes a first opposing portion that faces the second internal electrode layer via the dielectric layer, and a side surface drawn portion that is drawn from the first opposing portion to the side surface of the laminate, the second internal electrode layer includes a second opposing portion opposing the first internal electrode layer via the dielectric layer, and an end surface drawn portion drawn from the opposing portion to the two end surfaces of the laminate, the internal electrode layers communicate with each other in the stacking direction and have through holes into which the dielectric constituting the dielectric layers penetrate, 2. The multilayer ceramic capacitor according to claim 1, wherein the presence rate of the communicating holes in the first internal electrode layer is higher in a connection region of the first opposing portion where the side drawn portion is connected than in a central portion of the first opposing portion and higher than in a central portion of the side drawn portion.

3. 3. The multilayer ceramic capacitor according to claim 2, wherein, in the spacing in the stacking direction between the first internal electrode layers adjacent to each other in the stacking direction, a spacing T1 in the connection region overlapping with the second internal electrode layer when the first internal electrode layer is viewed in a plane from the stacking direction is longer than a spacing T2 in a center portion of the first opposing portion, and has a portion longer than a spacing T3 in the side lead portion not overlapping with the second internal electrode layer when the first internal electrode layer is viewed in a plane from the stacking direction.

4. In the first internal electrode layer having two side surface lead-out portions led out to two side surfaces of the laminate opposing each other in the width direction, 3. The multilayer ceramic capacitor according to claim 2, wherein the rate of presence of the through holes into which the dielectric has entered is higher in the two connection regions where the two side lead portions of the first opposing portion are connected than in the center of the first opposing portion and higher than in the center of the two lead portions.

5. 3. The multilayer ceramic capacitor according to claim 2, wherein in said first internal electrode layer, the length of said side lead-out portion in said longitudinal direction is shorter than the length of said first opposing portion in said longitudinal direction.

6. 6. The multilayer ceramic capacitor according to claim 2, wherein in the first internal electrode layer, the length in the longitudinal direction of the two side lead-out portions led out to the two side surfaces of the laminate opposing in the width direction is both shorter than the length in the longitudinal direction of the first opposing portion.

7. 3. The multilayer ceramic capacitor according to claim 2, wherein in said second internal electrode layer, the length in said width direction of said end surface drawn-out portion is shorter than the length in said width direction of said first opposing portion.

8. 8. The multilayer ceramic capacitor according to claim 2, wherein in the second internal electrode layer, the lengths of the two end surface lead portions in the width direction are both shorter than the length of the first opposing portion in the width direction.

9. the laminate including the inner layer portion in which the dielectric layers and the internal electrode layers are alternately stacked a plurality of times, the laminate having two principal surfaces opposed to each other in the stacking direction, two end faces opposed to each other in a length direction intersecting with the stacking direction, and two side surfaces opposed to each other in a width direction intersecting with the stacking direction and the length direction; external electrodes connected to the internal electrode layers on the side surfaces and end surfaces of the laminate; A multilayer ceramic capacitor comprising: the internal electrode layers include the first internal electrode layers and the second internal electrode layers, the first internal electrode layer includes a first opposing portion that faces the second internal electrode layer via the dielectric layer, and a side surface drawn portion that is drawn from the first opposing portion to the side surface of the laminate, the second internal electrode layer includes a second opposing portion opposing the first internal electrode layer via the dielectric layer, and an end surface drawn portion drawn from the opposing portion to the two end surfaces of the laminate, the internal electrode layers communicate with each other in the stacking direction and have through holes into which the dielectric constituting the dielectric layers penetrate, 2. The multilayer ceramic capacitor according to claim 1, wherein the presence rate of the communicating holes in the second internal electrode layer is higher in a connection region of the second opposing portion where the end surface drawn-out portion is connected than in a central portion of the second opposing portion and higher than in a central portion of the end surface drawn-out portion.