Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor (100) comprises: a capacitor body (1) in which a plurality of dielectric layers (2), a plurality of first internal electrodes (3), and a plurality of second internal electrodes (4) are stacked; a first via conductor (5) provided in the capacitor body (1) and electrically connected to the plurality of first internal electrodes (3); a second via conductor (6) provided in the capacitor body (1) and electrically connected to the plurality of second internal electrodes (4); a first external electrode (11) provided on at least one of a first main surface (1a) and a second main surface (1b) opposing each other in a stacking direction among the surfaces of the capacitor body (1), the first external electrode (11) being connected to the first via conductor (5); a second external electrode (12) provided on at least one main surface of the capacitor body (1) and connected to the second via conductor (6); and a first metal layer (21) provided on a side surface of the capacitor body (1) and electrically connected to the first via conductor (5).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer capacitors are known in which the ESL (equivalent series inductance) is reduced by widening the route through which current flows, shortening the route through which current flows, canceling out magnetic fields generated by currents of opposite polarity, etc. Patent Document 1 discloses an example of a multilayer capacitor with reduced ESL.

[0003] The multilayer capacitor disclosed in Patent Document 1 includes a capacitor body formed by laminating a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes. The capacitor body is provided with a plurality of first via conductors electrically connected to the plurality of first internal electrodes and extending to one main surface of the capacitor body, and a plurality of second via conductors electrically connected to the plurality of second internal electrodes and extending to the one main surface of the capacitor body. The one main surface of the capacitor body is provided with a plurality of first external electrodes electrically connected to the plurality of first via conductors, respectively, and a plurality of second external electrodes electrically connected to the plurality of second via conductors, respectively.

[0004] Japanese Patent Application Laid-Open No. 2006-135333

[0005] Here, when manufacturing the multilayer capacitor described in the above-mentioned Patent Document 1, a method of forming the first external electrodes and the second external electrodes by a plating process using a rotary plating method is considered. In barrel plating, which is an example of a rotary plating method, for example, a large number of capacitor bodies and a large number of conductive media are placed in a rotatable barrel, and the barrel is rotated in a plating solution. Electricity is applied to the barrel, and plating is formed in plating formation areas on the surface of the capacitor body where the first via conductors and the second via conductors are exposed. The conductive media are, for example, metal spheres. Using the rotary plating method, the first external electrodes and the second external electrodes can be formed on the surfaces of a large number of capacitor bodies in a single plating process, making it possible to produce a large number of multilayer capacitors at once.

[0006] However, since the area of ​​the surface of the capacitor body where the first via conductor and the second via conductor are exposed is a small area, there is a possibility that the conductive medium will not come into contact with the plating formation area during the plating process, and a plating film will not be formed, or that a multilayer capacitor will be manufactured in which the plating film is not sufficiently formed.

[0007] The present invention has been made to solve the above-mentioned problems, and has an object to provide a multilayer ceramic capacitor in which external electrodes can be formed more reliably by rotary plating.

[0008] The multilayer ceramic capacitor of the present invention is characterized by comprising: a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; first via conductors provided inside the capacitor body and electrically connected to the plurality of first internal electrodes; second via conductors provided inside the capacitor body and electrically connected to the plurality of second internal electrodes; a first external electrode provided on at least one of a first main surface and a second main surface facing in a stacking direction of the dielectric layers, the first internal electrodes, and the second internal electrodes, of the surface of the capacitor body, and connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; and a first metal layer provided on a side surface of the capacitor body other than the first main surface and the second main surface, and electrically connected to the first via conductor.

[0009] In another aspect of the present invention, a multilayer ceramic capacitor comprises: a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; first via conductors provided inside the capacitor body and electrically connected to the plurality of first internal electrodes; second via conductors provided inside the capacitor body and electrically connected to the plurality of second internal electrodes; a first external electrode provided on at least one of a first main surface and a second main surface facing in a stacking direction of the dielectric layers, the first internal electrodes, and the second internal electrodes, of the surface of the capacitor body, and connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; a first metal layer provided on a side surface of the capacitor body other than the first main surface and the second main surface, and electrically connected to the first via conductor; and a second metal layer provided on the side surface of the capacitor body and electrically connected to the second via conductor.

[0010] According to the multilayer ceramic capacitor of the present invention, the first metal layer electrically connected to the first via conductor is provided on the side surface of the capacitor body, so that the formation of the external electrode by rotary plating can be more reliably performed. That is, during rotary plating, the plating area can be plated not only when the conductive medium abuts on the plating area where the first via conductor is exposed, but also when the conductive medium abuts on the first metal layer, so that the formation of the first external electrode can be more reliably performed.

[0011] In another aspect of the present invention, a multilayer ceramic capacitor includes a first metal layer electrically connected to the first via conductor and a second metal layer electrically connected to the second via conductor on the side surface of the capacitor body, which allows the external electrodes to be formed more reliably by rotary plating. That is, during rotary plating, the external electrodes can be plated not only when the conductive medium contacts the plating formation area where the first and second via conductors are exposed, but also when the conductive medium contacts the first and second metal layers. This allows the first and second external electrodes to be formed more reliably.

[0012] 1A is a top view schematically showing a multilayer ceramic capacitor according to a first embodiment of the present invention, and FIG. 1B is a bottom view schematically showing the multilayer ceramic capacitor according to the first embodiment. It is a side view of the multilayer ceramic capacitor shown in FIG. 1 as viewed in the direction of arrow Y1. It is a cross-sectional view schematically showing the structure of the multilayer ceramic capacitor shown in FIG. 1 when cut along line III-III. It is a plan view schematically showing a first internal electrode, and it is a plan view schematically showing a second internal electrode. It is a partially enlarged view schematically showing various examples of the positional relationship between the second metal layer and the second connecting layer, and it is a partially enlarged view schematically showing examples of the shape of the second connecting layer corresponding to it in FIG. 1A to FIG. 1D. It is a side view schematically showing the state in which the multilayer ceramic capacitor according to the first embodiment is mounted on a mounting substrate. 10A is a plan view schematically showing a first internal electrode when a first connection layer and a second connection layer are provided on one layer, and FIG. 10B is a plan view schematically showing a second internal electrode when a first connection layer and a second connection layer are provided on one layer. (a) is a plan view schematically showing a first internal electrode and a first connection layer when a first connection layer is provided on a layer on which a first internal electrode is provided but a second connection layer is not provided. (b) is a plan view schematically showing a second internal electrode and a second connection layer when a second connection layer is provided on a layer on which a second internal electrode is provided but a first connection layer is not provided. (b) is a flowchart for explaining an example of a method for manufacturing a multilayer ceramic capacitor. (a) is a top view schematically showing a multilayer ceramic capacitor according to a second embodiment, and (b) is a bottom view schematically showing a multilayer ceramic capacitor according to the second embodiment. (c) is a side view of the multilayer ceramic capacitor shown in FIG. 10 as viewed in the direction of arrow Y2. 1A is a plan view schematically showing a first internal electrode of a multilayer ceramic capacitor according to a second embodiment, FIG. 1B is a plan view schematically showing a second internal electrode of the multilayer ceramic capacitor according to a third embodiment, FIG. 1A is a top view schematically showing a multilayer ceramic capacitor according to a third embodiment, and FIG. 1B is a bottom view schematically showing the multilayer ceramic capacitor.15A and 15B are plan views each showing a first internal electrode and a second internal electrode of a multilayer ceramic capacitor according to a third embodiment. (a) is a top view showing a multilayer ceramic capacitor according to a fourth embodiment, and (b) is a bottom view showing the multilayer ceramic capacitor. (b) is a side view of the multilayer ceramic capacitor shown in FIG. 15 as viewed in the direction of arrow Y3. (a) is a plan view showing a first internal electrode and a second internal electrode of a multilayer ceramic capacitor according to a fourth embodiment. (b) is a plan view showing a second internal electrode of a multilayer ceramic capacitor according to a fourth embodiment. (a) is a plan view showing a first internal electrode and a first connecting layer in a case where a first connecting layer is provided on a layer on which a first internal electrode is provided but a second connecting layer is not provided. (b) is a plan view showing a second internal electrode and a second connecting layer in a case where a second connecting layer is provided on a layer on which a second internal electrode is provided but a first connecting layer is not provided. 1A and 1B are top views of a multilayer ceramic capacitor schematically showing another arrangement pattern of the external electrodes when the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is odd, respectively; and 1A and 1B are top views of a multilayer ceramic capacitor schematically showing another arrangement pattern of the external electrodes when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd, respectively; and 1A and 1B are top views of a multilayer ceramic capacitor schematically showing another arrangement pattern of the external electrodes when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is even, respectively.

[0013] The features of the present invention will be described in detail below with reference to embodiments of the present invention. <First Embodiment> Fig. 1(a) is a top view schematically showing a multilayer ceramic capacitor 100 according to a first embodiment of the present invention, and Fig. 1(b) is a bottom view schematically showing the multilayer ceramic capacitor 100 according to the first embodiment. Here, a first main surface 1a of a capacitor body 1 (described later) is referred to as the top surface, and a second main surface 1b is referred to as the bottom surface. Fig. 2 is a side view of the multilayer ceramic capacitor 100 shown in Fig. 1 as viewed in the direction of arrow Y1. Fig. 3 is a cross-sectional view schematically showing the structure of the multilayer ceramic capacitor 100 shown in Fig. 1 when cut along line III-III.

[0014] The multilayer ceramic capacitor 100 includes a capacitor body 1, first via conductors 5, second via conductors 6, a first external electrode 11, a second external electrode 12, and a first metal layer 21. The multilayer ceramic capacitor 100 of this embodiment further includes a second metal layer 22. The multilayer ceramic capacitor 100 of this embodiment also includes a first connecting layer 31 and a second connecting layer 32.

[0015] 3, the capacitor body 1 has a structure in which a plurality of dielectric layers 2, a plurality of first internal electrodes 3, and a plurality of second internal electrodes 4 are laminated. More specifically, the capacitor body 1 has a structure in which the first internal electrodes 3 and the second internal electrodes 4 are alternately laminated with the dielectric layers 2 interposed therebetween.

[0016] The dielectric layer 2 may be made of any material, such as a ceramic material containing BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as a main component. Subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be added to these main components in amounts less than the main components.

[0017] The capacitor body 1 may have any shape. In this embodiment, the capacitor body 1 has a rectangular parallelepiped shape as a whole. A rectangular parallelepiped shape as a whole refers to a shape that is not a perfect rectangular parallelepiped shape, such as a shape in which the corners and ridges of the rectangular parallelepiped are rounded or a shape in which the surface of the rectangular parallelepiped has irregularities, but has six surfaces and can be regarded as a rectangular parallelepiped as a whole. Therefore, the capacitor body 1 has a first main surface 1a, a second main surface 1b, a first side surface 1c, a second side surface 1d, a third side surface 1e, and a fourth side surface 1f.

[0018] The first main surface 1a and the second main surface 1b of the capacitor body 1 are surfaces that face the stacking direction T of the dielectric layers 2, the first internal electrodes 3, and the second internal electrodes 4. The first side surface 1c to the fourth side surface 1f of the capacitor body 1 constitute four side surfaces of the capacitor body 1 other than the first main surface 1a and the second main surface 1b. The first side surface 1c faces the third side surface 1e, and the second side surface 1d faces the fourth side surface 1f. In this embodiment, the first side surface 1c to the fourth side surface 1f of the capacitor body 1 are orthogonal to the first main surface 1a and the second main surface 1b, respectively, but they do not have to be orthogonal.

[0019] The dimensions of the capacitor body 1 are arbitrary. For example, the vertical dimension of the rectangular capacitor body 1 in plan view in the stacking direction T can be 0.3 mm to 3.0 mm, the horizontal dimension can be 0.3 mm to 3.0 mm, and the dimension in the stacking direction T can be 50 μm to 200 μm. The dimension of the capacitor body 1 in the stacking direction T refers to the thickness of the capacitor body 1.

[0020] Fig. 4(a) is a plan view schematically showing the first internal electrode 3, and Fig. 4(b) is a plan view schematically showing the second internal electrode 4. Figs. 4(a) and 4(b) also show the dielectric layer 2, the first via conductor 5, and the second via conductor 6. Fig. 4(a) also shows the second connecting layer 32, which will be described later, and Fig. 4(b) also shows the first connecting layer 31, which will be described later.

[0021] As shown in Figures 4(a) and (b), in this embodiment, the shape of the dielectric layer 2 when viewed in the stacking direction T is rectangular. The shape of the first internal electrode 3 when viewed in the stacking direction T is not rectangular. Specifically, as shown in Figure 4(a), the first internal electrode 3 has a shape obtained by removing a pair of corners from a rectangle. The shape of the removed corners is, for example, rectangular. Furthermore, the shape of the second internal electrode 4 when viewed in the stacking direction T is not rectangular. Specifically, as shown in Figure 4(b), the second internal electrode 4 has a shape obtained by removing a pair of corners from a rectangle. The shape of the removed corners is, for example, rectangular. However, the shape of the first internal electrode 3 is not limited to the shape shown in Figure 4(a), and the shape of the second internal electrode 4 is not limited to the shape shown in Figure 4(b).

[0022] The first internal electrode 3 and the second internal electrode 4 may be made of any material, and may be, for example, a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals. The first internal electrode 3 and the second internal electrode 4 may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 2. In this case, the proportion of the common material contained in the first internal electrode 3 and the second internal electrode 4 is, for example, 20 vol % or less.

[0023] The thickness of the first internal electrode 3 and the second internal electrode 4 is arbitrary, and can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode 3 and the second internal electrode 4 is arbitrary. For example, the total number of layers of the first internal electrode 3 and the second internal electrode 4 can be about 10 layers or more and 150 layers or less.

[0024] In the multilayer ceramic capacitor 100, the first internal electrode 3 and the second internal electrode 4 face each other with the dielectric layer 2 interposed therebetween, thereby forming a capacitance.

[0025] The first via conductors 5 and the second via conductors 6 are provided inside the capacitor body 1. In this embodiment, as shown in FIG. 1 , a plurality of first via conductors 5 and a plurality of second via conductors 6 are arranged in a matrix. More specifically, four via conductors, including two first via conductors 5 and two second via conductors 6, are provided at positions corresponding to the four corners of the rectangular capacitor body 1 in a plan view in the stacking direction T. However, the arrangement of the first via conductors 5 and the second via conductors 6 is not limited to a matrix arrangement. Furthermore, the number of first via conductors 5 and the number of second via conductors 6 are not limited to two, and can be any number.

[0026] 3 , the first via conductors 5 are provided inside the capacitor body 1 so as to extend in the stacking direction T from the first main surface 1 a toward the second main surface 1 b of the capacitor body 1, and are electrically connected to the plurality of first internal electrodes 3. The first via conductors 5 are spaced apart from the second internal electrodes 4 and are insulated from the second internal electrodes 4.

[0027] 3 , the second via conductors 6 are provided inside the capacitor body 1 so as to extend in the stacking direction T from the first main surface 1 a to the second main surface 1 b of the capacitor body 1, and are electrically connected to the plurality of second internal electrodes 4. The second via conductors 6 are spaced apart from the first internal electrodes 3 and are insulated from the first internal electrodes 3.

[0028] As shown in FIG. 3, the first via conductor 5 and the second via conductor 6 are not exposed on the second main surface 1b of the capacitor body 1, but may be exposed.

[0029] The material of the first via conductor 5 and the second via conductor 6 is arbitrary, and for example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn or Au, or alloys containing these metals, can be used.

[0030] The first via conductor 5 and the second via conductor 6 may have any shape, for example, a cylindrical shape, and in this case, the diameter of the first via conductor 5 and the second via conductor 6 is, for example, about 30 μm or more and 150 μm or less.

[0031] The first external electrode 11 is provided on at least one of the first and second principal surfaces 1a and 1b of the capacitor body 1, and is connected to the first via conductors 5. In this embodiment, the first via conductors 5 are exposed on the first principal surface 1a of the capacitor body 1, and the first external electrode 11 is provided on the first principal surface 1a of the capacitor body 1. More specifically, the first external electrode 11 is provided at a position overlapping the first via conductors 5 in the stacking direction T. The number of first external electrodes 11 is the same as the number of first via conductors 5, which is two in the example shown in FIG. 1 . However, the number of first external electrodes 11 is not limited to two. As described above, the first via conductors 5 are electrically connected to a plurality of first internal electrodes 3, and therefore the first external electrode 11 is electrically connected to a plurality of first internal electrodes 3.

[0032] The second external electrode 12 is provided on at least one of the principal surfaces of the capacitor body 1 and is connected to the second via conductor 6. In this embodiment, the second via conductor 6 is exposed on the first principal surface 1a of the capacitor body 1, and like the first external electrode 11, the second external electrode 12 is provided on the first principal surface 1a of the capacitor body 1. More specifically, the second external electrode 12 is provided at a position overlapping the second via conductor 6 in the stacking direction T. The number of second external electrodes 12 is the same as the number of second via conductors 6, which is two in the example shown in FIG. 1 . However, the number of second external electrodes 12 is not limited to two. As described above, the second via conductor 6 is electrically connected to a plurality of second internal electrodes 4, and therefore the second external electrode 12 is electrically connected to a plurality of second internal electrodes 4.

[0033] In addition, the first via conductor 5 and the second via conductor 6 may each be exposed on the second main surface 1b of the capacitor body 1, and the first external electrode 11 and the second external electrode 12 may each be provided on the second main surface 1b.

[0034] The first external electrode 11 and the second external electrode 12 may be made of any material. In this embodiment, the first external electrode 11 and the second external electrode 12 are plated electrodes formed by a plating process using a rotary plating method. Examples of materials that can be used to form the plated electrodes include Cu, Ni, and Sn. The plated electrodes may be formed of a single layer or multiple layers.

[0035] The first metal layer 21 is provided on a side surface of the capacitor body 1 and is electrically connected to the first via conductor 5. In this embodiment, as shown in Fig. 1 , the first metal layer 21 is provided at a corner position spanning from the first side surface 1c to the second side surface 1d of the capacitor body 1 and at a corner position spanning from the third side surface 1e to the fourth side surface 1f. However, the position at which the first metal layer 21 is provided is not limited to the position shown in Fig. 1 .

[0036] The second metal layer 22 is provided on a side surface of the capacitor body 1 and is electrically connected to the second via conductor 6. In this embodiment, as shown in Fig. 1 , the second metal layer 22 is provided at a corner position spanning from the second side surface 1d to the third side surface 1e of the capacitor body 1 and at a corner position spanning from the fourth side surface 1f to the first side surface 1c. However, the position at which the second metal layer 22 is provided is not limited to the position shown in Fig. 1 .

[0037] The first metal layer 21 and the second metal layer 22 may be made of any material. In this embodiment, the first metal layer 21 and the second metal layer 22 are plated layers formed by a plating process using a rotary plating method. Examples of materials that can be used to form the plated layers include Cu, Ni, and Sn. The plated layers may be formed as a single layer or multiple layers.

[0038] In the multilayer ceramic capacitor 100 of this embodiment, a first connection layer 31 for electrically connecting the first via conductors 5 and the first metal layer 21, and a second connection layer 32 for electrically connecting the second via conductors 6 and the second metal layer 22 are provided inside the capacitor body 1. The first connection layer 31 and the second connection layer 32 have a planar shape extending in a direction perpendicular to the stacking direction T.

[0039] In this embodiment, as shown in Fig. 4(b), the first connection layer 31 is provided on the same layer as the second internal electrode 4. The first connection layer 31 may be provided on all of the layers on which the second internal electrode 4 is provided, or may be provided on only some of the layers. As shown in Fig. 4(a), the second connection layer 32 is provided on the same layer as the first internal electrode 3. The second connection layer 32 may be provided on all of the layers on which the first internal electrode 3 is provided, or may be provided on only some of the layers.

[0040] As shown in Fig. 4(b), the first connection layer 31 is in contact with the first via conductor 5 but is spaced apart from the second internal electrode 4. As shown in Fig. 4(a), the second connection layer 32 is in contact with the second via conductor 6 but is spaced apart from the first internal electrode 3.

[0041] The first connection layer 31 and the second connection layer 32 may have any shape. In this embodiment, as shown in Fig. 4(b), the first connection layer 31 has a quarter-circle shape. As shown in Fig. 4(a), the second connection layer 32 has a quarter-circle shape.

[0042] The conductive first connection layer 31 and second connection layer 32 may be made of any material, and may be made of the same material as the first internal electrode 3 and second internal electrode 4, for example.

[0043] In the manufacturing process of the multilayer ceramic capacitor 100, the first connection layer 31 and the second connection layer 32 are exposed on the side surface of the capacitor body 1 before the first metal layer 21 and the second metal layer 22 are provided. The first metal layer 21 is provided in a manner covering the first connection layer 31 exposed on the side surface of the capacitor body 1. The second metal layer 22 is provided in a manner covering the second connection layer 32 exposed on the side surface of the capacitor body 1.

[0044] The shape of the first metal layer 21 can be changed by changing the shape of the portion of the first connection layer 31 that is exposed on the side surface of the capacitor body 1. Similarly, the shape of the second metal layer 22 can be changed by changing the shape of the portion of the second connection layer 32 that is exposed on the side surface of the capacitor body 1.

[0045] Fig. 5(a) is a partially enlarged view schematically illustrating the positional relationship between the second metal layer 22 and the second connecting layer 32 of the multilayer ceramic capacitor 100 shown in Figs. 1 to 3. Figs. 5(b), 5(c), and 5(d) are partially enlarged views schematically illustrating the positional relationship between the second metal layer 22 and the second connecting layer 32, each having a shape different from that shown in Fig. 5(a). Figs. 5(e) to 5(h) are partially enlarged views schematically illustrating examples of the shape of the second connecting layer 32 corresponding to Figs. 5(a) to 5(d). Figs. 5(e) to 5(h) also show portions of the dielectric layer 2, the first internal electrode 3, and the second via conductor 6.

[0046] The configuration shown in Fig. 5(b) has a smaller area of ​​the second metal layer 22 than the configuration shown in Fig. 5(a). As can be seen by comparing Fig. 5(e) and Fig. 5(f), it is possible to reduce the area of ​​the second metal layer 22 by reducing the area of ​​the portion of the second connection layer 32 that is exposed on the side surface of the capacitor body 1. Although not shown, the same is true for the first metal layer 21 and the first connection layer 31.

[0047] In the configuration shown in FIG. 5( c), two second metal layers 22 are provided on one side surface of the capacitor body 1. The two second metal layers 22 are provided at positions spaced apart from each other. While FIG. 5( c) shows two second metal layers 22 provided on the first side surface 1c of the capacitor body 1, two second metal layers 22 may also be provided on the second side surface 1d, the third side surface 1e, and the fourth side surface 1f. To achieve such a configuration, the second connection layer 32 has a shape exposed at two locations on one side surface of the capacitor body 1, as shown in FIG. 5( g). Although not shown, the same applies to the first metal layer 21 and the first connection layer 31. Note that the number of first metal layers 21 and the number of second metal layers 22 provided on one side surface of the capacitor body 1 are not limited to two and may be three or more.

[0048] In the configuration shown in FIG. 5( d ), the second metal layer 22 is provided only in the region of the side surface of the capacitor body 1 that faces the first principal surface 1 a, where the first external electrode 11 and the second external electrode 12 are provided. That is, when the side surface of the capacitor body 1 is divided into a region on the first principal surface 1 a side and a region on the second principal surface 1 b side, the second metal layer 22 is provided only in the region on the first principal surface 1 a side. In this case, the second connection layer 32 only needs to be provided on the layer on the first principal surface 1 a side in the stacking direction T. Note that, as shown in FIG. 5( h ), the shape of the second connection layer 32 can be the same as the shape of the second connection layer 32 shown in FIG. 5( b ).

[0049] As will be described later, when the multilayer ceramic capacitor 100 of this embodiment is mounted on a mounting substrate, the first metal layer 21 and the second metal layer 22 can also be joined to the land electrodes of the mounting substrate via solder. According to the configuration shown in Fig. 5(d), the first metal layer 21 and the second metal layer 22 are not provided in areas that are not soldered when the multilayer ceramic capacitor 100 is mounted, which simplifies the configuration and reduces manufacturing costs.

[0050] According to the multilayer ceramic capacitor 100 of this embodiment, the first metal layer 21 electrically connected to the first via conductors 5 and the second metal layer 22 electrically connected to the second via conductors 6 are provided on the side surfaces of the capacitor body 1, so that the external electrodes can be formed more reliably by spin plating. As will be described later, during spin plating, plating can be applied to the plate formation areas not only when a conductive medium abuts on the plate formation areas on the surface of the capacitor body 1 where the first via conductors 5 and the second via conductors 6 are exposed, but also when a conductive medium abuts on the first metal layer 21 and the second metal layer 22. This makes it possible to more reliably form the first external electrode 11 and the second external electrode 12.

[0051] Furthermore, according to the multilayer ceramic capacitor 100 of this embodiment, when mounting on a mounting substrate, not only the first external electrode 11 and the second external electrode 12 but also the first metal layer 21 and the second metal layer 22 are joined to the land electrodes of the mounting substrate, thereby enabling stable mounting.

[0052] 6 is a side view schematically showing a state in which the multilayer ceramic capacitor 100 of this embodiment is mounted on a mounting substrate 200. The first external electrode 11 and the second external electrode 12 of the multilayer ceramic capacitor 100 are each joined to a land electrode 210 of the mounting substrate 200 via solder 220. The first metal layer 21 and the second metal layer 22 provided on the side surface of the capacitor body 1 are each joined to the land electrode 210 of the mounting substrate 200 via solder 220. Since the first metal layer 21 and the second metal layer 22 are also joined to the land electrode 210 of the mounting substrate 200 in addition to the first external electrode 11 and the second external electrode 12, more stable mounting is possible.

[0053] Furthermore, by joining the first metal layer 21 and the second metal layer 22 to the land electrode 210 of the mounting substrate 200 via the solder 220, it is also possible to visually check whether the multilayer ceramic capacitor 100 is mounted or not.

[0054] (Variation 1 of the First Embodiment) As shown in Figures 4(a) and (b), the first connection layer 31 and the second connection layer 32 are alternately provided on different layers, but it is also possible to configure the first connection layer 31 and the second connection layer 32 to be provided on the same layer.

[0055] 7(a) is a plan view showing a schematic view of the first internal electrode 3 when the first connection layer 31 and the second connection layer 32 are provided on the same layer, and FIG. 7(b) is a plan view showing a schematic view of the second internal electrode 4. In FIGS. 7(a) and 7(b), the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connection layer 31, and the second connection layer 32 are also shown.

[0056] 7A, the layer on which the first internal electrode 3 is provided has a first connection layer 31 as well as a second connection layer 32. The first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5. The first connection layer 31 is not in direct contact with the first internal electrode 3.

[0057] 7(b), the layer on which the second internal electrode 4 is provided has a first connection layer 31 and a second connection layer 32. The second connection layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 through the second via conductor 6. The second connection layer 32 is not in direct contact with the second internal electrode 4.

[0058] 4( a) and 4(b), this configuration example has a larger number of first connection layers 31 connecting the first via conductors 5 and the first metal layer 21, and a larger number of second connection layers 32 connecting the second via conductors 6 and the second metal layer 22. This makes the electrical connection between the first via conductors 5 and the first metal layer 21 via the first connection layers 31, and the electrical connection between the second via conductors 6 and the second metal layer 22 via the second connection layers 32, more reliable, and allows the first external electrode 11 and the second external electrode 12 to be formed more reliably by spin plating.

[0059] Furthermore, because the first connection layer 31 is not in direct contact with the first internal electrode 3, it is possible to prevent the intrusion of plating solution from the outside into the interior during manufacturing, and it is also possible to prevent the intrusion of moisture, etc. from the outside into the interior of the finished product. That is, in a configuration in which the first connection layer 31 is in direct contact with the first internal electrode 3, plating solution, moisture, etc. easily infiltrate from the outside of the capacitor body 1 into the interior through the first connection layer 31 and the first internal electrode 3, but because the first connection layer 31 is separated from the first internal electrode 3, it is possible to prevent the intrusion of plating solution, moisture, etc. into the interior. Similarly, because the second connection layer 32 is not in direct contact with the second internal electrode 4, it is possible to prevent the intrusion of plating solution, moisture, etc. from the outside into the interior of the capacitor body 1.

[0060] 4(a) and 4(b) compared to the configuration shown in Figures 7(a) and 7(b), the internal electrodes and connection layers are completely separated in one layer, and therefore the configuration shown in Figures 4(a) and 4(b) can more effectively prevent the penetration of plating solution, moisture, and the like from the outside to the inside of the capacitor body 1.

[0061] 4(a) and 4(b) , the second connection layer 32 is provided on the layer on which the first internal electrode 3 is provided, and the first connection layer 31 is provided on the layer on which the second internal electrode 4 is provided. However, a configuration in which the first connection layer 31 is provided on the layer on which the first internal electrode 3 is provided, and the second connection layer 32 is provided on the layer on which the second internal electrode 4 is provided, may also be used. In this case, a plan view schematically showing the first internal electrode 3 and the first connection layer 31 is shown in FIG. 8(a) , and a plan view schematically showing the second internal electrode 4 and the second connection layer 32 is shown in FIG. 8(a) and 8(b) . The dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown.

[0062] As shown in Fig. 8(a), the first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5. The first connection layer 31 is not in direct contact with the first internal electrode 3. As shown in Fig. 8(a), the second connection layer 32 is not provided on the layer on which the first internal electrode 3 is provided.

[0063] As shown in Fig. 8(b), the second connection layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 through the second via conductor 6. The second connection layer 32 is not in direct contact with the second internal electrode 4. As shown in Fig. 8(b), the first connection layer 31 is not provided on the layer on which the second internal electrode 4 is provided.

[0064] 8(a) and 8(b) , the number of first connection layers 31 and second connection layers 32 can be reduced by approximately half compared to the configuration shown in FIGS. 7(a) and 7(b) , thereby preventing the intrusion of plating solution from the outside into the interior during manufacturing and preventing the intrusion of moisture and the like from the outside into the interior of the finished product. That is, while plating solution and moisture are likely to infiltrate the capacitor body 1 at locations on the side surfaces where the first connection layers 31 and second connection layers 32 are exposed, the reduced number of first connection layers 31 and second connection layers 32 prevents the intrusion of plating solution and moisture and the like into the interior. This is also true for the configuration shown in FIGS. 4(a) and 4(b) .

[0065] (Method for Manufacturing Multilayer Ceramic Capacitor) An example of a method for manufacturing the multilayer ceramic capacitor 100 described above will be described with reference to the flowchart shown in FIG.

[0066] 9, ceramic green sheets, a conductive paste for internal electrodes, and a conductive paste for connection layers are prepared. Known ceramic green sheets can be used, and can be obtained, for example, by applying a ceramic slurry containing ceramic powder, a resin component, and a solvent onto a substrate and drying it.

[0067] The conductive paste for internal electrodes is a conductive paste for forming the first internal electrodes 3 and the second internal electrodes 4, and a known conductive paste can be used. The conductive paste for internal electrodes contains particles made of a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or a precursor thereof, and a solvent. The conductive paste for internal electrodes may further contain a resin component that serves as a dispersant or binder.

[0068] The conductive paste for the connection layers is a conductive paste for forming the first connection layer 31 and the second connection layer 32, and may be the same as the conductive paste for the internal electrodes, for example. However, a conductive paste different from the conductive paste for the internal electrodes may also be used as the conductive paste for the connection layers.

[0069] In step S2 following step S1, the prepared ceramic green sheets are coated with a conductive paste for internal electrodes and a conductive paste for connection layers by a method such as printing. The conductive paste for internal electrodes is coated at positions where the first internal electrodes 3 and second internal electrodes 4 will be formed. The conductive paste for connection layers is coated at positions where the first connection layers 31 and second connection layers 32 will be formed. Here, electrode patterns and connection layer patterns are formed that enable multiple multilayer ceramic capacitors 100 to be manufactured at once.

[0070] In step S3 following step S2, a mother laminate is produced by stacking multiple ceramic green sheets coated with the conductive paste for the internal electrodes and the conductive paste for the connection layers. When producing the mother laminate, ceramic green sheets without electrode patterns and connection layer patterns may be arranged on the outer sides in the stacking direction. Here, multiple ceramic green sheets are stacked and then pressed in the stacking direction to produce the mother laminate. Any pressing method can be used, and for example, a rigid press or a hydrostatic press can be used.

[0071] In step S4 following step S3, a plurality of through holes extending in the stacking direction are formed in the mother laminate, and the formed through holes are filled with a conductive paste for via conductors. The through holes can be formed by any method, for example, by laser. The conductive paste for via conductors is a conductive paste for forming the first via conductors 5 and the second via conductors 6, and contains particles made of a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or a precursor thereof, and a solvent. The conductive paste for via conductors may further contain a resin component that serves as a dispersant or binder.

[0072] In step S5 following step S4, the mother laminate is cut into a plurality of individual unfired chips. The mother laminate can be cut by, for example, a method such as press cutting, dicing, or laser cutting.

[0073] In step S6 following step S5, the unsintered chip is fired to produce the capacitor body 1. The first via conductors 5 and the second via conductors 6 are exposed on the first main surface 1a of the produced capacitor body 1, and the first connecting layer 31 and the second connecting layer 32 are exposed on the side surfaces.

[0074] In step S7 following step S6, the first external electrode 11 and the second external electrode 12 are formed on the surface of the capacitor body 1. Here, the first external electrode 11 and the second external electrode 12 are formed by a plating process using barrel plating, which is an example of a rotary plating method. Specifically, a large number of capacitor bodies 1 and a large number of conductive media are placed in a rotatable barrel, and the barrel is rotated in a plating solution. Electricity is applied to the plating formation regions of the first main surface 1a of the capacitor body 1, where the first via conductors 5 and the second via conductors 6 are exposed. The conductive media are, for example, metal spheres. A plating film is formed in the plating formation regions, forming the first external electrode 11 and the second external electrode 12, which are plating electrodes.

[0075] In addition, by plating using the rotary plating method, a plating film is formed on the side of the capacitor body 1 in the areas where the first connection layer 31 and the second connection layer 32 are exposed, thereby forming the first metal layer 21 and the second metal layer 22, which are plating layers.

[0076] The plating film in the plating formation region is formed not only when the conductive medium contacts and conducts electricity with the first via conductors 5 and second via conductors 6 exposed on the first main surface 1 a of the capacitor body 1, but also when the conductive medium contacts and conducts electricity with the first connection layer 31 and second connection layer 32 exposed on the side surface of the capacitor body 1, and when the conductive medium contacts and conducts electricity with the first metal layer 21 and second metal layer 22 formed by plating on the side surface of the capacitor body 1. Therefore, the first external electrode 11 and the second external electrode 12 can be formed more reliably by plating using the rotation plating method.

[0077] As described above, in the multilayer ceramic capacitor 100 of this embodiment, the first metal layer 21 and the second metal layer 22 are provided at positions that straddle two side surfaces of the capacitor body 1. Therefore, compared to a configuration in which the first metal layer 21 and the second metal layer 22 are provided on only one side surface of the capacitor body 1, there are more opportunities for the conductive medium to come into contact with the first metal layer 21 and the second metal layer 22 during spin plating, and the first external electrode 11 and the second external electrode 12 can be formed more reliably.

[0078] The above-described manufacturing method provides the multilayer ceramic capacitor 100. Second Embodiment In the multilayer ceramic capacitor 100 of the first embodiment, the number of first external electrodes 11 and the number of second external electrodes 12 are two, but as described above, the number is not limited to two.

[0079] Fig. 10(a) is a top view schematically showing a multilayer ceramic capacitor 100A according to the second embodiment, and Fig. 10(b) is a bottom view schematically showing the multilayer ceramic capacitor 100A. Fig. 11 is a side view of the multilayer ceramic capacitor 100A shown in Fig. 10 as viewed in the direction of arrow Y2.

[0080] In the multilayer ceramic capacitor 100A according to the second embodiment, six first external electrodes 11 and six second external electrodes 12 are provided. A total of 12 external electrodes including the first external electrodes 11 and the second external electrodes 12 are arranged in a matrix. Here, four external electrodes are arranged in the row direction (horizontal direction in the drawing) and three external electrodes are arranged in the column direction (vertical direction in the drawing), but the number of external electrodes in the row direction is not limited to four, and the number of external electrodes in the column direction is not limited to three.

[0081] 10(a), the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the row direction, and only the first external electrodes 11 or only the second external electrodes 12 are arranged in the column direction. However, the arrangement pattern of the first external electrodes 11 and the second external electrodes 12 is not limited to the arrangement pattern shown in FIG.

[0082] Fig. 12(a) is a plan view schematically showing the first inner electrode 3, and Fig. 12(b) is a plan view schematically showing the second inner electrode 4. Figs. 12(a) and 12(b) also show the dielectric layer 2, the first via conductor 5, and the second via conductor 6. Fig. 12(a) also shows the first connecting layer 31, and Fig. 12(b) also shows the second connecting layer 32.

[0083] The first inner electrode 3 has a plurality of first through holes 3a formed therein for inserting the second via conductors 6. The second inner electrode 4 has a plurality of second through holes 4a formed therein for inserting the first via conductors 5.

[0084] 12(b), the first via conductor 5 provided at a position overlapping with the second internal electrode 4 in the stacking direction T passes through the second through hole 4a formed in the second internal electrode 4, and is insulated from the second internal electrode 4. Also, as shown in Fig. 12(a), the second via conductor 6 provided at a position overlapping with the first internal electrode 3 in the stacking direction T passes through the first through hole 3a formed in the first internal electrode 3, and is insulated from the first internal electrode 3.

[0085] As shown in Fig. 12(a), the first connection layer 31 is provided on the layer on which the first internal electrode 3 is provided. The first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5. The first connection layer 31 is not in direct contact with the first internal electrode 3. As shown in Fig. 12(a), the second connection layer 32 is not provided on the layer on which the first internal electrode 3 is provided.

[0086] As shown in Fig. 12(b), the second connection layer 32 is provided on the layer on which the second internal electrode 4 is provided. The second connection layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 through the second via conductor 6. The second connection layer 32 is not in direct contact with the second internal electrode 4. As shown in Fig. 12(b), the first connection layer 31 is not provided on the layer on which the second internal electrode 4 is provided.

[0087] Like the multilayer ceramic capacitor 100 in the first embodiment, the multilayer ceramic capacitor 100A in this embodiment has a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 provided on the side of the capacitor body 1, so that the formation of the first external electrode 11 and the second external electrode 12 by rotary plating can be more reliably carried out.

[0088] <Third Embodiment> In the multilayer ceramic capacitor 100 of the first embodiment and the multilayer ceramic capacitor 100A of the second embodiment described above, the first metal layer 21 and the second metal layer 22 are provided on the side surfaces of the capacitor body 1, but a configuration in which only the first metal layer 21 is provided is also possible.

[0089] FIG. 13A is a top view schematically showing a multilayer ceramic capacitor 100B according to the third embodiment, and FIG. 13B is a bottom view schematically showing the multilayer ceramic capacitor 100B according to the third embodiment.

[0090] The multilayer ceramic capacitor 100B according to the third embodiment is provided with five first external electrodes 11 and four second external electrodes 12. A total of nine external electrodes including the first external electrodes 11 and the second external electrodes 12 are arranged in a matrix. Here, three external electrodes are arranged in the row direction and three external electrodes in the column direction, but the number of external electrodes in the row direction is not limited to three, and the number of external electrodes in the column direction is not limited to three.

[0091] In this embodiment, the first external electrodes 11 are provided at the four corner positions and the central position out of the nine positions arranged in three rows and three columns, and the second external electrodes 12 are provided at the other positions.

[0092] The multilayer ceramic capacitor 100B of this embodiment includes a first metal layer 21 provided on the side surface of the capacitor body 1, but does not include a second metal layer. In this embodiment, the first metal layers 21 are provided at four locations: a corner extending from the first side surface 1c to the second side surface 1d of the capacitor body 1, a corner extending from the second side surface 1d to the third side surface 1e, a corner extending from the third side surface 1e to the fourth side surface 1f, and a corner extending from the fourth side surface 1f to the first side surface 1c. However, the locations at which the first metal layers 21 are provided are not limited to the above-described locations, and the number of first metal layers 21 is not limited to four.

[0093] Fig. 14(a) is a plan view schematically showing the first inner electrode 3, and Fig. 14(b) is a plan view schematically showing the second inner electrode 4. Figs. 14(a) and 14(b) also show the dielectric layer 2, the first via conductor 5, the second via conductor 6, and the first connecting layer 31.

[0094] The first inner electrode 3 has a plurality of first through holes 3a formed therein for inserting the second via conductors 6. The second inner electrode 4 has a plurality of second through holes 4a formed therein for inserting the first via conductors 5.

[0095] 14(b), the first via conductor 5 provided at a position overlapping with the second internal electrode 4 in the stacking direction T passes through the second through hole 4a formed in the second internal electrode 4, and is insulated from the second internal electrode 4. Also, as shown in Fig. 14(a), the second via conductor 6 provided at a position overlapping with the first internal electrode 3 in the stacking direction T passes through the first through hole 3a formed in the first internal electrode 3, and is insulated from the first internal electrode 3.

[0096] 14( a) and 14(b), the first connection layer 31 is provided on each of the layers on which the first internal electrodes 3 are provided and the layers on which the second internal electrodes 4 are provided. The first connection layers 31 are provided at the four corner positions of the rectangular dielectric layer 2 when viewed in the stacking direction T. The first connection layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5. The first connection layer 31 is not in direct contact with the first internal electrode 3.

[0097] According to the multilayer ceramic capacitor 100B of this embodiment, a first metal layer 21 electrically connected to the first via conductor 5 is provided on the side of the capacitor body 1, so that the formation of the first external electrode 11 by rotary plating can be carried out more reliably.

[0098] <Fourth Embodiment> As described above, in the multilayer ceramic capacitor 100B according to the third embodiment, a total of nine external electrodes are arranged in a matrix, and only the first metal layer 21 is provided on the side surface of the capacitor body 1.

[0099] In contrast, in the multilayer ceramic capacitor 100C of the fourth embodiment, a total of nine external electrodes are arranged in a matrix, and a first metal layer 21 and a second metal layer 22 are provided on the side surfaces of the capacitor body 1.

[0100] Fig. 15(a) is a top view schematically showing a multilayer ceramic capacitor 100C according to the fourth embodiment, and Fig. 15(b) is a bottom view schematically showing the multilayer ceramic capacitor 100C. Fig. 16 is a side view of the multilayer ceramic capacitor 100C shown in Fig. 15 as viewed in the direction of arrow Y3.

[0101] Like the multilayer ceramic capacitor 100B according to the third embodiment, the multilayer ceramic capacitor 100C according to the fourth embodiment also has five first external electrodes 11 and four second external electrodes 12. As shown in Fig. 15(a) , the positions of the first external electrodes 11 and the second external electrodes 12 are the same as those of the multilayer ceramic capacitor 100B according to the third embodiment.

[0102] The positions of the first metal layers 21 are also the same as those of the multilayer ceramic capacitor 100B according to the third embodiment. That is, the first metal layers 21 are provided at four positions at the corners that straddle two side surfaces of the capacitor body 1.

[0103] In this embodiment, the second metal layer 22 is provided between two first metal layers 21 on each of the first side surface 1c, the second side surface 1d, the third side surface 1e, and the fourth side surface 1f of the capacitor body 1. That is, as shown in FIG. 16 , the second metal layer 22 provided on the first side surface 1c of the capacitor body 1 is located between the two first metal layers 21 provided on the first side surface 1c. Similarly, the second metal layer 22 provided on the second side surface 1d of the capacitor body 1 is located between the two first metal layers 21 provided on the second side surface 1d. The second metal layer 22 provided on the third side surface 1e of the capacitor body 1 is located between the two first metal layers 21 provided on the third side surface 1e. The second metal layer 22 provided on the fourth side surface 1f of the capacitor body 1 is located between the two first metal layers 21 provided on the fourth side surface 1f.

[0104] Fig. 17(a) is a plan view schematically showing a first internal electrode 3, and Fig. 17(b) is a plan view schematically showing a second internal electrode 4. Figs. 17(a) and 17(b) also show a dielectric layer 2, a first via conductor 5, a second via conductor 6, a first connecting layer 31, and a second connecting layer 32.

[0105] The first inner electrode 3 has a plurality of first through holes 3a formed therein for inserting the second via conductors 6. The second inner electrode 4 has a plurality of second through holes 4a formed therein for inserting the first via conductors 5.

[0106] 17(b), the first via conductor 5 provided at a position overlapping with the second internal electrode 4 in the stacking direction T passes through the second through hole 4a formed in the second internal electrode 4, and is insulated from the second internal electrode 4. Also, as shown in Fig. 17(a), the second via conductor 6 provided at a position overlapping with the first internal electrode 3 in the stacking direction T passes through the first through hole 3a formed in the first internal electrode 3, and is insulated from the first internal electrode 3.

[0107] 17( a) and 17(b), the first connection layer 31 and the second connection layer 32 are provided on the layer on which the first internal electrode 3 is provided and the layer on which the second internal electrode 4 is provided, respectively. The first connection layer 31 is provided at the four corner positions of the rectangular dielectric layer 2 when viewed in the stacking direction T. The first connection layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5. The first connection layer 31 is not in direct contact with the first internal electrode 3.

[0108] 17( a) and 17(b), the second connection layers 32 are provided at the center positions of the four sides of the rectangular dielectric layer 2 when viewed in the stacking direction T. The second connection layers 32 are in contact with the nearest second via conductors 6 and are electrically connected to the second internal electrodes 4 through the second via conductors 6. The second connection layers 32 are not in direct contact with the second internal electrodes 4.

[0109] Like the multilayer ceramic capacitor 100 in the first embodiment, the multilayer ceramic capacitor 100C in the fourth embodiment has a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 provided on the side of the capacitor body 1, so that the formation of the first external electrode 11 and the second external electrode 12 by rotary plating can be more reliably carried out.

[0110] (Variation of the Fourth Embodiment) In the configuration shown in Figures 17(a) and 17(b), a first connection layer 31 and a second connection layer 32 are provided on the layer on which the first internal electrode 3 is provided and the layer on which the second internal electrode 4 is provided, respectively. However, a configuration in which the first connection layer 31 is provided on the layer on which the first internal electrode 3 is provided and the second connection layer 32 is provided on the layer on which the second internal electrode 4 is provided may also be used. Figure 18(a) is a plan view schematically showing the first internal electrode 3 and the first connection layer 31 in this case, and Figure 18(b) is a plan view schematically showing the second internal electrode 4 and the second connection layer 32. Figures 18(a) and 18(b) also show the dielectric layer 2, the first via conductors 5, and the second via conductors 6. The number and positions of the first via conductors 5 and the second via conductors 6 are the same as those of the first via conductors 5 and the second via conductors 6 shown in Figure 17.

[0111] As shown in Fig. 18(a), the first connection layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not in direct contact with the first internal electrode 3. The position of the first connection layer 31 when viewed in the stacking direction T is the same as the position shown in Fig. 17(a). As shown in Fig. 18(a), the second connection layer 32 is not provided on the layer on which the first internal electrode 3 is provided.

[0112] As shown in Fig. 18(b), the second connection layer 32 is in contact with the nearest second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connection layer 32 is not in direct contact with the second internal electrode 4. The position of the second connection layer 32 when viewed in the stacking direction T is the same as the position shown in Fig. 17(b). As shown in Fig. 18(b), the first connection layer 31 is not provided on the layer on which the second internal electrode 4 is provided.

[0113] 18(a) and 18(b), the number of first connection layers 31 and second connection layers 32 can be reduced by approximately half compared to the configuration shown in Figures 17(a) and 17(b), which makes it possible to prevent the intrusion of plating solution from the outside into the interior during manufacturing and to prevent the intrusion of moisture, etc. from the outside into the interior of the finished product. That is, although plating solution and moisture are likely to infiltrate the interior at positions on the side surfaces of capacitor body 1 where first connection layers 31 and second connection layers 32 are exposed, the intrusion of plating solution, moisture, etc. into the interior is prevented by reducing the number of first connection layers 31 and second connection layers 32.

[0114] The present invention is not limited to the above-described embodiments, and various applications and modifications can be made within the scope of the present invention. For example, the characteristic configurations described in each embodiment and their modifications can be combined as appropriate.

[0115] The arrangement pattern of the multiple external electrodes arranged in a matrix is ​​not limited to the arrangement patterns of the above-described embodiment and modified examples. For example, when the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is odd, the arrangement pattern shown in FIG. 19 can also be used. In the arrangement pattern shown in FIG. 19 , external electrodes of the same type are arranged in the row direction, and first external electrodes 11 and second external electrodes 12 are arranged alternately in the column direction. However, the first external electrodes 11 and second external electrodes 12 may be arranged alternately in the row direction, and external electrodes of the same type may be arranged in the column direction. In the arrangement pattern shown in FIG. 19 , as in the arrangement pattern shown in FIG. 13 , only the first external electrode 11 is provided on the side surface of the capacitor body 1.

[0116] When the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd, the arrangement patterns shown in Figures 20(a) and 20(b) can be used. In the arrangement pattern shown in Figure 20(a), the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are also alternately arranged in the column direction. In the arrangement pattern shown in Figure 20(b), the same type of external electrodes are arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the column direction. In the arrangement pattern shown in Figure 20(a), a first metal layer 21 and a second metal layer 22 are provided on the side surface of the capacitor body 1, while in the arrangement pattern shown in Figure 20(b), only the first metal layer 21 is provided on the side surface of the capacitor body 1. In addition, even when the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is even, the external electrodes can be arranged in the same arrangement pattern as when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd.

[0117] When the number of external electrodes is greater than two rows and two columns, and the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is even, the arrangement patterns shown in Figures 21(a) and 21(b) can be used. In the arrangement pattern shown in Figure 21(a), the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the column direction. In the arrangement pattern shown in Figure 21(b), the same type of external electrodes are arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the column direction. However, it is also possible to alternate the first external electrodes 11 and the second external electrodes 12 in the row direction and arrange the same type of external electrodes in the column direction. In the arrangement patterns shown in Figures 21(a) and 21(b), a first metal layer 21 and a second metal layer 22 are each provided on the side surface of the capacitor body 1.

[0118] When mounting the multilayer ceramic capacitor 100 on a mounting substrate, the first metal layer 21 and the second metal layer 22 may not be joined to the land electrodes of the mounting substrate. In this case, the first metal layer 21 and the second metal layer 22 are unnecessary for practical use in the finished product, and therefore the first metal layer 21 and the second metal layer 22 may be covered with a resin or the like.

[0119] In the multilayer ceramic capacitors of the above-described embodiments and their modified examples, the first connection layer 31 that electrically connects the first via conductor 5 and the first metal layer 21 is provided inside the capacitor body 1. However, the first connection layer 31 may not be provided, and the first via conductor 5 and the first metal layer 21 may be electrically connected by the first internal electrode 3. In this case, the first internal electrode 3 may be shaped so as to extend to the side surface of the capacitor body 1. Similarly, in a multilayer ceramic capacitor including the second metal layer 22, the second via conductor 6 and the second metal layer 22 may be electrically connected by the second internal electrode 4, without providing the second connection layer 32.

[0120] The multilayer ceramic capacitor in the present application is as follows: <1>. A multilayer ceramic capacitor comprising: a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; first via conductors provided inside the capacitor body and electrically connected to the plurality of first internal electrodes; second via conductors provided inside the capacitor body and electrically connected to the plurality of second internal electrodes; first external electrodes provided on at least one of a first main surface and a second main surface facing in a stacking direction of the dielectric layers, the first internal electrodes, and the second internal electrodes, and connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; and a first metal layer provided on a side surface of the capacitor body other than the first main surface and the second main surface, and electrically connected to the first via conductor.

[0121] <2> The multilayer ceramic capacitor according to <1>, further comprising a first connection layer provided inside the capacitor body and electrically connecting the first via conductor and the first metal layer.

[0122] <3> A multilayer ceramic capacitor comprising: a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the plurality of first internal electrodes; a second via conductor provided inside the capacitor body and electrically connected to the plurality of second internal electrodes; a first external electrode provided on at least one of a first main surface and a second main surface facing in a lamination direction of the dielectric layers, the first internal electrodes, and the second internal electrodes, and connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; a first metal layer provided on a side surface of the capacitor body that is a surface other than the first main surface and the second main surface, and electrically connected to the first via conductor; and a second metal layer provided on the side surface of the capacitor body and electrically connected to the second via conductor.

[0123] <4> The multilayer ceramic capacitor according to <3>, further comprising: a first connection layer provided inside the capacitor body and electrically connecting the first via conductor and the first metal layer; and a second connection layer provided inside the capacitor body and electrically connecting the second via conductor and the second metal layer.

[0124] <5> The multilayer ceramic capacitor according to <3> or <4>, wherein the first metal layer and the second metal layer are each provided at a corner position spanning the two side surfaces of the capacitor body.

[0125] <6> The multilayer ceramic capacitor according to any one of <3> to <5>, wherein the capacitor body has four side surfaces, one of the first metal layer and the second metal layer is provided at four corner positions spanning two of the side surfaces of the capacitor body, and the other metal layer is provided at a position between two of the one metal layers on each of the four side surfaces.

[0126] <7>. The multilayer ceramic capacitor according to <4>, characterized in that the first connection layer is provided on a layer on which the second internal electrodes are provided, and the second connection layer is provided on a layer on which the first internal electrodes are provided.

[0127] <8> The multilayer ceramic capacitor according to <4>, characterized in that the first connection layer and the second connection layer are provided on a layer on which the first internal electrode is provided and a layer on which the second internal electrode is provided, respectively.

[0128] <9> The multilayer ceramic capacitor according to <4>, characterized in that the first connection layer is provided on a layer on which the first internal electrodes are provided, and the second connection layer is provided on a layer on which the second internal electrodes are provided.

[0129] <10>. The multilayer ceramic capacitor according to <8> or <9>, characterized in that the first connection layer is in contact with the first via conductor but not in contact with the first internal electrode, and the second connection layer is in contact with the second via conductor but not in contact with the second internal electrode.

[0130] <11>. The multilayer ceramic capacitor according to any one of <1> to <10>, wherein the first metal layer is a plated layer, and the first external electrode and the second external electrode are plated electrodes.

[0131] 1 Capacitor body, 2 Dielectric layer, 3 First internal electrode, 3a First through hole, 4 Second internal electrode, 4a Second through hole, 5 First via conductor, 6 Second via conductor, 11 First external electrode, 12 Second external electrode, 21 First metal layer, 22 Second metal layer, 31 First connecting layer, 32 Second connecting layer, 100, 100A, 100B, 100C Multilayer ceramic capacitor, 200 Connecting substrate, 210 Land electrode, 220 Solder.

Claims

1. a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the plurality of first internal electrodes; second via conductors provided inside the capacitor body and electrically connected to the plurality of second internal electrodes; a first external electrode provided on at least one of a first main surface and a second main surface of the capacitor body, the first main surface and the second main surface being opposed to each other in a stacking direction of the dielectric layers, the first internal electrodes, and the second internal electrodes, and connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; a first metal layer provided on a side surface of the capacitor body other than the first principal surface and the second principal surface, the first metal layer being electrically connected to the first via conductor; a second metal layer provided on the side surface of the capacitor body and electrically connected to the second via conductor; Equipped with The multilayer ceramic capacitor, wherein the first metal layer and the second metal layer are each provided at a corner position spanning the two side surfaces of the capacitor body.

2. a first connection layer provided inside the capacitor body and electrically connecting the first via conductor and the first metal layer; a second connection layer provided inside the capacitor body and electrically connecting the second via conductor and the second metal layer; The multilayer ceramic capacitor according to claim 1 , further comprising:

3. The capacitor body has four side surfaces, 2. The multilayer ceramic capacitor according to claim 1, wherein one of the first metal layer and the second metal layer is provided at four corner positions spanning two of the side surfaces of the capacitor body, and the other metal layer is provided at a position between two of the one metal layers on each of the four side surfaces.

4. The capacitor body has four side surfaces, 3. The multilayer ceramic capacitor according to claim 2, wherein one of the first metal layer and the second metal layer is provided at four corner positions spanning two of the side surfaces of the capacitor body, and the other metal layer is provided at a position between two of the one metal layers on each of the four side surfaces.

5. the first connection layer is provided on a layer on which the second internal electrodes are provided, 3. The multilayer ceramic capacitor according to claim 2, wherein the second connection layer is provided on the layer on which the first internal electrodes are provided.

6. 3. The multilayer ceramic capacitor according to claim 2, wherein the first connection layer and the second connection layer are provided on a layer on which the first internal electrode is provided and a layer on which the second internal electrode is provided, respectively.

7. the first connection layer is provided on a layer on which the first internal electrodes are provided, 3. The multilayer ceramic capacitor according to claim 2, wherein the second connection layer is provided on a layer on which the second internal electrodes are provided.

8. the first connection layer is in contact with the first via conductor but not in contact with the first internal electrode; 7. The multilayer ceramic capacitor according to claim 6, wherein the second connection layer is in contact with the second via conductor but not in contact with the second internal electrode.

9. The first connection layer is in contact with the first via conductor but not in contact with the first internal electrode; 8. The multilayer ceramic capacitor according to claim 7, wherein the second connection layer is in contact with the second via conductor but not in contact with the second internal electrode.

10. the first metal layer is a plating layer, 10. The multilayer ceramic capacitor according to claim 1, wherein the first external electrodes and the second external electrodes are plated electrodes.